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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma
[linux-2.6-block.git] / drivers / infiniband / hw / hns / hns_roce_hem.c
CommitLineData
9a443537 1/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
9a443537 34#include "hns_roce_device.h"
35#include "hns_roce_hem.h"
36#include "hns_roce_common.h"
37
2f49de21
XW		 38#define HEM_INDEX_BUF BIT(0)
39#define HEM_INDEX_L0 BIT(1)
40#define HEM_INDEX_L1 BIT(2)
41struct hns_roce_hem_index {
42 u64 buf;
43 u64 l0;
44 u64 l1;
45 u32 inited; /* indicate which index is available */
46};
47
a25d13cb
SX		 48bool hns_roce_check_whether_mhop(struct hns_roce_dev *hr_dev, u32 type)
49{
d7019c0f
LO		 50 int hop_num = 0;
51
52 switch (type) {
53 case HEM_TYPE_QPC:
54 hop_num = hr_dev->caps.qpc_hop_num;
55 break;
56 case HEM_TYPE_MTPT:
57 hop_num = hr_dev->caps.mpt_hop_num;
58 break;
59 case HEM_TYPE_CQC:
60 hop_num = hr_dev->caps.cqc_hop_num;
61 break;
62 case HEM_TYPE_SRQC:
63 hop_num = hr_dev->caps.srqc_hop_num;
64 break;
65 case HEM_TYPE_SCCC:
66 hop_num = hr_dev->caps.sccc_hop_num;
67 break;
68 case HEM_TYPE_QPC_TIMER:
69 hop_num = hr_dev->caps.qpc_timer_hop_num;
70 break;
71 case HEM_TYPE_CQC_TIMER:
72 hop_num = hr_dev->caps.cqc_timer_hop_num;
73 break;
d6d91e46
WL		 74 case HEM_TYPE_GMV:
75 hop_num = hr_dev->caps.gmv_hop_num;
76 break;
d7019c0f
LO		 77 default:
78 return false;
79 }
80
272bba19 81 return hop_num;
a25d13cb 82}
a25d13cb 83
38dcb350
XW		 84static bool hns_roce_check_hem_null(struct hns_roce_hem **hem, u64 hem_idx,
85 u32 bt_chunk_num, u64 hem_max_num)
a25d13cb 86{
38dcb350 87 u64 start_idx = round_down(hem_idx, bt_chunk_num);
9bba3f0c
XW		 88 u64 check_max_num = start_idx + bt_chunk_num;
89 u64 i;
a25d13cb 90
9bba3f0c 91 for (i = start_idx; (i < check_max_num) && (i < hem_max_num); i++)
38dcb350 92 if (i != hem_idx && hem[i])
a25d13cb
SX		 93 return false;
94
95 return true;
96}
97
38dcb350 98static bool hns_roce_check_bt_null(u64 **bt, u64 ba_idx, u32 bt_chunk_num)
a25d13cb 99{
38dcb350 100 u64 start_idx = round_down(ba_idx, bt_chunk_num);
a25d13cb
SX		 101 int i;
102
103 for (i = 0; i < bt_chunk_num; i++)
38dcb350 104 if (i != ba_idx && bt[start_idx + i])
a25d13cb
SX		 105 return false;
106
107 return true;
108}
109
110static int hns_roce_get_bt_num(u32 table_type, u32 hop_num)
111{
112 if (check_whether_bt_num_3(table_type, hop_num))
113 return 3;
114 else if (check_whether_bt_num_2(table_type, hop_num))
115 return 2;
116 else if (check_whether_bt_num_1(table_type, hop_num))
117 return 1;
118 else
119 return 0;
120}
121
d7019c0f
LO		 122static int get_hem_table_config(struct hns_roce_dev *hr_dev,
123 struct hns_roce_hem_mhop *mhop,
124 u32 type)
a25d13cb
SX		 125{
126 struct device *dev = hr_dev->dev;
a25d13cb 127
d7019c0f 128 switch (type) {
a25d13cb
SX		 129 case HEM_TYPE_QPC:
130 mhop->buf_chunk_size = 1 << (hr_dev->caps.qpc_buf_pg_sz
131 + PAGE_SHIFT);
132 mhop->bt_chunk_size = 1 << (hr_dev->caps.qpc_ba_pg_sz
133 + PAGE_SHIFT);
134 mhop->ba_l0_num = hr_dev->caps.qpc_bt_num;
135 mhop->hop_num = hr_dev->caps.qpc_hop_num;
136 break;
137 case HEM_TYPE_MTPT:
138 mhop->buf_chunk_size = 1 << (hr_dev->caps.mpt_buf_pg_sz
139 + PAGE_SHIFT);
140 mhop->bt_chunk_size = 1 << (hr_dev->caps.mpt_ba_pg_sz
141 + PAGE_SHIFT);
142 mhop->ba_l0_num = hr_dev->caps.mpt_bt_num;
143 mhop->hop_num = hr_dev->caps.mpt_hop_num;
144 break;
145 case HEM_TYPE_CQC:
146 mhop->buf_chunk_size = 1 << (hr_dev->caps.cqc_buf_pg_sz
147 + PAGE_SHIFT);
148 mhop->bt_chunk_size = 1 << (hr_dev->caps.cqc_ba_pg_sz
149 + PAGE_SHIFT);
150 mhop->ba_l0_num = hr_dev->caps.cqc_bt_num;
151 mhop->hop_num = hr_dev->caps.cqc_hop_num;
152 break;
6a157f7d
YL		 153 case HEM_TYPE_SCCC:
154 mhop->buf_chunk_size = 1 << (hr_dev->caps.sccc_buf_pg_sz
155 + PAGE_SHIFT);
156 mhop->bt_chunk_size = 1 << (hr_dev->caps.sccc_ba_pg_sz
157 + PAGE_SHIFT);
158 mhop->ba_l0_num = hr_dev->caps.sccc_bt_num;
159 mhop->hop_num = hr_dev->caps.sccc_hop_num;
160 break;
0e40dc2f
YL		 161 case HEM_TYPE_QPC_TIMER:
162 mhop->buf_chunk_size = 1 << (hr_dev->caps.qpc_timer_buf_pg_sz
163 + PAGE_SHIFT);
164 mhop->bt_chunk_size = 1 << (hr_dev->caps.qpc_timer_ba_pg_sz
165 + PAGE_SHIFT);
166 mhop->ba_l0_num = hr_dev->caps.qpc_timer_bt_num;
167 mhop->hop_num = hr_dev->caps.qpc_timer_hop_num;
168 break;
169 case HEM_TYPE_CQC_TIMER:
170 mhop->buf_chunk_size = 1 << (hr_dev->caps.cqc_timer_buf_pg_sz
171 + PAGE_SHIFT);
172 mhop->bt_chunk_size = 1 << (hr_dev->caps.cqc_timer_ba_pg_sz
173 + PAGE_SHIFT);
174 mhop->ba_l0_num = hr_dev->caps.cqc_timer_bt_num;
175 mhop->hop_num = hr_dev->caps.cqc_timer_hop_num;
176 break;
a25d13cb
SX		 177 case HEM_TYPE_SRQC:
178 mhop->buf_chunk_size = 1 << (hr_dev->caps.srqc_buf_pg_sz
179 + PAGE_SHIFT);
180 mhop->bt_chunk_size = 1 << (hr_dev->caps.srqc_ba_pg_sz
181 + PAGE_SHIFT);
182 mhop->ba_l0_num = hr_dev->caps.srqc_bt_num;
183 mhop->hop_num = hr_dev->caps.srqc_hop_num;
184 break;
d6d91e46
WL		 185 case HEM_TYPE_GMV:
186 mhop->buf_chunk_size = 1 << (hr_dev->caps.gmv_buf_pg_sz +
187 PAGE_SHIFT);
188 mhop->bt_chunk_size = 1 << (hr_dev->caps.gmv_ba_pg_sz +
189 PAGE_SHIFT);
190 mhop->ba_l0_num = hr_dev->caps.gmv_bt_num;
191 mhop->hop_num = hr_dev->caps.gmv_hop_num;
192 break;
a25d13cb 193 default:
61918e9b 194 dev_err(dev, "table %u not support multi-hop addressing!\n",
d7019c0f 195 type);
a25d13cb
SX		 196 return -EINVAL;
197 }
198
d7019c0f
LO		 199 return 0;
200}
201
202int hns_roce_calc_hem_mhop(struct hns_roce_dev *hr_dev,
203 struct hns_roce_hem_table *table, unsigned long *obj,
204 struct hns_roce_hem_mhop *mhop)
205{
206 struct device *dev = hr_dev->dev;
207 u32 chunk_ba_num;
dc93a0d9 208 u32 chunk_size;
d7019c0f
LO		 209 u32 table_idx;
210 u32 bt_num;
d7019c0f
LO		 211
212 if (get_hem_table_config(hr_dev, mhop, table->type))
213 return -EINVAL;
214
a25d13cb
SX		 215 if (!obj)
216 return 0;
217
6a93c77a 218 /*
6a157f7d 219 * QPC/MTPT/CQC/SRQC/SCCC alloc hem for buffer pages.
6a93c77a
SX		 220 * MTT/CQE alloc hem for bt pages.
221 */
a25d13cb 222 bt_num = hns_roce_get_bt_num(table->type, mhop->hop_num);
2a3d923f 223 chunk_ba_num = mhop->bt_chunk_size / BA_BYTE_LEN;
6a93c77a
SX		 224 chunk_size = table->type < HEM_TYPE_MTT ? mhop->buf_chunk_size :
225 mhop->bt_chunk_size;
61b460d1 226 table_idx = *obj / (chunk_size / table->obj_size);
a25d13cb
SX		 227 switch (bt_num) {
228 case 3:
229 mhop->l2_idx = table_idx & (chunk_ba_num - 1);
230 mhop->l1_idx = table_idx / chunk_ba_num & (chunk_ba_num - 1);
73b4e1f4 231 mhop->l0_idx = (table_idx / chunk_ba_num) / chunk_ba_num;
a25d13cb
SX		 232 break;
233 case 2:
234 mhop->l1_idx = table_idx & (chunk_ba_num - 1);
235 mhop->l0_idx = table_idx / chunk_ba_num;
236 break;
237 case 1:
238 mhop->l0_idx = table_idx;
239 break;
240 default:
61918e9b
YL		 241 dev_err(dev, "table %u not support hop_num = %u!\n",
242 table->type, mhop->hop_num);
a25d13cb
SX		 243 return -EINVAL;
244 }
245 if (mhop->l0_idx >= mhop->ba_l0_num)
246 mhop->l0_idx %= mhop->ba_l0_num;
247
248 return 0;
249}
a25d13cb
SX		 250
251static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev,
a25d13cb
SX		 252 unsigned long hem_alloc_size,
253 gfp_t gfp_mask)
9a443537 254{
9a443537 255 struct hns_roce_hem *hem;
9a443537 256 int order;
257 void *buf;
258
259 WARN_ON(gfp_mask & __GFP_HIGHMEM);
260
c00743cb
YL		 261 order = get_order(hem_alloc_size);
262 if (PAGE_SIZE << order != hem_alloc_size) {
263 dev_err(hr_dev->dev, "invalid hem_alloc_size: %lu!\n",
264 hem_alloc_size);
265 return NULL;
266 }
267
9a443537 268 hem = kmalloc(sizeof(*hem),
269 gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
270 if (!hem)
271 return NULL;
272
c00743cb
YL		 273 buf = dma_alloc_coherent(hr_dev->dev, hem_alloc_size,
274 &hem->dma, gfp_mask);
275 if (!buf)
276 goto fail;
9a443537 277
c00743cb
YL		 278 hem->buf = buf;
279 hem->size = hem_alloc_size;
9a443537 280
281 return hem;
282
283fail:
dc3bda6e 284 kfree(hem);
9a443537 285 return NULL;
286}
287
288void hns_roce_free_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem *hem)
289{
9a443537 290 if (!hem)
291 return;
292
c00743cb 293 dma_free_coherent(hr_dev->dev, hem->size, hem->buf, hem->dma);
9a443537 294
295 kfree(hem);
296}
297
2f49de21
XW		 298static int calc_hem_config(struct hns_roce_dev *hr_dev,
299 struct hns_roce_hem_table *table, unsigned long obj,
300 struct hns_roce_hem_mhop *mhop,
301 struct hns_roce_hem_index *index)
a25d13cb 302{
2f49de21
XW		 303 struct ib_device *ibdev = &hr_dev->ib_dev;
304 unsigned long mhop_obj = obj;
305 u32 l0_idx, l1_idx, l2_idx;
a25d13cb 306 u32 chunk_ba_num;
a25d13cb 307 u32 bt_num;
a25d13cb
SX		 308 int ret;
309
2f49de21 310 ret = hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, mhop);
a25d13cb
SX		 311 if (ret)
312 return ret;
313
2f49de21
XW		 314 l0_idx = mhop->l0_idx;
315 l1_idx = mhop->l1_idx;
316 l2_idx = mhop->l2_idx;
317 chunk_ba_num = mhop->bt_chunk_size / BA_BYTE_LEN;
318 bt_num = hns_roce_get_bt_num(table->type, mhop->hop_num);
a25d13cb
SX		 319 switch (bt_num) {
320 case 3:
2f49de21
XW		 321 index->l1 = l0_idx * chunk_ba_num + l1_idx;
322 index->l0 = l0_idx;
323 index->buf = l0_idx * chunk_ba_num * chunk_ba_num +
324 l1_idx * chunk_ba_num + l2_idx;
a25d13cb
SX		 325 break;
326 case 2:
2f49de21
XW		 327 index->l0 = l0_idx;
328 index->buf = l0_idx * chunk_ba_num + l1_idx;
a25d13cb
SX		 329 break;
330 case 1:
2f49de21 331 index->buf = l0_idx;
a25d13cb
SX		 332 break;
333 default:
61918e9b 334 ibdev_err(ibdev, "table %u not support mhop.hop_num = %u!\n",
2f49de21 335 table->type, mhop->hop_num);
a25d13cb
SX		 336 return -EINVAL;
337 }
338
2f49de21 339 if (unlikely(index->buf >= table->num_hem)) {
61918e9b 340 ibdev_err(ibdev, "table %u exceed hem limt idx %llu, max %lu!\n",
2f49de21 341 table->type, index->buf, table->num_hem);
9bba3f0c
XW		 342 return -EINVAL;
343 }
344
2f49de21
XW		 345 return 0;
346}
a25d13cb 347
2f49de21
XW		 348static void free_mhop_hem(struct hns_roce_dev *hr_dev,
349 struct hns_roce_hem_table *table,
350 struct hns_roce_hem_mhop *mhop,
351 struct hns_roce_hem_index *index)
352{
353 u32 bt_size = mhop->bt_chunk_size;
354 struct device *dev = hr_dev->dev;
355
356 if (index->inited & HEM_INDEX_BUF) {
357 hns_roce_free_hem(hr_dev, table->hem[index->buf]);
358 table->hem[index->buf] = NULL;
359 }
360
361 if (index->inited & HEM_INDEX_L1) {
362 dma_free_coherent(dev, bt_size, table->bt_l1[index->l1],
363 table->bt_l1_dma_addr[index->l1]);
364 table->bt_l1[index->l1] = NULL;
365 }
366
367 if (index->inited & HEM_INDEX_L0) {
368 dma_free_coherent(dev, bt_size, table->bt_l0[index->l0],
369 table->bt_l0_dma_addr[index->l0]);
370 table->bt_l0[index->l0] = NULL;
a25d13cb 371 }
2f49de21
XW		 372}
373
374static int alloc_mhop_hem(struct hns_roce_dev *hr_dev,
375 struct hns_roce_hem_table *table,
376 struct hns_roce_hem_mhop *mhop,
377 struct hns_roce_hem_index *index)
378{
379 u32 bt_size = mhop->bt_chunk_size;
380 struct device *dev = hr_dev->dev;
2f49de21
XW		 381 gfp_t flag;
382 u64 bt_ba;
383 u32 size;
384 int ret;
a25d13cb
SX		 385
386 /* alloc L1 BA's chunk */
2f49de21
XW		 387 if ((check_whether_bt_num_3(table->type, mhop->hop_num) ||
388 check_whether_bt_num_2(table->type, mhop->hop_num)) &&
389 !table->bt_l0[index->l0]) {
390 table->bt_l0[index->l0] = dma_alloc_coherent(dev, bt_size,
391 &table->bt_l0_dma_addr[index->l0],
a25d13cb 392 GFP_KERNEL);
2f49de21 393 if (!table->bt_l0[index->l0]) {
a25d13cb
SX		 394 ret = -ENOMEM;
395 goto out;
396 }
2f49de21 397 index->inited |= HEM_INDEX_L0;
a25d13cb
SX		 398 }
399
400 /* alloc L2 BA's chunk */
2f49de21
XW		 401 if (check_whether_bt_num_3(table->type, mhop->hop_num) &&
402 !table->bt_l1[index->l1]) {
403 table->bt_l1[index->l1] = dma_alloc_coherent(dev, bt_size,
404 &table->bt_l1_dma_addr[index->l1],
a25d13cb 405 GFP_KERNEL);
2f49de21 406 if (!table->bt_l1[index->l1]) {
a25d13cb 407 ret = -ENOMEM;
2f49de21 408 goto err_alloc_hem;
a25d13cb 409 }
2f49de21
XW		 410 index->inited |= HEM_INDEX_L1;
411 *(table->bt_l0[index->l0] + mhop->l1_idx) =
412 table->bt_l1_dma_addr[index->l1];
a25d13cb
SX		 413 }
414
6a93c77a 415 /*
6a157f7d 416 * alloc buffer space chunk for QPC/MTPT/CQC/SRQC/SCCC.
6a93c77a
SX		 417 * alloc bt space chunk for MTT/CQE.
418 */
2f49de21 419 size = table->type < HEM_TYPE_MTT ? mhop->buf_chunk_size : bt_size;
29dc0635 420 flag = GFP_KERNEL | __GFP_NOWARN;
c00743cb 421 table->hem[index->buf] = hns_roce_alloc_hem(hr_dev, size, flag);
2f49de21 422 if (!table->hem[index->buf]) {
a25d13cb 423 ret = -ENOMEM;
2f49de21 424 goto err_alloc_hem;
a25d13cb
SX		 425 }
426
2f49de21 427 index->inited |= HEM_INDEX_BUF;
c00743cb
YL		 428 bt_ba = table->hem[index->buf]->dma;
429
a25d13cb 430 if (table->type < HEM_TYPE_MTT) {
2f49de21
XW		 431 if (mhop->hop_num == 2)
432 *(table->bt_l1[index->l1] + mhop->l2_idx) = bt_ba;
433 else if (mhop->hop_num == 1)
434 *(table->bt_l0[index->l0] + mhop->l1_idx) = bt_ba;
435 } else if (mhop->hop_num == 2) {
436 *(table->bt_l0[index->l0] + mhop->l1_idx) = bt_ba;
437 }
438
439 return 0;
440err_alloc_hem:
441 free_mhop_hem(hr_dev, table, mhop, index);
442out:
443 return ret;
444}
445
446static int set_mhop_hem(struct hns_roce_dev *hr_dev,
447 struct hns_roce_hem_table *table, unsigned long obj,
448 struct hns_roce_hem_mhop *mhop,
449 struct hns_roce_hem_index *index)
450{
451 struct ib_device *ibdev = &hr_dev->ib_dev;
e50cda2b 452 u32 step_idx;
d35dc58d 453 int ret = 0;
2f49de21
XW		 454
455 if (index->inited & HEM_INDEX_L0) {
456 ret = hr_dev->hw->set_hem(hr_dev, table, obj, 0);
457 if (ret) {
458 ibdev_err(ibdev, "set HEM step 0 failed!\n");
459 goto out;
a25d13cb 460 }
2f49de21 461 }
a25d13cb 462
2f49de21
XW		 463 if (index->inited & HEM_INDEX_L1) {
464 ret = hr_dev->hw->set_hem(hr_dev, table, obj, 1);
465 if (ret) {
466 ibdev_err(ibdev, "set HEM step 1 failed!\n");
467 goto out;
a25d13cb
SX		 468 }
469 }
470
2f49de21
XW		 471 if (index->inited & HEM_INDEX_BUF) {
472 if (mhop->hop_num == HNS_ROCE_HOP_NUM_0)
473 step_idx = 0;
474 else
475 step_idx = mhop->hop_num;
476 ret = hr_dev->hw->set_hem(hr_dev, table, obj, step_idx);
477 if (ret)
478 ibdev_err(ibdev, "set HEM step last failed!\n");
479 }
480out:
481 return ret;
482}
483
484static int hns_roce_table_mhop_get(struct hns_roce_dev *hr_dev,
485 struct hns_roce_hem_table *table,
486 unsigned long obj)
487{
488 struct ib_device *ibdev = &hr_dev->ib_dev;
489 struct hns_roce_hem_index index = {};
490 struct hns_roce_hem_mhop mhop = {};
491 int ret;
a25d13cb 492
2f49de21
XW		 493 ret = calc_hem_config(hr_dev, table, obj, &mhop, &index);
494 if (ret) {
495 ibdev_err(ibdev, "calc hem config failed!\n");
496 return ret;
a25d13cb
SX		 497 }
498
2f49de21
XW		 499 mutex_lock(&table->mutex);
500 if (table->hem[index.buf]) {
82eb481d 501 refcount_inc(&table->hem[index.buf]->refcount);
2f49de21 502 goto out;
a25d13cb
SX		 503 }
504
2f49de21
XW		 505 ret = alloc_mhop_hem(hr_dev, table, &mhop, &index);
506 if (ret) {
507 ibdev_err(ibdev, "alloc mhop hem failed!\n");
508 goto out;
509 }
510
511 /* set HEM base address to hardware */
512 if (table->type < HEM_TYPE_MTT) {
513 ret = set_mhop_hem(hr_dev, table, obj, &mhop, &index);
514 if (ret) {
515 ibdev_err(ibdev, "set HEM address to HW failed!\n");
516 goto err_alloc;
517 }
518 }
519
82eb481d 520 refcount_set(&table->hem[index.buf]->refcount, 1);
2f49de21
XW		 521 goto out;
522
523err_alloc:
524 free_mhop_hem(hr_dev, table, &mhop, &index);
a25d13cb
SX		 525out:
526 mutex_unlock(&table->mutex);
527 return ret;
528}
529
9a443537 530int hns_roce_table_get(struct hns_roce_dev *hr_dev,
531 struct hns_roce_hem_table *table, unsigned long obj)
532{
13ca970e 533 struct device *dev = hr_dev->dev;
9a443537 534 unsigned long i;
dc93a0d9 535 int ret = 0;
9a443537 536
a25d13cb
SX		 537 if (hns_roce_check_whether_mhop(hr_dev, table->type))
538 return hns_roce_table_mhop_get(hr_dev, table, obj);
539
61b460d1 540 i = obj / (table->table_chunk_size / table->obj_size);
9a443537 541
542 mutex_lock(&table->mutex);
543
544 if (table->hem[i]) {
82eb481d 545 refcount_inc(&table->hem[i]->refcount);
9a443537 546 goto out;
547 }
548
549 table->hem[i] = hns_roce_alloc_hem(hr_dev,
29a1fe5d 550 table->table_chunk_size,
29dc0635 551 GFP_KERNEL | __GFP_NOWARN);
9a443537 552 if (!table->hem[i]) {
553 ret = -ENOMEM;
554 goto out;
555 }
556
557 /* Set HEM base address(128K/page, pa) to Hardware */
cf5b608f
CT		 558 ret = hr_dev->hw->set_hem(hr_dev, table, obj, HEM_HOP_STEP_DIRECT);
559 if (ret) {
08eb3018
WHX		 560 hns_roce_free_hem(hr_dev, table->hem[i]);
561 table->hem[i] = NULL;
cf5b608f
CT		 562 dev_err(dev, "set HEM base address to HW failed, ret = %d.\n",
563 ret);
9a443537 564 goto out;
565 }
566
82eb481d 567 refcount_set(&table->hem[i]->refcount, 1);
9a443537 568out:
569 mutex_unlock(&table->mutex);
570 return ret;
571}
572
38dcb350
XW		 573static void clear_mhop_hem(struct hns_roce_dev *hr_dev,
574 struct hns_roce_hem_table *table, unsigned long obj,
575 struct hns_roce_hem_mhop *mhop,
576 struct hns_roce_hem_index *index)
577{
578 struct ib_device *ibdev = &hr_dev->ib_dev;
579 u32 hop_num = mhop->hop_num;
580 u32 chunk_ba_num;
e50cda2b 581 u32 step_idx;
a519a612 582 int ret;
38dcb350
XW		 583
584 index->inited = HEM_INDEX_BUF;
585 chunk_ba_num = mhop->bt_chunk_size / BA_BYTE_LEN;
586 if (check_whether_bt_num_2(table->type, hop_num)) {
587 if (hns_roce_check_hem_null(table->hem, index->buf,
588 chunk_ba_num, table->num_hem))
589 index->inited |= HEM_INDEX_L0;
590 } else if (check_whether_bt_num_3(table->type, hop_num)) {
591 if (hns_roce_check_hem_null(table->hem, index->buf,
592 chunk_ba_num, table->num_hem)) {
593 index->inited |= HEM_INDEX_L1;
594 if (hns_roce_check_bt_null(table->bt_l1, index->l1,
595 chunk_ba_num))
596 index->inited |= HEM_INDEX_L0;
597 }
598 }
599
600 if (table->type < HEM_TYPE_MTT) {
601 if (hop_num == HNS_ROCE_HOP_NUM_0)
602 step_idx = 0;
603 else
604 step_idx = hop_num;
605
a519a612
CT		 606 ret = hr_dev->hw->clear_hem(hr_dev, table, obj, step_idx);
607 if (ret)
608 ibdev_warn(ibdev, "failed to clear hop%u HEM, ret = %d.\n",
609 hop_num, ret);
610
611 if (index->inited & HEM_INDEX_L1) {
612 ret = hr_dev->hw->clear_hem(hr_dev, table, obj, 1);
613 if (ret)
614 ibdev_warn(ibdev, "failed to clear HEM step 1, ret = %d.\n",
615 ret);
616 }
38dcb350 617
a519a612
CT		 618 if (index->inited & HEM_INDEX_L0) {
619 ret = hr_dev->hw->clear_hem(hr_dev, table, obj, 0);
620 if (ret)
621 ibdev_warn(ibdev, "failed to clear HEM step 0, ret = %d.\n",
622 ret);
623 }
38dcb350
XW		 624 }
625}
626
281d0ccf
CIK		 627static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev,
628 struct hns_roce_hem_table *table,
629 unsigned long obj,
630 int check_refcount)
a25d13cb 631{
38dcb350
XW		 632 struct ib_device *ibdev = &hr_dev->ib_dev;
633 struct hns_roce_hem_index index = {};
634 struct hns_roce_hem_mhop mhop = {};
a25d13cb
SX		 635 int ret;
636
38dcb350
XW		 637 ret = calc_hem_config(hr_dev, table, obj, &mhop, &index);
638 if (ret) {
639 ibdev_err(ibdev, "calc hem config failed!\n");
a25d13cb
SX		 640 return;
641 }
642
82eb481d
WL		 643 if (!check_refcount)
644 mutex_lock(&table->mutex);
645 else if (!refcount_dec_and_mutex_lock(&table->hem[index.buf]->refcount,
646 &table->mutex))
a25d13cb 647 return;
a25d13cb 648
38dcb350
XW		 649 clear_mhop_hem(hr_dev, table, obj, &mhop, &index);
650 free_mhop_hem(hr_dev, table, &mhop, &index);
a25d13cb
SX		 651
652 mutex_unlock(&table->mutex);
653}
654
9a443537 655void hns_roce_table_put(struct hns_roce_dev *hr_dev,
656 struct hns_roce_hem_table *table, unsigned long obj)
657{
13ca970e 658 struct device *dev = hr_dev->dev;
9a443537 659 unsigned long i;
a519a612 660 int ret;
9a443537 661
a25d13cb
SX		 662 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
663 hns_roce_table_mhop_put(hr_dev, table, obj, 1);
664 return;
665 }
666
61b460d1 667 i = obj / (table->table_chunk_size / table->obj_size);
9a443537 668
82eb481d
WL		 669 if (!refcount_dec_and_mutex_lock(&table->hem[i]->refcount,
670 &table->mutex))
671 return;
9a443537 672
a519a612
CT		 673 ret = hr_dev->hw->clear_hem(hr_dev, table, obj, HEM_HOP_STEP_DIRECT);
674 if (ret)
675 dev_warn(dev, "failed to clear HEM base address, ret = %d.\n",
676 ret);
9a443537 677
82eb481d
WL		 678 hns_roce_free_hem(hr_dev, table->hem[i]);
679 table->hem[i] = NULL;
9a443537 680
681 mutex_unlock(&table->mutex);
682}
683
6a93c77a
SX		 684void *hns_roce_table_find(struct hns_roce_dev *hr_dev,
685 struct hns_roce_hem_table *table,
686 unsigned long obj, dma_addr_t *dma_handle)
9a443537 687{
6a93c77a 688 struct hns_roce_hem_mhop mhop;
9a443537 689 struct hns_roce_hem *hem;
6a93c77a 690 unsigned long mhop_obj = obj;
0203b14c 691 unsigned long obj_per_chunk;
692 unsigned long idx_offset;
6a93c77a 693 int offset, dma_offset;
dc93a0d9
LC		 694 void *addr = NULL;
695 u32 hem_idx = 0;
6a93c77a 696 int i, j;
9a443537 697
9a443537 698 mutex_lock(&table->mutex);
6a93c77a
SX		 699
700 if (!hns_roce_check_whether_mhop(hr_dev, table->type)) {
0203b14c 701 obj_per_chunk = table->table_chunk_size / table->obj_size;
61b460d1
XW		 702 hem = table->hem[obj / obj_per_chunk];
703 idx_offset = obj % obj_per_chunk;
0203b14c 704 dma_offset = offset = idx_offset * table->obj_size;
6a93c77a 705 } else {
4772e03d
LO		 706 u32 seg_size = 64; /* 8 bytes per BA and 8 BA per segment */
707
0e20ebf8
LC		 708 if (hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop))
709 goto out;
6a93c77a
SX		 710 /* mtt mhop */
711 i = mhop.l0_idx;
712 j = mhop.l1_idx;
713 if (mhop.hop_num == 2)
2a3d923f 714 hem_idx = i * (mhop.bt_chunk_size / BA_BYTE_LEN) + j;
6a93c77a
SX		 715 else if (mhop.hop_num == 1 ||
716 mhop.hop_num == HNS_ROCE_HOP_NUM_0)
717 hem_idx = i;
718
719 hem = table->hem[hem_idx];
61b460d1 720 dma_offset = offset = obj * seg_size % mhop.bt_chunk_size;
6a93c77a
SX		 721 if (mhop.hop_num == 2)
722 dma_offset = offset = 0;
723 }
9a443537 724
725 if (!hem)
726 goto out;
727
c00743cb
YL		 728 *dma_handle = hem->dma + dma_offset;
729 addr = hem->buf + offset;
9a443537 730
731out:
732 mutex_unlock(&table->mutex);
378efe79 733 return addr;
9a443537 734}
735
9a443537 736int hns_roce_init_hem_table(struct hns_roce_dev *hr_dev,
737 struct hns_roce_hem_table *table, u32 type,
29dc0635 738 unsigned long obj_size, unsigned long nobj)
9a443537 739{
740 unsigned long obj_per_chunk;
741 unsigned long num_hem;
742
a25d13cb 743 if (!hns_roce_check_whether_mhop(hr_dev, type)) {
29a1fe5d
WHX		 744 table->table_chunk_size = hr_dev->caps.chunk_sz;
745 obj_per_chunk = table->table_chunk_size / obj_size;
61b460d1 746 num_hem = DIV_ROUND_UP(nobj, obj_per_chunk);
a25d13cb
SX		 747
748 table->hem = kcalloc(num_hem, sizeof(*table->hem), GFP_KERNEL);
749 if (!table->hem)
750 return -ENOMEM;
751 } else {
d7019c0f 752 struct hns_roce_hem_mhop mhop = {};
a25d13cb
SX		 753 unsigned long buf_chunk_size;
754 unsigned long bt_chunk_size;
755 unsigned long bt_chunk_num;
62f3b70e 756 unsigned long num_bt_l0;
a25d13cb
SX		 757 u32 hop_num;
758
d7019c0f 759 if (get_hem_table_config(hr_dev, &mhop, type))
a25d13cb 760 return -EINVAL;
d7019c0f
LO		 761
762 buf_chunk_size = mhop.buf_chunk_size;
763 bt_chunk_size = mhop.bt_chunk_size;
764 num_bt_l0 = mhop.ba_l0_num;
765 hop_num = mhop.hop_num;
766
a25d13cb 767 obj_per_chunk = buf_chunk_size / obj_size;
61b460d1 768 num_hem = DIV_ROUND_UP(nobj, obj_per_chunk);
2a3d923f 769 bt_chunk_num = bt_chunk_size / BA_BYTE_LEN;
61b460d1 770
215a8c09 771 if (type >= HEM_TYPE_MTT)
6a93c77a 772 num_bt_l0 = bt_chunk_num;
a25d13cb
SX		 773
774 table->hem = kcalloc(num_hem, sizeof(*table->hem),
775 GFP_KERNEL);
776 if (!table->hem)
777 goto err_kcalloc_hem_buf;
778
215a8c09 779 if (check_whether_bt_num_3(type, hop_num)) {
a25d13cb
SX		 780 unsigned long num_bt_l1;
781
61b460d1 782 num_bt_l1 = DIV_ROUND_UP(num_hem, bt_chunk_num);
a25d13cb
SX		 783 table->bt_l1 = kcalloc(num_bt_l1,
784 sizeof(*table->bt_l1),
785 GFP_KERNEL);
786 if (!table->bt_l1)
787 goto err_kcalloc_bt_l1;
788
789 table->bt_l1_dma_addr = kcalloc(num_bt_l1,
790 sizeof(*table->bt_l1_dma_addr),
791 GFP_KERNEL);
792
793 if (!table->bt_l1_dma_addr)
794 goto err_kcalloc_l1_dma;
795 }
9a443537 796
215a8c09 797 if (check_whether_bt_num_2(type, hop_num) ||
798 check_whether_bt_num_3(type, hop_num)) {
a25d13cb
SX		 799 table->bt_l0 = kcalloc(num_bt_l0, sizeof(*table->bt_l0),
800 GFP_KERNEL);
801 if (!table->bt_l0)
802 goto err_kcalloc_bt_l0;
803
804 table->bt_l0_dma_addr = kcalloc(num_bt_l0,
805 sizeof(*table->bt_l0_dma_addr),
806 GFP_KERNEL);
807 if (!table->bt_l0_dma_addr)
808 goto err_kcalloc_l0_dma;
809 }
810 }
9a443537 811
812 table->type = type;
813 table->num_hem = num_hem;
9a443537 814 table->obj_size = obj_size;
9a443537 815 mutex_init(&table->mutex);
816
817 return 0;
a25d13cb
SX		 818
819err_kcalloc_l0_dma:
820 kfree(table->bt_l0);
821 table->bt_l0 = NULL;
822
823err_kcalloc_bt_l0:
824 kfree(table->bt_l1_dma_addr);
825 table->bt_l1_dma_addr = NULL;
826
827err_kcalloc_l1_dma:
828 kfree(table->bt_l1);
829 table->bt_l1 = NULL;
830
831err_kcalloc_bt_l1:
832 kfree(table->hem);
833 table->hem = NULL;
834
835err_kcalloc_hem_buf:
836 return -ENOMEM;
837}
838
281d0ccf
CIK		 839static void hns_roce_cleanup_mhop_hem_table(struct hns_roce_dev *hr_dev,
840 struct hns_roce_hem_table *table)
a25d13cb
SX		 841{
842 struct hns_roce_hem_mhop mhop;
843 u32 buf_chunk_size;
a25d13cb 844 u64 obj;
dc93a0d9 845 int i;
a25d13cb 846
0e20ebf8
LC		 847 if (hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop))
848 return;
6a93c77a
SX		 849 buf_chunk_size = table->type < HEM_TYPE_MTT ? mhop.buf_chunk_size :
850 mhop.bt_chunk_size;
a25d13cb
SX		 851
852 for (i = 0; i < table->num_hem; ++i) {
853 obj = i * buf_chunk_size / table->obj_size;
854 if (table->hem[i])
855 hns_roce_table_mhop_put(hr_dev, table, obj, 0);
856 }
857
858 kfree(table->hem);
859 table->hem = NULL;
860 kfree(table->bt_l1);
861 table->bt_l1 = NULL;
862 kfree(table->bt_l1_dma_addr);
863 table->bt_l1_dma_addr = NULL;
864 kfree(table->bt_l0);
865 table->bt_l0 = NULL;
866 kfree(table->bt_l0_dma_addr);
867 table->bt_l0_dma_addr = NULL;
9a443537 868}
869
870void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev,
871 struct hns_roce_hem_table *table)
872{
13ca970e 873 struct device *dev = hr_dev->dev;
9a443537 874 unsigned long i;
a519a612
CT		 875 int obj;
876 int ret;
9a443537 877
a25d13cb
SX		 878 if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
879 hns_roce_cleanup_mhop_hem_table(hr_dev, table);
9a84848d 880 mutex_destroy(&table->mutex);
a25d13cb
SX		 881 return;
882 }
883
9a443537 884 for (i = 0; i < table->num_hem; ++i)
885 if (table->hem[i]) {
a519a612
CT		 886 obj = i * table->table_chunk_size / table->obj_size;
887 ret = hr_dev->hw->clear_hem(hr_dev, table, obj, 0);
888 if (ret)
889 dev_err(dev, "clear HEM base address failed, ret = %d.\n",
890 ret);
9a443537 891
892 hns_roce_free_hem(hr_dev, table->hem[i]);
893 }
894
9a84848d 895 mutex_destroy(&table->mutex);
9a443537 896 kfree(table->hem);
897}
898
899void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev)
900{
4ddeacf6 901 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
5c1f167a
LO		 902 hns_roce_cleanup_hem_table(hr_dev,
903 &hr_dev->srq_table.table);
9a443537 904 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
0e40dc2f
YL		 905 if (hr_dev->caps.qpc_timer_entry_sz)
906 hns_roce_cleanup_hem_table(hr_dev,
907 &hr_dev->qpc_timer_table);
908 if (hr_dev->caps.cqc_timer_entry_sz)
909 hns_roce_cleanup_hem_table(hr_dev,
910 &hr_dev->cqc_timer_table);
4ddeacf6 911 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
6a157f7d
YL		 912 hns_roce_cleanup_hem_table(hr_dev,
913 &hr_dev->qp_table.sccc_table);
e92f2c18 914 if (hr_dev->caps.trrl_entry_sz)
915 hns_roce_cleanup_hem_table(hr_dev,
916 &hr_dev->qp_table.trrl_table);
d6d91e46
WL		 917
918 if (hr_dev->caps.gmv_entry_sz)
919 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->gmv_table);
920
ae25db00 921 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
9a443537 922 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
923 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
9a443537 924}
38389eaa 925
1f704d8c 926struct hns_roce_hem_item {
38389eaa
LO		 927 struct list_head list; /* link all hems in the same bt level */
928 struct list_head sibling; /* link all hems in last hop for mtt */
929 void *addr;
930 dma_addr_t dma_addr;
931 size_t count; /* max ba numbers */
932 int start; /* start buf offset in this hem */
933 int end; /* end buf offset in this hem */
934};
935
1f704d8c
XW		 936/* All HEM items are linked in a tree structure */
937struct hns_roce_hem_head {
938 struct list_head branch[HNS_ROCE_MAX_BT_REGION];
939 struct list_head root;
940 struct list_head leaf;
941};
942
943static struct hns_roce_hem_item *
944hem_list_alloc_item(struct hns_roce_dev *hr_dev, int start, int end, int count,
be1eeb66 945 bool exist_bt)
38389eaa 946{
1f704d8c 947 struct hns_roce_hem_item *hem;
38389eaa
LO		 948
949 hem = kzalloc(sizeof(*hem), GFP_KERNEL);
950 if (!hem)
951 return NULL;
952
953 if (exist_bt) {
9ea9a53e
XW		 954 hem->addr = dma_alloc_coherent(hr_dev->dev, count * BA_BYTE_LEN,
955 &hem->dma_addr, GFP_KERNEL);
38389eaa
LO		 956 if (!hem->addr) {
957 kfree(hem);
958 return NULL;
959 }
960 }
961
962 hem->count = count;
963 hem->start = start;
964 hem->end = end;
965 INIT_LIST_HEAD(&hem->list);
966 INIT_LIST_HEAD(&hem->sibling);
967
968 return hem;
969}
970
971static void hem_list_free_item(struct hns_roce_dev *hr_dev,
1f704d8c 972 struct hns_roce_hem_item *hem, bool exist_bt)
38389eaa
LO		 973{
974 if (exist_bt)
975 dma_free_coherent(hr_dev->dev, hem->count * BA_BYTE_LEN,
976 hem->addr, hem->dma_addr);
977 kfree(hem);
978}
979
980static void hem_list_free_all(struct hns_roce_dev *hr_dev,
981 struct list_head *head, bool exist_bt)
982{
1f704d8c 983 struct hns_roce_hem_item *hem, *temp_hem;
38389eaa
LO		 984
985 list_for_each_entry_safe(hem, temp_hem, head, list) {
986 list_del(&hem->list);
987 hem_list_free_item(hr_dev, hem, exist_bt);
988 }
989}
990
f4caa864 991static void hem_list_link_bt(void *base_addr, u64 table_addr)
38389eaa
LO		 992{
993 *(u64 *)(base_addr) = table_addr;
994}
995
996/* assign L0 table address to hem from root bt */
f4caa864 997static void hem_list_assign_bt(struct hns_roce_hem_item *hem, void *cpu_addr,
38389eaa
LO		 998 u64 phy_addr)
999{
1000 hem->addr = cpu_addr;
1001 hem->dma_addr = (dma_addr_t)phy_addr;
1002}
1003
1f704d8c 1004static inline bool hem_list_page_is_in_range(struct hns_roce_hem_item *hem,
38389eaa
LO		 1005 int offset)
1006{
1007 return (hem->start <= offset && offset <= hem->end);
1008}
1009
1f704d8c
XW		 1010static struct hns_roce_hem_item *hem_list_search_item(struct list_head *ba_list,
1011 int page_offset)
38389eaa 1012{
1f704d8c
XW		 1013 struct hns_roce_hem_item *hem, *temp_hem;
1014 struct hns_roce_hem_item *found = NULL;
38389eaa
LO		 1015
1016 list_for_each_entry_safe(hem, temp_hem, ba_list, list) {
1017 if (hem_list_page_is_in_range(hem, page_offset)) {
1018 found = hem;
1019 break;
1020 }
1021 }
1022
1023 return found;
1024}
1025
1026static bool hem_list_is_bottom_bt(int hopnum, int bt_level)
1027{
1028 /*
1029 * hopnum base address table levels
1030 * 0 L0(buf)
1031 * 1 L0 -> buf
1032 * 2 L0 -> L1 -> buf
1033 * 3 L0 -> L1 -> L2 -> buf
1034 */
1035 return bt_level >= (hopnum ? hopnum - 1 : hopnum);
1036}
1037
bf194997 1038/*
38389eaa
LO		 1039 * calc base address entries num
1040 * @hopnum: num of mutihop addressing
1041 * @bt_level: base address table level
1042 * @unit: ba entries per bt page
1043 */
1044static u32 hem_list_calc_ba_range(int hopnum, int bt_level, int unit)
1045{
1046 u32 step;
1047 int max;
1048 int i;
1049
1050 if (hopnum <= bt_level)
1051 return 0;
1052 /*
1053 * hopnum bt_level range
1054 * 1 0 unit
1055 * ------------
1056 * 2 0 unit * unit
1057 * 2 1 unit
1058 * ------------
1059 * 3 0 unit * unit * unit
1060 * 3 1 unit * unit
1061 * 3 2 unit
1062 */
1063 step = 1;
1064 max = hopnum - bt_level;
1065 for (i = 0; i < max; i++)
1066 step = step * unit;
1067
1068 return step;
1069}
1070
bf194997 1071/*
38389eaa
LO		 1072 * calc the root ba entries which could cover all regions
1073 * @regions: buf region array
1074 * @region_cnt: array size of @regions
1075 * @unit: ba entries per bt page
1076 */
1077int hns_roce_hem_list_calc_root_ba(const struct hns_roce_buf_region *regions,
1078 int region_cnt, int unit)
1079{
1080 struct hns_roce_buf_region *r;
1081 int total = 0;
1082 int step;
1083 int i;
1084
1085 for (i = 0; i < region_cnt; i++) {
1086 r = (struct hns_roce_buf_region *)&regions[i];
1087 if (r->hopnum > 1) {
1088 step = hem_list_calc_ba_range(r->hopnum, 1, unit);
1089 if (step > 0)
1090 total += (r->count + step - 1) / step;
1091 } else {
1092 total += r->count;
1093 }
1094 }
1095
1096 return total;
1097}
1098
1099static int hem_list_alloc_mid_bt(struct hns_roce_dev *hr_dev,
1100 const struct hns_roce_buf_region *r, int unit,
1101 int offset, struct list_head *mid_bt,
1102 struct list_head *btm_bt)
1103{
1f704d8c 1104 struct hns_roce_hem_item *hem_ptrs[HNS_ROCE_MAX_BT_LEVEL] = { NULL };
38389eaa 1105 struct list_head temp_list[HNS_ROCE_MAX_BT_LEVEL];
1f704d8c 1106 struct hns_roce_hem_item *cur, *pre;
38389eaa
LO		 1107 const int hopnum = r->hopnum;
1108 int start_aligned;
1109 int distance;
1110 int ret = 0;
1111 int max_ofs;
1112 int level;
1113 u32 step;
1114 int end;
1115
1116 if (hopnum <= 1)
1117 return 0;
1118
1119 if (hopnum > HNS_ROCE_MAX_BT_LEVEL) {
1120 dev_err(hr_dev->dev, "invalid hopnum %d!\n", hopnum);
1121 return -EINVAL;
1122 }
1123
1124 if (offset < r->offset) {
61918e9b 1125 dev_err(hr_dev->dev, "invalid offset %d, min %u!\n",
38389eaa
LO		 1126 offset, r->offset);
1127 return -EINVAL;
1128 }
1129
1130 distance = offset - r->offset;
1131 max_ofs = r->offset + r->count - 1;
1132 for (level = 0; level < hopnum; level++)
1133 INIT_LIST_HEAD(&temp_list[level]);
1134
1135 /* config L1 bt to last bt and link them to corresponding parent */
1136 for (level = 1; level < hopnum; level++) {
1137 cur = hem_list_search_item(&mid_bt[level], offset);
1138 if (cur) {
1139 hem_ptrs[level] = cur;
1140 continue;
1141 }
1142
1143 step = hem_list_calc_ba_range(hopnum, level, unit);
1144 if (step < 1) {
1145 ret = -EINVAL;
1146 goto err_exit;
1147 }
1148
1149 start_aligned = (distance / step) * step + r->offset;
1150 end = min_t(int, start_aligned + step - 1, max_ofs);
1151 cur = hem_list_alloc_item(hr_dev, start_aligned, end, unit,
be1eeb66 1152 true);
38389eaa
LO		 1153 if (!cur) {
1154 ret = -ENOMEM;
1155 goto err_exit;
1156 }
1157 hem_ptrs[level] = cur;
1158 list_add(&cur->list, &temp_list[level]);
1159 if (hem_list_is_bottom_bt(hopnum, level))
1160 list_add(&cur->sibling, &temp_list[0]);
1161
1162 /* link bt to parent bt */
1163 if (level > 1) {
1164 pre = hem_ptrs[level - 1];
1165 step = (cur->start - pre->start) / step * BA_BYTE_LEN;
f4caa864 1166 hem_list_link_bt(pre->addr + step, cur->dma_addr);
38389eaa
LO		 1167 }
1168 }
1169
1170 list_splice(&temp_list[0], btm_bt);
1171 for (level = 1; level < hopnum; level++)
1172 list_splice(&temp_list[level], &mid_bt[level]);
1173
1174 return 0;
1175
1176err_exit:
1177 for (level = 1; level < hopnum; level++)
1178 hem_list_free_all(hr_dev, &temp_list[level], true);
1179
1180 return ret;
1181}
1182
1f704d8c
XW		 1183static struct hns_roce_hem_item *
1184alloc_root_hem(struct hns_roce_dev *hr_dev, int unit, int *max_ba_num,
1185 const struct hns_roce_buf_region *regions, int region_cnt)
38389eaa 1186{
38389eaa 1187 const struct hns_roce_buf_region *r;
1f704d8c 1188 struct hns_roce_hem_item *hem;
11334014 1189 int ba_num;
38389eaa 1190 int offset;
38389eaa 1191
11334014
XW		 1192 ba_num = hns_roce_hem_list_calc_root_ba(regions, region_cnt, unit);
1193 if (ba_num < 1)
1f704d8c 1194 return ERR_PTR(-ENOMEM);
11334014 1195
9ea9a53e 1196 if (ba_num > unit)
1f704d8c 1197 return ERR_PTR(-ENOBUFS);
9ea9a53e 1198
1f704d8c 1199 offset = regions[0].offset;
38389eaa
LO		 1200 /* indicate to last region */
1201 r = &regions[region_cnt - 1];
1f704d8c 1202 hem = hem_list_alloc_item(hr_dev, offset, r->offset + r->count - 1,
be1eeb66 1203 ba_num, true);
1f704d8c
XW		 1204 if (!hem)
1205 return ERR_PTR(-ENOMEM);
1206
1207 *max_ba_num = ba_num;
1208
1209 return hem;
1210}
1211
1212static int alloc_fake_root_bt(struct hns_roce_dev *hr_dev, void *cpu_base,
1213 u64 phy_base, const struct hns_roce_buf_region *r,
1214 struct list_head *branch_head,
1215 struct list_head *leaf_head)
1216{
1217 struct hns_roce_hem_item *hem;
1218
1219 hem = hem_list_alloc_item(hr_dev, r->offset, r->offset + r->count - 1,
be1eeb66 1220 r->count, false);
1f704d8c 1221 if (!hem)
38389eaa 1222 return -ENOMEM;
38389eaa 1223
f4caa864 1224 hem_list_assign_bt(hem, cpu_base, phy_base);
1f704d8c
XW		 1225 list_add(&hem->list, branch_head);
1226 list_add(&hem->sibling, leaf_head);
38389eaa 1227
1f704d8c
XW		 1228 return r->count;
1229}
1230
1231static int setup_middle_bt(struct hns_roce_dev *hr_dev, void *cpu_base,
1232 int unit, const struct hns_roce_buf_region *r,
1233 const struct list_head *branch_head)
1234{
1235 struct hns_roce_hem_item *hem, *temp_hem;
1236 int total = 0;
1237 int offset;
1238 int step;
1239
1240 step = hem_list_calc_ba_range(r->hopnum, 1, unit);
1241 if (step < 1)
1242 return -EINVAL;
1243
1244 /* if exist mid bt, link L1 to L0 */
1245 list_for_each_entry_safe(hem, temp_hem, branch_head, list) {
1246 offset = (hem->start - r->offset) / step * BA_BYTE_LEN;
f4caa864 1247 hem_list_link_bt(cpu_base + offset, hem->dma_addr);
1f704d8c
XW		 1248 total++;
1249 }
1250
1251 return total;
1252}
1253
1254static int
1255setup_root_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem_list *hem_list,
1256 int unit, int max_ba_num, struct hns_roce_hem_head *head,
1257 const struct hns_roce_buf_region *regions, int region_cnt)
1258{
1259 const struct hns_roce_buf_region *r;
1260 struct hns_roce_hem_item *root_hem;
1261 void *cpu_base;
1262 u64 phy_base;
1263 int i, total;
1264 int ret;
1265
1266 root_hem = list_first_entry(&head->root,
1267 struct hns_roce_hem_item, list);
1268 if (!root_hem)
1269 return -ENOMEM;
38389eaa
LO		 1270
1271 total = 0;
1f704d8c 1272 for (i = 0; i < region_cnt && total < max_ba_num; i++) {
38389eaa
LO		 1273 r = &regions[i];
1274 if (!r->count)
1275 continue;
1276
1277 /* all regions's mid[x][0] shared the root_bt's trunk */
1278 cpu_base = root_hem->addr + total * BA_BYTE_LEN;
1279 phy_base = root_hem->dma_addr + total * BA_BYTE_LEN;
1280
1281 /* if hopnum is 0 or 1, cut a new fake hem from the root bt
1282 * which's address share to all regions.
1283 */
1f704d8c
XW		 1284 if (hem_list_is_bottom_bt(r->hopnum, 0))
1285 ret = alloc_fake_root_bt(hr_dev, cpu_base, phy_base, r,
1286 &head->branch[i], &head->leaf);
1287 else
1288 ret = setup_middle_bt(hr_dev, cpu_base, unit, r,
1289 &hem_list->mid_bt[i][1]);
1290
1291 if (ret < 0)
1292 return ret;
1293
1294 total += ret;
38389eaa
LO		 1295 }
1296
1f704d8c
XW		 1297 list_splice(&head->leaf, &hem_list->btm_bt);
1298 list_splice(&head->root, &hem_list->root_bt);
38389eaa 1299 for (i = 0; i < region_cnt; i++)
1f704d8c 1300 list_splice(&head->branch[i], &hem_list->mid_bt[i][0]);
38389eaa
LO		 1301
1302 return 0;
1f704d8c 1303}
38389eaa 1304
1f704d8c
XW		 1305static int hem_list_alloc_root_bt(struct hns_roce_dev *hr_dev,
1306 struct hns_roce_hem_list *hem_list, int unit,
1307 const struct hns_roce_buf_region *regions,
1308 int region_cnt)
1309{
1310 struct hns_roce_hem_item *root_hem;
1311 struct hns_roce_hem_head head;
1312 int max_ba_num;
1313 int ret;
1314 int i;
1315
1316 root_hem = hem_list_search_item(&hem_list->root_bt, regions[0].offset);
1317 if (root_hem)
1318 return 0;
1319
1320 max_ba_num = 0;
1321 root_hem = alloc_root_hem(hr_dev, unit, &max_ba_num, regions,
1322 region_cnt);
1323 if (IS_ERR(root_hem))
1324 return PTR_ERR(root_hem);
1325
1326 /* List head for storing all allocated HEM items */
1327 INIT_LIST_HEAD(&head.root);
1328 INIT_LIST_HEAD(&head.leaf);
38389eaa 1329 for (i = 0; i < region_cnt; i++)
1f704d8c 1330 INIT_LIST_HEAD(&head.branch[i]);
38389eaa 1331
1f704d8c
XW		 1332 hem_list->root_ba = root_hem->dma_addr;
1333 list_add(&root_hem->list, &head.root);
1334 ret = setup_root_hem(hr_dev, hem_list, unit, max_ba_num, &head, regions,
1335 region_cnt);
1336 if (ret) {
1337 for (i = 0; i < region_cnt; i++)
1338 hem_list_free_all(hr_dev, &head.branch[i], false);
1339
1340 hem_list_free_all(hr_dev, &head.root, true);
1341 }
38389eaa
LO		 1342
1343 return ret;
1344}
1345
1346/* construct the base address table and link them by address hop config */
1347int hns_roce_hem_list_request(struct hns_roce_dev *hr_dev,
1348 struct hns_roce_hem_list *hem_list,
1349 const struct hns_roce_buf_region *regions,
82d07a4e 1350 int region_cnt, unsigned int bt_pg_shift)
38389eaa
LO		 1351{
1352 const struct hns_roce_buf_region *r;
1353 int ofs, end;
38389eaa 1354 int unit;
dc93a0d9 1355 int ret;
38389eaa
LO		 1356 int i;
1357
1358 if (region_cnt > HNS_ROCE_MAX_BT_REGION) {
1359 dev_err(hr_dev->dev, "invalid region region_cnt %d!\n",
1360 region_cnt);
1361 return -EINVAL;
1362 }
1363
3c873161 1364 unit = (1 << bt_pg_shift) / BA_BYTE_LEN;
38389eaa
LO		 1365 for (i = 0; i < region_cnt; i++) {
1366 r = &regions[i];
1367 if (!r->count)
1368 continue;
1369
1370 end = r->offset + r->count;
1371 for (ofs = r->offset; ofs < end; ofs += unit) {
1372 ret = hem_list_alloc_mid_bt(hr_dev, r, unit, ofs,
1373 hem_list->mid_bt[i],
1374 &hem_list->btm_bt);
1375 if (ret) {
1376 dev_err(hr_dev->dev,
f0588567 1377 "alloc hem trunk fail ret = %d!\n", ret);
38389eaa
LO		 1378 goto err_alloc;
1379 }
1380 }
1381 }
1382
1383 ret = hem_list_alloc_root_bt(hr_dev, hem_list, unit, regions,
1384 region_cnt);
1385 if (ret)
f0588567 1386 dev_err(hr_dev->dev, "alloc hem root fail ret = %d!\n", ret);
38389eaa
LO		 1387 else
1388 return 0;
1389
1390err_alloc:
1391 hns_roce_hem_list_release(hr_dev, hem_list);
1392
1393 return ret;
1394}
1395
1396void hns_roce_hem_list_release(struct hns_roce_dev *hr_dev,
1397 struct hns_roce_hem_list *hem_list)
1398{
1399 int i, j;
1400
1401 for (i = 0; i < HNS_ROCE_MAX_BT_REGION; i++)
1402 for (j = 0; j < HNS_ROCE_MAX_BT_LEVEL; j++)
1403 hem_list_free_all(hr_dev, &hem_list->mid_bt[i][j],
1404 j != 0);
1405
1406 hem_list_free_all(hr_dev, &hem_list->root_bt, true);
1407 INIT_LIST_HEAD(&hem_list->btm_bt);
1408 hem_list->root_ba = 0;
1409}
1410
3c873161 1411void hns_roce_hem_list_init(struct hns_roce_hem_list *hem_list)
38389eaa
LO		 1412{
1413 int i, j;
1414
1415 INIT_LIST_HEAD(&hem_list->root_bt);
1416 INIT_LIST_HEAD(&hem_list->btm_bt);
1417 for (i = 0; i < HNS_ROCE_MAX_BT_REGION; i++)
1418 for (j = 0; j < HNS_ROCE_MAX_BT_LEVEL; j++)
1419 INIT_LIST_HEAD(&hem_list->mid_bt[i][j]);
38389eaa
LO		 1420}
1421
1422void *hns_roce_hem_list_find_mtt(struct hns_roce_dev *hr_dev,
1423 struct hns_roce_hem_list *hem_list,
5f652387 1424 int offset, int *mtt_cnt)
38389eaa
LO		 1425{
1426 struct list_head *head = &hem_list->btm_bt;
1f704d8c 1427 struct hns_roce_hem_item *hem, *temp_hem;
38389eaa 1428 void *cpu_base = NULL;
38389eaa
LO		 1429 int nr = 0;
1430
1431 list_for_each_entry_safe(hem, temp_hem, head, sibling) {
1432 if (hem_list_page_is_in_range(hem, offset)) {
1433 nr = offset - hem->start;
1434 cpu_base = hem->addr + nr * BA_BYTE_LEN;
38389eaa
LO		 1435 nr = hem->end + 1 - offset;
1436 break;
1437 }
1438 }
1439
1440 if (mtt_cnt)
1441 *mtt_cnt = nr;
1442
38389eaa
LO		 1443 return cpu_base;
1444}
Linux 6.x block layer and io_uring tree(s)