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9a443537 | 1 | /* |
2 | * Copyright (c) 2016 Hisilicon Limited. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef _HNS_ROCE_DEVICE_H | |
34 | #define _HNS_ROCE_DEVICE_H | |
35 | ||
36 | #include <rdma/ib_verbs.h> | |
53ef4999 | 37 | #include <rdma/hns-abi.h> |
9a443537 | 38 | |
39 | #define DRV_NAME "hns_roce" | |
40 | ||
a247fd28 | 41 | #define PCI_REVISION_ID_HIP08 0x21 |
247fc16d | 42 | #define PCI_REVISION_ID_HIP09 0x30 |
2a3d923f | 43 | |
8f3e9f3e WHX |
44 | #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') |
45 | ||
9a443537 | 46 | #define HNS_ROCE_MAX_MSG_LEN 0x80000000 |
47 | ||
9a443537 | 48 | #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 |
49 | ||
2a3d923f LO |
50 | #define BA_BYTE_LEN 8 |
51 | ||
9a443537 | 52 | /* Hardware specification only for v1 engine */ |
53 | #define HNS_ROCE_MIN_CQE_NUM 0x40 | |
54 | #define HNS_ROCE_MIN_WQE_NUM 0x20 | |
6ee00fbf | 55 | #define HNS_ROCE_MIN_SRQ_WQE_NUM 1 |
9a443537 | 56 | |
57 | /* Hardware specification only for v1 engine */ | |
58 | #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 | |
59 | #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 | |
60 | ||
afb6b092 SX |
61 | #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 |
62 | #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ | |
63 | (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) | |
64 | #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 | |
65 | #define HNS_ROCE_MIN_CQE_CNT 16 | |
66 | ||
9dd05247 LC |
67 | #define HNS_ROCE_RESERVED_SGE 1 |
68 | ||
b16f8188 | 69 | #define HNS_ROCE_MAX_IRQ_NUM 128 |
9a443537 | 70 | |
2a3d923f LO |
71 | #define HNS_ROCE_SGE_IN_WQE 2 |
72 | #define HNS_ROCE_SGE_SHIFT 4 | |
73 | ||
b16f8188 YL |
74 | #define EQ_ENABLE 1 |
75 | #define EQ_DISABLE 0 | |
9a443537 | 76 | |
b16f8188 YL |
77 | #define HNS_ROCE_CEQ 0 |
78 | #define HNS_ROCE_AEQ 1 | |
79 | ||
247fc16d WL |
80 | #define HNS_ROCE_CEQE_SIZE 0x4 |
81 | #define HNS_ROCE_AEQE_SIZE 0x10 | |
82 | ||
83 | #define HNS_ROCE_V3_EQE_SIZE 0x40 | |
9a443537 | 84 | |
09a5f210 WL |
85 | #define HNS_ROCE_V2_CQE_SIZE 32 |
86 | #define HNS_ROCE_V3_CQE_SIZE 64 | |
87 | ||
98912ee8 WL |
88 | #define HNS_ROCE_V2_QPC_SZ 256 |
89 | #define HNS_ROCE_V3_QPC_SZ 512 | |
90 | ||
9a443537 | 91 | #define HNS_ROCE_MAX_PORTS 6 |
9a443537 | 92 | #define HNS_ROCE_GID_SIZE 16 |
2a3d923f | 93 | #define HNS_ROCE_SGE_SIZE 16 |
01584a5e | 94 | #define HNS_ROCE_DWQE_SIZE 65536 |
9a443537 | 95 | |
a25d13cb SX |
96 | #define HNS_ROCE_HOP_NUM_0 0xff |
97 | ||
9a443537 | 98 | #define MR_TYPE_MR 0x00 |
68a997c5 | 99 | #define MR_TYPE_FRMR 0x01 |
9a443537 | 100 | #define MR_TYPE_DMA 0x03 |
101 | ||
68a997c5 YL |
102 | #define HNS_ROCE_FRMR_MAX_PA 512 |
103 | ||
9a443537 | 104 | #define PKEY_ID 0xffff |
31644665 | 105 | #define GUID_LEN 8 |
9a443537 | 106 | #define NODE_DESC_SIZE 64 |
509bf0c2 | 107 | #define DB_REG_OFFSET 0x1000 |
9a443537 | 108 | |
5e6e78db YL |
109 | /* Configure to HW for PAGE_SIZE larger than 4KB */ |
110 | #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) | |
111 | ||
9a443537 | 112 | #define PAGES_SHIFT_8 8 |
113 | #define PAGES_SHIFT_16 16 | |
114 | #define PAGES_SHIFT_24 24 | |
115 | #define PAGES_SHIFT_32 32 | |
116 | ||
c7bcb134 LO |
117 | #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 |
118 | #define SRQ_DB_REG 0x230 | |
119 | ||
71586dd2 | 120 | #define HNS_ROCE_QP_BANK_NUM 8 |
1bbd4380 YL |
121 | #define HNS_ROCE_CQ_BANK_NUM 4 |
122 | ||
123 | #define CQ_BANKID_SHIFT 2 | |
71586dd2 | 124 | |
90c559b1 LO |
125 | /* The chip implementation of the consumer index is calculated |
126 | * according to twice the actual EQ depth | |
127 | */ | |
128 | #define EQ_DEPTH_COEFF 2 | |
129 | ||
5e049a5d LO |
130 | enum { |
131 | SERV_TYPE_RC, | |
132 | SERV_TYPE_UC, | |
133 | SERV_TYPE_RD, | |
134 | SERV_TYPE_UD, | |
32548870 | 135 | SERV_TYPE_XRC = 5, |
5e049a5d LO |
136 | }; |
137 | ||
9a443537 | 138 | enum hns_roce_qp_state { |
139 | HNS_ROCE_QP_STATE_RST, | |
140 | HNS_ROCE_QP_STATE_INIT, | |
141 | HNS_ROCE_QP_STATE_RTR, | |
142 | HNS_ROCE_QP_STATE_RTS, | |
143 | HNS_ROCE_QP_STATE_SQD, | |
144 | HNS_ROCE_QP_STATE_ERR, | |
145 | HNS_ROCE_QP_NUM_STATE, | |
146 | }; | |
147 | ||
148 | enum hns_roce_event { | |
149 | HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, | |
150 | HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, | |
151 | HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, | |
152 | HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, | |
153 | HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
154 | HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, | |
155 | HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, | |
156 | HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, | |
157 | HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, | |
158 | HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, | |
159 | HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, | |
160 | HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, | |
161 | HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, | |
162 | HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, | |
163 | /* 0x10 and 0x11 is unused in currently application case */ | |
164 | HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, | |
165 | HNS_ROCE_EVENT_TYPE_MB = 0x13, | |
a5073d60 | 166 | HNS_ROCE_EVENT_TYPE_FLR = 0x15, |
32548870 WL |
167 | HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, |
168 | HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, | |
9a443537 | 169 | }; |
170 | ||
30661322 WL |
171 | #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 |
172 | ||
a2c80b7b WHX |
173 | enum { |
174 | HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), | |
023c1477 | 175 | HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), |
e088a685 | 176 | HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), |
cf8cd4cc YL |
177 | HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), |
178 | HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), | |
d16da119 | 179 | HNS_ROCE_CAP_FLAG_SRQ = BIT(5), |
32548870 | 180 | HNS_ROCE_CAP_FLAG_XRC = BIT(6), |
c7c28191 | 181 | HNS_ROCE_CAP_FLAG_MW = BIT(7), |
68a997c5 | 182 | HNS_ROCE_CAP_FLAG_FRMR = BIT(8), |
aa84fa18 | 183 | HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), |
384f8818 | 184 | HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), |
aba457ca | 185 | HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), |
bfefae9f | 186 | HNS_ROCE_CAP_FLAG_STASH = BIT(17), |
a2c80b7b WHX |
187 | }; |
188 | ||
2a3d923f LO |
189 | #define HNS_ROCE_DB_TYPE_COUNT 2 |
190 | #define HNS_ROCE_DB_UNIT_SIZE 4 | |
191 | ||
e088a685 YL |
192 | enum { |
193 | HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 | |
194 | }; | |
195 | ||
d061effc WHX |
196 | enum hns_roce_reset_stage { |
197 | HNS_ROCE_STATE_NON_RST, | |
198 | HNS_ROCE_STATE_RST_BEF_DOWN, | |
199 | HNS_ROCE_STATE_RST_DOWN, | |
200 | HNS_ROCE_STATE_RST_UNINIT, | |
201 | HNS_ROCE_STATE_RST_INIT, | |
202 | HNS_ROCE_STATE_RST_INITED, | |
203 | }; | |
204 | ||
205 | enum hns_roce_instance_state { | |
206 | HNS_ROCE_STATE_NON_INIT, | |
207 | HNS_ROCE_STATE_INIT, | |
208 | HNS_ROCE_STATE_INITED, | |
209 | HNS_ROCE_STATE_UNINIT, | |
210 | }; | |
211 | ||
212 | enum { | |
213 | HNS_ROCE_RST_DIRECT_RETURN = 0, | |
214 | }; | |
215 | ||
9a443537 | 216 | #define HNS_ROCE_CMD_SUCCESS 1 |
217 | ||
9581a356 XW |
218 | /* The minimum page size is 4K for hardware */ |
219 | #define HNS_HW_PAGE_SHIFT 12 | |
220 | #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) | |
9a443537 | 221 | |
222 | struct hns_roce_uar { | |
223 | u64 pfn; | |
224 | unsigned long index; | |
5b6eb54f | 225 | unsigned long logic_idx; |
9a443537 | 226 | }; |
227 | ||
228 | struct hns_roce_ucontext { | |
229 | struct ib_ucontext ibucontext; | |
230 | struct hns_roce_uar uar; | |
e088a685 YL |
231 | struct list_head page_list; |
232 | struct mutex page_mutex; | |
9a443537 | 233 | }; |
234 | ||
235 | struct hns_roce_pd { | |
236 | struct ib_pd ibpd; | |
237 | unsigned long pdn; | |
238 | }; | |
239 | ||
32548870 WL |
240 | struct hns_roce_xrcd { |
241 | struct ib_xrcd ibxrcd; | |
242 | u32 xrcdn; | |
243 | }; | |
244 | ||
9a443537 | 245 | struct hns_roce_bitmap { |
246 | /* Bitmap Traversal last a bit which is 1 */ | |
247 | unsigned long last; | |
248 | unsigned long top; | |
249 | unsigned long max; | |
250 | unsigned long reserved_top; | |
251 | unsigned long mask; | |
252 | spinlock_t lock; | |
253 | unsigned long *table; | |
254 | }; | |
255 | ||
d38936f0 YL |
256 | struct hns_roce_ida { |
257 | struct ida ida; | |
258 | u32 min; /* Lowest ID to allocate. */ | |
259 | u32 max; /* Highest ID to allocate. */ | |
260 | }; | |
261 | ||
9a443537 | 262 | /* For Hardware Entry Memory */ |
263 | struct hns_roce_hem_table { | |
264 | /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ | |
265 | u32 type; | |
266 | /* HEM array elment num */ | |
267 | unsigned long num_hem; | |
6def7de6 | 268 | /* Single obj size */ |
9a443537 | 269 | unsigned long obj_size; |
29a1fe5d | 270 | unsigned long table_chunk_size; |
9a443537 | 271 | int lowmem; |
272 | struct mutex mutex; | |
273 | struct hns_roce_hem **hem; | |
a25d13cb SX |
274 | u64 **bt_l1; |
275 | dma_addr_t *bt_l1_dma_addr; | |
276 | u64 **bt_l0; | |
277 | dma_addr_t *bt_l0_dma_addr; | |
9a443537 | 278 | }; |
279 | ||
38389eaa | 280 | struct hns_roce_buf_region { |
dcdc366a | 281 | u32 offset; /* page offset */ |
6def7de6 | 282 | u32 count; /* page count */ |
38389eaa LO |
283 | int hopnum; /* addressing hop num */ |
284 | }; | |
285 | ||
286 | #define HNS_ROCE_MAX_BT_REGION 3 | |
287 | #define HNS_ROCE_MAX_BT_LEVEL 3 | |
288 | struct hns_roce_hem_list { | |
289 | struct list_head root_bt; | |
290 | /* link all bt dma mem by hop config */ | |
291 | struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; | |
292 | struct list_head btm_bt; /* link all bottom bt in @mid_bt */ | |
293 | dma_addr_t root_ba; /* pointer to the root ba table */ | |
3c873161 XW |
294 | }; |
295 | ||
296 | struct hns_roce_buf_attr { | |
297 | struct { | |
298 | size_t size; /* region size */ | |
299 | int hopnum; /* multi-hop addressing hop num */ | |
300 | } region[HNS_ROCE_MAX_BT_REGION]; | |
dcdc366a | 301 | unsigned int region_count; /* valid region count */ |
82d07a4e | 302 | unsigned int page_shift; /* buffer page shift */ |
dcdc366a | 303 | unsigned int user_access; /* umem access flag */ |
3c873161 | 304 | bool mtt_only; /* only alloc buffer-required MTT memory */ |
38389eaa LO |
305 | }; |
306 | ||
cc33b23e XW |
307 | struct hns_roce_hem_cfg { |
308 | dma_addr_t root_ba; /* root BA table's address */ | |
309 | bool is_direct; /* addressing without BA table */ | |
310 | unsigned int ba_pg_shift; /* BA table page shift */ | |
311 | unsigned int buf_pg_shift; /* buffer page shift */ | |
312 | unsigned int buf_pg_count; /* buffer page count */ | |
313 | struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; | |
dcdc366a | 314 | unsigned int region_count; |
cc33b23e XW |
315 | }; |
316 | ||
38389eaa LO |
317 | /* memory translate region */ |
318 | struct hns_roce_mtr { | |
3c873161 | 319 | struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ |
82d07a4e WL |
320 | struct ib_umem *umem; /* user space buffer */ |
321 | struct hns_roce_buf *kmem; /* kernel space buffer */ | |
cc33b23e | 322 | struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ |
38389eaa LO |
323 | }; |
324 | ||
c7c28191 YL |
325 | struct hns_roce_mw { |
326 | struct ib_mw ibmw; | |
327 | u32 pdn; | |
328 | u32 rkey; | |
329 | int enabled; /* MW's active status */ | |
330 | u32 pbl_hop_num; | |
331 | u32 pbl_ba_pg_sz; | |
332 | u32 pbl_buf_pg_sz; | |
333 | }; | |
334 | ||
9a443537 | 335 | /* Only support 4K page size for mr register */ |
336 | #define MR_SIZE_4K 0 | |
337 | ||
338 | struct hns_roce_mr { | |
339 | struct ib_mr ibmr; | |
9a443537 | 340 | u64 iova; /* MR's virtual orignal addr */ |
341 | u64 size; /* Address range of MR */ | |
342 | u32 key; /* Key of MR */ | |
343 | u32 pd; /* PD num of MR */ | |
6def7de6 | 344 | u32 access; /* Access permission of MR */ |
9a443537 | 345 | int enabled; /* MR's active status */ |
346 | int type; /* MR's register type */ | |
6def7de6 | 347 | u32 pbl_hop_num; /* multi-hop number */ |
9b2cf76c XW |
348 | struct hns_roce_mtr pbl_mtr; |
349 | u32 npages; | |
350 | dma_addr_t *page_list; | |
9a443537 | 351 | }; |
352 | ||
353 | struct hns_roce_mr_table { | |
d38936f0 | 354 | struct hns_roce_ida mtpt_ida; |
9a443537 | 355 | struct hns_roce_hem_table mtpt_table; |
356 | }; | |
357 | ||
358 | struct hns_roce_wq { | |
359 | u64 *wrid; /* Work request ID */ | |
360 | spinlock_t lock; | |
47688202 | 361 | u32 wqe_cnt; /* WQE num */ |
dcdc366a | 362 | u32 max_gs; |
9dd05247 | 363 | u32 rsv_sge; |
9a443537 | 364 | int offset; |
6def7de6 | 365 | int wqe_shift; /* WQE size */ |
9a443537 | 366 | u32 head; |
367 | u32 tail; | |
704d68f5 | 368 | void __iomem *db_reg; |
9a443537 | 369 | }; |
370 | ||
926a01dc | 371 | struct hns_roce_sge { |
13aa13dd | 372 | unsigned int sge_cnt; /* SGE num */ |
926a01dc | 373 | int offset; |
6def7de6 | 374 | int sge_shift; /* SGE size */ |
926a01dc WHX |
375 | }; |
376 | ||
9a443537 | 377 | struct hns_roce_buf_list { |
378 | void *buf; | |
379 | dma_addr_t map; | |
380 | }; | |
381 | ||
6f6e2dcb XW |
382 | /* |
383 | * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous | |
384 | * dma address range. | |
385 | * | |
386 | * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. | |
387 | * | |
388 | * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even | |
389 | * the allocated size is smaller than the required size. | |
390 | */ | |
391 | enum { | |
392 | HNS_ROCE_BUF_DIRECT = BIT(0), | |
393 | HNS_ROCE_BUF_NOSLEEP = BIT(1), | |
394 | HNS_ROCE_BUF_NOFAIL = BIT(2), | |
395 | }; | |
396 | ||
9a443537 | 397 | struct hns_roce_buf { |
6f6e2dcb XW |
398 | struct hns_roce_buf_list *trunk_list; |
399 | u32 ntrunks; | |
9a443537 | 400 | u32 npages; |
6f6e2dcb | 401 | unsigned int trunk_shift; |
82d07a4e | 402 | unsigned int page_shift; |
9a443537 | 403 | }; |
404 | ||
e088a685 YL |
405 | struct hns_roce_db_pgdir { |
406 | struct list_head list; | |
407 | DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); | |
2a3d923f LO |
408 | DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); |
409 | unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; | |
e088a685 YL |
410 | u32 *page; |
411 | dma_addr_t db_dma; | |
412 | }; | |
413 | ||
414 | struct hns_roce_user_db_page { | |
415 | struct list_head list; | |
416 | struct ib_umem *umem; | |
417 | unsigned long user_virt; | |
418 | refcount_t refcount; | |
419 | }; | |
420 | ||
421 | struct hns_roce_db { | |
422 | u32 *db_record; | |
423 | union { | |
424 | struct hns_roce_db_pgdir *pgdir; | |
425 | struct hns_roce_user_db_page *user_page; | |
426 | } u; | |
427 | dma_addr_t dma; | |
0425e3e6 | 428 | void *virt_addr; |
dcdc366a WL |
429 | unsigned long index; |
430 | unsigned long order; | |
e088a685 YL |
431 | }; |
432 | ||
9a443537 | 433 | struct hns_roce_cq { |
434 | struct ib_cq ib_cq; | |
744b7bdf | 435 | struct hns_roce_mtr mtr; |
9b44703d | 436 | struct hns_roce_db db; |
05e6a5a6 | 437 | u32 flags; |
9a443537 | 438 | spinlock_t lock; |
9a443537 | 439 | u32 cq_depth; |
440 | u32 cons_index; | |
86188a88 | 441 | u32 *set_ci_db; |
704d68f5 | 442 | void __iomem *db_reg; |
8f3e9f3e | 443 | u16 *tptr_addr; |
26beb85f | 444 | int arm_sn; |
09a5f210 | 445 | int cqe_size; |
9a443537 | 446 | unsigned long cqn; |
447 | u32 vector; | |
cc9e5a84 | 448 | refcount_t refcount; |
9a443537 | 449 | struct completion free; |
626903e9 XW |
450 | struct list_head sq_list; /* all qps on this send cq */ |
451 | struct list_head rq_list; /* all qps on this recv cq */ | |
452 | int is_armed; /* cq is armed */ | |
453 | struct list_head node; /* all armed cqs are on a list */ | |
9a443537 | 454 | }; |
455 | ||
c7bcb134 | 456 | struct hns_roce_idx_que { |
6fd610c5 | 457 | struct hns_roce_mtr mtr; |
67954a6e | 458 | int entry_shift; |
97545b10 | 459 | unsigned long *bitmap; |
1620f09b WL |
460 | u32 head; |
461 | u32 tail; | |
c7bcb134 LO |
462 | }; |
463 | ||
9a443537 | 464 | struct hns_roce_srq { |
465 | struct ib_srq ibsrq; | |
c7bcb134 | 466 | unsigned long srqn; |
d938d785 | 467 | u32 wqe_cnt; |
c7bcb134 | 468 | int max_gs; |
9dd05247 | 469 | u32 rsv_sge; |
c7bcb134 | 470 | int wqe_shift; |
0fee4516 | 471 | u32 cqn; |
32548870 | 472 | u32 xrcdn; |
704d68f5 | 473 | void __iomem *db_reg; |
c7bcb134 | 474 | |
33649cd3 | 475 | refcount_t refcount; |
c7bcb134 LO |
476 | struct completion free; |
477 | ||
6fd610c5 XW |
478 | struct hns_roce_mtr buf_mtr; |
479 | ||
c7bcb134 | 480 | u64 *wrid; |
c7bcb134 LO |
481 | struct hns_roce_idx_que idx_que; |
482 | spinlock_t lock; | |
c7bcb134 | 483 | struct mutex mutex; |
d938d785 | 484 | void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); |
9a443537 | 485 | }; |
486 | ||
487 | struct hns_roce_uar_table { | |
488 | struct hns_roce_bitmap bitmap; | |
489 | }; | |
490 | ||
71586dd2 YL |
491 | struct hns_roce_bank { |
492 | struct ida ida; | |
493 | u32 inuse; /* Number of IDs allocated */ | |
494 | u32 min; /* Lowest ID to allocate. */ | |
495 | u32 max; /* Highest ID to allocate. */ | |
496 | u32 next; /* Next ID to allocate. */ | |
497 | }; | |
498 | ||
9a443537 | 499 | struct hns_roce_qp_table { |
9a443537 | 500 | struct hns_roce_hem_table qp_table; |
501 | struct hns_roce_hem_table irrl_table; | |
e92f2c18 | 502 | struct hns_roce_hem_table trrl_table; |
6a157f7d | 503 | struct hns_roce_hem_table sccc_table; |
aa84fa18 | 504 | struct mutex scc_mutex; |
71586dd2 | 505 | struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; |
9293d3fc | 506 | struct mutex bank_mutex; |
9a443537 | 507 | }; |
508 | ||
509 | struct hns_roce_cq_table { | |
27e19f45 | 510 | struct xarray array; |
9a443537 | 511 | struct hns_roce_hem_table table; |
1bbd4380 YL |
512 | struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; |
513 | struct mutex bank_mutex; | |
9a443537 | 514 | }; |
515 | ||
5c1f167a LO |
516 | struct hns_roce_srq_table { |
517 | struct hns_roce_bitmap bitmap; | |
518 | struct xarray xa; | |
519 | struct hns_roce_hem_table table; | |
520 | }; | |
521 | ||
9a443537 | 522 | struct hns_roce_raq_table { |
523 | struct hns_roce_buf_list *e_raq_buf; | |
524 | }; | |
525 | ||
526 | struct hns_roce_av { | |
074bf2c2 WL |
527 | u8 port; |
528 | u8 gid_index; | |
529 | u8 stat_rate; | |
530 | u8 hop_limit; | |
531 | u32 flowlabel; | |
532 | u16 udp_sport; | |
533 | u8 sl; | |
534 | u8 tclass; | |
535 | u8 dgid[HNS_ROCE_GID_SIZE]; | |
536 | u8 mac[ETH_ALEN]; | |
537 | u16 vlan_id; | |
7406c003 | 538 | u8 vlan_en; |
9a443537 | 539 | }; |
540 | ||
541 | struct hns_roce_ah { | |
542 | struct ib_ah ibah; | |
543 | struct hns_roce_av av; | |
544 | }; | |
545 | ||
546 | struct hns_roce_cmd_context { | |
547 | struct completion done; | |
548 | int result; | |
549 | int next; | |
550 | u64 out_param; | |
551 | u16 token; | |
a389d016 | 552 | u16 busy; |
9a443537 | 553 | }; |
554 | ||
555 | struct hns_roce_cmdq { | |
556 | struct dma_pool *pool; | |
9a443537 | 557 | struct semaphore poll_sem; |
558 | /* | |
e84e40be S |
559 | * Event mode: cmd register mutex protection, |
560 | * ensure to not exceed max_cmds and user use limit region | |
561 | */ | |
9a443537 | 562 | struct semaphore event_sem; |
563 | int max_cmds; | |
564 | spinlock_t context_lock; | |
565 | int free_head; | |
566 | struct hns_roce_cmd_context *context; | |
9a443537 | 567 | /* |
e84e40be S |
568 | * Process whether use event mode, init default non-zero |
569 | * After the event queue of cmd event ready, | |
570 | * can switch into event mode | |
571 | * close device, switch into poll mode(non event mode) | |
572 | */ | |
9a443537 | 573 | u8 use_events; |
9a443537 | 574 | }; |
575 | ||
bfcc681b SX |
576 | struct hns_roce_cmd_mailbox { |
577 | void *buf; | |
578 | dma_addr_t dma; | |
579 | }; | |
580 | ||
9a443537 | 581 | struct hns_roce_dev; |
582 | ||
0009c2db | 583 | struct hns_roce_rinl_sge { |
584 | void *addr; | |
585 | u32 len; | |
586 | }; | |
587 | ||
588 | struct hns_roce_rinl_wqe { | |
589 | struct hns_roce_rinl_sge *sg_list; | |
590 | u32 sge_cnt; | |
591 | }; | |
592 | ||
593 | struct hns_roce_rinl_buf { | |
594 | struct hns_roce_rinl_wqe *wqe_list; | |
595 | u32 wqe_cnt; | |
596 | }; | |
597 | ||
b5374286 YL |
598 | enum { |
599 | HNS_ROCE_FLUSH_FLAG = 0, | |
600 | }; | |
601 | ||
ffd541d4 YL |
602 | struct hns_roce_work { |
603 | struct hns_roce_dev *hr_dev; | |
604 | struct work_struct work; | |
ffd541d4 YL |
605 | int event_type; |
606 | int sub_type; | |
d8cc403b | 607 | u32 queue_num; |
ffd541d4 YL |
608 | }; |
609 | ||
01584a5e YL |
610 | enum { |
611 | HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5), | |
612 | }; | |
613 | ||
9a443537 | 614 | struct hns_roce_qp { |
615 | struct ib_qp ibqp; | |
9a443537 | 616 | struct hns_roce_wq rq; |
e088a685 | 617 | struct hns_roce_db rdb; |
0425e3e6 | 618 | struct hns_roce_db sdb; |
90ae0b57 | 619 | unsigned long en_flags; |
8b9b8d14 | 620 | u32 doorbell_qpn; |
ea4092f3 | 621 | enum ib_sig_type sq_signal_bits; |
9a443537 | 622 | struct hns_roce_wq sq; |
623 | ||
8d18ad83 | 624 | struct hns_roce_mtr mtr; |
8d18ad83 | 625 | |
9a443537 | 626 | u32 buff_size; |
627 | struct mutex mutex; | |
628 | u8 port; | |
7716809e | 629 | u8 phy_port; |
9a443537 | 630 | u8 sl; |
631 | u8 resp_depth; | |
632 | u8 state; | |
633 | u32 access_flags; | |
ace1c541 | 634 | u32 atomic_rd_en; |
9a443537 | 635 | u32 pkey_index; |
0fa95a9a | 636 | u32 qkey; |
fd012f1c | 637 | void (*event)(struct hns_roce_qp *qp, |
638 | enum hns_roce_event event_type); | |
9a443537 | 639 | unsigned long qpn; |
640 | ||
32548870 WL |
641 | u32 xrcdn; |
642 | ||
8f9513d8 | 643 | refcount_t refcount; |
9a443537 | 644 | struct completion free; |
926a01dc WHX |
645 | |
646 | struct hns_roce_sge sge; | |
647 | u32 next_sge; | |
30b70788 WL |
648 | enum ib_mtu path_mtu; |
649 | u32 max_inline_data; | |
0009c2db | 650 | |
b5374286 YL |
651 | /* 0: flush needed, 1: unneeded */ |
652 | unsigned long flush_flag; | |
ffd541d4 | 653 | struct hns_roce_work flush_work; |
0009c2db | 654 | struct hns_roce_rinl_buf rq_inl_buf; |
626903e9 XW |
655 | struct list_head node; /* all qps are on a list */ |
656 | struct list_head rq_node; /* all recv qps are on a list */ | |
657 | struct list_head sq_node; /* all send qps are on a list */ | |
9a443537 | 658 | }; |
659 | ||
9a443537 | 660 | struct hns_roce_ib_iboe { |
661 | spinlock_t lock; | |
662 | struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; | |
663 | struct notifier_block nb; | |
9a443537 | 664 | u8 phy_port[HNS_ROCE_MAX_PORTS]; |
665 | }; | |
666 | ||
b16f8188 YL |
667 | enum { |
668 | HNS_ROCE_EQ_STAT_INVALID = 0, | |
669 | HNS_ROCE_EQ_STAT_VALID = 2, | |
670 | }; | |
671 | ||
672 | struct hns_roce_ceqe { | |
247fc16d WL |
673 | __le32 comp; |
674 | __le32 rsv[15]; | |
b16f8188 YL |
675 | }; |
676 | ||
677 | struct hns_roce_aeqe { | |
0576cbde | 678 | __le32 asyn; |
b16f8188 YL |
679 | union { |
680 | struct { | |
d8cc403b | 681 | __le32 num; |
b16f8188 YL |
682 | u32 rsv0; |
683 | u32 rsv1; | |
d8cc403b | 684 | } queue_event; |
b16f8188 YL |
685 | |
686 | struct { | |
687 | __le64 out_param; | |
688 | __le16 token; | |
689 | u8 status; | |
690 | u8 rsv0; | |
691 | } __packed cmd; | |
692 | } event; | |
247fc16d | 693 | __le32 rsv[12]; |
b16f8188 YL |
694 | }; |
695 | ||
9a443537 | 696 | struct hns_roce_eq { |
697 | struct hns_roce_dev *hr_dev; | |
704d68f5 | 698 | void __iomem *db_reg; |
9a443537 | 699 | |
6def7de6 | 700 | int type_flag; /* Aeq:1 ceq:0 */ |
9a443537 | 701 | int eqn; |
702 | u32 entries; | |
dcdc366a | 703 | u32 log_entries; |
9a443537 | 704 | int eqe_size; |
705 | int irq; | |
706 | int log_page_size; | |
dcdc366a | 707 | u32 cons_index; |
9a443537 | 708 | struct hns_roce_buf_list *buf_list; |
a5073d60 YL |
709 | int over_ignore; |
710 | int coalesce; | |
711 | int arm_st; | |
a5073d60 | 712 | int hop_num; |
d7e2d343 | 713 | struct hns_roce_mtr mtr; |
13aa13dd | 714 | u16 eq_max_cnt; |
dcdc366a | 715 | u32 eq_period; |
a5073d60 | 716 | int shift; |
0425e3e6 YL |
717 | int event_type; |
718 | int sub_type; | |
9a443537 | 719 | }; |
720 | ||
721 | struct hns_roce_eq_table { | |
722 | struct hns_roce_eq *eq; | |
b16f8188 | 723 | void __iomem **eqc_base; /* only for hw v1 */ |
9a443537 | 724 | }; |
725 | ||
f91696f2 YL |
726 | enum cong_type { |
727 | CONG_TYPE_DCQCN, | |
728 | CONG_TYPE_LDCP, | |
729 | CONG_TYPE_HC3, | |
730 | CONG_TYPE_DIP, | |
731 | }; | |
732 | ||
9a443537 | 733 | struct hns_roce_caps { |
3a63c964 | 734 | u64 fw_ver; |
9a443537 | 735 | u8 num_ports; |
736 | int gid_table_len[HNS_ROCE_MAX_PORTS]; | |
737 | int pkey_table_len[HNS_ROCE_MAX_PORTS]; | |
738 | int local_ca_ack_delay; | |
739 | int num_uars; | |
740 | u32 phy_num_uars; | |
6def7de6 LC |
741 | u32 max_sq_sg; |
742 | u32 max_sq_inline; | |
743 | u32 max_rq_sg; | |
05ad5482 | 744 | u32 max_extend_sg; |
dcdc366a | 745 | u32 num_qps; |
61b460d1 | 746 | u32 num_pi_qps; |
dcdc366a | 747 | u32 reserved_qps; |
0e40dc2f YL |
748 | int num_qpc_timer; |
749 | int num_cqc_timer; | |
5c1f167a | 750 | int num_srqs; |
6def7de6 | 751 | u32 max_wqes; |
d16da119 LO |
752 | u32 max_srq_wrs; |
753 | u32 max_srq_sges; | |
6def7de6 LC |
754 | u32 max_sq_desc_sz; |
755 | u32 max_rq_desc_sz; | |
cfc85f3e | 756 | u32 max_srq_desc_sz; |
9a443537 | 757 | int max_qp_init_rdma; |
758 | int max_qp_dest_rdma; | |
dcdc366a | 759 | u32 num_cqs; |
e2b2744a YL |
760 | u32 max_cqes; |
761 | u32 min_cqes; | |
926a01dc | 762 | u32 min_wqes; |
1bbd4380 | 763 | u32 reserved_cqs; |
5c1f167a | 764 | int reserved_srqs; |
6def7de6 | 765 | int num_aeq_vectors; |
a5073d60 | 766 | int num_comp_vectors; |
9a443537 | 767 | int num_other_vectors; |
dcdc366a | 768 | u32 num_mtpts; |
9a443537 | 769 | u32 num_mtt_segs; |
5c1f167a LO |
770 | u32 num_srqwqe_segs; |
771 | u32 num_idx_segs; | |
9a443537 | 772 | int reserved_mrws; |
773 | int reserved_uars; | |
774 | int num_pds; | |
775 | int reserved_pds; | |
32548870 WL |
776 | u32 num_xrcds; |
777 | u32 reserved_xrcds; | |
9a443537 | 778 | u32 mtt_entry_sz; |
09a5f210 | 779 | u32 cqe_sz; |
9a443537 | 780 | u32 page_size_cap; |
781 | u32 reserved_lkey; | |
782 | int mtpt_entry_sz; | |
98912ee8 | 783 | int qpc_sz; |
9a443537 | 784 | int irrl_entry_sz; |
e92f2c18 | 785 | int trrl_entry_sz; |
9a443537 | 786 | int cqc_entry_sz; |
3cb2c996 | 787 | int sccc_sz; |
0e40dc2f YL |
788 | int qpc_timer_entry_sz; |
789 | int cqc_timer_entry_sz; | |
5c1f167a LO |
790 | int srqc_entry_sz; |
791 | int idx_entry_sz; | |
ff795f71 WHX |
792 | u32 pbl_ba_pg_sz; |
793 | u32 pbl_buf_pg_sz; | |
794 | u32 pbl_hop_num; | |
9a443537 | 795 | int aeqe_depth; |
b16f8188 | 796 | int ceqe_depth; |
247fc16d WL |
797 | u32 aeqe_size; |
798 | u32 ceqe_size; | |
9a443537 | 799 | enum ib_mtu max_mtu; |
cfc85f3e | 800 | u32 qpc_bt_num; |
0e40dc2f | 801 | u32 qpc_timer_bt_num; |
cfc85f3e WHX |
802 | u32 srqc_bt_num; |
803 | u32 cqc_bt_num; | |
0e40dc2f | 804 | u32 cqc_timer_bt_num; |
cfc85f3e | 805 | u32 mpt_bt_num; |
2a424e1d WX |
806 | u32 eqc_bt_num; |
807 | u32 smac_bt_num; | |
808 | u32 sgid_bt_num; | |
6a157f7d | 809 | u32 sccc_bt_num; |
d6d91e46 | 810 | u32 gmv_bt_num; |
a25d13cb SX |
811 | u32 qpc_ba_pg_sz; |
812 | u32 qpc_buf_pg_sz; | |
813 | u32 qpc_hop_num; | |
814 | u32 srqc_ba_pg_sz; | |
815 | u32 srqc_buf_pg_sz; | |
816 | u32 srqc_hop_num; | |
817 | u32 cqc_ba_pg_sz; | |
818 | u32 cqc_buf_pg_sz; | |
819 | u32 cqc_hop_num; | |
820 | u32 mpt_ba_pg_sz; | |
821 | u32 mpt_buf_pg_sz; | |
822 | u32 mpt_hop_num; | |
6a93c77a SX |
823 | u32 mtt_ba_pg_sz; |
824 | u32 mtt_buf_pg_sz; | |
825 | u32 mtt_hop_num; | |
8d18ad83 LO |
826 | u32 wqe_sq_hop_num; |
827 | u32 wqe_sge_hop_num; | |
828 | u32 wqe_rq_hop_num; | |
6a157f7d YL |
829 | u32 sccc_ba_pg_sz; |
830 | u32 sccc_buf_pg_sz; | |
831 | u32 sccc_hop_num; | |
0e40dc2f YL |
832 | u32 qpc_timer_ba_pg_sz; |
833 | u32 qpc_timer_buf_pg_sz; | |
834 | u32 qpc_timer_hop_num; | |
835 | u32 cqc_timer_ba_pg_sz; | |
836 | u32 cqc_timer_buf_pg_sz; | |
837 | u32 cqc_timer_hop_num; | |
b14c95be | 838 | u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ |
6a93c77a SX |
839 | u32 cqe_buf_pg_sz; |
840 | u32 cqe_hop_num; | |
c7bcb134 LO |
841 | u32 srqwqe_ba_pg_sz; |
842 | u32 srqwqe_buf_pg_sz; | |
843 | u32 srqwqe_hop_num; | |
844 | u32 idx_ba_pg_sz; | |
845 | u32 idx_buf_pg_sz; | |
846 | u32 idx_hop_num; | |
a5073d60 YL |
847 | u32 eqe_ba_pg_sz; |
848 | u32 eqe_buf_pg_sz; | |
849 | u32 eqe_hop_num; | |
d6d91e46 WL |
850 | u32 gmv_entry_num; |
851 | u32 gmv_entry_sz; | |
852 | u32 gmv_ba_pg_sz; | |
853 | u32 gmv_buf_pg_sz; | |
854 | u32 gmv_hop_num; | |
6b63597d | 855 | u32 sl_num; |
b6989da8 | 856 | u32 llm_buf_pg_sz; |
6def7de6 | 857 | u32 chunk_sz; /* chunk size in non multihop mode */ |
a2c80b7b | 858 | u64 flags; |
ba6bb7e9 LO |
859 | u16 default_ceq_max_cnt; |
860 | u16 default_ceq_period; | |
861 | u16 default_aeq_max_cnt; | |
862 | u16 default_aeq_period; | |
863 | u16 default_aeq_arm_st; | |
864 | u16 default_ceq_arm_st; | |
f91696f2 | 865 | enum cong_type cong_type; |
9a443537 | 866 | }; |
867 | ||
e1c9a0dc LO |
868 | struct hns_roce_dfx_hw { |
869 | int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, | |
870 | int *buffer); | |
871 | }; | |
872 | ||
626903e9 XW |
873 | enum hns_roce_device_state { |
874 | HNS_ROCE_DEVICE_STATE_INITED, | |
875 | HNS_ROCE_DEVICE_STATE_RST_DOWN, | |
876 | HNS_ROCE_DEVICE_STATE_UNINIT, | |
877 | }; | |
878 | ||
9a443537 | 879 | struct hns_roce_hw { |
880 | int (*reset)(struct hns_roce_dev *hr_dev, bool enable); | |
a04ff739 WHX |
881 | int (*cmq_init)(struct hns_roce_dev *hr_dev); |
882 | void (*cmq_exit)(struct hns_roce_dev *hr_dev); | |
cfc85f3e | 883 | int (*hw_profile)(struct hns_roce_dev *hr_dev); |
9a443537 | 884 | int (*hw_init)(struct hns_roce_dev *hr_dev); |
885 | void (*hw_exit)(struct hns_roce_dev *hr_dev); | |
a680f2f3 WHX |
886 | int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, |
887 | u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, | |
888 | u16 token, int event); | |
ee82e688 XW |
889 | int (*poll_mbox_done)(struct hns_roce_dev *hr_dev, |
890 | unsigned int timeout); | |
891 | bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); | |
1fb7f897 | 892 | int (*set_gid)(struct hns_roce_dev *hr_dev, u32 port, int gid_index, |
f4df9a7c | 893 | const union ib_gid *gid, const struct ib_gid_attr *attr); |
a74dc41d | 894 | int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); |
9a443537 | 895 | void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, |
896 | enum ib_mtu mtu); | |
98a61519 YL |
897 | int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, |
898 | struct hns_roce_mr *mr, unsigned long mtpt_idx); | |
a2c80b7b | 899 | int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, |
4e9fc1da | 900 | struct hns_roce_mr *mr, int flags, |
a2c80b7b | 901 | void *mb_buf); |
98a61519 YL |
902 | int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, |
903 | struct hns_roce_mr *mr); | |
c7c28191 | 904 | int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); |
9a443537 | 905 | void (*write_cqc)(struct hns_roce_dev *hr_dev, |
906 | struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, | |
e2b2744a | 907 | dma_addr_t dma_handle); |
a25d13cb SX |
908 | int (*set_hem)(struct hns_roce_dev *hr_dev, |
909 | struct hns_roce_hem_table *table, int obj, int step_idx); | |
97f0e39f | 910 | int (*clear_hem)(struct hns_roce_dev *hr_dev, |
a25d13cb SX |
911 | struct hns_roce_hem_table *table, int obj, |
912 | int step_idx); | |
9a443537 | 913 | int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, |
914 | int attr_mask, enum ib_qp_state cur_state, | |
915 | enum ib_qp_state new_state); | |
aa84fa18 YL |
916 | int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, |
917 | struct hns_roce_qp *hr_qp); | |
c4367a26 SR |
918 | int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, |
919 | struct ib_udata *udata); | |
43d781b9 | 920 | int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); |
b16f8188 YL |
921 | int (*init_eq)(struct hns_roce_dev *hr_dev); |
922 | void (*cleanup_eq)(struct hns_roce_dev *hr_dev); | |
eacb45ca | 923 | int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); |
7f645a58 KH |
924 | const struct ib_device_ops *hns_roce_dev_ops; |
925 | const struct ib_device_ops *hns_roce_dev_srq_ops; | |
9a443537 | 926 | }; |
927 | ||
928 | struct hns_roce_dev { | |
929 | struct ib_device ib_dev; | |
930 | struct platform_device *pdev; | |
dd74282d WHX |
931 | struct pci_dev *pci_dev; |
932 | struct device *dev; | |
9a443537 | 933 | struct hns_roce_uar priv_uar; |
528f1deb | 934 | const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; |
9a443537 | 935 | spinlock_t sm_lock; |
9a443537 | 936 | spinlock_t bt_cmd_lock; |
cb7a94c9 WHX |
937 | bool active; |
938 | bool is_reset; | |
d3743fa9 | 939 | bool dis_db; |
d061effc | 940 | unsigned long reset_cnt; |
9a443537 | 941 | struct hns_roce_ib_iboe iboe; |
626903e9 XW |
942 | enum hns_roce_device_state state; |
943 | struct list_head qp_list; /* list of all qps on this dev */ | |
944 | spinlock_t qp_list_lock; /* protect qp_list */ | |
f91696f2 YL |
945 | struct list_head dip_list; /* list of all dest ips on this dev */ |
946 | spinlock_t dip_list_lock; /* protect dip_list */ | |
9a443537 | 947 | |
472bc0fb YL |
948 | struct list_head pgdir_list; |
949 | struct mutex pgdir_mutex; | |
9a443537 | 950 | int irq[HNS_ROCE_MAX_IRQ_NUM]; |
951 | u8 __iomem *reg_base; | |
01584a5e | 952 | void __iomem *mem_base; |
9a443537 | 953 | struct hns_roce_caps caps; |
736b5a70 | 954 | struct xarray qp_table_xa; |
9a443537 | 955 | |
2a3d923f | 956 | unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; |
9a443537 | 957 | u64 sys_image_guid; |
958 | u32 vendor_id; | |
959 | u32 vendor_part_id; | |
960 | u32 hw_rev; | |
961 | void __iomem *priv_addr; | |
962 | ||
963 | struct hns_roce_cmdq cmd; | |
645f0593 | 964 | struct hns_roce_ida pd_ida; |
da43b7be | 965 | struct hns_roce_ida xrcd_ida; |
9a443537 | 966 | struct hns_roce_uar_table uar_table; |
967 | struct hns_roce_mr_table mr_table; | |
968 | struct hns_roce_cq_table cq_table; | |
5c1f167a | 969 | struct hns_roce_srq_table srq_table; |
9a443537 | 970 | struct hns_roce_qp_table qp_table; |
971 | struct hns_roce_eq_table eq_table; | |
0e40dc2f YL |
972 | struct hns_roce_hem_table qpc_timer_table; |
973 | struct hns_roce_hem_table cqc_timer_table; | |
d6d91e46 WL |
974 | /* GMV is the memory area that the driver allocates for the hardware |
975 | * to store SGID, SMAC and VLAN information. | |
976 | */ | |
977 | struct hns_roce_hem_table gmv_table; | |
9a443537 | 978 | |
979 | int cmd_mod; | |
980 | int loop_idc; | |
2d407888 WHX |
981 | u32 sdb_offset; |
982 | u32 odb_offset; | |
6def7de6 LC |
983 | dma_addr_t tptr_dma_addr; /* only for hw v1 */ |
984 | u32 tptr_size; /* only for hw v1 */ | |
08805fdb | 985 | const struct hns_roce_hw *hw; |
016a0059 | 986 | void *priv; |
0425e3e6 | 987 | struct workqueue_struct *irq_workq; |
e1c9a0dc | 988 | const struct hns_roce_dfx_hw *dfx; |
5b03a422 | 989 | u32 func_num; |
0b567cde | 990 | u32 is_vf; |
e079d87d | 991 | u32 cong_algo_tmpl_id; |
9a443537 | 992 | }; |
993 | ||
994 | static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) | |
995 | { | |
996 | return container_of(ib_dev, struct hns_roce_dev, ib_dev); | |
997 | } | |
998 | ||
999 | static inline struct hns_roce_ucontext | |
1000 | *to_hr_ucontext(struct ib_ucontext *ibucontext) | |
1001 | { | |
1002 | return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); | |
1003 | } | |
1004 | ||
1005 | static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) | |
1006 | { | |
1007 | return container_of(ibpd, struct hns_roce_pd, ibpd); | |
1008 | } | |
1009 | ||
32548870 WL |
1010 | static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) |
1011 | { | |
1012 | return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); | |
1013 | } | |
1014 | ||
9a443537 | 1015 | static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) |
1016 | { | |
1017 | return container_of(ibah, struct hns_roce_ah, ibah); | |
1018 | } | |
1019 | ||
1020 | static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) | |
1021 | { | |
1022 | return container_of(ibmr, struct hns_roce_mr, ibmr); | |
1023 | } | |
1024 | ||
c7c28191 YL |
1025 | static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) |
1026 | { | |
1027 | return container_of(ibmw, struct hns_roce_mw, ibmw); | |
1028 | } | |
1029 | ||
9a443537 | 1030 | static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) |
1031 | { | |
1032 | return container_of(ibqp, struct hns_roce_qp, ibqp); | |
1033 | } | |
1034 | ||
1035 | static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) | |
1036 | { | |
1037 | return container_of(ib_cq, struct hns_roce_cq, ib_cq); | |
1038 | } | |
1039 | ||
1040 | static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) | |
1041 | { | |
1042 | return container_of(ibsrq, struct hns_roce_srq, ibsrq); | |
1043 | } | |
1044 | ||
0576cbde | 1045 | static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) |
9a443537 | 1046 | { |
86f767e6 | 1047 | writeq(*(u64 *)val, dest); |
9a443537 | 1048 | } |
1049 | ||
1050 | static inline struct hns_roce_qp | |
1051 | *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) | |
1052 | { | |
61b460d1 | 1053 | return xa_load(&hr_dev->qp_table_xa, qpn); |
9a443537 | 1054 | } |
1055 | ||
dcdc366a WL |
1056 | static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, |
1057 | unsigned int offset) | |
9a443537 | 1058 | { |
6f6e2dcb XW |
1059 | return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + |
1060 | (offset & ((1 << buf->trunk_shift) - 1)); | |
cc23267a XW |
1061 | } |
1062 | ||
7b0006db XW |
1063 | static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf, |
1064 | unsigned int offset) | |
cc23267a | 1065 | { |
6f6e2dcb XW |
1066 | return buf->trunk_list[offset >> buf->trunk_shift].map + |
1067 | (offset & ((1 << buf->trunk_shift) - 1)); | |
9a443537 | 1068 | } |
1069 | ||
7b0006db XW |
1070 | static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) |
1071 | { | |
1072 | return hns_roce_buf_dma_addr(buf, idx << buf->page_shift); | |
1073 | } | |
1074 | ||
9581a356 | 1075 | #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) |
54d66387 | 1076 | |
3c873161 XW |
1077 | static inline u64 to_hr_hw_page_addr(u64 addr) |
1078 | { | |
9581a356 | 1079 | return addr >> HNS_HW_PAGE_SHIFT; |
3c873161 XW |
1080 | } |
1081 | ||
1082 | static inline u32 to_hr_hw_page_shift(u32 page_shift) | |
1083 | { | |
9581a356 | 1084 | return page_shift - HNS_HW_PAGE_SHIFT; |
3c873161 XW |
1085 | } |
1086 | ||
54d66387 XW |
1087 | static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) |
1088 | { | |
1089 | if (count > 0) | |
1090 | return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; | |
1091 | ||
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) | |
1096 | { | |
1097 | return hr_hw_page_align(count << buf_shift); | |
1098 | } | |
1099 | ||
1100 | static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) | |
1101 | { | |
1102 | return hr_hw_page_align(count << buf_shift) >> buf_shift; | |
1103 | } | |
1104 | ||
1105 | static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) | |
1106 | { | |
d4d81387 WL |
1107 | if (!count) |
1108 | return 0; | |
1109 | ||
54d66387 XW |
1110 | return ilog2(to_hr_hem_entries_count(count, buf_shift)); |
1111 | } | |
1112 | ||
603bee93 WL |
1113 | #define DSCP_SHIFT 2 |
1114 | ||
1115 | static inline u8 get_tclass(const struct ib_global_route *grh) | |
1116 | { | |
1117 | return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? | |
1118 | grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; | |
1119 | } | |
1120 | ||
9a443537 | 1121 | int hns_roce_init_uar_table(struct hns_roce_dev *dev); |
1122 | int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); | |
1123 | void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); | |
1124 | void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); | |
1125 | ||
1126 | int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); | |
1127 | void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); | |
1128 | void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, | |
1129 | u64 out_param); | |
1130 | int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); | |
1131 | void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); | |
1132 | ||
38389eaa LO |
1133 | /* hns roce hw need current block and next block addr from mtt */ |
1134 | #define MTT_MIN_COUNT 2 | |
1135 | int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
1136 | int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); | |
3c873161 | 1137 | int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, |
82d07a4e WL |
1138 | struct hns_roce_buf_attr *buf_attr, |
1139 | unsigned int page_shift, struct ib_udata *udata, | |
1140 | unsigned long user_addr); | |
3c873161 XW |
1141 | void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, |
1142 | struct hns_roce_mtr *mtr); | |
1143 | int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
dcdc366a | 1144 | dma_addr_t *pages, unsigned int page_cnt); |
38389eaa | 1145 | |
645f0593 | 1146 | void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); |
d38936f0 | 1147 | void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); |
1bbd4380 | 1148 | void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); |
a33958ca | 1149 | void hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); |
5c1f167a | 1150 | int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); |
da43b7be | 1151 | void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); |
9a443537 | 1152 | |
9a443537 | 1153 | void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); |
1154 | void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); | |
1155 | void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); | |
5c1f167a | 1156 | void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); |
9a443537 | 1157 | |
1158 | int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); | |
38e375b7 | 1159 | void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj); |
9a443537 | 1160 | int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, |
1161 | u32 reserved_bot, u32 resetrved_top); | |
1162 | void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); | |
1163 | void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); | |
9a443537 | 1164 | |
fa5d010c MG |
1165 | int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, |
1166 | struct ib_udata *udata); | |
90898850 | 1167 | int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); |
9a9ebf8c LR |
1168 | static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) |
1169 | { | |
1170 | return 0; | |
1171 | } | |
9a443537 | 1172 | |
ff23dfa1 | 1173 | int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); |
91a7c58f | 1174 | int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); |
9a443537 | 1175 | |
1176 | struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); | |
1177 | struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
1178 | u64 virt_addr, int access_flags, | |
1179 | struct ib_udata *udata); | |
6e0954b1 JG |
1180 | struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, |
1181 | u64 length, u64 virt_addr, | |
1182 | int mr_access_flags, struct ib_pd *pd, | |
1183 | struct ib_udata *udata); | |
68a997c5 | 1184 | struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, |
42a3b153 | 1185 | u32 max_num_sg); |
68a997c5 YL |
1186 | int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
1187 | unsigned int *sg_offset); | |
c4367a26 | 1188 | int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); |
6eef5242 YL |
1189 | int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, |
1190 | struct hns_roce_cmd_mailbox *mailbox, | |
1191 | unsigned long mpt_index); | |
bfcc681b | 1192 | unsigned long key_to_hw_index(u32 key); |
9a443537 | 1193 | |
d18bb3e1 | 1194 | int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); |
c7c28191 YL |
1195 | int hns_roce_dealloc_mw(struct ib_mw *ibmw); |
1196 | ||
cc23267a | 1197 | void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); |
6f6e2dcb XW |
1198 | struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, |
1199 | u32 page_shift, u32 flags); | |
9a443537 | 1200 | |
2ac0bc5e | 1201 | int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, |
7b0006db XW |
1202 | int buf_cnt, struct hns_roce_buf *buf, |
1203 | unsigned int page_shift); | |
2ac0bc5e | 1204 | int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, |
7b0006db | 1205 | int buf_cnt, struct ib_umem *umem, |
82d07a4e | 1206 | unsigned int page_shift); |
2ac0bc5e | 1207 | |
68e326de LR |
1208 | int hns_roce_create_srq(struct ib_srq *srq, |
1209 | struct ib_srq_init_attr *srq_init_attr, | |
1210 | struct ib_udata *udata); | |
c7bcb134 LO |
1211 | int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, |
1212 | enum ib_srq_attr_mask srq_attr_mask, | |
1213 | struct ib_udata *udata); | |
119181d1 | 1214 | int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); |
c7bcb134 | 1215 | |
32548870 WL |
1216 | int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); |
1217 | int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); | |
1218 | ||
9a443537 | 1219 | struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, |
1220 | struct ib_qp_init_attr *init_attr, | |
1221 | struct ib_udata *udata); | |
1222 | int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
1223 | int attr_mask, struct ib_udata *udata); | |
ffd541d4 | 1224 | void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); |
dcdc366a WL |
1225 | void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); |
1226 | void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); | |
1227 | void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); | |
1228 | bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, | |
9a443537 | 1229 | struct ib_cq *ib_cq); |
1230 | enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); | |
1231 | void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, | |
1232 | struct hns_roce_cq *recv_cq); | |
1233 | void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, | |
1234 | struct hns_roce_cq *recv_cq); | |
1235 | void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); | |
e365b26c XW |
1236 | void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, |
1237 | struct ib_udata *udata); | |
f696bf6d | 1238 | __be32 send_ieth(const struct ib_send_wr *wr); |
9a443537 | 1239 | int to_hr_qp_type(int qp_type); |
1240 | ||
707783ab YL |
1241 | int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, |
1242 | struct ib_udata *udata); | |
9a443537 | 1243 | |
43d781b9 | 1244 | int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); |
69e0a42f | 1245 | int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, |
e088a685 YL |
1246 | struct hns_roce_db *db); |
1247 | void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, | |
1248 | struct hns_roce_db *db); | |
472bc0fb YL |
1249 | int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, |
1250 | int order); | |
1251 | void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); | |
1252 | ||
9a443537 | 1253 | void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); |
1254 | void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); | |
c462a024 | 1255 | void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp); |
9a443537 | 1256 | void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); |
81fce629 | 1257 | void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); |
1fb7f897 | 1258 | u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index); |
626903e9 | 1259 | void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); |
08805fdb WHX |
1260 | int hns_roce_init(struct hns_roce_dev *hr_dev); |
1261 | void hns_roce_exit(struct hns_roce_dev *hr_dev); | |
9e2a187a MG |
1262 | int hns_roce_fill_res_cq_entry(struct sk_buff *msg, |
1263 | struct ib_cq *ib_cq); | |
9a443537 | 1264 | #endif /* _HNS_ROCE_DEVICE_H */ |