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9a443537 | 1 | /* |
2 | * Copyright (c) 2016 Hisilicon Limited. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef _HNS_ROCE_DEVICE_H | |
34 | #define _HNS_ROCE_DEVICE_H | |
35 | ||
36 | #include <rdma/ib_verbs.h> | |
37 | ||
38 | #define DRV_NAME "hns_roce" | |
39 | ||
2a3d923f LO |
40 | /* hip08 is a pci device, it includes two version according pci version id */ |
41 | #define PCI_REVISION_ID_HIP08_A 0x20 | |
42 | #define PCI_REVISION_ID_HIP08_B 0x21 | |
43 | ||
8f3e9f3e WHX |
44 | #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') |
45 | ||
9a443537 | 46 | #define HNS_ROCE_MAX_MSG_LEN 0x80000000 |
47 | ||
9a443537 | 48 | #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 |
49 | ||
50 | #define HNS_ROCE_BA_SIZE (32 * 4096) | |
51 | ||
2a3d923f LO |
52 | #define BA_BYTE_LEN 8 |
53 | ||
9a443537 | 54 | /* Hardware specification only for v1 engine */ |
55 | #define HNS_ROCE_MIN_CQE_NUM 0x40 | |
56 | #define HNS_ROCE_MIN_WQE_NUM 0x20 | |
57 | ||
58 | /* Hardware specification only for v1 engine */ | |
59 | #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 | |
60 | #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 | |
2a3d923f | 61 | #define HNS_ROCE_MAX_SGE_NUM 2 |
9a443537 | 62 | |
afb6b092 SX |
63 | #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 |
64 | #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ | |
65 | (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) | |
66 | #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 | |
67 | #define HNS_ROCE_MIN_CQE_CNT 16 | |
68 | ||
b16f8188 | 69 | #define HNS_ROCE_MAX_IRQ_NUM 128 |
9a443537 | 70 | |
2a3d923f LO |
71 | #define HNS_ROCE_SGE_IN_WQE 2 |
72 | #define HNS_ROCE_SGE_SHIFT 4 | |
73 | ||
b16f8188 YL |
74 | #define EQ_ENABLE 1 |
75 | #define EQ_DISABLE 0 | |
9a443537 | 76 | |
b16f8188 YL |
77 | #define HNS_ROCE_CEQ 0 |
78 | #define HNS_ROCE_AEQ 1 | |
79 | ||
80 | #define HNS_ROCE_CEQ_ENTRY_SIZE 0x4 | |
81 | #define HNS_ROCE_AEQ_ENTRY_SIZE 0x10 | |
9a443537 | 82 | |
ac11125b | 83 | #define HNS_ROCE_SL_SHIFT 28 |
9a443537 | 84 | #define HNS_ROCE_TCLASS_SHIFT 20 |
cdfa4ad5 | 85 | #define HNS_ROCE_FLOW_LABEL_MASK 0xfffff |
9a443537 | 86 | |
87 | #define HNS_ROCE_MAX_PORTS 6 | |
88 | #define HNS_ROCE_MAX_GID_NUM 16 | |
89 | #define HNS_ROCE_GID_SIZE 16 | |
2a3d923f | 90 | #define HNS_ROCE_SGE_SIZE 16 |
9a443537 | 91 | |
a25d13cb SX |
92 | #define HNS_ROCE_HOP_NUM_0 0xff |
93 | ||
5e6ff78a WHX |
94 | #define BITMAP_NO_RR 0 |
95 | #define BITMAP_RR 1 | |
96 | ||
9a443537 | 97 | #define MR_TYPE_MR 0x00 |
68a997c5 | 98 | #define MR_TYPE_FRMR 0x01 |
9a443537 | 99 | #define MR_TYPE_DMA 0x03 |
100 | ||
68a997c5 YL |
101 | #define HNS_ROCE_FRMR_MAX_PA 512 |
102 | ||
9a443537 | 103 | #define PKEY_ID 0xffff |
31644665 | 104 | #define GUID_LEN 8 |
9a443537 | 105 | #define NODE_DESC_SIZE 64 |
509bf0c2 | 106 | #define DB_REG_OFFSET 0x1000 |
9a443537 | 107 | |
5e6e78db YL |
108 | /* Configure to HW for PAGE_SIZE larger than 4KB */ |
109 | #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) | |
110 | ||
9a443537 | 111 | #define PAGES_SHIFT_8 8 |
112 | #define PAGES_SHIFT_16 16 | |
113 | #define PAGES_SHIFT_24 24 | |
114 | #define PAGES_SHIFT_32 32 | |
115 | ||
2a3d923f LO |
116 | #define HNS_ROCE_PCI_BAR_NUM 2 |
117 | ||
c7bcb134 LO |
118 | #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 |
119 | #define SRQ_DB_REG 0x230 | |
120 | ||
90c559b1 LO |
121 | /* The chip implementation of the consumer index is calculated |
122 | * according to twice the actual EQ depth | |
123 | */ | |
124 | #define EQ_DEPTH_COEFF 2 | |
125 | ||
5e049a5d LO |
126 | enum { |
127 | SERV_TYPE_RC, | |
128 | SERV_TYPE_UC, | |
129 | SERV_TYPE_RD, | |
130 | SERV_TYPE_UD, | |
131 | }; | |
132 | ||
e088a685 YL |
133 | enum { |
134 | HNS_ROCE_SUPPORT_RQ_RECORD_DB = 1 << 0, | |
0425e3e6 | 135 | HNS_ROCE_SUPPORT_SQ_RECORD_DB = 1 << 1, |
e088a685 YL |
136 | }; |
137 | ||
9b44703d YL |
138 | enum { |
139 | HNS_ROCE_SUPPORT_CQ_RECORD_DB = 1 << 0, | |
140 | }; | |
141 | ||
9a443537 | 142 | enum hns_roce_qp_state { |
143 | HNS_ROCE_QP_STATE_RST, | |
144 | HNS_ROCE_QP_STATE_INIT, | |
145 | HNS_ROCE_QP_STATE_RTR, | |
146 | HNS_ROCE_QP_STATE_RTS, | |
147 | HNS_ROCE_QP_STATE_SQD, | |
148 | HNS_ROCE_QP_STATE_ERR, | |
149 | HNS_ROCE_QP_NUM_STATE, | |
150 | }; | |
151 | ||
152 | enum hns_roce_event { | |
153 | HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, | |
154 | HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, | |
155 | HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, | |
156 | HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, | |
157 | HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
158 | HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, | |
159 | HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, | |
160 | HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, | |
161 | HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, | |
162 | HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, | |
163 | HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, | |
164 | HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, | |
165 | HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, | |
166 | HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, | |
167 | /* 0x10 and 0x11 is unused in currently application case */ | |
168 | HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, | |
169 | HNS_ROCE_EVENT_TYPE_MB = 0x13, | |
170 | HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14, | |
a5073d60 | 171 | HNS_ROCE_EVENT_TYPE_FLR = 0x15, |
9a443537 | 172 | }; |
173 | ||
174 | /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */ | |
175 | enum { | |
176 | HNS_ROCE_LWQCE_QPC_ERROR = 1, | |
177 | HNS_ROCE_LWQCE_MTU_ERROR = 2, | |
178 | HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3, | |
179 | HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4, | |
180 | HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5, | |
181 | HNS_ROCE_LWQCE_SL_ERROR = 6, | |
182 | HNS_ROCE_LWQCE_PORT_ERROR = 7, | |
183 | }; | |
184 | ||
185 | /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */ | |
186 | enum { | |
187 | HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1, | |
188 | HNS_ROCE_LAVWQE_LENGTH_ERROR = 2, | |
189 | HNS_ROCE_LAVWQE_VA_ERROR = 3, | |
190 | HNS_ROCE_LAVWQE_PD_ERROR = 4, | |
191 | HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5, | |
192 | HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6, | |
193 | HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7, | |
194 | }; | |
195 | ||
196 | /* DOORBELL overflow subtype */ | |
197 | enum { | |
198 | HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1, | |
199 | HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2, | |
200 | HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3, | |
201 | HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4, | |
202 | HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5, | |
203 | HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6, | |
204 | }; | |
205 | ||
206 | enum { | |
207 | /* RQ&SRQ related operations */ | |
208 | HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06, | |
209 | HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, | |
210 | }; | |
211 | ||
a2c80b7b WHX |
212 | enum { |
213 | HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), | |
023c1477 | 214 | HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), |
e088a685 | 215 | HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), |
0425e3e6 YL |
216 | HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), |
217 | HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), | |
d16da119 | 218 | HNS_ROCE_CAP_FLAG_SRQ = BIT(5), |
c7c28191 | 219 | HNS_ROCE_CAP_FLAG_MW = BIT(7), |
68a997c5 | 220 | HNS_ROCE_CAP_FLAG_FRMR = BIT(8), |
aa84fa18 | 221 | HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), |
384f8818 | 222 | HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), |
a2c80b7b WHX |
223 | }; |
224 | ||
9766edc3 | 225 | enum hns_roce_mtt_type { |
400d324a | 226 | MTT_TYPE_WQE, |
9766edc3 | 227 | MTT_TYPE_CQE, |
5c1f167a LO |
228 | MTT_TYPE_SRQWQE, |
229 | MTT_TYPE_IDX | |
9766edc3 SX |
230 | }; |
231 | ||
2a3d923f LO |
232 | #define HNS_ROCE_DB_TYPE_COUNT 2 |
233 | #define HNS_ROCE_DB_UNIT_SIZE 4 | |
234 | ||
e088a685 YL |
235 | enum { |
236 | HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 | |
237 | }; | |
238 | ||
d061effc WHX |
239 | enum hns_roce_reset_stage { |
240 | HNS_ROCE_STATE_NON_RST, | |
241 | HNS_ROCE_STATE_RST_BEF_DOWN, | |
242 | HNS_ROCE_STATE_RST_DOWN, | |
243 | HNS_ROCE_STATE_RST_UNINIT, | |
244 | HNS_ROCE_STATE_RST_INIT, | |
245 | HNS_ROCE_STATE_RST_INITED, | |
246 | }; | |
247 | ||
248 | enum hns_roce_instance_state { | |
249 | HNS_ROCE_STATE_NON_INIT, | |
250 | HNS_ROCE_STATE_INIT, | |
251 | HNS_ROCE_STATE_INITED, | |
252 | HNS_ROCE_STATE_UNINIT, | |
253 | }; | |
254 | ||
255 | enum { | |
256 | HNS_ROCE_RST_DIRECT_RETURN = 0, | |
257 | }; | |
258 | ||
6a04aed6 WHX |
259 | enum { |
260 | CMD_RST_PRC_OTHERS, | |
261 | CMD_RST_PRC_SUCCESS, | |
262 | CMD_RST_PRC_EBUSY, | |
263 | }; | |
264 | ||
9a443537 | 265 | #define HNS_ROCE_CMD_SUCCESS 1 |
266 | ||
267 | #define HNS_ROCE_PORT_DOWN 0 | |
268 | #define HNS_ROCE_PORT_UP 1 | |
269 | ||
270 | #define HNS_ROCE_MTT_ENTRY_PER_SEG 8 | |
271 | ||
272 | #define PAGE_ADDR_SHIFT 12 | |
273 | ||
274 | struct hns_roce_uar { | |
275 | u64 pfn; | |
276 | unsigned long index; | |
5b6eb54f | 277 | unsigned long logic_idx; |
9a443537 | 278 | }; |
279 | ||
280 | struct hns_roce_ucontext { | |
281 | struct ib_ucontext ibucontext; | |
282 | struct hns_roce_uar uar; | |
e088a685 YL |
283 | struct list_head page_list; |
284 | struct mutex page_mutex; | |
9a443537 | 285 | }; |
286 | ||
287 | struct hns_roce_pd { | |
288 | struct ib_pd ibpd; | |
289 | unsigned long pdn; | |
290 | }; | |
291 | ||
292 | struct hns_roce_bitmap { | |
293 | /* Bitmap Traversal last a bit which is 1 */ | |
294 | unsigned long last; | |
295 | unsigned long top; | |
296 | unsigned long max; | |
297 | unsigned long reserved_top; | |
298 | unsigned long mask; | |
299 | spinlock_t lock; | |
300 | unsigned long *table; | |
301 | }; | |
302 | ||
303 | /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */ | |
304 | /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */ | |
305 | /* Every bit repesent to a partner free/used status in bitmap */ | |
306 | /* | |
e84e40be S |
307 | * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1 |
308 | * Bit = 1 represent to idle and available; bit = 0: not available | |
309 | */ | |
9a443537 | 310 | struct hns_roce_buddy { |
311 | /* Members point to every order level bitmap */ | |
312 | unsigned long **bits; | |
313 | /* Represent to avail bits of the order level bitmap */ | |
314 | u32 *num_free; | |
315 | int max_order; | |
316 | spinlock_t lock; | |
317 | }; | |
318 | ||
319 | /* For Hardware Entry Memory */ | |
320 | struct hns_roce_hem_table { | |
321 | /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ | |
322 | u32 type; | |
323 | /* HEM array elment num */ | |
324 | unsigned long num_hem; | |
325 | /* HEM entry record obj total num */ | |
326 | unsigned long num_obj; | |
6def7de6 | 327 | /* Single obj size */ |
9a443537 | 328 | unsigned long obj_size; |
29a1fe5d | 329 | unsigned long table_chunk_size; |
9a443537 | 330 | int lowmem; |
331 | struct mutex mutex; | |
332 | struct hns_roce_hem **hem; | |
a25d13cb SX |
333 | u64 **bt_l1; |
334 | dma_addr_t *bt_l1_dma_addr; | |
335 | u64 **bt_l0; | |
336 | dma_addr_t *bt_l0_dma_addr; | |
9a443537 | 337 | }; |
338 | ||
339 | struct hns_roce_mtt { | |
9766edc3 SX |
340 | unsigned long first_seg; |
341 | int order; | |
342 | int page_shift; | |
343 | enum hns_roce_mtt_type mtt_type; | |
9a443537 | 344 | }; |
345 | ||
38389eaa LO |
346 | struct hns_roce_buf_region { |
347 | int offset; /* page offset */ | |
6def7de6 | 348 | u32 count; /* page count */ |
38389eaa LO |
349 | int hopnum; /* addressing hop num */ |
350 | }; | |
351 | ||
352 | #define HNS_ROCE_MAX_BT_REGION 3 | |
353 | #define HNS_ROCE_MAX_BT_LEVEL 3 | |
354 | struct hns_roce_hem_list { | |
355 | struct list_head root_bt; | |
356 | /* link all bt dma mem by hop config */ | |
357 | struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; | |
358 | struct list_head btm_bt; /* link all bottom bt in @mid_bt */ | |
359 | dma_addr_t root_ba; /* pointer to the root ba table */ | |
360 | int bt_pg_shift; | |
361 | }; | |
362 | ||
363 | /* memory translate region */ | |
364 | struct hns_roce_mtr { | |
365 | struct hns_roce_hem_list hem_list; | |
366 | int buf_pg_shift; | |
367 | }; | |
368 | ||
c7c28191 YL |
369 | struct hns_roce_mw { |
370 | struct ib_mw ibmw; | |
371 | u32 pdn; | |
372 | u32 rkey; | |
373 | int enabled; /* MW's active status */ | |
374 | u32 pbl_hop_num; | |
375 | u32 pbl_ba_pg_sz; | |
376 | u32 pbl_buf_pg_sz; | |
377 | }; | |
378 | ||
9a443537 | 379 | /* Only support 4K page size for mr register */ |
380 | #define MR_SIZE_4K 0 | |
381 | ||
382 | struct hns_roce_mr { | |
383 | struct ib_mr ibmr; | |
384 | struct ib_umem *umem; | |
385 | u64 iova; /* MR's virtual orignal addr */ | |
386 | u64 size; /* Address range of MR */ | |
387 | u32 key; /* Key of MR */ | |
388 | u32 pd; /* PD num of MR */ | |
6def7de6 | 389 | u32 access; /* Access permission of MR */ |
68a997c5 | 390 | u32 npages; |
9a443537 | 391 | int enabled; /* MR's active status */ |
392 | int type; /* MR's register type */ | |
6def7de6 | 393 | u64 *pbl_buf; /* MR's PBL space */ |
9a443537 | 394 | dma_addr_t pbl_dma_addr; /* MR's PBL space PA */ |
6def7de6 LC |
395 | u32 pbl_size; /* PA number in the PBL */ |
396 | u64 pbl_ba; /* page table address */ | |
397 | u32 l0_chunk_last_num; /* L0 last number */ | |
398 | u32 l1_chunk_last_num; /* L1 last number */ | |
399 | u64 **pbl_bt_l2; /* PBL BT L2 */ | |
400 | u64 **pbl_bt_l1; /* PBL BT L1 */ | |
401 | u64 *pbl_bt_l0; /* PBL BT L0 */ | |
402 | dma_addr_t *pbl_l2_dma_addr; /* PBL BT L2 dma addr */ | |
403 | dma_addr_t *pbl_l1_dma_addr; /* PBL BT L1 dma addr */ | |
404 | dma_addr_t pbl_l0_dma_addr; /* PBL BT L0 dma addr */ | |
405 | u32 pbl_ba_pg_sz; /* BT chunk page size */ | |
406 | u32 pbl_buf_pg_sz; /* buf chunk page size */ | |
407 | u32 pbl_hop_num; /* multi-hop number */ | |
9a443537 | 408 | }; |
409 | ||
410 | struct hns_roce_mr_table { | |
411 | struct hns_roce_bitmap mtpt_bitmap; | |
412 | struct hns_roce_buddy mtt_buddy; | |
413 | struct hns_roce_hem_table mtt_table; | |
414 | struct hns_roce_hem_table mtpt_table; | |
9766edc3 SX |
415 | struct hns_roce_buddy mtt_cqe_buddy; |
416 | struct hns_roce_hem_table mtt_cqe_table; | |
5c1f167a LO |
417 | struct hns_roce_buddy mtt_srqwqe_buddy; |
418 | struct hns_roce_hem_table mtt_srqwqe_table; | |
419 | struct hns_roce_buddy mtt_idx_buddy; | |
420 | struct hns_roce_hem_table mtt_idx_table; | |
9a443537 | 421 | }; |
422 | ||
423 | struct hns_roce_wq { | |
424 | u64 *wrid; /* Work request ID */ | |
425 | spinlock_t lock; | |
47688202 | 426 | u32 wqe_cnt; /* WQE num */ |
9a443537 | 427 | int max_gs; |
428 | int offset; | |
6def7de6 | 429 | int wqe_shift; /* WQE size */ |
9a443537 | 430 | u32 head; |
431 | u32 tail; | |
432 | void __iomem *db_reg_l; | |
433 | }; | |
434 | ||
926a01dc | 435 | struct hns_roce_sge { |
6def7de6 | 436 | int sge_cnt; /* SGE num */ |
926a01dc | 437 | int offset; |
6def7de6 | 438 | int sge_shift; /* SGE size */ |
926a01dc WHX |
439 | }; |
440 | ||
9a443537 | 441 | struct hns_roce_buf_list { |
442 | void *buf; | |
443 | dma_addr_t map; | |
444 | }; | |
445 | ||
446 | struct hns_roce_buf { | |
447 | struct hns_roce_buf_list direct; | |
448 | struct hns_roce_buf_list *page_list; | |
449 | int nbufs; | |
450 | u32 npages; | |
18a96d25 | 451 | u32 size; |
9a443537 | 452 | int page_shift; |
453 | }; | |
454 | ||
e088a685 YL |
455 | struct hns_roce_db_pgdir { |
456 | struct list_head list; | |
457 | DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); | |
2a3d923f LO |
458 | DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); |
459 | unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; | |
e088a685 YL |
460 | u32 *page; |
461 | dma_addr_t db_dma; | |
462 | }; | |
463 | ||
464 | struct hns_roce_user_db_page { | |
465 | struct list_head list; | |
466 | struct ib_umem *umem; | |
467 | unsigned long user_virt; | |
468 | refcount_t refcount; | |
469 | }; | |
470 | ||
471 | struct hns_roce_db { | |
472 | u32 *db_record; | |
473 | union { | |
474 | struct hns_roce_db_pgdir *pgdir; | |
475 | struct hns_roce_user_db_page *user_page; | |
476 | } u; | |
477 | dma_addr_t dma; | |
0425e3e6 | 478 | void *virt_addr; |
e088a685 YL |
479 | int index; |
480 | int order; | |
481 | }; | |
482 | ||
9a443537 | 483 | struct hns_roce_cq { |
484 | struct ib_cq ib_cq; | |
18a96d25 YL |
485 | struct hns_roce_buf buf; |
486 | struct hns_roce_mtt mtt; | |
9b44703d YL |
487 | struct hns_roce_db db; |
488 | u8 db_en; | |
9a443537 | 489 | spinlock_t lock; |
9a443537 | 490 | struct ib_umem *umem; |
9a443537 | 491 | u32 cq_depth; |
492 | u32 cons_index; | |
86188a88 | 493 | u32 *set_ci_db; |
9a443537 | 494 | void __iomem *cq_db_l; |
8f3e9f3e | 495 | u16 *tptr_addr; |
26beb85f | 496 | int arm_sn; |
9a443537 | 497 | unsigned long cqn; |
498 | u32 vector; | |
499 | atomic_t refcount; | |
500 | struct completion free; | |
626903e9 XW |
501 | struct list_head sq_list; /* all qps on this send cq */ |
502 | struct list_head rq_list; /* all qps on this recv cq */ | |
503 | int is_armed; /* cq is armed */ | |
504 | struct list_head node; /* all armed cqs are on a list */ | |
9a443537 | 505 | }; |
506 | ||
c7bcb134 LO |
507 | struct hns_roce_idx_que { |
508 | struct hns_roce_buf idx_buf; | |
509 | int entry_sz; | |
510 | u32 buf_size; | |
511 | struct ib_umem *umem; | |
512 | struct hns_roce_mtt mtt; | |
97545b10 | 513 | unsigned long *bitmap; |
c7bcb134 LO |
514 | }; |
515 | ||
9a443537 | 516 | struct hns_roce_srq { |
517 | struct ib_srq ibsrq; | |
c7bcb134 | 518 | unsigned long srqn; |
d938d785 | 519 | u32 wqe_cnt; |
c7bcb134 LO |
520 | int max_gs; |
521 | int wqe_shift; | |
522 | void __iomem *db_reg_l; | |
523 | ||
524 | atomic_t refcount; | |
525 | struct completion free; | |
526 | ||
527 | struct hns_roce_buf buf; | |
528 | u64 *wrid; | |
529 | struct ib_umem *umem; | |
530 | struct hns_roce_mtt mtt; | |
531 | struct hns_roce_idx_que idx_que; | |
532 | spinlock_t lock; | |
533 | int head; | |
534 | int tail; | |
c7bcb134 | 535 | struct mutex mutex; |
d938d785 | 536 | void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); |
9a443537 | 537 | }; |
538 | ||
539 | struct hns_roce_uar_table { | |
540 | struct hns_roce_bitmap bitmap; | |
541 | }; | |
542 | ||
543 | struct hns_roce_qp_table { | |
544 | struct hns_roce_bitmap bitmap; | |
9a443537 | 545 | struct hns_roce_hem_table qp_table; |
546 | struct hns_roce_hem_table irrl_table; | |
e92f2c18 | 547 | struct hns_roce_hem_table trrl_table; |
6a157f7d | 548 | struct hns_roce_hem_table sccc_table; |
aa84fa18 | 549 | struct mutex scc_mutex; |
9a443537 | 550 | }; |
551 | ||
552 | struct hns_roce_cq_table { | |
553 | struct hns_roce_bitmap bitmap; | |
27e19f45 | 554 | struct xarray array; |
9a443537 | 555 | struct hns_roce_hem_table table; |
556 | }; | |
557 | ||
5c1f167a LO |
558 | struct hns_roce_srq_table { |
559 | struct hns_roce_bitmap bitmap; | |
560 | struct xarray xa; | |
561 | struct hns_roce_hem_table table; | |
562 | }; | |
563 | ||
9a443537 | 564 | struct hns_roce_raq_table { |
565 | struct hns_roce_buf_list *e_raq_buf; | |
566 | }; | |
567 | ||
568 | struct hns_roce_av { | |
82e620d9 | 569 | u8 port; |
9a443537 | 570 | u8 gid_index; |
571 | u8 stat_rate; | |
572 | u8 hop_limit; | |
82e620d9 LC |
573 | u32 flowlabel; |
574 | u8 sl; | |
575 | u8 tclass; | |
9a443537 | 576 | u8 dgid[HNS_ROCE_GID_SIZE]; |
2a3d923f | 577 | u8 mac[ETH_ALEN]; |
32883228 | 578 | u16 vlan_id; |
8320deb8 | 579 | bool vlan_en; |
9a443537 | 580 | }; |
581 | ||
582 | struct hns_roce_ah { | |
583 | struct ib_ah ibah; | |
584 | struct hns_roce_av av; | |
585 | }; | |
586 | ||
587 | struct hns_roce_cmd_context { | |
588 | struct completion done; | |
589 | int result; | |
590 | int next; | |
591 | u64 out_param; | |
592 | u16 token; | |
593 | }; | |
594 | ||
595 | struct hns_roce_cmdq { | |
596 | struct dma_pool *pool; | |
9a443537 | 597 | struct mutex hcr_mutex; |
598 | struct semaphore poll_sem; | |
599 | /* | |
e84e40be S |
600 | * Event mode: cmd register mutex protection, |
601 | * ensure to not exceed max_cmds and user use limit region | |
602 | */ | |
9a443537 | 603 | struct semaphore event_sem; |
604 | int max_cmds; | |
605 | spinlock_t context_lock; | |
606 | int free_head; | |
607 | struct hns_roce_cmd_context *context; | |
608 | /* | |
e84e40be S |
609 | * Result of get integer part |
610 | * which max_comds compute according a power of 2 | |
611 | */ | |
9a443537 | 612 | u16 token_mask; |
613 | /* | |
e84e40be S |
614 | * Process whether use event mode, init default non-zero |
615 | * After the event queue of cmd event ready, | |
616 | * can switch into event mode | |
617 | * close device, switch into poll mode(non event mode) | |
618 | */ | |
9a443537 | 619 | u8 use_events; |
9a443537 | 620 | }; |
621 | ||
bfcc681b SX |
622 | struct hns_roce_cmd_mailbox { |
623 | void *buf; | |
624 | dma_addr_t dma; | |
625 | }; | |
626 | ||
9a443537 | 627 | struct hns_roce_dev; |
628 | ||
0009c2db | 629 | struct hns_roce_rinl_sge { |
630 | void *addr; | |
631 | u32 len; | |
632 | }; | |
633 | ||
634 | struct hns_roce_rinl_wqe { | |
635 | struct hns_roce_rinl_sge *sg_list; | |
636 | u32 sge_cnt; | |
637 | }; | |
638 | ||
639 | struct hns_roce_rinl_buf { | |
640 | struct hns_roce_rinl_wqe *wqe_list; | |
641 | u32 wqe_cnt; | |
642 | }; | |
643 | ||
b5374286 YL |
644 | enum { |
645 | HNS_ROCE_FLUSH_FLAG = 0, | |
646 | }; | |
647 | ||
ffd541d4 YL |
648 | struct hns_roce_work { |
649 | struct hns_roce_dev *hr_dev; | |
650 | struct work_struct work; | |
651 | u32 qpn; | |
652 | u32 cqn; | |
653 | int event_type; | |
654 | int sub_type; | |
655 | }; | |
656 | ||
9a443537 | 657 | struct hns_roce_qp { |
658 | struct ib_qp ibqp; | |
659 | struct hns_roce_buf hr_buf; | |
660 | struct hns_roce_wq rq; | |
e088a685 | 661 | struct hns_roce_db rdb; |
0425e3e6 | 662 | struct hns_roce_db sdb; |
e088a685 | 663 | u8 rdb_en; |
0425e3e6 | 664 | u8 sdb_en; |
8b9b8d14 | 665 | u32 doorbell_qpn; |
bfe86035 | 666 | u32 sq_signal_bits; |
9a443537 | 667 | struct hns_roce_wq sq; |
668 | ||
669 | struct ib_umem *umem; | |
670 | struct hns_roce_mtt mtt; | |
8d18ad83 LO |
671 | struct hns_roce_mtr mtr; |
672 | ||
673 | /* this define must less than HNS_ROCE_MAX_BT_REGION */ | |
674 | #define HNS_ROCE_WQE_REGION_MAX 3 | |
675 | struct hns_roce_buf_region regions[HNS_ROCE_WQE_REGION_MAX]; | |
676 | int region_cnt; | |
677 | int wqe_bt_pg_shift; | |
678 | ||
9a443537 | 679 | u32 buff_size; |
680 | struct mutex mutex; | |
681 | u8 port; | |
7716809e | 682 | u8 phy_port; |
9a443537 | 683 | u8 sl; |
684 | u8 resp_depth; | |
685 | u8 state; | |
686 | u32 access_flags; | |
ace1c541 | 687 | u32 atomic_rd_en; |
9a443537 | 688 | u32 pkey_index; |
0fa95a9a | 689 | u32 qkey; |
fd012f1c | 690 | void (*event)(struct hns_roce_qp *qp, |
691 | enum hns_roce_event event_type); | |
9a443537 | 692 | unsigned long qpn; |
693 | ||
694 | atomic_t refcount; | |
695 | struct completion free; | |
926a01dc WHX |
696 | |
697 | struct hns_roce_sge sge; | |
698 | u32 next_sge; | |
0009c2db | 699 | |
b5374286 YL |
700 | /* 0: flush needed, 1: unneeded */ |
701 | unsigned long flush_flag; | |
ffd541d4 | 702 | struct hns_roce_work flush_work; |
0009c2db | 703 | struct hns_roce_rinl_buf rq_inl_buf; |
626903e9 XW |
704 | struct list_head node; /* all qps are on a list */ |
705 | struct list_head rq_node; /* all recv qps are on a list */ | |
706 | struct list_head sq_node; /* all send qps are on a list */ | |
9a443537 | 707 | }; |
708 | ||
9a443537 | 709 | struct hns_roce_ib_iboe { |
710 | spinlock_t lock; | |
711 | struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; | |
712 | struct notifier_block nb; | |
9a443537 | 713 | u8 phy_port[HNS_ROCE_MAX_PORTS]; |
714 | }; | |
715 | ||
b16f8188 YL |
716 | enum { |
717 | HNS_ROCE_EQ_STAT_INVALID = 0, | |
718 | HNS_ROCE_EQ_STAT_VALID = 2, | |
719 | }; | |
720 | ||
721 | struct hns_roce_ceqe { | |
bfe86035 | 722 | __le32 comp; |
b16f8188 YL |
723 | }; |
724 | ||
725 | struct hns_roce_aeqe { | |
0576cbde | 726 | __le32 asyn; |
b16f8188 YL |
727 | union { |
728 | struct { | |
0576cbde | 729 | __le32 qp; |
b16f8188 YL |
730 | u32 rsv0; |
731 | u32 rsv1; | |
732 | } qp_event; | |
733 | ||
81fce629 LO |
734 | struct { |
735 | __le32 srq; | |
736 | u32 rsv0; | |
737 | u32 rsv1; | |
738 | } srq_event; | |
739 | ||
b16f8188 | 740 | struct { |
0576cbde | 741 | __le32 cq; |
b16f8188 YL |
742 | u32 rsv0; |
743 | u32 rsv1; | |
744 | } cq_event; | |
745 | ||
746 | struct { | |
0576cbde | 747 | __le32 ceqe; |
b16f8188 YL |
748 | u32 rsv0; |
749 | u32 rsv1; | |
750 | } ce_event; | |
751 | ||
752 | struct { | |
753 | __le64 out_param; | |
754 | __le16 token; | |
755 | u8 status; | |
756 | u8 rsv0; | |
757 | } __packed cmd; | |
758 | } event; | |
759 | }; | |
760 | ||
9a443537 | 761 | struct hns_roce_eq { |
762 | struct hns_roce_dev *hr_dev; | |
763 | void __iomem *doorbell; | |
764 | ||
6def7de6 | 765 | int type_flag; /* Aeq:1 ceq:0 */ |
9a443537 | 766 | int eqn; |
767 | u32 entries; | |
768 | int log_entries; | |
769 | int eqe_size; | |
770 | int irq; | |
771 | int log_page_size; | |
772 | int cons_index; | |
773 | struct hns_roce_buf_list *buf_list; | |
a5073d60 YL |
774 | int over_ignore; |
775 | int coalesce; | |
776 | int arm_st; | |
777 | u64 eqe_ba; | |
778 | int eqe_ba_pg_sz; | |
779 | int eqe_buf_pg_sz; | |
780 | int hop_num; | |
d7e2d343 XW |
781 | struct hns_roce_mtr mtr; |
782 | struct hns_roce_buf buf; | |
a5073d60 YL |
783 | int eq_max_cnt; |
784 | int eq_period; | |
785 | int shift; | |
786 | dma_addr_t cur_eqe_ba; | |
787 | dma_addr_t nxt_eqe_ba; | |
0425e3e6 YL |
788 | int event_type; |
789 | int sub_type; | |
9a443537 | 790 | }; |
791 | ||
792 | struct hns_roce_eq_table { | |
793 | struct hns_roce_eq *eq; | |
b16f8188 | 794 | void __iomem **eqc_base; /* only for hw v1 */ |
9a443537 | 795 | }; |
796 | ||
797 | struct hns_roce_caps { | |
3a63c964 | 798 | u64 fw_ver; |
9a443537 | 799 | u8 num_ports; |
800 | int gid_table_len[HNS_ROCE_MAX_PORTS]; | |
801 | int pkey_table_len[HNS_ROCE_MAX_PORTS]; | |
802 | int local_ca_ack_delay; | |
803 | int num_uars; | |
804 | u32 phy_num_uars; | |
6def7de6 LC |
805 | u32 max_sq_sg; |
806 | u32 max_sq_inline; | |
807 | u32 max_rq_sg; | |
05ad5482 | 808 | u32 max_extend_sg; |
6def7de6 | 809 | int num_qps; |
06ef0ee4 | 810 | int reserved_qps; |
0e40dc2f YL |
811 | int num_qpc_timer; |
812 | int num_cqc_timer; | |
5c1f167a | 813 | int num_srqs; |
6def7de6 | 814 | u32 max_wqes; |
d16da119 LO |
815 | u32 max_srq_wrs; |
816 | u32 max_srq_sges; | |
6def7de6 LC |
817 | u32 max_sq_desc_sz; |
818 | u32 max_rq_desc_sz; | |
cfc85f3e | 819 | u32 max_srq_desc_sz; |
9a443537 | 820 | int max_qp_init_rdma; |
821 | int max_qp_dest_rdma; | |
9a443537 | 822 | int num_cqs; |
e2b2744a YL |
823 | u32 max_cqes; |
824 | u32 min_cqes; | |
926a01dc | 825 | u32 min_wqes; |
9a443537 | 826 | int reserved_cqs; |
5c1f167a | 827 | int reserved_srqs; |
6def7de6 | 828 | int num_aeq_vectors; |
a5073d60 | 829 | int num_comp_vectors; |
9a443537 | 830 | int num_other_vectors; |
831 | int num_mtpts; | |
832 | u32 num_mtt_segs; | |
cfc85f3e | 833 | u32 num_cqe_segs; |
5c1f167a LO |
834 | u32 num_srqwqe_segs; |
835 | u32 num_idx_segs; | |
9a443537 | 836 | int reserved_mrws; |
837 | int reserved_uars; | |
838 | int num_pds; | |
839 | int reserved_pds; | |
840 | u32 mtt_entry_sz; | |
841 | u32 cq_entry_sz; | |
842 | u32 page_size_cap; | |
843 | u32 reserved_lkey; | |
844 | int mtpt_entry_sz; | |
845 | int qpc_entry_sz; | |
846 | int irrl_entry_sz; | |
e92f2c18 | 847 | int trrl_entry_sz; |
9a443537 | 848 | int cqc_entry_sz; |
6a157f7d | 849 | int sccc_entry_sz; |
0e40dc2f YL |
850 | int qpc_timer_entry_sz; |
851 | int cqc_timer_entry_sz; | |
5c1f167a LO |
852 | int srqc_entry_sz; |
853 | int idx_entry_sz; | |
ff795f71 WHX |
854 | u32 pbl_ba_pg_sz; |
855 | u32 pbl_buf_pg_sz; | |
856 | u32 pbl_hop_num; | |
9a443537 | 857 | int aeqe_depth; |
b16f8188 | 858 | int ceqe_depth; |
9a443537 | 859 | enum ib_mtu max_mtu; |
cfc85f3e | 860 | u32 qpc_bt_num; |
0e40dc2f | 861 | u32 qpc_timer_bt_num; |
cfc85f3e WHX |
862 | u32 srqc_bt_num; |
863 | u32 cqc_bt_num; | |
0e40dc2f | 864 | u32 cqc_timer_bt_num; |
cfc85f3e | 865 | u32 mpt_bt_num; |
6a157f7d | 866 | u32 sccc_bt_num; |
a25d13cb SX |
867 | u32 qpc_ba_pg_sz; |
868 | u32 qpc_buf_pg_sz; | |
869 | u32 qpc_hop_num; | |
870 | u32 srqc_ba_pg_sz; | |
871 | u32 srqc_buf_pg_sz; | |
872 | u32 srqc_hop_num; | |
873 | u32 cqc_ba_pg_sz; | |
874 | u32 cqc_buf_pg_sz; | |
875 | u32 cqc_hop_num; | |
876 | u32 mpt_ba_pg_sz; | |
877 | u32 mpt_buf_pg_sz; | |
878 | u32 mpt_hop_num; | |
6a93c77a SX |
879 | u32 mtt_ba_pg_sz; |
880 | u32 mtt_buf_pg_sz; | |
881 | u32 mtt_hop_num; | |
8d18ad83 LO |
882 | u32 wqe_sq_hop_num; |
883 | u32 wqe_sge_hop_num; | |
884 | u32 wqe_rq_hop_num; | |
6a157f7d YL |
885 | u32 sccc_ba_pg_sz; |
886 | u32 sccc_buf_pg_sz; | |
887 | u32 sccc_hop_num; | |
0e40dc2f YL |
888 | u32 qpc_timer_ba_pg_sz; |
889 | u32 qpc_timer_buf_pg_sz; | |
890 | u32 qpc_timer_hop_num; | |
891 | u32 cqc_timer_ba_pg_sz; | |
892 | u32 cqc_timer_buf_pg_sz; | |
893 | u32 cqc_timer_hop_num; | |
b14c95be | 894 | u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ |
6a93c77a SX |
895 | u32 cqe_buf_pg_sz; |
896 | u32 cqe_hop_num; | |
c7bcb134 LO |
897 | u32 srqwqe_ba_pg_sz; |
898 | u32 srqwqe_buf_pg_sz; | |
899 | u32 srqwqe_hop_num; | |
900 | u32 idx_ba_pg_sz; | |
901 | u32 idx_buf_pg_sz; | |
902 | u32 idx_hop_num; | |
a5073d60 YL |
903 | u32 eqe_ba_pg_sz; |
904 | u32 eqe_buf_pg_sz; | |
905 | u32 eqe_hop_num; | |
6b63597d | 906 | u32 sl_num; |
907 | u32 tsq_buf_pg_sz; | |
ded58ff9 | 908 | u32 tpq_buf_pg_sz; |
6def7de6 | 909 | u32 chunk_sz; /* chunk size in non multihop mode */ |
a2c80b7b | 910 | u64 flags; |
ba6bb7e9 LO |
911 | u16 default_ceq_max_cnt; |
912 | u16 default_ceq_period; | |
913 | u16 default_aeq_max_cnt; | |
914 | u16 default_aeq_period; | |
915 | u16 default_aeq_arm_st; | |
916 | u16 default_ceq_arm_st; | |
9a443537 | 917 | }; |
918 | ||
e1c9a0dc LO |
919 | struct hns_roce_dfx_hw { |
920 | int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, | |
921 | int *buffer); | |
922 | }; | |
923 | ||
626903e9 XW |
924 | enum hns_roce_device_state { |
925 | HNS_ROCE_DEVICE_STATE_INITED, | |
926 | HNS_ROCE_DEVICE_STATE_RST_DOWN, | |
927 | HNS_ROCE_DEVICE_STATE_UNINIT, | |
928 | }; | |
929 | ||
9a443537 | 930 | struct hns_roce_hw { |
931 | int (*reset)(struct hns_roce_dev *hr_dev, bool enable); | |
a04ff739 WHX |
932 | int (*cmq_init)(struct hns_roce_dev *hr_dev); |
933 | void (*cmq_exit)(struct hns_roce_dev *hr_dev); | |
cfc85f3e | 934 | int (*hw_profile)(struct hns_roce_dev *hr_dev); |
9a443537 | 935 | int (*hw_init)(struct hns_roce_dev *hr_dev); |
936 | void (*hw_exit)(struct hns_roce_dev *hr_dev); | |
a680f2f3 WHX |
937 | int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, |
938 | u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, | |
939 | u16 token, int event); | |
940 | int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout); | |
6a04aed6 | 941 | int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev); |
b5ff0f61 | 942 | int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, |
f4df9a7c | 943 | const union ib_gid *gid, const struct ib_gid_attr *attr); |
a74dc41d | 944 | int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); |
9a443537 | 945 | void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, |
946 | enum ib_mtu mtu); | |
947 | int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr, | |
948 | unsigned long mtpt_idx); | |
a2c80b7b WHX |
949 | int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, |
950 | struct hns_roce_mr *mr, int flags, u32 pdn, | |
951 | int mr_access_flags, u64 iova, u64 size, | |
952 | void *mb_buf); | |
68a997c5 | 953 | int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr); |
c7c28191 | 954 | int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); |
9a443537 | 955 | void (*write_cqc)(struct hns_roce_dev *hr_dev, |
956 | struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, | |
e2b2744a | 957 | dma_addr_t dma_handle); |
a25d13cb SX |
958 | int (*set_hem)(struct hns_roce_dev *hr_dev, |
959 | struct hns_roce_hem_table *table, int obj, int step_idx); | |
97f0e39f | 960 | int (*clear_hem)(struct hns_roce_dev *hr_dev, |
a25d13cb SX |
961 | struct hns_roce_hem_table *table, int obj, |
962 | int step_idx); | |
9a443537 | 963 | int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, |
964 | int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); | |
965 | int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, | |
966 | int attr_mask, enum ib_qp_state cur_state, | |
967 | enum ib_qp_state new_state); | |
c4367a26 | 968 | int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata); |
aa84fa18 YL |
969 | int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, |
970 | struct hns_roce_qp *hr_qp); | |
d34ac5cd BVA |
971 | int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
972 | const struct ib_send_wr **bad_wr); | |
973 | int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr, | |
974 | const struct ib_recv_wr **bad_recv_wr); | |
9a443537 | 975 | int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); |
976 | int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); | |
c4367a26 SR |
977 | int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, |
978 | struct ib_udata *udata); | |
a52c8e24 | 979 | void (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); |
b156269d | 980 | int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period); |
b16f8188 YL |
981 | int (*init_eq)(struct hns_roce_dev *hr_dev); |
982 | void (*cleanup_eq)(struct hns_roce_dev *hr_dev); | |
c7bcb134 LO |
983 | void (*write_srqc)(struct hns_roce_dev *hr_dev, |
984 | struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn, | |
985 | void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx, | |
986 | dma_addr_t dma_handle_wqe, | |
987 | dma_addr_t dma_handle_idx); | |
988 | int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, | |
989 | enum ib_srq_attr_mask srq_attr_mask, | |
990 | struct ib_udata *udata); | |
991 | int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr); | |
992 | int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, | |
993 | const struct ib_recv_wr **bad_wr); | |
7f645a58 KH |
994 | const struct ib_device_ops *hns_roce_dev_ops; |
995 | const struct ib_device_ops *hns_roce_dev_srq_ops; | |
9a443537 | 996 | }; |
997 | ||
998 | struct hns_roce_dev { | |
999 | struct ib_device ib_dev; | |
1000 | struct platform_device *pdev; | |
dd74282d WHX |
1001 | struct pci_dev *pci_dev; |
1002 | struct device *dev; | |
9a443537 | 1003 | struct hns_roce_uar priv_uar; |
528f1deb | 1004 | const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; |
9a443537 | 1005 | spinlock_t sm_lock; |
9a443537 | 1006 | spinlock_t bt_cmd_lock; |
cb7a94c9 WHX |
1007 | bool active; |
1008 | bool is_reset; | |
d3743fa9 | 1009 | bool dis_db; |
d061effc | 1010 | unsigned long reset_cnt; |
9a443537 | 1011 | struct hns_roce_ib_iboe iboe; |
626903e9 XW |
1012 | enum hns_roce_device_state state; |
1013 | struct list_head qp_list; /* list of all qps on this dev */ | |
1014 | spinlock_t qp_list_lock; /* protect qp_list */ | |
9a443537 | 1015 | |
472bc0fb YL |
1016 | struct list_head pgdir_list; |
1017 | struct mutex pgdir_mutex; | |
9a443537 | 1018 | int irq[HNS_ROCE_MAX_IRQ_NUM]; |
1019 | u8 __iomem *reg_base; | |
1020 | struct hns_roce_caps caps; | |
736b5a70 | 1021 | struct xarray qp_table_xa; |
9a443537 | 1022 | |
2a3d923f | 1023 | unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; |
9a443537 | 1024 | u64 sys_image_guid; |
1025 | u32 vendor_id; | |
1026 | u32 vendor_part_id; | |
1027 | u32 hw_rev; | |
1028 | void __iomem *priv_addr; | |
1029 | ||
1030 | struct hns_roce_cmdq cmd; | |
1031 | struct hns_roce_bitmap pd_bitmap; | |
1032 | struct hns_roce_uar_table uar_table; | |
1033 | struct hns_roce_mr_table mr_table; | |
1034 | struct hns_roce_cq_table cq_table; | |
5c1f167a | 1035 | struct hns_roce_srq_table srq_table; |
9a443537 | 1036 | struct hns_roce_qp_table qp_table; |
1037 | struct hns_roce_eq_table eq_table; | |
0e40dc2f YL |
1038 | struct hns_roce_hem_table qpc_timer_table; |
1039 | struct hns_roce_hem_table cqc_timer_table; | |
9a443537 | 1040 | |
1041 | int cmd_mod; | |
1042 | int loop_idc; | |
2d407888 WHX |
1043 | u32 sdb_offset; |
1044 | u32 odb_offset; | |
6def7de6 LC |
1045 | dma_addr_t tptr_dma_addr; /* only for hw v1 */ |
1046 | u32 tptr_size; /* only for hw v1 */ | |
08805fdb | 1047 | const struct hns_roce_hw *hw; |
016a0059 | 1048 | void *priv; |
0425e3e6 | 1049 | struct workqueue_struct *irq_workq; |
e1c9a0dc | 1050 | const struct hns_roce_dfx_hw *dfx; |
9a443537 | 1051 | }; |
1052 | ||
1053 | static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) | |
1054 | { | |
1055 | return container_of(ib_dev, struct hns_roce_dev, ib_dev); | |
1056 | } | |
1057 | ||
1058 | static inline struct hns_roce_ucontext | |
1059 | *to_hr_ucontext(struct ib_ucontext *ibucontext) | |
1060 | { | |
1061 | return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); | |
1062 | } | |
1063 | ||
1064 | static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) | |
1065 | { | |
1066 | return container_of(ibpd, struct hns_roce_pd, ibpd); | |
1067 | } | |
1068 | ||
1069 | static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) | |
1070 | { | |
1071 | return container_of(ibah, struct hns_roce_ah, ibah); | |
1072 | } | |
1073 | ||
1074 | static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) | |
1075 | { | |
1076 | return container_of(ibmr, struct hns_roce_mr, ibmr); | |
1077 | } | |
1078 | ||
c7c28191 YL |
1079 | static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) |
1080 | { | |
1081 | return container_of(ibmw, struct hns_roce_mw, ibmw); | |
1082 | } | |
1083 | ||
9a443537 | 1084 | static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) |
1085 | { | |
1086 | return container_of(ibqp, struct hns_roce_qp, ibqp); | |
1087 | } | |
1088 | ||
1089 | static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) | |
1090 | { | |
1091 | return container_of(ib_cq, struct hns_roce_cq, ib_cq); | |
1092 | } | |
1093 | ||
1094 | static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) | |
1095 | { | |
1096 | return container_of(ibsrq, struct hns_roce_srq, ibsrq); | |
1097 | } | |
1098 | ||
0576cbde | 1099 | static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) |
9a443537 | 1100 | { |
1101 | __raw_writeq(*(u64 *) val, dest); | |
1102 | } | |
1103 | ||
1104 | static inline struct hns_roce_qp | |
1105 | *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) | |
1106 | { | |
736b5a70 | 1107 | return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1)); |
9a443537 | 1108 | } |
1109 | ||
1110 | static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) | |
1111 | { | |
9a8982dc | 1112 | u32 page_size = 1 << buf->page_shift; |
9a443537 | 1113 | |
b1c15835 | 1114 | if (buf->nbufs == 1) |
9a443537 | 1115 | return (char *)(buf->direct.buf) + offset; |
1116 | else | |
9a8982dc WHX |
1117 | return (char *)(buf->page_list[offset >> buf->page_shift].buf) + |
1118 | (offset & (page_size - 1)); | |
9a443537 | 1119 | } |
1120 | ||
1121 | int hns_roce_init_uar_table(struct hns_roce_dev *dev); | |
1122 | int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); | |
1123 | void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); | |
1124 | void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); | |
1125 | ||
1126 | int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); | |
1127 | void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); | |
1128 | void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, | |
1129 | u64 out_param); | |
1130 | int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); | |
1131 | void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); | |
1132 | ||
1133 | int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift, | |
1134 | struct hns_roce_mtt *mtt); | |
1135 | void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev, | |
1136 | struct hns_roce_mtt *mtt); | |
1137 | int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev, | |
1138 | struct hns_roce_mtt *mtt, struct hns_roce_buf *buf); | |
1139 | ||
38389eaa LO |
1140 | void hns_roce_mtr_init(struct hns_roce_mtr *mtr, int bt_pg_shift, |
1141 | int buf_pg_shift); | |
1142 | int hns_roce_mtr_attach(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
1143 | dma_addr_t **bufs, struct hns_roce_buf_region *regions, | |
1144 | int region_cnt); | |
1145 | void hns_roce_mtr_cleanup(struct hns_roce_dev *hr_dev, | |
1146 | struct hns_roce_mtr *mtr); | |
1147 | ||
1148 | /* hns roce hw need current block and next block addr from mtt */ | |
1149 | #define MTT_MIN_COUNT 2 | |
1150 | int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
1151 | int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); | |
1152 | ||
9a443537 | 1153 | int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); |
1154 | int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); | |
9a443537 | 1155 | int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); |
1156 | int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); | |
5c1f167a | 1157 | int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); |
9a443537 | 1158 | |
1159 | void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); | |
1160 | void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); | |
1161 | void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); | |
1162 | void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); | |
1163 | void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); | |
5c1f167a | 1164 | void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); |
9a443537 | 1165 | |
1166 | int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); | |
5e6ff78a WHX |
1167 | void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, |
1168 | int rr); | |
9a443537 | 1169 | int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, |
1170 | u32 reserved_bot, u32 resetrved_top); | |
1171 | void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); | |
1172 | void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); | |
1173 | int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, | |
1174 | int align, unsigned long *obj); | |
1175 | void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, | |
5e6ff78a WHX |
1176 | unsigned long obj, int cnt, |
1177 | int rr); | |
9a443537 | 1178 | |
d3456914 LR |
1179 | int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr, |
1180 | u32 flags, struct ib_udata *udata); | |
90898850 | 1181 | int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); |
d3456914 | 1182 | void hns_roce_destroy_ah(struct ib_ah *ah, u32 flags); |
9a443537 | 1183 | |
ff23dfa1 | 1184 | int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); |
c4367a26 | 1185 | void hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); |
9a443537 | 1186 | |
1187 | struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); | |
1188 | struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
1189 | u64 virt_addr, int access_flags, | |
1190 | struct ib_udata *udata); | |
a2c80b7b WHX |
1191 | int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length, |
1192 | u64 virt_addr, int mr_access_flags, struct ib_pd *pd, | |
1193 | struct ib_udata *udata); | |
68a997c5 | 1194 | struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, |
c4367a26 | 1195 | u32 max_num_sg, struct ib_udata *udata); |
68a997c5 YL |
1196 | int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
1197 | unsigned int *sg_offset); | |
c4367a26 | 1198 | int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); |
6eef5242 YL |
1199 | int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, |
1200 | struct hns_roce_cmd_mailbox *mailbox, | |
1201 | unsigned long mpt_index); | |
bfcc681b | 1202 | unsigned long key_to_hw_index(u32 key); |
9a443537 | 1203 | |
c7c28191 YL |
1204 | struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type, |
1205 | struct ib_udata *udata); | |
1206 | int hns_roce_dealloc_mw(struct ib_mw *ibmw); | |
1207 | ||
9a443537 | 1208 | void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size, |
1209 | struct hns_roce_buf *buf); | |
1210 | int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, | |
9a8982dc | 1211 | struct hns_roce_buf *buf, u32 page_shift); |
9a443537 | 1212 | |
1213 | int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev, | |
1214 | struct hns_roce_mtt *mtt, struct ib_umem *umem); | |
1215 | ||
2ac0bc5e LO |
1216 | void hns_roce_init_buf_region(struct hns_roce_buf_region *region, int hopnum, |
1217 | int offset, int buf_cnt); | |
1218 | int hns_roce_alloc_buf_list(struct hns_roce_buf_region *regions, | |
1219 | dma_addr_t **bufs, int count); | |
1220 | void hns_roce_free_buf_list(dma_addr_t **bufs, int count); | |
1221 | ||
1222 | int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, | |
1223 | int buf_cnt, int start, struct hns_roce_buf *buf); | |
1224 | int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, | |
1225 | int buf_cnt, int start, struct ib_umem *umem, | |
1226 | int page_shift); | |
1227 | ||
68e326de LR |
1228 | int hns_roce_create_srq(struct ib_srq *srq, |
1229 | struct ib_srq_init_attr *srq_init_attr, | |
1230 | struct ib_udata *udata); | |
c7bcb134 LO |
1231 | int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, |
1232 | enum ib_srq_attr_mask srq_attr_mask, | |
1233 | struct ib_udata *udata); | |
68e326de | 1234 | void hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); |
c7bcb134 | 1235 | |
9a443537 | 1236 | struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, |
1237 | struct ib_qp_init_attr *init_attr, | |
1238 | struct ib_udata *udata); | |
1239 | int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
1240 | int attr_mask, struct ib_udata *udata); | |
ffd541d4 | 1241 | void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); |
9a443537 | 1242 | void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n); |
1243 | void *get_send_wqe(struct hns_roce_qp *hr_qp, int n); | |
926a01dc | 1244 | void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n); |
9a443537 | 1245 | bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, |
1246 | struct ib_cq *ib_cq); | |
1247 | enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); | |
1248 | void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, | |
1249 | struct hns_roce_cq *recv_cq); | |
1250 | void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, | |
1251 | struct hns_roce_cq *recv_cq); | |
1252 | void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); | |
1253 | void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); | |
1254 | void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn, | |
1255 | int cnt); | |
f696bf6d | 1256 | __be32 send_ieth(const struct ib_send_wr *wr); |
9a443537 | 1257 | int to_hr_qp_type(int qp_type); |
1258 | ||
707783ab YL |
1259 | int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, |
1260 | struct ib_udata *udata); | |
9a443537 | 1261 | |
707783ab YL |
1262 | void hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); |
1263 | void hns_roce_free_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq); | |
9a443537 | 1264 | |
b0ea0fa5 JG |
1265 | int hns_roce_db_map_user(struct hns_roce_ucontext *context, |
1266 | struct ib_udata *udata, unsigned long virt, | |
e088a685 YL |
1267 | struct hns_roce_db *db); |
1268 | void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, | |
1269 | struct hns_roce_db *db); | |
472bc0fb YL |
1270 | int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, |
1271 | int order); | |
1272 | void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); | |
1273 | ||
9a443537 | 1274 | void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); |
1275 | void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); | |
1276 | void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); | |
81fce629 | 1277 | void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); |
9a443537 | 1278 | int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); |
626903e9 | 1279 | void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); |
08805fdb WHX |
1280 | int hns_roce_init(struct hns_roce_dev *hr_dev); |
1281 | void hns_roce_exit(struct hns_roce_dev *hr_dev); | |
9a443537 | 1282 | |
e1c9a0dc LO |
1283 | int hns_roce_fill_res_entry(struct sk_buff *msg, |
1284 | struct rdma_restrack_entry *res); | |
9a443537 | 1285 | #endif /* _HNS_ROCE_DEVICE_H */ |