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9a443537 | 1 | /* |
2 | * Copyright (c) 2016 Hisilicon Limited. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef _HNS_ROCE_DEVICE_H | |
34 | #define _HNS_ROCE_DEVICE_H | |
35 | ||
36 | #include <rdma/ib_verbs.h> | |
53ef4999 | 37 | #include <rdma/hns-abi.h> |
9a443537 | 38 | |
a247fd28 | 39 | #define PCI_REVISION_ID_HIP08 0x21 |
247fc16d | 40 | #define PCI_REVISION_ID_HIP09 0x30 |
2a3d923f | 41 | |
9a443537 | 42 | #define HNS_ROCE_MAX_MSG_LEN 0x80000000 |
43 | ||
9a443537 | 44 | #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 |
45 | ||
2a3d923f LO |
46 | #define BA_BYTE_LEN 8 |
47 | ||
9a443537 | 48 | #define HNS_ROCE_MIN_CQE_NUM 0x40 |
6ee00fbf | 49 | #define HNS_ROCE_MIN_SRQ_WQE_NUM 1 |
9a443537 | 50 | |
b16f8188 | 51 | #define HNS_ROCE_MAX_IRQ_NUM 128 |
9a443537 | 52 | |
2a3d923f LO |
53 | #define HNS_ROCE_SGE_IN_WQE 2 |
54 | #define HNS_ROCE_SGE_SHIFT 4 | |
55 | ||
b16f8188 YL |
56 | #define EQ_ENABLE 1 |
57 | #define EQ_DISABLE 0 | |
9a443537 | 58 | |
b16f8188 YL |
59 | #define HNS_ROCE_CEQ 0 |
60 | #define HNS_ROCE_AEQ 1 | |
61 | ||
247fc16d WL |
62 | #define HNS_ROCE_CEQE_SIZE 0x4 |
63 | #define HNS_ROCE_AEQE_SIZE 0x10 | |
64 | ||
65 | #define HNS_ROCE_V3_EQE_SIZE 0x40 | |
9a443537 | 66 | |
09a5f210 WL |
67 | #define HNS_ROCE_V2_CQE_SIZE 32 |
68 | #define HNS_ROCE_V3_CQE_SIZE 64 | |
69 | ||
98912ee8 WL |
70 | #define HNS_ROCE_V2_QPC_SZ 256 |
71 | #define HNS_ROCE_V3_QPC_SZ 512 | |
72 | ||
9a443537 | 73 | #define HNS_ROCE_MAX_PORTS 6 |
9a443537 | 74 | #define HNS_ROCE_GID_SIZE 16 |
2a3d923f | 75 | #define HNS_ROCE_SGE_SIZE 16 |
01584a5e | 76 | #define HNS_ROCE_DWQE_SIZE 65536 |
9a443537 | 77 | |
a25d13cb SX |
78 | #define HNS_ROCE_HOP_NUM_0 0xff |
79 | ||
9a443537 | 80 | #define MR_TYPE_MR 0x00 |
68a997c5 | 81 | #define MR_TYPE_FRMR 0x01 |
9a443537 | 82 | #define MR_TYPE_DMA 0x03 |
83 | ||
68a997c5 YL |
84 | #define HNS_ROCE_FRMR_MAX_PA 512 |
85 | ||
9a443537 | 86 | #define PKEY_ID 0xffff |
87 | #define NODE_DESC_SIZE 64 | |
509bf0c2 | 88 | #define DB_REG_OFFSET 0x1000 |
9a443537 | 89 | |
5e6e78db YL |
90 | /* Configure to HW for PAGE_SIZE larger than 4KB */ |
91 | #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) | |
92 | ||
c7bcb134 LO |
93 | #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 |
94 | #define SRQ_DB_REG 0x230 | |
95 | ||
71586dd2 | 96 | #define HNS_ROCE_QP_BANK_NUM 8 |
1bbd4380 YL |
97 | #define HNS_ROCE_CQ_BANK_NUM 4 |
98 | ||
99 | #define CQ_BANKID_SHIFT 2 | |
71586dd2 | 100 | |
5e049a5d LO |
101 | enum { |
102 | SERV_TYPE_RC, | |
103 | SERV_TYPE_UC, | |
104 | SERV_TYPE_RD, | |
105 | SERV_TYPE_UD, | |
32548870 | 106 | SERV_TYPE_XRC = 5, |
5e049a5d LO |
107 | }; |
108 | ||
9a443537 | 109 | enum hns_roce_qp_state { |
110 | HNS_ROCE_QP_STATE_RST, | |
111 | HNS_ROCE_QP_STATE_INIT, | |
112 | HNS_ROCE_QP_STATE_RTR, | |
113 | HNS_ROCE_QP_STATE_RTS, | |
114 | HNS_ROCE_QP_STATE_SQD, | |
115 | HNS_ROCE_QP_STATE_ERR, | |
116 | HNS_ROCE_QP_NUM_STATE, | |
117 | }; | |
118 | ||
119 | enum hns_roce_event { | |
120 | HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, | |
121 | HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, | |
122 | HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, | |
123 | HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, | |
124 | HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
125 | HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, | |
126 | HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, | |
127 | HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, | |
128 | HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, | |
129 | HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, | |
130 | HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, | |
131 | HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, | |
132 | HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, | |
133 | HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, | |
134 | /* 0x10 and 0x11 is unused in currently application case */ | |
135 | HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, | |
136 | HNS_ROCE_EVENT_TYPE_MB = 0x13, | |
a5073d60 | 137 | HNS_ROCE_EVENT_TYPE_FLR = 0x15, |
32548870 WL |
138 | HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, |
139 | HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, | |
9a443537 | 140 | }; |
141 | ||
30661322 WL |
142 | #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 |
143 | ||
a2c80b7b WHX |
144 | enum { |
145 | HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), | |
023c1477 | 146 | HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), |
e088a685 | 147 | HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), |
cf8cd4cc YL |
148 | HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), |
149 | HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), | |
d16da119 | 150 | HNS_ROCE_CAP_FLAG_SRQ = BIT(5), |
32548870 | 151 | HNS_ROCE_CAP_FLAG_XRC = BIT(6), |
c7c28191 | 152 | HNS_ROCE_CAP_FLAG_MW = BIT(7), |
68a997c5 | 153 | HNS_ROCE_CAP_FLAG_FRMR = BIT(8), |
aa84fa18 | 154 | HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), |
384f8818 | 155 | HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), |
0045e0d3 | 156 | HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12), |
aba457ca | 157 | HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), |
bfefae9f | 158 | HNS_ROCE_CAP_FLAG_STASH = BIT(17), |
a2c80b7b WHX |
159 | }; |
160 | ||
2a3d923f LO |
161 | #define HNS_ROCE_DB_TYPE_COUNT 2 |
162 | #define HNS_ROCE_DB_UNIT_SIZE 4 | |
163 | ||
e088a685 YL |
164 | enum { |
165 | HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 | |
166 | }; | |
167 | ||
d061effc WHX |
168 | enum hns_roce_reset_stage { |
169 | HNS_ROCE_STATE_NON_RST, | |
170 | HNS_ROCE_STATE_RST_BEF_DOWN, | |
171 | HNS_ROCE_STATE_RST_DOWN, | |
172 | HNS_ROCE_STATE_RST_UNINIT, | |
173 | HNS_ROCE_STATE_RST_INIT, | |
174 | HNS_ROCE_STATE_RST_INITED, | |
175 | }; | |
176 | ||
177 | enum hns_roce_instance_state { | |
178 | HNS_ROCE_STATE_NON_INIT, | |
179 | HNS_ROCE_STATE_INIT, | |
180 | HNS_ROCE_STATE_INITED, | |
181 | HNS_ROCE_STATE_UNINIT, | |
182 | }; | |
183 | ||
184 | enum { | |
185 | HNS_ROCE_RST_DIRECT_RETURN = 0, | |
186 | }; | |
187 | ||
9a443537 | 188 | #define HNS_ROCE_CMD_SUCCESS 1 |
189 | ||
9581a356 XW |
190 | /* The minimum page size is 4K for hardware */ |
191 | #define HNS_HW_PAGE_SHIFT 12 | |
192 | #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) | |
9a443537 | 193 | |
194 | struct hns_roce_uar { | |
195 | u64 pfn; | |
196 | unsigned long index; | |
5b6eb54f | 197 | unsigned long logic_idx; |
9a443537 | 198 | }; |
199 | ||
6d202d9f CT |
200 | enum hns_roce_mmap_type { |
201 | HNS_ROCE_MMAP_TYPE_DB = 1, | |
0045e0d3 | 202 | HNS_ROCE_MMAP_TYPE_DWQE, |
6d202d9f CT |
203 | }; |
204 | ||
205 | struct hns_user_mmap_entry { | |
206 | struct rdma_user_mmap_entry rdma_entry; | |
207 | enum hns_roce_mmap_type mmap_type; | |
208 | u64 address; | |
209 | }; | |
210 | ||
9a443537 | 211 | struct hns_roce_ucontext { |
212 | struct ib_ucontext ibucontext; | |
213 | struct hns_roce_uar uar; | |
e088a685 YL |
214 | struct list_head page_list; |
215 | struct mutex page_mutex; | |
6d202d9f | 216 | struct hns_user_mmap_entry *db_mmap_entry; |
9a443537 | 217 | }; |
218 | ||
219 | struct hns_roce_pd { | |
220 | struct ib_pd ibpd; | |
221 | unsigned long pdn; | |
222 | }; | |
223 | ||
32548870 WL |
224 | struct hns_roce_xrcd { |
225 | struct ib_xrcd ibxrcd; | |
226 | u32 xrcdn; | |
227 | }; | |
228 | ||
9a443537 | 229 | struct hns_roce_bitmap { |
230 | /* Bitmap Traversal last a bit which is 1 */ | |
231 | unsigned long last; | |
232 | unsigned long top; | |
233 | unsigned long max; | |
234 | unsigned long reserved_top; | |
235 | unsigned long mask; | |
236 | spinlock_t lock; | |
237 | unsigned long *table; | |
238 | }; | |
239 | ||
d38936f0 YL |
240 | struct hns_roce_ida { |
241 | struct ida ida; | |
242 | u32 min; /* Lowest ID to allocate. */ | |
243 | u32 max; /* Highest ID to allocate. */ | |
244 | }; | |
245 | ||
9a443537 | 246 | /* For Hardware Entry Memory */ |
247 | struct hns_roce_hem_table { | |
248 | /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ | |
249 | u32 type; | |
250 | /* HEM array elment num */ | |
251 | unsigned long num_hem; | |
6def7de6 | 252 | /* Single obj size */ |
9a443537 | 253 | unsigned long obj_size; |
29a1fe5d | 254 | unsigned long table_chunk_size; |
9a443537 | 255 | int lowmem; |
256 | struct mutex mutex; | |
257 | struct hns_roce_hem **hem; | |
a25d13cb SX |
258 | u64 **bt_l1; |
259 | dma_addr_t *bt_l1_dma_addr; | |
260 | u64 **bt_l0; | |
261 | dma_addr_t *bt_l0_dma_addr; | |
9a443537 | 262 | }; |
263 | ||
38389eaa | 264 | struct hns_roce_buf_region { |
dcdc366a | 265 | u32 offset; /* page offset */ |
6def7de6 | 266 | u32 count; /* page count */ |
38389eaa LO |
267 | int hopnum; /* addressing hop num */ |
268 | }; | |
269 | ||
270 | #define HNS_ROCE_MAX_BT_REGION 3 | |
271 | #define HNS_ROCE_MAX_BT_LEVEL 3 | |
272 | struct hns_roce_hem_list { | |
273 | struct list_head root_bt; | |
274 | /* link all bt dma mem by hop config */ | |
275 | struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; | |
276 | struct list_head btm_bt; /* link all bottom bt in @mid_bt */ | |
277 | dma_addr_t root_ba; /* pointer to the root ba table */ | |
3c873161 XW |
278 | }; |
279 | ||
280 | struct hns_roce_buf_attr { | |
281 | struct { | |
282 | size_t size; /* region size */ | |
283 | int hopnum; /* multi-hop addressing hop num */ | |
284 | } region[HNS_ROCE_MAX_BT_REGION]; | |
dcdc366a | 285 | unsigned int region_count; /* valid region count */ |
82d07a4e | 286 | unsigned int page_shift; /* buffer page shift */ |
dcdc366a | 287 | unsigned int user_access; /* umem access flag */ |
3c873161 | 288 | bool mtt_only; /* only alloc buffer-required MTT memory */ |
38389eaa LO |
289 | }; |
290 | ||
cc33b23e XW |
291 | struct hns_roce_hem_cfg { |
292 | dma_addr_t root_ba; /* root BA table's address */ | |
293 | bool is_direct; /* addressing without BA table */ | |
294 | unsigned int ba_pg_shift; /* BA table page shift */ | |
295 | unsigned int buf_pg_shift; /* buffer page shift */ | |
296 | unsigned int buf_pg_count; /* buffer page count */ | |
297 | struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; | |
dcdc366a | 298 | unsigned int region_count; |
cc33b23e XW |
299 | }; |
300 | ||
38389eaa LO |
301 | /* memory translate region */ |
302 | struct hns_roce_mtr { | |
3c873161 | 303 | struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ |
82d07a4e WL |
304 | struct ib_umem *umem; /* user space buffer */ |
305 | struct hns_roce_buf *kmem; /* kernel space buffer */ | |
cc33b23e | 306 | struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ |
38389eaa LO |
307 | }; |
308 | ||
c7c28191 YL |
309 | struct hns_roce_mw { |
310 | struct ib_mw ibmw; | |
311 | u32 pdn; | |
312 | u32 rkey; | |
313 | int enabled; /* MW's active status */ | |
314 | u32 pbl_hop_num; | |
315 | u32 pbl_ba_pg_sz; | |
316 | u32 pbl_buf_pg_sz; | |
317 | }; | |
318 | ||
9a443537 | 319 | struct hns_roce_mr { |
320 | struct ib_mr ibmr; | |
f176199d | 321 | u64 iova; /* MR's virtual original addr */ |
9a443537 | 322 | u64 size; /* Address range of MR */ |
323 | u32 key; /* Key of MR */ | |
324 | u32 pd; /* PD num of MR */ | |
3aecfc38 | 325 | u32 access; /* Access permission of MR */ |
9a443537 | 326 | int enabled; /* MR's active status */ |
3aecfc38 XL |
327 | int type; /* MR's register type */ |
328 | u32 pbl_hop_num; /* multi-hop number */ | |
9b2cf76c XW |
329 | struct hns_roce_mtr pbl_mtr; |
330 | u32 npages; | |
331 | dma_addr_t *page_list; | |
9a443537 | 332 | }; |
333 | ||
334 | struct hns_roce_mr_table { | |
d38936f0 | 335 | struct hns_roce_ida mtpt_ida; |
9a443537 | 336 | struct hns_roce_hem_table mtpt_table; |
337 | }; | |
338 | ||
339 | struct hns_roce_wq { | |
340 | u64 *wrid; /* Work request ID */ | |
341 | spinlock_t lock; | |
47688202 | 342 | u32 wqe_cnt; /* WQE num */ |
dcdc366a | 343 | u32 max_gs; |
9dd05247 | 344 | u32 rsv_sge; |
d147583e XL |
345 | u32 offset; |
346 | u32 wqe_shift; /* WQE size */ | |
9a443537 | 347 | u32 head; |
348 | u32 tail; | |
704d68f5 | 349 | void __iomem *db_reg; |
9a443537 | 350 | }; |
351 | ||
926a01dc | 352 | struct hns_roce_sge { |
3aecfc38 | 353 | unsigned int sge_cnt; /* SGE num */ |
d147583e XL |
354 | u32 offset; |
355 | u32 sge_shift; /* SGE size */ | |
926a01dc WHX |
356 | }; |
357 | ||
9a443537 | 358 | struct hns_roce_buf_list { |
359 | void *buf; | |
360 | dma_addr_t map; | |
361 | }; | |
362 | ||
6f6e2dcb XW |
363 | /* |
364 | * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous | |
365 | * dma address range. | |
366 | * | |
367 | * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. | |
368 | * | |
369 | * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even | |
370 | * the allocated size is smaller than the required size. | |
371 | */ | |
372 | enum { | |
373 | HNS_ROCE_BUF_DIRECT = BIT(0), | |
374 | HNS_ROCE_BUF_NOSLEEP = BIT(1), | |
375 | HNS_ROCE_BUF_NOFAIL = BIT(2), | |
376 | }; | |
377 | ||
9a443537 | 378 | struct hns_roce_buf { |
6f6e2dcb XW |
379 | struct hns_roce_buf_list *trunk_list; |
380 | u32 ntrunks; | |
9a443537 | 381 | u32 npages; |
6f6e2dcb | 382 | unsigned int trunk_shift; |
82d07a4e | 383 | unsigned int page_shift; |
9a443537 | 384 | }; |
385 | ||
e088a685 YL |
386 | struct hns_roce_db_pgdir { |
387 | struct list_head list; | |
388 | DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); | |
2a3d923f LO |
389 | DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); |
390 | unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; | |
e088a685 YL |
391 | u32 *page; |
392 | dma_addr_t db_dma; | |
393 | }; | |
394 | ||
395 | struct hns_roce_user_db_page { | |
396 | struct list_head list; | |
397 | struct ib_umem *umem; | |
398 | unsigned long user_virt; | |
399 | refcount_t refcount; | |
400 | }; | |
401 | ||
402 | struct hns_roce_db { | |
403 | u32 *db_record; | |
404 | union { | |
405 | struct hns_roce_db_pgdir *pgdir; | |
406 | struct hns_roce_user_db_page *user_page; | |
407 | } u; | |
408 | dma_addr_t dma; | |
0425e3e6 | 409 | void *virt_addr; |
dcdc366a WL |
410 | unsigned long index; |
411 | unsigned long order; | |
e088a685 YL |
412 | }; |
413 | ||
9a443537 | 414 | struct hns_roce_cq { |
415 | struct ib_cq ib_cq; | |
744b7bdf | 416 | struct hns_roce_mtr mtr; |
9b44703d | 417 | struct hns_roce_db db; |
05e6a5a6 | 418 | u32 flags; |
9a443537 | 419 | spinlock_t lock; |
9a443537 | 420 | u32 cq_depth; |
421 | u32 cons_index; | |
86188a88 | 422 | u32 *set_ci_db; |
704d68f5 | 423 | void __iomem *db_reg; |
26beb85f | 424 | int arm_sn; |
09a5f210 | 425 | int cqe_size; |
9a443537 | 426 | unsigned long cqn; |
427 | u32 vector; | |
cc9e5a84 | 428 | refcount_t refcount; |
9a443537 | 429 | struct completion free; |
626903e9 XW |
430 | struct list_head sq_list; /* all qps on this send cq */ |
431 | struct list_head rq_list; /* all qps on this recv cq */ | |
432 | int is_armed; /* cq is armed */ | |
433 | struct list_head node; /* all armed cqs are on a list */ | |
9a443537 | 434 | }; |
435 | ||
c7bcb134 | 436 | struct hns_roce_idx_que { |
6fd610c5 | 437 | struct hns_roce_mtr mtr; |
d147583e | 438 | u32 entry_shift; |
97545b10 | 439 | unsigned long *bitmap; |
1620f09b WL |
440 | u32 head; |
441 | u32 tail; | |
c7bcb134 LO |
442 | }; |
443 | ||
9a443537 | 444 | struct hns_roce_srq { |
445 | struct ib_srq ibsrq; | |
c7bcb134 | 446 | unsigned long srqn; |
d938d785 | 447 | u32 wqe_cnt; |
c7bcb134 | 448 | int max_gs; |
9dd05247 | 449 | u32 rsv_sge; |
d147583e | 450 | u32 wqe_shift; |
0fee4516 | 451 | u32 cqn; |
32548870 | 452 | u32 xrcdn; |
704d68f5 | 453 | void __iomem *db_reg; |
c7bcb134 | 454 | |
33649cd3 | 455 | refcount_t refcount; |
c7bcb134 LO |
456 | struct completion free; |
457 | ||
6fd610c5 XW |
458 | struct hns_roce_mtr buf_mtr; |
459 | ||
c7bcb134 | 460 | u64 *wrid; |
c7bcb134 LO |
461 | struct hns_roce_idx_que idx_que; |
462 | spinlock_t lock; | |
c7bcb134 | 463 | struct mutex mutex; |
d938d785 | 464 | void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); |
9a443537 | 465 | }; |
466 | ||
467 | struct hns_roce_uar_table { | |
468 | struct hns_roce_bitmap bitmap; | |
469 | }; | |
470 | ||
71586dd2 YL |
471 | struct hns_roce_bank { |
472 | struct ida ida; | |
473 | u32 inuse; /* Number of IDs allocated */ | |
474 | u32 min; /* Lowest ID to allocate. */ | |
475 | u32 max; /* Highest ID to allocate. */ | |
476 | u32 next; /* Next ID to allocate. */ | |
477 | }; | |
478 | ||
eb653eda JH |
479 | struct hns_roce_idx_table { |
480 | u32 *spare_idx; | |
481 | u32 head; | |
482 | u32 tail; | |
483 | }; | |
484 | ||
9a443537 | 485 | struct hns_roce_qp_table { |
9a443537 | 486 | struct hns_roce_hem_table qp_table; |
487 | struct hns_roce_hem_table irrl_table; | |
e92f2c18 | 488 | struct hns_roce_hem_table trrl_table; |
6a157f7d | 489 | struct hns_roce_hem_table sccc_table; |
aa84fa18 | 490 | struct mutex scc_mutex; |
71586dd2 | 491 | struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; |
9293d3fc | 492 | struct mutex bank_mutex; |
eb653eda | 493 | struct hns_roce_idx_table idx_table; |
9a443537 | 494 | }; |
495 | ||
496 | struct hns_roce_cq_table { | |
27e19f45 | 497 | struct xarray array; |
9a443537 | 498 | struct hns_roce_hem_table table; |
1bbd4380 YL |
499 | struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; |
500 | struct mutex bank_mutex; | |
9a443537 | 501 | }; |
502 | ||
5c1f167a | 503 | struct hns_roce_srq_table { |
c4f11b36 | 504 | struct hns_roce_ida srq_ida; |
5c1f167a LO |
505 | struct xarray xa; |
506 | struct hns_roce_hem_table table; | |
507 | }; | |
508 | ||
9a443537 | 509 | struct hns_roce_av { |
074bf2c2 WL |
510 | u8 port; |
511 | u8 gid_index; | |
512 | u8 stat_rate; | |
513 | u8 hop_limit; | |
514 | u32 flowlabel; | |
515 | u16 udp_sport; | |
516 | u8 sl; | |
517 | u8 tclass; | |
518 | u8 dgid[HNS_ROCE_GID_SIZE]; | |
519 | u8 mac[ETH_ALEN]; | |
520 | u16 vlan_id; | |
7406c003 | 521 | u8 vlan_en; |
9a443537 | 522 | }; |
523 | ||
524 | struct hns_roce_ah { | |
525 | struct ib_ah ibah; | |
526 | struct hns_roce_av av; | |
527 | }; | |
528 | ||
529 | struct hns_roce_cmd_context { | |
530 | struct completion done; | |
531 | int result; | |
532 | int next; | |
533 | u64 out_param; | |
534 | u16 token; | |
a389d016 | 535 | u16 busy; |
9a443537 | 536 | }; |
537 | ||
538 | struct hns_roce_cmdq { | |
539 | struct dma_pool *pool; | |
9a443537 | 540 | struct semaphore poll_sem; |
541 | /* | |
e84e40be S |
542 | * Event mode: cmd register mutex protection, |
543 | * ensure to not exceed max_cmds and user use limit region | |
544 | */ | |
9a443537 | 545 | struct semaphore event_sem; |
546 | int max_cmds; | |
547 | spinlock_t context_lock; | |
548 | int free_head; | |
549 | struct hns_roce_cmd_context *context; | |
9a443537 | 550 | /* |
e84e40be S |
551 | * Process whether use event mode, init default non-zero |
552 | * After the event queue of cmd event ready, | |
553 | * can switch into event mode | |
554 | * close device, switch into poll mode(non event mode) | |
555 | */ | |
9a443537 | 556 | u8 use_events; |
9a443537 | 557 | }; |
558 | ||
bfcc681b SX |
559 | struct hns_roce_cmd_mailbox { |
560 | void *buf; | |
561 | dma_addr_t dma; | |
562 | }; | |
563 | ||
9a443537 | 564 | struct hns_roce_dev; |
565 | ||
0009c2db | 566 | struct hns_roce_rinl_sge { |
567 | void *addr; | |
568 | u32 len; | |
569 | }; | |
570 | ||
571 | struct hns_roce_rinl_wqe { | |
572 | struct hns_roce_rinl_sge *sg_list; | |
573 | u32 sge_cnt; | |
574 | }; | |
575 | ||
576 | struct hns_roce_rinl_buf { | |
577 | struct hns_roce_rinl_wqe *wqe_list; | |
578 | u32 wqe_cnt; | |
579 | }; | |
580 | ||
b5374286 YL |
581 | enum { |
582 | HNS_ROCE_FLUSH_FLAG = 0, | |
583 | }; | |
584 | ||
ffd541d4 YL |
585 | struct hns_roce_work { |
586 | struct hns_roce_dev *hr_dev; | |
587 | struct work_struct work; | |
ffd541d4 YL |
588 | int event_type; |
589 | int sub_type; | |
d8cc403b | 590 | u32 queue_num; |
ffd541d4 YL |
591 | }; |
592 | ||
9a443537 | 593 | struct hns_roce_qp { |
594 | struct ib_qp ibqp; | |
9a443537 | 595 | struct hns_roce_wq rq; |
e088a685 | 596 | struct hns_roce_db rdb; |
0425e3e6 | 597 | struct hns_roce_db sdb; |
90ae0b57 | 598 | unsigned long en_flags; |
8b9b8d14 | 599 | u32 doorbell_qpn; |
ea4092f3 | 600 | enum ib_sig_type sq_signal_bits; |
9a443537 | 601 | struct hns_roce_wq sq; |
602 | ||
8d18ad83 | 603 | struct hns_roce_mtr mtr; |
8d18ad83 | 604 | |
9a443537 | 605 | u32 buff_size; |
606 | struct mutex mutex; | |
607 | u8 port; | |
7716809e | 608 | u8 phy_port; |
9a443537 | 609 | u8 sl; |
610 | u8 resp_depth; | |
611 | u8 state; | |
ace1c541 | 612 | u32 atomic_rd_en; |
0fa95a9a | 613 | u32 qkey; |
fd012f1c | 614 | void (*event)(struct hns_roce_qp *qp, |
615 | enum hns_roce_event event_type); | |
9a443537 | 616 | unsigned long qpn; |
617 | ||
32548870 WL |
618 | u32 xrcdn; |
619 | ||
8f9513d8 | 620 | refcount_t refcount; |
9a443537 | 621 | struct completion free; |
926a01dc WHX |
622 | |
623 | struct hns_roce_sge sge; | |
624 | u32 next_sge; | |
30b70788 WL |
625 | enum ib_mtu path_mtu; |
626 | u32 max_inline_data; | |
0009c2db | 627 | |
b5374286 YL |
628 | /* 0: flush needed, 1: unneeded */ |
629 | unsigned long flush_flag; | |
ffd541d4 | 630 | struct hns_roce_work flush_work; |
0009c2db | 631 | struct hns_roce_rinl_buf rq_inl_buf; |
3aecfc38 XL |
632 | struct list_head node; /* all qps are on a list */ |
633 | struct list_head rq_node; /* all recv qps are on a list */ | |
634 | struct list_head sq_node; /* all send qps are on a list */ | |
0045e0d3 | 635 | struct hns_user_mmap_entry *dwqe_mmap_entry; |
9a443537 | 636 | }; |
637 | ||
9a443537 | 638 | struct hns_roce_ib_iboe { |
639 | spinlock_t lock; | |
640 | struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; | |
641 | struct notifier_block nb; | |
9a443537 | 642 | u8 phy_port[HNS_ROCE_MAX_PORTS]; |
643 | }; | |
644 | ||
b16f8188 | 645 | struct hns_roce_ceqe { |
247fc16d WL |
646 | __le32 comp; |
647 | __le32 rsv[15]; | |
b16f8188 YL |
648 | }; |
649 | ||
650 | struct hns_roce_aeqe { | |
0576cbde | 651 | __le32 asyn; |
b16f8188 YL |
652 | union { |
653 | struct { | |
d8cc403b | 654 | __le32 num; |
b16f8188 YL |
655 | u32 rsv0; |
656 | u32 rsv1; | |
d8cc403b | 657 | } queue_event; |
b16f8188 YL |
658 | |
659 | struct { | |
660 | __le64 out_param; | |
661 | __le16 token; | |
662 | u8 status; | |
663 | u8 rsv0; | |
664 | } __packed cmd; | |
665 | } event; | |
247fc16d | 666 | __le32 rsv[12]; |
b16f8188 YL |
667 | }; |
668 | ||
9a443537 | 669 | struct hns_roce_eq { |
670 | struct hns_roce_dev *hr_dev; | |
704d68f5 | 671 | void __iomem *db_reg; |
9a443537 | 672 | |
6def7de6 | 673 | int type_flag; /* Aeq:1 ceq:0 */ |
9a443537 | 674 | int eqn; |
675 | u32 entries; | |
9a443537 | 676 | int eqe_size; |
677 | int irq; | |
dcdc366a | 678 | u32 cons_index; |
a5073d60 YL |
679 | int over_ignore; |
680 | int coalesce; | |
681 | int arm_st; | |
a5073d60 | 682 | int hop_num; |
d7e2d343 | 683 | struct hns_roce_mtr mtr; |
13aa13dd | 684 | u16 eq_max_cnt; |
dcdc366a | 685 | u32 eq_period; |
a5073d60 | 686 | int shift; |
0425e3e6 YL |
687 | int event_type; |
688 | int sub_type; | |
9a443537 | 689 | }; |
690 | ||
691 | struct hns_roce_eq_table { | |
692 | struct hns_roce_eq *eq; | |
9a443537 | 693 | }; |
694 | ||
f91696f2 YL |
695 | enum cong_type { |
696 | CONG_TYPE_DCQCN, | |
697 | CONG_TYPE_LDCP, | |
698 | CONG_TYPE_HC3, | |
699 | CONG_TYPE_DIP, | |
700 | }; | |
701 | ||
9a443537 | 702 | struct hns_roce_caps { |
3a63c964 | 703 | u64 fw_ver; |
9a443537 | 704 | u8 num_ports; |
705 | int gid_table_len[HNS_ROCE_MAX_PORTS]; | |
706 | int pkey_table_len[HNS_ROCE_MAX_PORTS]; | |
707 | int local_ca_ack_delay; | |
708 | int num_uars; | |
709 | u32 phy_num_uars; | |
6def7de6 LC |
710 | u32 max_sq_sg; |
711 | u32 max_sq_inline; | |
712 | u32 max_rq_sg; | |
05ad5482 | 713 | u32 max_extend_sg; |
dcdc366a | 714 | u32 num_qps; |
61b460d1 | 715 | u32 num_pi_qps; |
dcdc366a | 716 | u32 reserved_qps; |
0e40dc2f YL |
717 | int num_qpc_timer; |
718 | int num_cqc_timer; | |
d147583e | 719 | u32 num_srqs; |
6def7de6 | 720 | u32 max_wqes; |
d16da119 LO |
721 | u32 max_srq_wrs; |
722 | u32 max_srq_sges; | |
6def7de6 LC |
723 | u32 max_sq_desc_sz; |
724 | u32 max_rq_desc_sz; | |
cfc85f3e | 725 | u32 max_srq_desc_sz; |
9a443537 | 726 | int max_qp_init_rdma; |
727 | int max_qp_dest_rdma; | |
dcdc366a | 728 | u32 num_cqs; |
e2b2744a YL |
729 | u32 max_cqes; |
730 | u32 min_cqes; | |
926a01dc | 731 | u32 min_wqes; |
1bbd4380 | 732 | u32 reserved_cqs; |
d147583e | 733 | u32 reserved_srqs; |
6def7de6 | 734 | int num_aeq_vectors; |
a5073d60 | 735 | int num_comp_vectors; |
9a443537 | 736 | int num_other_vectors; |
dcdc366a | 737 | u32 num_mtpts; |
9a443537 | 738 | u32 num_mtt_segs; |
5c1f167a LO |
739 | u32 num_srqwqe_segs; |
740 | u32 num_idx_segs; | |
9a443537 | 741 | int reserved_mrws; |
742 | int reserved_uars; | |
743 | int num_pds; | |
744 | int reserved_pds; | |
32548870 WL |
745 | u32 num_xrcds; |
746 | u32 reserved_xrcds; | |
9a443537 | 747 | u32 mtt_entry_sz; |
09a5f210 | 748 | u32 cqe_sz; |
9a443537 | 749 | u32 page_size_cap; |
750 | u32 reserved_lkey; | |
751 | int mtpt_entry_sz; | |
98912ee8 | 752 | int qpc_sz; |
9a443537 | 753 | int irrl_entry_sz; |
e92f2c18 | 754 | int trrl_entry_sz; |
9a443537 | 755 | int cqc_entry_sz; |
3cb2c996 | 756 | int sccc_sz; |
0e40dc2f YL |
757 | int qpc_timer_entry_sz; |
758 | int cqc_timer_entry_sz; | |
5c1f167a LO |
759 | int srqc_entry_sz; |
760 | int idx_entry_sz; | |
ff795f71 WHX |
761 | u32 pbl_ba_pg_sz; |
762 | u32 pbl_buf_pg_sz; | |
763 | u32 pbl_hop_num; | |
9a443537 | 764 | int aeqe_depth; |
b16f8188 | 765 | int ceqe_depth; |
247fc16d WL |
766 | u32 aeqe_size; |
767 | u32 ceqe_size; | |
9a443537 | 768 | enum ib_mtu max_mtu; |
cfc85f3e | 769 | u32 qpc_bt_num; |
0e40dc2f | 770 | u32 qpc_timer_bt_num; |
cfc85f3e WHX |
771 | u32 srqc_bt_num; |
772 | u32 cqc_bt_num; | |
0e40dc2f | 773 | u32 cqc_timer_bt_num; |
cfc85f3e | 774 | u32 mpt_bt_num; |
2a424e1d WX |
775 | u32 eqc_bt_num; |
776 | u32 smac_bt_num; | |
777 | u32 sgid_bt_num; | |
6a157f7d | 778 | u32 sccc_bt_num; |
d6d91e46 | 779 | u32 gmv_bt_num; |
a25d13cb SX |
780 | u32 qpc_ba_pg_sz; |
781 | u32 qpc_buf_pg_sz; | |
782 | u32 qpc_hop_num; | |
783 | u32 srqc_ba_pg_sz; | |
784 | u32 srqc_buf_pg_sz; | |
785 | u32 srqc_hop_num; | |
786 | u32 cqc_ba_pg_sz; | |
787 | u32 cqc_buf_pg_sz; | |
788 | u32 cqc_hop_num; | |
789 | u32 mpt_ba_pg_sz; | |
790 | u32 mpt_buf_pg_sz; | |
791 | u32 mpt_hop_num; | |
6a93c77a SX |
792 | u32 mtt_ba_pg_sz; |
793 | u32 mtt_buf_pg_sz; | |
794 | u32 mtt_hop_num; | |
8d18ad83 LO |
795 | u32 wqe_sq_hop_num; |
796 | u32 wqe_sge_hop_num; | |
797 | u32 wqe_rq_hop_num; | |
6a157f7d YL |
798 | u32 sccc_ba_pg_sz; |
799 | u32 sccc_buf_pg_sz; | |
800 | u32 sccc_hop_num; | |
0e40dc2f YL |
801 | u32 qpc_timer_ba_pg_sz; |
802 | u32 qpc_timer_buf_pg_sz; | |
803 | u32 qpc_timer_hop_num; | |
804 | u32 cqc_timer_ba_pg_sz; | |
805 | u32 cqc_timer_buf_pg_sz; | |
806 | u32 cqc_timer_hop_num; | |
3aecfc38 | 807 | u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ |
6a93c77a SX |
808 | u32 cqe_buf_pg_sz; |
809 | u32 cqe_hop_num; | |
c7bcb134 LO |
810 | u32 srqwqe_ba_pg_sz; |
811 | u32 srqwqe_buf_pg_sz; | |
812 | u32 srqwqe_hop_num; | |
813 | u32 idx_ba_pg_sz; | |
814 | u32 idx_buf_pg_sz; | |
815 | u32 idx_hop_num; | |
a5073d60 YL |
816 | u32 eqe_ba_pg_sz; |
817 | u32 eqe_buf_pg_sz; | |
818 | u32 eqe_hop_num; | |
d6d91e46 WL |
819 | u32 gmv_entry_num; |
820 | u32 gmv_entry_sz; | |
821 | u32 gmv_ba_pg_sz; | |
822 | u32 gmv_buf_pg_sz; | |
823 | u32 gmv_hop_num; | |
6b63597d | 824 | u32 sl_num; |
b6989da8 | 825 | u32 llm_buf_pg_sz; |
3aecfc38 | 826 | u32 chunk_sz; /* chunk size in non multihop mode */ |
a2c80b7b | 827 | u64 flags; |
ba6bb7e9 LO |
828 | u16 default_ceq_max_cnt; |
829 | u16 default_ceq_period; | |
830 | u16 default_aeq_max_cnt; | |
831 | u16 default_aeq_period; | |
832 | u16 default_aeq_arm_st; | |
833 | u16 default_ceq_arm_st; | |
f91696f2 | 834 | enum cong_type cong_type; |
9a443537 | 835 | }; |
836 | ||
e1c9a0dc LO |
837 | struct hns_roce_dfx_hw { |
838 | int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, | |
839 | int *buffer); | |
840 | }; | |
841 | ||
626903e9 XW |
842 | enum hns_roce_device_state { |
843 | HNS_ROCE_DEVICE_STATE_INITED, | |
844 | HNS_ROCE_DEVICE_STATE_RST_DOWN, | |
845 | HNS_ROCE_DEVICE_STATE_UNINIT, | |
846 | }; | |
847 | ||
9a443537 | 848 | struct hns_roce_hw { |
a04ff739 WHX |
849 | int (*cmq_init)(struct hns_roce_dev *hr_dev); |
850 | void (*cmq_exit)(struct hns_roce_dev *hr_dev); | |
cfc85f3e | 851 | int (*hw_profile)(struct hns_roce_dev *hr_dev); |
9a443537 | 852 | int (*hw_init)(struct hns_roce_dev *hr_dev); |
853 | void (*hw_exit)(struct hns_roce_dev *hr_dev); | |
a680f2f3 | 854 | int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, |
5a32949d | 855 | u64 out_param, u32 in_modifier, u16 op, |
a680f2f3 | 856 | u16 token, int event); |
0018ed4b | 857 | int (*poll_mbox_done)(struct hns_roce_dev *hr_dev); |
ee82e688 | 858 | bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); |
38d22088 | 859 | int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index, |
f4df9a7c | 860 | const union ib_gid *gid, const struct ib_gid_attr *attr); |
fd92213e JK |
861 | int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, |
862 | const u8 *addr); | |
98a61519 | 863 | int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, |
38d22088 | 864 | struct hns_roce_mr *mr); |
a2c80b7b | 865 | int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, |
4e9fc1da | 866 | struct hns_roce_mr *mr, int flags, |
a2c80b7b | 867 | void *mb_buf); |
98a61519 YL |
868 | int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, |
869 | struct hns_roce_mr *mr); | |
c7c28191 | 870 | int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); |
9a443537 | 871 | void (*write_cqc)(struct hns_roce_dev *hr_dev, |
872 | struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, | |
e2b2744a | 873 | dma_addr_t dma_handle); |
a25d13cb SX |
874 | int (*set_hem)(struct hns_roce_dev *hr_dev, |
875 | struct hns_roce_hem_table *table, int obj, int step_idx); | |
97f0e39f | 876 | int (*clear_hem)(struct hns_roce_dev *hr_dev, |
a25d13cb SX |
877 | struct hns_roce_hem_table *table, int obj, |
878 | int step_idx); | |
9a443537 | 879 | int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, |
880 | int attr_mask, enum ib_qp_state cur_state, | |
881 | enum ib_qp_state new_state); | |
aa84fa18 YL |
882 | int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, |
883 | struct hns_roce_qp *hr_qp); | |
b16f8188 YL |
884 | int (*init_eq)(struct hns_roce_dev *hr_dev); |
885 | void (*cleanup_eq)(struct hns_roce_dev *hr_dev); | |
eacb45ca | 886 | int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); |
7f645a58 KH |
887 | const struct ib_device_ops *hns_roce_dev_ops; |
888 | const struct ib_device_ops *hns_roce_dev_srq_ops; | |
9a443537 | 889 | }; |
890 | ||
891 | struct hns_roce_dev { | |
892 | struct ib_device ib_dev; | |
dd74282d WHX |
893 | struct pci_dev *pci_dev; |
894 | struct device *dev; | |
9a443537 | 895 | struct hns_roce_uar priv_uar; |
528f1deb | 896 | const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; |
9a443537 | 897 | spinlock_t sm_lock; |
cb7a94c9 WHX |
898 | bool active; |
899 | bool is_reset; | |
d3743fa9 | 900 | bool dis_db; |
d061effc | 901 | unsigned long reset_cnt; |
9a443537 | 902 | struct hns_roce_ib_iboe iboe; |
626903e9 XW |
903 | enum hns_roce_device_state state; |
904 | struct list_head qp_list; /* list of all qps on this dev */ | |
905 | spinlock_t qp_list_lock; /* protect qp_list */ | |
f91696f2 YL |
906 | struct list_head dip_list; /* list of all dest ips on this dev */ |
907 | spinlock_t dip_list_lock; /* protect dip_list */ | |
9a443537 | 908 | |
472bc0fb YL |
909 | struct list_head pgdir_list; |
910 | struct mutex pgdir_mutex; | |
9a443537 | 911 | int irq[HNS_ROCE_MAX_IRQ_NUM]; |
912 | u8 __iomem *reg_base; | |
01584a5e | 913 | void __iomem *mem_base; |
9a443537 | 914 | struct hns_roce_caps caps; |
736b5a70 | 915 | struct xarray qp_table_xa; |
9a443537 | 916 | |
2a3d923f | 917 | unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; |
9a443537 | 918 | u64 sys_image_guid; |
919 | u32 vendor_id; | |
920 | u32 vendor_part_id; | |
921 | u32 hw_rev; | |
922 | void __iomem *priv_addr; | |
923 | ||
924 | struct hns_roce_cmdq cmd; | |
645f0593 | 925 | struct hns_roce_ida pd_ida; |
da43b7be | 926 | struct hns_roce_ida xrcd_ida; |
8feafd90 | 927 | struct hns_roce_ida uar_ida; |
9a443537 | 928 | struct hns_roce_mr_table mr_table; |
929 | struct hns_roce_cq_table cq_table; | |
5c1f167a | 930 | struct hns_roce_srq_table srq_table; |
9a443537 | 931 | struct hns_roce_qp_table qp_table; |
932 | struct hns_roce_eq_table eq_table; | |
0e40dc2f YL |
933 | struct hns_roce_hem_table qpc_timer_table; |
934 | struct hns_roce_hem_table cqc_timer_table; | |
d6d91e46 WL |
935 | /* GMV is the memory area that the driver allocates for the hardware |
936 | * to store SGID, SMAC and VLAN information. | |
937 | */ | |
938 | struct hns_roce_hem_table gmv_table; | |
9a443537 | 939 | |
940 | int cmd_mod; | |
941 | int loop_idc; | |
2d407888 WHX |
942 | u32 sdb_offset; |
943 | u32 odb_offset; | |
08805fdb | 944 | const struct hns_roce_hw *hw; |
016a0059 | 945 | void *priv; |
0425e3e6 | 946 | struct workqueue_struct *irq_workq; |
e1c9a0dc | 947 | const struct hns_roce_dfx_hw *dfx; |
5b03a422 | 948 | u32 func_num; |
0b567cde | 949 | u32 is_vf; |
e079d87d | 950 | u32 cong_algo_tmpl_id; |
0045e0d3 | 951 | u64 dwqe_page; |
9a443537 | 952 | }; |
953 | ||
954 | static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) | |
955 | { | |
956 | return container_of(ib_dev, struct hns_roce_dev, ib_dev); | |
957 | } | |
958 | ||
959 | static inline struct hns_roce_ucontext | |
960 | *to_hr_ucontext(struct ib_ucontext *ibucontext) | |
961 | { | |
962 | return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); | |
963 | } | |
964 | ||
965 | static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) | |
966 | { | |
967 | return container_of(ibpd, struct hns_roce_pd, ibpd); | |
968 | } | |
969 | ||
32548870 WL |
970 | static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) |
971 | { | |
972 | return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); | |
973 | } | |
974 | ||
9a443537 | 975 | static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) |
976 | { | |
977 | return container_of(ibah, struct hns_roce_ah, ibah); | |
978 | } | |
979 | ||
980 | static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) | |
981 | { | |
982 | return container_of(ibmr, struct hns_roce_mr, ibmr); | |
983 | } | |
984 | ||
c7c28191 YL |
985 | static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) |
986 | { | |
987 | return container_of(ibmw, struct hns_roce_mw, ibmw); | |
988 | } | |
989 | ||
9a443537 | 990 | static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) |
991 | { | |
992 | return container_of(ibqp, struct hns_roce_qp, ibqp); | |
993 | } | |
994 | ||
995 | static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) | |
996 | { | |
997 | return container_of(ib_cq, struct hns_roce_cq, ib_cq); | |
998 | } | |
999 | ||
1000 | static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) | |
1001 | { | |
1002 | return container_of(ibsrq, struct hns_roce_srq, ibsrq); | |
1003 | } | |
1004 | ||
6d202d9f CT |
1005 | static inline struct hns_user_mmap_entry * |
1006 | to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry) | |
1007 | { | |
1008 | return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry); | |
1009 | } | |
1010 | ||
0576cbde | 1011 | static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) |
9a443537 | 1012 | { |
86f767e6 | 1013 | writeq(*(u64 *)val, dest); |
9a443537 | 1014 | } |
1015 | ||
1016 | static inline struct hns_roce_qp | |
1017 | *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) | |
1018 | { | |
61b460d1 | 1019 | return xa_load(&hr_dev->qp_table_xa, qpn); |
9a443537 | 1020 | } |
1021 | ||
dcdc366a WL |
1022 | static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, |
1023 | unsigned int offset) | |
9a443537 | 1024 | { |
6f6e2dcb XW |
1025 | return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + |
1026 | (offset & ((1 << buf->trunk_shift) - 1)); | |
cc23267a XW |
1027 | } |
1028 | ||
7b0006db XW |
1029 | static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf, |
1030 | unsigned int offset) | |
cc23267a | 1031 | { |
6f6e2dcb XW |
1032 | return buf->trunk_list[offset >> buf->trunk_shift].map + |
1033 | (offset & ((1 << buf->trunk_shift) - 1)); | |
9a443537 | 1034 | } |
1035 | ||
7b0006db XW |
1036 | static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) |
1037 | { | |
1038 | return hns_roce_buf_dma_addr(buf, idx << buf->page_shift); | |
1039 | } | |
1040 | ||
9581a356 | 1041 | #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) |
54d66387 | 1042 | |
3c873161 XW |
1043 | static inline u64 to_hr_hw_page_addr(u64 addr) |
1044 | { | |
9581a356 | 1045 | return addr >> HNS_HW_PAGE_SHIFT; |
3c873161 XW |
1046 | } |
1047 | ||
1048 | static inline u32 to_hr_hw_page_shift(u32 page_shift) | |
1049 | { | |
9581a356 | 1050 | return page_shift - HNS_HW_PAGE_SHIFT; |
3c873161 XW |
1051 | } |
1052 | ||
54d66387 XW |
1053 | static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) |
1054 | { | |
1055 | if (count > 0) | |
1056 | return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; | |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) | |
1062 | { | |
1063 | return hr_hw_page_align(count << buf_shift); | |
1064 | } | |
1065 | ||
1066 | static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) | |
1067 | { | |
1068 | return hr_hw_page_align(count << buf_shift) >> buf_shift; | |
1069 | } | |
1070 | ||
1071 | static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) | |
1072 | { | |
d4d81387 WL |
1073 | if (!count) |
1074 | return 0; | |
1075 | ||
54d66387 XW |
1076 | return ilog2(to_hr_hem_entries_count(count, buf_shift)); |
1077 | } | |
1078 | ||
603bee93 WL |
1079 | #define DSCP_SHIFT 2 |
1080 | ||
1081 | static inline u8 get_tclass(const struct ib_global_route *grh) | |
1082 | { | |
1083 | return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? | |
1084 | grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; | |
1085 | } | |
1086 | ||
8feafd90 | 1087 | void hns_roce_init_uar_table(struct hns_roce_dev *dev); |
9a443537 | 1088 | int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); |
9a443537 | 1089 | |
1090 | int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); | |
1091 | void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); | |
1092 | void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, | |
1093 | u64 out_param); | |
1094 | int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); | |
1095 | void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); | |
1096 | ||
38389eaa LO |
1097 | /* hns roce hw need current block and next block addr from mtt */ |
1098 | #define MTT_MIN_COUNT 2 | |
1099 | int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
d147583e | 1100 | u32 offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); |
3c873161 | 1101 | int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, |
82d07a4e WL |
1102 | struct hns_roce_buf_attr *buf_attr, |
1103 | unsigned int page_shift, struct ib_udata *udata, | |
1104 | unsigned long user_addr); | |
3c873161 XW |
1105 | void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, |
1106 | struct hns_roce_mtr *mtr); | |
1107 | int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
dcdc366a | 1108 | dma_addr_t *pages, unsigned int page_cnt); |
38389eaa | 1109 | |
645f0593 | 1110 | void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); |
d38936f0 | 1111 | void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); |
1bbd4380 | 1112 | void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); |
eb653eda | 1113 | int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); |
c4f11b36 | 1114 | void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); |
da43b7be | 1115 | void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); |
9a443537 | 1116 | |
9a443537 | 1117 | void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); |
1118 | void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); | |
1119 | void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); | |
1120 | ||
9a443537 | 1121 | void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); |
9a443537 | 1122 | |
fa5d010c MG |
1123 | int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, |
1124 | struct ib_udata *udata); | |
90898850 | 1125 | int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); |
9a9ebf8c LR |
1126 | static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) |
1127 | { | |
1128 | return 0; | |
1129 | } | |
9a443537 | 1130 | |
ff23dfa1 | 1131 | int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); |
91a7c58f | 1132 | int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); |
9a443537 | 1133 | |
1134 | struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); | |
1135 | struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
1136 | u64 virt_addr, int access_flags, | |
1137 | struct ib_udata *udata); | |
6e0954b1 JG |
1138 | struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, |
1139 | u64 length, u64 virt_addr, | |
1140 | int mr_access_flags, struct ib_pd *pd, | |
1141 | struct ib_udata *udata); | |
68a997c5 | 1142 | struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, |
42a3b153 | 1143 | u32 max_num_sg); |
68a997c5 YL |
1144 | int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
1145 | unsigned int *sg_offset); | |
c4367a26 | 1146 | int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); |
6eef5242 | 1147 | int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, |
6eef5242 | 1148 | unsigned long mpt_index); |
bfcc681b | 1149 | unsigned long key_to_hw_index(u32 key); |
9a443537 | 1150 | |
d18bb3e1 | 1151 | int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); |
c7c28191 YL |
1152 | int hns_roce_dealloc_mw(struct ib_mw *ibmw); |
1153 | ||
cc23267a | 1154 | void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); |
6f6e2dcb XW |
1155 | struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, |
1156 | u32 page_shift, u32 flags); | |
9a443537 | 1157 | |
2ac0bc5e | 1158 | int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, |
7b0006db XW |
1159 | int buf_cnt, struct hns_roce_buf *buf, |
1160 | unsigned int page_shift); | |
2ac0bc5e | 1161 | int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, |
7b0006db | 1162 | int buf_cnt, struct ib_umem *umem, |
82d07a4e | 1163 | unsigned int page_shift); |
2ac0bc5e | 1164 | |
68e326de LR |
1165 | int hns_roce_create_srq(struct ib_srq *srq, |
1166 | struct ib_srq_init_attr *srq_init_attr, | |
1167 | struct ib_udata *udata); | |
c7bcb134 LO |
1168 | int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, |
1169 | enum ib_srq_attr_mask srq_attr_mask, | |
1170 | struct ib_udata *udata); | |
119181d1 | 1171 | int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); |
c7bcb134 | 1172 | |
32548870 WL |
1173 | int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); |
1174 | int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); | |
1175 | ||
514aee66 LR |
1176 | int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr, |
1177 | struct ib_udata *udata); | |
9a443537 | 1178 | int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, |
1179 | int attr_mask, struct ib_udata *udata); | |
ffd541d4 | 1180 | void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); |
dcdc366a WL |
1181 | void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); |
1182 | void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); | |
1183 | void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); | |
1184 | bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, | |
9a443537 | 1185 | struct ib_cq *ib_cq); |
1186 | enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); | |
1187 | void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, | |
1188 | struct hns_roce_cq *recv_cq); | |
1189 | void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, | |
1190 | struct hns_roce_cq *recv_cq); | |
1191 | void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); | |
e365b26c XW |
1192 | void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, |
1193 | struct ib_udata *udata); | |
f696bf6d | 1194 | __be32 send_ieth(const struct ib_send_wr *wr); |
9a443537 | 1195 | int to_hr_qp_type(int qp_type); |
1196 | ||
707783ab YL |
1197 | int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, |
1198 | struct ib_udata *udata); | |
9a443537 | 1199 | |
43d781b9 | 1200 | int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); |
69e0a42f | 1201 | int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, |
e088a685 YL |
1202 | struct hns_roce_db *db); |
1203 | void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, | |
1204 | struct hns_roce_db *db); | |
472bc0fb YL |
1205 | int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, |
1206 | int order); | |
1207 | void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); | |
1208 | ||
9a443537 | 1209 | void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); |
1210 | void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); | |
c462a024 | 1211 | void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp); |
9a443537 | 1212 | void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); |
81fce629 | 1213 | void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); |
1fb7f897 | 1214 | u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index); |
626903e9 | 1215 | void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); |
08805fdb WHX |
1216 | int hns_roce_init(struct hns_roce_dev *hr_dev); |
1217 | void hns_roce_exit(struct hns_roce_dev *hr_dev); | |
9e2a187a MG |
1218 | int hns_roce_fill_res_cq_entry(struct sk_buff *msg, |
1219 | struct ib_cq *ib_cq); | |
6d202d9f CT |
1220 | struct hns_user_mmap_entry * |
1221 | hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, | |
1222 | size_t length, | |
1223 | enum hns_roce_mmap_type mmap_type); | |
9a443537 | 1224 | #endif /* _HNS_ROCE_DEVICE_H */ |