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RDMA/hns: Generate gid type of RoCEv2
[linux-block.git] / drivers / infiniband / hw / hns / hns_roce_device.h
CommitLineData
9a443537 1/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _HNS_ROCE_DEVICE_H
34#define _HNS_ROCE_DEVICE_H
35
36#include <rdma/ib_verbs.h>
37
38#define DRV_NAME "hns_roce"
39
8f3e9f3e
WHX		 40#define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
41
9a443537 42#define MAC_ADDR_OCTET_NUM 6
43#define HNS_ROCE_MAX_MSG_LEN 0x80000000
44
45#define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b))
46
47#define HNS_ROCE_IB_MIN_SQ_STRIDE 6
48
49#define HNS_ROCE_BA_SIZE (32 * 4096)
50
51/* Hardware specification only for v1 engine */
52#define HNS_ROCE_MIN_CQE_NUM 0x40
53#define HNS_ROCE_MIN_WQE_NUM 0x20
54
55/* Hardware specification only for v1 engine */
56#define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7
57#define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000
58
afb6b092
SX		 59#define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20
60#define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \
61 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
62#define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
63#define HNS_ROCE_MIN_CQE_CNT 16
64
9a443537 65#define HNS_ROCE_MAX_IRQ_NUM 34
66
67#define HNS_ROCE_COMP_VEC_NUM 32
68
69#define HNS_ROCE_AEQE_VEC_NUM 1
70#define HNS_ROCE_AEQE_OF_VEC_NUM 1
71
72/* 4G/4K = 1M */
ac11125b 73#define HNS_ROCE_SL_SHIFT 28
9a443537 74#define HNS_ROCE_TCLASS_SHIFT 20
75#define HNS_ROCE_FLOW_LABLE_MASK 0xfffff
76
77#define HNS_ROCE_MAX_PORTS 6
78#define HNS_ROCE_MAX_GID_NUM 16
79#define HNS_ROCE_GID_SIZE 16
80
a25d13cb
SX		 81#define HNS_ROCE_HOP_NUM_0 0xff
82
5e6ff78a
WHX		 83#define BITMAP_NO_RR 0
84#define BITMAP_RR 1
85
9a443537 86#define MR_TYPE_MR 0x00
87#define MR_TYPE_DMA 0x03
88
89#define PKEY_ID 0xffff
31644665 90#define GUID_LEN 8
9a443537 91#define NODE_DESC_SIZE 64
509bf0c2 92#define DB_REG_OFFSET 0x1000
9a443537 93
94#define SERV_TYPE_RC 0
95#define SERV_TYPE_RD 1
96#define SERV_TYPE_UC 2
97#define SERV_TYPE_UD 3
98
99#define PAGES_SHIFT_8 8
100#define PAGES_SHIFT_16 16
101#define PAGES_SHIFT_24 24
102#define PAGES_SHIFT_32 32
103
104enum hns_roce_qp_state {
105 HNS_ROCE_QP_STATE_RST,
106 HNS_ROCE_QP_STATE_INIT,
107 HNS_ROCE_QP_STATE_RTR,
108 HNS_ROCE_QP_STATE_RTS,
109 HNS_ROCE_QP_STATE_SQD,
110 HNS_ROCE_QP_STATE_ERR,
111 HNS_ROCE_QP_NUM_STATE,
112};
113
114enum hns_roce_event {
115 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
116 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
117 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
118 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
119 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
120 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
121 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
122 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
123 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
124 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
125 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
126 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
127 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
128 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
129 /* 0x10 and 0x11 is unused in currently application case */
130 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
131 HNS_ROCE_EVENT_TYPE_MB = 0x13,
132 HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14,
133};
134
135/* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
136enum {
137 HNS_ROCE_LWQCE_QPC_ERROR = 1,
138 HNS_ROCE_LWQCE_MTU_ERROR = 2,
139 HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3,
140 HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4,
141 HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5,
142 HNS_ROCE_LWQCE_SL_ERROR = 6,
143 HNS_ROCE_LWQCE_PORT_ERROR = 7,
144};
145
146/* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
147enum {
148 HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1,
149 HNS_ROCE_LAVWQE_LENGTH_ERROR = 2,
150 HNS_ROCE_LAVWQE_VA_ERROR = 3,
151 HNS_ROCE_LAVWQE_PD_ERROR = 4,
152 HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5,
153 HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6,
154 HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7,
155};
156
157/* DOORBELL overflow subtype */
158enum {
159 HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1,
160 HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2,
161 HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3,
162 HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4,
163 HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5,
164 HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6,
165};
166
167enum {
168 /* RQ&SRQ related operations */
169 HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06,
170 HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07,
171};
172
a2c80b7b
WHX		 173enum {
174 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
023c1477 175 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
a2c80b7b
WHX		 176};
177
9766edc3 178enum hns_roce_mtt_type {
400d324a 179 MTT_TYPE_WQE,
9766edc3
SX		 180 MTT_TYPE_CQE,
181};
182
9a443537 183#define HNS_ROCE_CMD_SUCCESS 1
184
185#define HNS_ROCE_PORT_DOWN 0
186#define HNS_ROCE_PORT_UP 1
187
188#define HNS_ROCE_MTT_ENTRY_PER_SEG 8
189
190#define PAGE_ADDR_SHIFT 12
191
192struct hns_roce_uar {
193 u64 pfn;
194 unsigned long index;
195};
196
197struct hns_roce_ucontext {
198 struct ib_ucontext ibucontext;
199 struct hns_roce_uar uar;
200};
201
202struct hns_roce_pd {
203 struct ib_pd ibpd;
204 unsigned long pdn;
205};
206
207struct hns_roce_bitmap {
208 /* Bitmap Traversal last a bit which is 1 */
209 unsigned long last;
210 unsigned long top;
211 unsigned long max;
212 unsigned long reserved_top;
213 unsigned long mask;
214 spinlock_t lock;
215 unsigned long *table;
216};
217
218/* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */
219/* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */
220/* Every bit repesent to a partner free/used status in bitmap */
221/*
e84e40be
S		 222 * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1
223 * Bit = 1 represent to idle and available; bit = 0: not available
224 */
9a443537 225struct hns_roce_buddy {
226 /* Members point to every order level bitmap */
227 unsigned long **bits;
228 /* Represent to avail bits of the order level bitmap */
229 u32 *num_free;
230 int max_order;
231 spinlock_t lock;
232};
233
234/* For Hardware Entry Memory */
235struct hns_roce_hem_table {
236 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
237 u32 type;
238 /* HEM array elment num */
239 unsigned long num_hem;
240 /* HEM entry record obj total num */
241 unsigned long num_obj;
242 /*Single obj size */
243 unsigned long obj_size;
29a1fe5d 244 unsigned long table_chunk_size;
9a443537 245 int lowmem;
246 struct mutex mutex;
247 struct hns_roce_hem **hem;
a25d13cb
SX		 248 u64 **bt_l1;
249 dma_addr_t *bt_l1_dma_addr;
250 u64 **bt_l0;
251 dma_addr_t *bt_l0_dma_addr;
9a443537 252};
253
254struct hns_roce_mtt {
9766edc3
SX		 255 unsigned long first_seg;
256 int order;
257 int page_shift;
258 enum hns_roce_mtt_type mtt_type;
9a443537 259};
260
261/* Only support 4K page size for mr register */
262#define MR_SIZE_4K 0
263
264struct hns_roce_mr {
265 struct ib_mr ibmr;
266 struct ib_umem *umem;
267 u64 iova; /* MR's virtual orignal addr */
268 u64 size; /* Address range of MR */
269 u32 key; /* Key of MR */
270 u32 pd; /* PD num of MR */
271 u32 access;/* Access permission of MR */
272 int enabled; /* MR's active status */
273 int type; /* MR's register type */
274 u64 *pbl_buf;/* MR's PBL space */
275 dma_addr_t pbl_dma_addr; /* MR's PBL space PA */
ff795f71
WHX		 276 u32 pbl_size;/* PA number in the PBL */
277 u64 pbl_ba;/* page table address */
278 u32 l0_chunk_last_num;/* L0 last number */
279 u32 l1_chunk_last_num;/* L1 last number */
280 u64 **pbl_bt_l2;/* PBL BT L2 */
281 u64 **pbl_bt_l1;/* PBL BT L1 */
282 u64 *pbl_bt_l0;/* PBL BT L0 */
283 dma_addr_t *pbl_l2_dma_addr;/* PBL BT L2 dma addr */
284 dma_addr_t *pbl_l1_dma_addr;/* PBL BT L1 dma addr */
285 dma_addr_t pbl_l0_dma_addr;/* PBL BT L0 dma addr */
286 u32 pbl_ba_pg_sz;/* BT chunk page size */
287 u32 pbl_buf_pg_sz;/* buf chunk page size */
288 u32 pbl_hop_num;/* multi-hop number */
9a443537 289};
290
291struct hns_roce_mr_table {
292 struct hns_roce_bitmap mtpt_bitmap;
293 struct hns_roce_buddy mtt_buddy;
294 struct hns_roce_hem_table mtt_table;
295 struct hns_roce_hem_table mtpt_table;
9766edc3
SX		 296 struct hns_roce_buddy mtt_cqe_buddy;
297 struct hns_roce_hem_table mtt_cqe_table;
9a443537 298};
299
300struct hns_roce_wq {
301 u64 *wrid; /* Work request ID */
302 spinlock_t lock;
303 int wqe_cnt; /* WQE num */
304 u32 max_post;
305 int max_gs;
306 int offset;
307 int wqe_shift;/* WQE size */
308 u32 head;
309 u32 tail;
310 void __iomem *db_reg_l;
311};
312
926a01dc
WHX		 313struct hns_roce_sge {
314 int sge_cnt; /* SGE num */
315 int offset;
316 int sge_shift;/* SGE size */
317};
318
9a443537 319struct hns_roce_buf_list {
320 void *buf;
321 dma_addr_t map;
322};
323
324struct hns_roce_buf {
325 struct hns_roce_buf_list direct;
326 struct hns_roce_buf_list *page_list;
327 int nbufs;
328 u32 npages;
329 int page_shift;
330};
331
332struct hns_roce_cq_buf {
333 struct hns_roce_buf hr_buf;
334 struct hns_roce_mtt hr_mtt;
335};
336
9a443537 337struct hns_roce_cq {
338 struct ib_cq ib_cq;
339 struct hns_roce_cq_buf hr_buf;
9a443537 340 spinlock_t lock;
9a443537 341 struct ib_umem *umem;
9a443537 342 void (*comp)(struct hns_roce_cq *);
343 void (*event)(struct hns_roce_cq *, enum hns_roce_event);
344
345 struct hns_roce_uar *uar;
346 u32 cq_depth;
347 u32 cons_index;
348 void __iomem *cq_db_l;
8f3e9f3e 349 u16 *tptr_addr;
9a443537 350 unsigned long cqn;
351 u32 vector;
352 atomic_t refcount;
353 struct completion free;
354};
355
356struct hns_roce_srq {
357 struct ib_srq ibsrq;
358 int srqn;
359};
360
361struct hns_roce_uar_table {
362 struct hns_roce_bitmap bitmap;
363};
364
365struct hns_roce_qp_table {
366 struct hns_roce_bitmap bitmap;
367 spinlock_t lock;
368 struct hns_roce_hem_table qp_table;
369 struct hns_roce_hem_table irrl_table;
370};
371
372struct hns_roce_cq_table {
373 struct hns_roce_bitmap bitmap;
374 spinlock_t lock;
375 struct radix_tree_root tree;
376 struct hns_roce_hem_table table;
377};
378
379struct hns_roce_raq_table {
380 struct hns_roce_buf_list *e_raq_buf;
381};
382
383struct hns_roce_av {
384 __le32 port_pd;
385 u8 gid_index;
386 u8 stat_rate;
387 u8 hop_limit;
388 __le32 sl_tclass_flowlabel;
389 u8 dgid[HNS_ROCE_GID_SIZE];
390 u8 mac[6];
391 __le16 vlan;
392};
393
394struct hns_roce_ah {
395 struct ib_ah ibah;
396 struct hns_roce_av av;
397};
398
399struct hns_roce_cmd_context {
400 struct completion done;
401 int result;
402 int next;
403 u64 out_param;
404 u16 token;
405};
406
407struct hns_roce_cmdq {
408 struct dma_pool *pool;
9a443537 409 struct mutex hcr_mutex;
410 struct semaphore poll_sem;
411 /*
e84e40be
S		 412 * Event mode: cmd register mutex protection,
413 * ensure to not exceed max_cmds and user use limit region
414 */
9a443537 415 struct semaphore event_sem;
416 int max_cmds;
417 spinlock_t context_lock;
418 int free_head;
419 struct hns_roce_cmd_context *context;
420 /*
e84e40be
S		 421 * Result of get integer part
422 * which max_comds compute according a power of 2
423 */
9a443537 424 u16 token_mask;
425 /*
e84e40be
S		 426 * Process whether use event mode, init default non-zero
427 * After the event queue of cmd event ready,
428 * can switch into event mode
429 * close device, switch into poll mode(non event mode)
430 */
9a443537 431 u8 use_events;
432 u8 toggle;
433};
434
bfcc681b
SX		 435struct hns_roce_cmd_mailbox {
436 void *buf;
437 dma_addr_t dma;
438};
439
9a443537 440struct hns_roce_dev;
441
442struct hns_roce_qp {
443 struct ib_qp ibqp;
444 struct hns_roce_buf hr_buf;
445 struct hns_roce_wq rq;
446 __le64 doorbell_qpn;
447 __le32 sq_signal_bits;
448 u32 sq_next_wqe;
449 int sq_max_wqes_per_wr;
450 int sq_spare_wqes;
451 struct hns_roce_wq sq;
452
453 struct ib_umem *umem;
454 struct hns_roce_mtt mtt;
455 u32 buff_size;
456 struct mutex mutex;
457 u8 port;
7716809e 458 u8 phy_port;
9a443537 459 u8 sl;
460 u8 resp_depth;
461 u8 state;
462 u32 access_flags;
463 u32 pkey_index;
464 void (*event)(struct hns_roce_qp *,
465 enum hns_roce_event);
466 unsigned long qpn;
467
468 atomic_t refcount;
469 struct completion free;
926a01dc
WHX		 470
471 struct hns_roce_sge sge;
472 u32 next_sge;
9a443537 473};
474
475struct hns_roce_sqp {
476 struct hns_roce_qp hr_qp;
477};
478
479struct hns_roce_ib_iboe {
480 spinlock_t lock;
481 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
482 struct notifier_block nb;
9a443537 483 u8 phy_port[HNS_ROCE_MAX_PORTS];
484};
485
486struct hns_roce_eq {
487 struct hns_roce_dev *hr_dev;
488 void __iomem *doorbell;
489
490 int type_flag;/* Aeq:1 ceq:0 */
491 int eqn;
492 u32 entries;
493 int log_entries;
494 int eqe_size;
495 int irq;
496 int log_page_size;
497 int cons_index;
498 struct hns_roce_buf_list *buf_list;
499};
500
501struct hns_roce_eq_table {
502 struct hns_roce_eq *eq;
503 void __iomem **eqc_base;
504};
505
506struct hns_roce_caps {
507 u8 num_ports;
508 int gid_table_len[HNS_ROCE_MAX_PORTS];
509 int pkey_table_len[HNS_ROCE_MAX_PORTS];
510 int local_ca_ack_delay;
511 int num_uars;
512 u32 phy_num_uars;
513 u32 max_sq_sg; /* 2 */
514 u32 max_sq_inline; /* 32 */
515 u32 max_rq_sg; /* 2 */
516 int num_qps; /* 256k */
517 u32 max_wqes; /* 16k */
518 u32 max_sq_desc_sz; /* 64 */
519 u32 max_rq_desc_sz; /* 64 */
cfc85f3e 520 u32 max_srq_desc_sz;
9a443537 521 int max_qp_init_rdma;
522 int max_qp_dest_rdma;
9a443537 523 int num_cqs;
524 int max_cqes;
93aa2187 525 int min_cqes;
926a01dc 526 u32 min_wqes;
9a443537 527 int reserved_cqs;
528 int num_aeq_vectors; /* 1 */
529 int num_comp_vectors; /* 32 ceq */
530 int num_other_vectors;
531 int num_mtpts;
532 u32 num_mtt_segs;
cfc85f3e 533 u32 num_cqe_segs;
9a443537 534 int reserved_mrws;
535 int reserved_uars;
536 int num_pds;
537 int reserved_pds;
538 u32 mtt_entry_sz;
539 u32 cq_entry_sz;
540 u32 page_size_cap;
541 u32 reserved_lkey;
542 int mtpt_entry_sz;
543 int qpc_entry_sz;
544 int irrl_entry_sz;
545 int cqc_entry_sz;
ff795f71
WHX		 546 u32 pbl_ba_pg_sz;
547 u32 pbl_buf_pg_sz;
548 u32 pbl_hop_num;
9a443537 549 int aeqe_depth;
550 int ceqe_depth[HNS_ROCE_COMP_VEC_NUM];
551 enum ib_mtu max_mtu;
cfc85f3e
WHX		 552 u32 qpc_bt_num;
553 u32 srqc_bt_num;
554 u32 cqc_bt_num;
555 u32 mpt_bt_num;
a25d13cb
SX		 556 u32 qpc_ba_pg_sz;
557 u32 qpc_buf_pg_sz;
558 u32 qpc_hop_num;
559 u32 srqc_ba_pg_sz;
560 u32 srqc_buf_pg_sz;
561 u32 srqc_hop_num;
562 u32 cqc_ba_pg_sz;
563 u32 cqc_buf_pg_sz;
564 u32 cqc_hop_num;
565 u32 mpt_ba_pg_sz;
566 u32 mpt_buf_pg_sz;
567 u32 mpt_hop_num;
6a93c77a
SX		 568 u32 mtt_ba_pg_sz;
569 u32 mtt_buf_pg_sz;
570 u32 mtt_hop_num;
571 u32 cqe_ba_pg_sz;
572 u32 cqe_buf_pg_sz;
573 u32 cqe_hop_num;
29a1fe5d 574 u32 chunk_sz; /* chunk size in non multihop mode*/
a2c80b7b 575 u64 flags;
9a443537 576};
577
578struct hns_roce_hw {
579 int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
a04ff739
WHX		 580 int (*cmq_init)(struct hns_roce_dev *hr_dev);
581 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
cfc85f3e 582 int (*hw_profile)(struct hns_roce_dev *hr_dev);
9a443537 583 int (*hw_init)(struct hns_roce_dev *hr_dev);
584 void (*hw_exit)(struct hns_roce_dev *hr_dev);
a680f2f3
WHX		 585 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
586 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
587 u16 token, int event);
588 int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
9a443537 589 void (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
590 union ib_gid *gid);
a74dc41d 591 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
9a443537 592 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
593 enum ib_mtu mtu);
594 int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr,
595 unsigned long mtpt_idx);
a2c80b7b
WHX		 596 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
597 struct hns_roce_mr *mr, int flags, u32 pdn,
598 int mr_access_flags, u64 iova, u64 size,
599 void *mb_buf);
9a443537 600 void (*write_cqc)(struct hns_roce_dev *hr_dev,
601 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
602 dma_addr_t dma_handle, int nent, u32 vector);
a25d13cb
SX		 603 int (*set_hem)(struct hns_roce_dev *hr_dev,
604 struct hns_roce_hem_table *table, int obj, int step_idx);
97f0e39f 605 int (*clear_hem)(struct hns_roce_dev *hr_dev,
a25d13cb
SX		 606 struct hns_roce_hem_table *table, int obj,
607 int step_idx);
9a443537 608 int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
609 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
610 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
611 int attr_mask, enum ib_qp_state cur_state,
612 enum ib_qp_state new_state);
613 int (*destroy_qp)(struct ib_qp *ibqp);
614 int (*post_send)(struct ib_qp *ibqp, struct ib_send_wr *wr,
615 struct ib_send_wr **bad_wr);
616 int (*post_recv)(struct ib_qp *qp, struct ib_recv_wr *recv_wr,
617 struct ib_recv_wr **bad_recv_wr);
618 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
619 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
bfcc681b 620 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr);
afb6b092 621 int (*destroy_cq)(struct ib_cq *ibcq);
b156269d 622 int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
9a443537 623};
624
625struct hns_roce_dev {
626 struct ib_device ib_dev;
627 struct platform_device *pdev;
dd74282d
WHX		 628 struct pci_dev *pci_dev;
629 struct device *dev;
9a443537 630 struct hns_roce_uar priv_uar;
528f1deb 631 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
9a443537 632 spinlock_t sm_lock;
9a443537 633 spinlock_t bt_cmd_lock;
634 struct hns_roce_ib_iboe iboe;
635
636 int irq[HNS_ROCE_MAX_IRQ_NUM];
637 u8 __iomem *reg_base;
638 struct hns_roce_caps caps;
639 struct radix_tree_root qp_table_tree;
640
641 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][MAC_ADDR_OCTET_NUM];
642 u64 sys_image_guid;
643 u32 vendor_id;
644 u32 vendor_part_id;
645 u32 hw_rev;
646 void __iomem *priv_addr;
647
648 struct hns_roce_cmdq cmd;
649 struct hns_roce_bitmap pd_bitmap;
650 struct hns_roce_uar_table uar_table;
651 struct hns_roce_mr_table mr_table;
652 struct hns_roce_cq_table cq_table;
653 struct hns_roce_qp_table qp_table;
654 struct hns_roce_eq_table eq_table;
655
656 int cmd_mod;
657 int loop_idc;
2d407888
WHX		 658 u32 sdb_offset;
659 u32 odb_offset;
8f3e9f3e
WHX		 660 dma_addr_t tptr_dma_addr; /*only for hw v1*/
661 u32 tptr_size; /*only for hw v1*/
08805fdb 662 const struct hns_roce_hw *hw;
016a0059 663 void *priv;
9a443537 664};
665
666static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
667{
668 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
669}
670
671static inline struct hns_roce_ucontext
672 *to_hr_ucontext(struct ib_ucontext *ibucontext)
673{
674 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
675}
676
677static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
678{
679 return container_of(ibpd, struct hns_roce_pd, ibpd);
680}
681
682static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
683{
684 return container_of(ibah, struct hns_roce_ah, ibah);
685}
686
687static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
688{
689 return container_of(ibmr, struct hns_roce_mr, ibmr);
690}
691
692static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
693{
694 return container_of(ibqp, struct hns_roce_qp, ibqp);
695}
696
697static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
698{
699 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
700}
701
702static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
703{
704 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
705}
706
707static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp)
708{
709 return container_of(hr_qp, struct hns_roce_sqp, hr_qp);
710}
711
712static inline void hns_roce_write64_k(__be32 val[2], void __iomem *dest)
713{
714 __raw_writeq(*(u64 *) val, dest);
715}
716
717static inline struct hns_roce_qp
718 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
719{
720 return radix_tree_lookup(&hr_dev->qp_table_tree,
721 qpn & (hr_dev->caps.num_qps - 1));
722}
723
724static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
725{
726 u32 bits_per_long_val = BITS_PER_LONG;
9a8982dc 727 u32 page_size = 1 << buf->page_shift;
9a443537 728
9a8982dc
WHX		 729 if ((bits_per_long_val == 64 && buf->page_shift == PAGE_SHIFT) ||
730 buf->nbufs == 1)
9a443537 731 return (char *)(buf->direct.buf) + offset;
732 else
9a8982dc
WHX		 733 return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
734 (offset & (page_size - 1));
9a443537 735}
736
737int hns_roce_init_uar_table(struct hns_roce_dev *dev);
738int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
739void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
740void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
741
742int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
743void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
744void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
745 u64 out_param);
746int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
747void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
748
749int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
750 struct hns_roce_mtt *mtt);
751void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev,
752 struct hns_roce_mtt *mtt);
753int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
754 struct hns_roce_mtt *mtt, struct hns_roce_buf *buf);
755
756int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
757int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
758int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev);
759int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
760int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
761
762void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
763void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
764void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
765void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
766void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
767
768int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
5e6ff78a
WHX		 769void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
770 int rr);
9a443537 771int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
772 u32 reserved_bot, u32 resetrved_top);
773void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
774void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
775int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
776 int align, unsigned long *obj);
777void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
5e6ff78a
WHX		 778 unsigned long obj, int cnt,
779 int rr);
9a443537 780
90898850
DC		 781struct ib_ah *hns_roce_create_ah(struct ib_pd *pd,
782 struct rdma_ah_attr *ah_attr,
477864c8 783 struct ib_udata *udata);
90898850 784int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
9a443537 785int hns_roce_destroy_ah(struct ib_ah *ah);
786
787struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev,
788 struct ib_ucontext *context,
789 struct ib_udata *udata);
790int hns_roce_dealloc_pd(struct ib_pd *pd);
791
792struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
793struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
794 u64 virt_addr, int access_flags,
795 struct ib_udata *udata);
a2c80b7b
WHX		 796int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
797 u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
798 struct ib_udata *udata);
9a443537 799int hns_roce_dereg_mr(struct ib_mr *ibmr);
bfcc681b
SX		 800int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
801 struct hns_roce_cmd_mailbox *mailbox,
802 unsigned long mpt_index);
803unsigned long key_to_hw_index(u32 key);
9a443537 804
805void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
806 struct hns_roce_buf *buf);
807int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
9a8982dc 808 struct hns_roce_buf *buf, u32 page_shift);
9a443537 809
810int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
811 struct hns_roce_mtt *mtt, struct ib_umem *umem);
812
813struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
814 struct ib_qp_init_attr *init_attr,
815 struct ib_udata *udata);
816int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
817 int attr_mask, struct ib_udata *udata);
818void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
819void *get_send_wqe(struct hns_roce_qp *hr_qp, int n);
926a01dc 820void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n);
9a443537 821bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
822 struct ib_cq *ib_cq);
823enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
824void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
825 struct hns_roce_cq *recv_cq);
826void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
827 struct hns_roce_cq *recv_cq);
828void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
829void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
830void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
831 int cnt);
832__be32 send_ieth(struct ib_send_wr *wr);
833int to_hr_qp_type(int qp_type);
834
835struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
836 const struct ib_cq_init_attr *attr,
837 struct ib_ucontext *context,
838 struct ib_udata *udata);
839
840int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq);
afb6b092 841void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq);
9a443537 842
843void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
844void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
845void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
846int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
08805fdb
WHX		 847int hns_roce_init(struct hns_roce_dev *hr_dev);
848void hns_roce_exit(struct hns_roce_dev *hr_dev);
9a443537 849
850#endif /* _HNS_ROCE_DEVICE_H */
Linux 6.x block layer and io_uring tree(s)