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9a443537 | 1 | /* |
2 | * Copyright (c) 2016 Hisilicon Limited. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef _HNS_ROCE_DEVICE_H | |
34 | #define _HNS_ROCE_DEVICE_H | |
35 | ||
36 | #include <rdma/ib_verbs.h> | |
37 | ||
38 | #define DRV_NAME "hns_roce" | |
39 | ||
2a3d923f LO |
40 | /* hip08 is a pci device, it includes two version according pci version id */ |
41 | #define PCI_REVISION_ID_HIP08_A 0x20 | |
42 | #define PCI_REVISION_ID_HIP08_B 0x21 | |
43 | ||
8f3e9f3e WHX |
44 | #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6') |
45 | ||
9a443537 | 46 | #define HNS_ROCE_MAX_MSG_LEN 0x80000000 |
47 | ||
9a443537 | 48 | #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 |
49 | ||
50 | #define HNS_ROCE_BA_SIZE (32 * 4096) | |
51 | ||
2a3d923f LO |
52 | #define BA_BYTE_LEN 8 |
53 | ||
9a443537 | 54 | /* Hardware specification only for v1 engine */ |
55 | #define HNS_ROCE_MIN_CQE_NUM 0x40 | |
56 | #define HNS_ROCE_MIN_WQE_NUM 0x20 | |
57 | ||
58 | /* Hardware specification only for v1 engine */ | |
59 | #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 | |
60 | #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 | |
2a3d923f | 61 | #define HNS_ROCE_MAX_SGE_NUM 2 |
9a443537 | 62 | |
afb6b092 SX |
63 | #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20 |
64 | #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \ | |
65 | (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS) | |
66 | #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 | |
67 | #define HNS_ROCE_MIN_CQE_CNT 16 | |
68 | ||
711195e5 LO |
69 | #define HNS_ROCE_RESERVED_SGE 1 |
70 | ||
b16f8188 | 71 | #define HNS_ROCE_MAX_IRQ_NUM 128 |
9a443537 | 72 | |
2a3d923f LO |
73 | #define HNS_ROCE_SGE_IN_WQE 2 |
74 | #define HNS_ROCE_SGE_SHIFT 4 | |
75 | ||
b16f8188 YL |
76 | #define EQ_ENABLE 1 |
77 | #define EQ_DISABLE 0 | |
9a443537 | 78 | |
b16f8188 YL |
79 | #define HNS_ROCE_CEQ 0 |
80 | #define HNS_ROCE_AEQ 1 | |
81 | ||
82 | #define HNS_ROCE_CEQ_ENTRY_SIZE 0x4 | |
83 | #define HNS_ROCE_AEQ_ENTRY_SIZE 0x10 | |
9a443537 | 84 | |
ac11125b | 85 | #define HNS_ROCE_SL_SHIFT 28 |
9a443537 | 86 | #define HNS_ROCE_TCLASS_SHIFT 20 |
cdfa4ad5 | 87 | #define HNS_ROCE_FLOW_LABEL_MASK 0xfffff |
9a443537 | 88 | |
89 | #define HNS_ROCE_MAX_PORTS 6 | |
90 | #define HNS_ROCE_MAX_GID_NUM 16 | |
91 | #define HNS_ROCE_GID_SIZE 16 | |
2a3d923f | 92 | #define HNS_ROCE_SGE_SIZE 16 |
9a443537 | 93 | |
a25d13cb SX |
94 | #define HNS_ROCE_HOP_NUM_0 0xff |
95 | ||
5e6ff78a WHX |
96 | #define BITMAP_NO_RR 0 |
97 | #define BITMAP_RR 1 | |
98 | ||
9a443537 | 99 | #define MR_TYPE_MR 0x00 |
68a997c5 | 100 | #define MR_TYPE_FRMR 0x01 |
9a443537 | 101 | #define MR_TYPE_DMA 0x03 |
102 | ||
68a997c5 YL |
103 | #define HNS_ROCE_FRMR_MAX_PA 512 |
104 | ||
9a443537 | 105 | #define PKEY_ID 0xffff |
31644665 | 106 | #define GUID_LEN 8 |
9a443537 | 107 | #define NODE_DESC_SIZE 64 |
509bf0c2 | 108 | #define DB_REG_OFFSET 0x1000 |
9a443537 | 109 | |
5e6e78db YL |
110 | /* Configure to HW for PAGE_SIZE larger than 4KB */ |
111 | #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) | |
112 | ||
9a443537 | 113 | #define PAGES_SHIFT_8 8 |
114 | #define PAGES_SHIFT_16 16 | |
115 | #define PAGES_SHIFT_24 24 | |
116 | #define PAGES_SHIFT_32 32 | |
117 | ||
2a3d923f LO |
118 | #define HNS_ROCE_PCI_BAR_NUM 2 |
119 | ||
c7bcb134 LO |
120 | #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 |
121 | #define SRQ_DB_REG 0x230 | |
122 | ||
90c559b1 LO |
123 | /* The chip implementation of the consumer index is calculated |
124 | * according to twice the actual EQ depth | |
125 | */ | |
126 | #define EQ_DEPTH_COEFF 2 | |
127 | ||
5e049a5d LO |
128 | enum { |
129 | SERV_TYPE_RC, | |
130 | SERV_TYPE_UC, | |
131 | SERV_TYPE_RD, | |
132 | SERV_TYPE_UD, | |
133 | }; | |
134 | ||
e088a685 | 135 | enum { |
90ae0b57 LC |
136 | HNS_ROCE_QP_CAP_RQ_RECORD_DB = BIT(0), |
137 | HNS_ROCE_QP_CAP_SQ_RECORD_DB = BIT(1), | |
e088a685 YL |
138 | }; |
139 | ||
05e6a5a6 LC |
140 | enum hns_roce_cq_flags { |
141 | HNS_ROCE_CQ_FLAG_RECORD_DB = BIT(0), | |
9b44703d YL |
142 | }; |
143 | ||
9a443537 | 144 | enum hns_roce_qp_state { |
145 | HNS_ROCE_QP_STATE_RST, | |
146 | HNS_ROCE_QP_STATE_INIT, | |
147 | HNS_ROCE_QP_STATE_RTR, | |
148 | HNS_ROCE_QP_STATE_RTS, | |
149 | HNS_ROCE_QP_STATE_SQD, | |
150 | HNS_ROCE_QP_STATE_ERR, | |
151 | HNS_ROCE_QP_NUM_STATE, | |
152 | }; | |
153 | ||
154 | enum hns_roce_event { | |
155 | HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, | |
156 | HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, | |
157 | HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, | |
158 | HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, | |
159 | HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
160 | HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, | |
161 | HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, | |
162 | HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, | |
163 | HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, | |
164 | HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, | |
165 | HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, | |
166 | HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, | |
167 | HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, | |
168 | HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, | |
169 | /* 0x10 and 0x11 is unused in currently application case */ | |
170 | HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, | |
171 | HNS_ROCE_EVENT_TYPE_MB = 0x13, | |
172 | HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW = 0x14, | |
a5073d60 | 173 | HNS_ROCE_EVENT_TYPE_FLR = 0x15, |
9a443537 | 174 | }; |
175 | ||
176 | /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */ | |
177 | enum { | |
178 | HNS_ROCE_LWQCE_QPC_ERROR = 1, | |
179 | HNS_ROCE_LWQCE_MTU_ERROR = 2, | |
180 | HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR = 3, | |
181 | HNS_ROCE_LWQCE_WQE_ADDR_ERROR = 4, | |
182 | HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR = 5, | |
183 | HNS_ROCE_LWQCE_SL_ERROR = 6, | |
184 | HNS_ROCE_LWQCE_PORT_ERROR = 7, | |
185 | }; | |
186 | ||
187 | /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */ | |
188 | enum { | |
189 | HNS_ROCE_LAVWQE_R_KEY_VIOLATION = 1, | |
190 | HNS_ROCE_LAVWQE_LENGTH_ERROR = 2, | |
191 | HNS_ROCE_LAVWQE_VA_ERROR = 3, | |
192 | HNS_ROCE_LAVWQE_PD_ERROR = 4, | |
193 | HNS_ROCE_LAVWQE_RW_ACC_ERROR = 5, | |
194 | HNS_ROCE_LAVWQE_KEY_STATE_ERROR = 6, | |
195 | HNS_ROCE_LAVWQE_MR_OPERATION_ERROR = 7, | |
196 | }; | |
197 | ||
198 | /* DOORBELL overflow subtype */ | |
199 | enum { | |
200 | HNS_ROCE_DB_SUBTYPE_SDB_OVF = 1, | |
201 | HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF = 2, | |
202 | HNS_ROCE_DB_SUBTYPE_ODB_OVF = 3, | |
203 | HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF = 4, | |
204 | HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP = 5, | |
205 | HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP = 6, | |
206 | }; | |
207 | ||
208 | enum { | |
209 | /* RQ&SRQ related operations */ | |
210 | HNS_ROCE_OPCODE_SEND_DATA_RECEIVE = 0x06, | |
211 | HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE = 0x07, | |
212 | }; | |
213 | ||
30661322 WL |
214 | #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12 |
215 | ||
a2c80b7b WHX |
216 | enum { |
217 | HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), | |
023c1477 | 218 | HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), |
e088a685 | 219 | HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), |
0425e3e6 YL |
220 | HNS_ROCE_CAP_FLAG_RECORD_DB = BIT(3), |
221 | HNS_ROCE_CAP_FLAG_SQ_RECORD_DB = BIT(4), | |
d16da119 | 222 | HNS_ROCE_CAP_FLAG_SRQ = BIT(5), |
c7c28191 | 223 | HNS_ROCE_CAP_FLAG_MW = BIT(7), |
68a997c5 | 224 | HNS_ROCE_CAP_FLAG_FRMR = BIT(8), |
aa84fa18 | 225 | HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), |
384f8818 | 226 | HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), |
a2c80b7b WHX |
227 | }; |
228 | ||
2a3d923f LO |
229 | #define HNS_ROCE_DB_TYPE_COUNT 2 |
230 | #define HNS_ROCE_DB_UNIT_SIZE 4 | |
231 | ||
e088a685 YL |
232 | enum { |
233 | HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 | |
234 | }; | |
235 | ||
d061effc WHX |
236 | enum hns_roce_reset_stage { |
237 | HNS_ROCE_STATE_NON_RST, | |
238 | HNS_ROCE_STATE_RST_BEF_DOWN, | |
239 | HNS_ROCE_STATE_RST_DOWN, | |
240 | HNS_ROCE_STATE_RST_UNINIT, | |
241 | HNS_ROCE_STATE_RST_INIT, | |
242 | HNS_ROCE_STATE_RST_INITED, | |
243 | }; | |
244 | ||
245 | enum hns_roce_instance_state { | |
246 | HNS_ROCE_STATE_NON_INIT, | |
247 | HNS_ROCE_STATE_INIT, | |
248 | HNS_ROCE_STATE_INITED, | |
249 | HNS_ROCE_STATE_UNINIT, | |
250 | }; | |
251 | ||
252 | enum { | |
253 | HNS_ROCE_RST_DIRECT_RETURN = 0, | |
254 | }; | |
255 | ||
6a04aed6 WHX |
256 | enum { |
257 | CMD_RST_PRC_OTHERS, | |
258 | CMD_RST_PRC_SUCCESS, | |
259 | CMD_RST_PRC_EBUSY, | |
260 | }; | |
261 | ||
9a443537 | 262 | #define HNS_ROCE_CMD_SUCCESS 1 |
263 | ||
264 | #define HNS_ROCE_PORT_DOWN 0 | |
265 | #define HNS_ROCE_PORT_UP 1 | |
266 | ||
9581a356 XW |
267 | /* The minimum page size is 4K for hardware */ |
268 | #define HNS_HW_PAGE_SHIFT 12 | |
269 | #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) | |
9a443537 | 270 | |
3c873161 XW |
271 | /* The minimum page count for hardware access page directly. */ |
272 | #define HNS_HW_DIRECT_PAGE_COUNT 2 | |
273 | ||
9a443537 | 274 | struct hns_roce_uar { |
275 | u64 pfn; | |
276 | unsigned long index; | |
5b6eb54f | 277 | unsigned long logic_idx; |
9a443537 | 278 | }; |
279 | ||
280 | struct hns_roce_ucontext { | |
281 | struct ib_ucontext ibucontext; | |
282 | struct hns_roce_uar uar; | |
e088a685 YL |
283 | struct list_head page_list; |
284 | struct mutex page_mutex; | |
9a443537 | 285 | }; |
286 | ||
287 | struct hns_roce_pd { | |
288 | struct ib_pd ibpd; | |
289 | unsigned long pdn; | |
290 | }; | |
291 | ||
292 | struct hns_roce_bitmap { | |
293 | /* Bitmap Traversal last a bit which is 1 */ | |
294 | unsigned long last; | |
295 | unsigned long top; | |
296 | unsigned long max; | |
297 | unsigned long reserved_top; | |
298 | unsigned long mask; | |
299 | spinlock_t lock; | |
300 | unsigned long *table; | |
301 | }; | |
302 | ||
9a443537 | 303 | /* For Hardware Entry Memory */ |
304 | struct hns_roce_hem_table { | |
305 | /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ | |
306 | u32 type; | |
307 | /* HEM array elment num */ | |
308 | unsigned long num_hem; | |
309 | /* HEM entry record obj total num */ | |
310 | unsigned long num_obj; | |
6def7de6 | 311 | /* Single obj size */ |
9a443537 | 312 | unsigned long obj_size; |
29a1fe5d | 313 | unsigned long table_chunk_size; |
9a443537 | 314 | int lowmem; |
315 | struct mutex mutex; | |
316 | struct hns_roce_hem **hem; | |
a25d13cb SX |
317 | u64 **bt_l1; |
318 | dma_addr_t *bt_l1_dma_addr; | |
319 | u64 **bt_l0; | |
320 | dma_addr_t *bt_l0_dma_addr; | |
9a443537 | 321 | }; |
322 | ||
38389eaa LO |
323 | struct hns_roce_buf_region { |
324 | int offset; /* page offset */ | |
6def7de6 | 325 | u32 count; /* page count */ |
38389eaa LO |
326 | int hopnum; /* addressing hop num */ |
327 | }; | |
328 | ||
329 | #define HNS_ROCE_MAX_BT_REGION 3 | |
330 | #define HNS_ROCE_MAX_BT_LEVEL 3 | |
331 | struct hns_roce_hem_list { | |
332 | struct list_head root_bt; | |
333 | /* link all bt dma mem by hop config */ | |
334 | struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; | |
335 | struct list_head btm_bt; /* link all bottom bt in @mid_bt */ | |
336 | dma_addr_t root_ba; /* pointer to the root ba table */ | |
3c873161 XW |
337 | }; |
338 | ||
339 | struct hns_roce_buf_attr { | |
340 | struct { | |
341 | size_t size; /* region size */ | |
342 | int hopnum; /* multi-hop addressing hop num */ | |
343 | } region[HNS_ROCE_MAX_BT_REGION]; | |
344 | int region_count; /* valid region count */ | |
82d07a4e | 345 | unsigned int page_shift; /* buffer page shift */ |
3c873161 XW |
346 | bool fixed_page; /* decide page shift is fixed-size or maximum size */ |
347 | int user_access; /* umem access flag */ | |
348 | bool mtt_only; /* only alloc buffer-required MTT memory */ | |
38389eaa LO |
349 | }; |
350 | ||
351 | /* memory translate region */ | |
352 | struct hns_roce_mtr { | |
3c873161 | 353 | struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ |
82d07a4e WL |
354 | struct ib_umem *umem; /* user space buffer */ |
355 | struct hns_roce_buf *kmem; /* kernel space buffer */ | |
3c873161 | 356 | struct { |
82d07a4e WL |
357 | dma_addr_t root_ba; /* root BA table's address */ |
358 | bool is_direct; /* addressing without BA table */ | |
359 | unsigned int ba_pg_shift; /* BA table page shift */ | |
360 | unsigned int buf_pg_shift; /* buffer page shift */ | |
361 | int buf_pg_count; /* buffer page count */ | |
8e029d38 XW |
362 | struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; |
363 | unsigned int region_count; | |
3c873161 | 364 | } hem_cfg; /* config for hardware addressing */ |
38389eaa LO |
365 | }; |
366 | ||
c7c28191 YL |
367 | struct hns_roce_mw { |
368 | struct ib_mw ibmw; | |
369 | u32 pdn; | |
370 | u32 rkey; | |
371 | int enabled; /* MW's active status */ | |
372 | u32 pbl_hop_num; | |
373 | u32 pbl_ba_pg_sz; | |
374 | u32 pbl_buf_pg_sz; | |
375 | }; | |
376 | ||
9a443537 | 377 | /* Only support 4K page size for mr register */ |
378 | #define MR_SIZE_4K 0 | |
379 | ||
380 | struct hns_roce_mr { | |
381 | struct ib_mr ibmr; | |
9a443537 | 382 | u64 iova; /* MR's virtual orignal addr */ |
383 | u64 size; /* Address range of MR */ | |
384 | u32 key; /* Key of MR */ | |
385 | u32 pd; /* PD num of MR */ | |
6def7de6 | 386 | u32 access; /* Access permission of MR */ |
9a443537 | 387 | int enabled; /* MR's active status */ |
388 | int type; /* MR's register type */ | |
6def7de6 | 389 | u32 pbl_hop_num; /* multi-hop number */ |
9b2cf76c XW |
390 | struct hns_roce_mtr pbl_mtr; |
391 | u32 npages; | |
392 | dma_addr_t *page_list; | |
9a443537 | 393 | }; |
394 | ||
395 | struct hns_roce_mr_table { | |
396 | struct hns_roce_bitmap mtpt_bitmap; | |
9a443537 | 397 | struct hns_roce_hem_table mtpt_table; |
398 | }; | |
399 | ||
400 | struct hns_roce_wq { | |
401 | u64 *wrid; /* Work request ID */ | |
402 | spinlock_t lock; | |
47688202 | 403 | u32 wqe_cnt; /* WQE num */ |
9a443537 | 404 | int max_gs; |
405 | int offset; | |
6def7de6 | 406 | int wqe_shift; /* WQE size */ |
9a443537 | 407 | u32 head; |
408 | u32 tail; | |
409 | void __iomem *db_reg_l; | |
410 | }; | |
411 | ||
926a01dc | 412 | struct hns_roce_sge { |
13aa13dd | 413 | unsigned int sge_cnt; /* SGE num */ |
926a01dc | 414 | int offset; |
6def7de6 | 415 | int sge_shift; /* SGE size */ |
926a01dc WHX |
416 | }; |
417 | ||
9a443537 | 418 | struct hns_roce_buf_list { |
419 | void *buf; | |
420 | dma_addr_t map; | |
421 | }; | |
422 | ||
423 | struct hns_roce_buf { | |
424 | struct hns_roce_buf_list direct; | |
425 | struct hns_roce_buf_list *page_list; | |
9a443537 | 426 | u32 npages; |
18a96d25 | 427 | u32 size; |
82d07a4e | 428 | unsigned int page_shift; |
9a443537 | 429 | }; |
430 | ||
e088a685 YL |
431 | struct hns_roce_db_pgdir { |
432 | struct list_head list; | |
433 | DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); | |
2a3d923f LO |
434 | DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); |
435 | unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; | |
e088a685 YL |
436 | u32 *page; |
437 | dma_addr_t db_dma; | |
438 | }; | |
439 | ||
440 | struct hns_roce_user_db_page { | |
441 | struct list_head list; | |
442 | struct ib_umem *umem; | |
443 | unsigned long user_virt; | |
444 | refcount_t refcount; | |
445 | }; | |
446 | ||
447 | struct hns_roce_db { | |
448 | u32 *db_record; | |
449 | union { | |
450 | struct hns_roce_db_pgdir *pgdir; | |
451 | struct hns_roce_user_db_page *user_page; | |
452 | } u; | |
453 | dma_addr_t dma; | |
0425e3e6 | 454 | void *virt_addr; |
e088a685 YL |
455 | int index; |
456 | int order; | |
457 | }; | |
458 | ||
9a443537 | 459 | struct hns_roce_cq { |
460 | struct ib_cq ib_cq; | |
744b7bdf | 461 | struct hns_roce_mtr mtr; |
9b44703d | 462 | struct hns_roce_db db; |
05e6a5a6 | 463 | u32 flags; |
9a443537 | 464 | spinlock_t lock; |
9a443537 | 465 | u32 cq_depth; |
466 | u32 cons_index; | |
86188a88 | 467 | u32 *set_ci_db; |
9a443537 | 468 | void __iomem *cq_db_l; |
8f3e9f3e | 469 | u16 *tptr_addr; |
26beb85f | 470 | int arm_sn; |
9a443537 | 471 | unsigned long cqn; |
472 | u32 vector; | |
473 | atomic_t refcount; | |
474 | struct completion free; | |
626903e9 XW |
475 | struct list_head sq_list; /* all qps on this send cq */ |
476 | struct list_head rq_list; /* all qps on this recv cq */ | |
477 | int is_armed; /* cq is armed */ | |
478 | struct list_head node; /* all armed cqs are on a list */ | |
9a443537 | 479 | }; |
480 | ||
c7bcb134 | 481 | struct hns_roce_idx_que { |
6fd610c5 | 482 | struct hns_roce_mtr mtr; |
67954a6e | 483 | int entry_shift; |
97545b10 | 484 | unsigned long *bitmap; |
c7bcb134 LO |
485 | }; |
486 | ||
9a443537 | 487 | struct hns_roce_srq { |
488 | struct ib_srq ibsrq; | |
c7bcb134 | 489 | unsigned long srqn; |
d938d785 | 490 | u32 wqe_cnt; |
c7bcb134 LO |
491 | int max_gs; |
492 | int wqe_shift; | |
493 | void __iomem *db_reg_l; | |
494 | ||
495 | atomic_t refcount; | |
496 | struct completion free; | |
497 | ||
6fd610c5 XW |
498 | struct hns_roce_mtr buf_mtr; |
499 | ||
c7bcb134 | 500 | u64 *wrid; |
c7bcb134 LO |
501 | struct hns_roce_idx_que idx_que; |
502 | spinlock_t lock; | |
503 | int head; | |
504 | int tail; | |
c7bcb134 | 505 | struct mutex mutex; |
d938d785 | 506 | void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); |
9a443537 | 507 | }; |
508 | ||
509 | struct hns_roce_uar_table { | |
510 | struct hns_roce_bitmap bitmap; | |
511 | }; | |
512 | ||
513 | struct hns_roce_qp_table { | |
514 | struct hns_roce_bitmap bitmap; | |
9a443537 | 515 | struct hns_roce_hem_table qp_table; |
516 | struct hns_roce_hem_table irrl_table; | |
e92f2c18 | 517 | struct hns_roce_hem_table trrl_table; |
6a157f7d | 518 | struct hns_roce_hem_table sccc_table; |
aa84fa18 | 519 | struct mutex scc_mutex; |
9a443537 | 520 | }; |
521 | ||
522 | struct hns_roce_cq_table { | |
523 | struct hns_roce_bitmap bitmap; | |
27e19f45 | 524 | struct xarray array; |
9a443537 | 525 | struct hns_roce_hem_table table; |
526 | }; | |
527 | ||
5c1f167a LO |
528 | struct hns_roce_srq_table { |
529 | struct hns_roce_bitmap bitmap; | |
530 | struct xarray xa; | |
531 | struct hns_roce_hem_table table; | |
532 | }; | |
533 | ||
9a443537 | 534 | struct hns_roce_raq_table { |
535 | struct hns_roce_buf_list *e_raq_buf; | |
536 | }; | |
537 | ||
538 | struct hns_roce_av { | |
82e620d9 | 539 | u8 port; |
9a443537 | 540 | u8 gid_index; |
541 | u8 stat_rate; | |
542 | u8 hop_limit; | |
82e620d9 LC |
543 | u32 flowlabel; |
544 | u8 sl; | |
545 | u8 tclass; | |
9a443537 | 546 | u8 dgid[HNS_ROCE_GID_SIZE]; |
2a3d923f | 547 | u8 mac[ETH_ALEN]; |
32883228 | 548 | u16 vlan_id; |
8320deb8 | 549 | bool vlan_en; |
9a443537 | 550 | }; |
551 | ||
552 | struct hns_roce_ah { | |
553 | struct ib_ah ibah; | |
554 | struct hns_roce_av av; | |
555 | }; | |
556 | ||
557 | struct hns_roce_cmd_context { | |
558 | struct completion done; | |
559 | int result; | |
560 | int next; | |
561 | u64 out_param; | |
562 | u16 token; | |
563 | }; | |
564 | ||
565 | struct hns_roce_cmdq { | |
566 | struct dma_pool *pool; | |
9a443537 | 567 | struct mutex hcr_mutex; |
568 | struct semaphore poll_sem; | |
569 | /* | |
e84e40be S |
570 | * Event mode: cmd register mutex protection, |
571 | * ensure to not exceed max_cmds and user use limit region | |
572 | */ | |
9a443537 | 573 | struct semaphore event_sem; |
574 | int max_cmds; | |
575 | spinlock_t context_lock; | |
576 | int free_head; | |
577 | struct hns_roce_cmd_context *context; | |
578 | /* | |
e84e40be S |
579 | * Result of get integer part |
580 | * which max_comds compute according a power of 2 | |
581 | */ | |
9a443537 | 582 | u16 token_mask; |
583 | /* | |
e84e40be S |
584 | * Process whether use event mode, init default non-zero |
585 | * After the event queue of cmd event ready, | |
586 | * can switch into event mode | |
587 | * close device, switch into poll mode(non event mode) | |
588 | */ | |
9a443537 | 589 | u8 use_events; |
9a443537 | 590 | }; |
591 | ||
bfcc681b SX |
592 | struct hns_roce_cmd_mailbox { |
593 | void *buf; | |
594 | dma_addr_t dma; | |
595 | }; | |
596 | ||
9a443537 | 597 | struct hns_roce_dev; |
598 | ||
0009c2db | 599 | struct hns_roce_rinl_sge { |
600 | void *addr; | |
601 | u32 len; | |
602 | }; | |
603 | ||
604 | struct hns_roce_rinl_wqe { | |
605 | struct hns_roce_rinl_sge *sg_list; | |
606 | u32 sge_cnt; | |
607 | }; | |
608 | ||
609 | struct hns_roce_rinl_buf { | |
610 | struct hns_roce_rinl_wqe *wqe_list; | |
611 | u32 wqe_cnt; | |
612 | }; | |
613 | ||
b5374286 YL |
614 | enum { |
615 | HNS_ROCE_FLUSH_FLAG = 0, | |
616 | }; | |
617 | ||
ffd541d4 YL |
618 | struct hns_roce_work { |
619 | struct hns_roce_dev *hr_dev; | |
620 | struct work_struct work; | |
621 | u32 qpn; | |
622 | u32 cqn; | |
623 | int event_type; | |
624 | int sub_type; | |
625 | }; | |
626 | ||
9a443537 | 627 | struct hns_roce_qp { |
628 | struct ib_qp ibqp; | |
9a443537 | 629 | struct hns_roce_wq rq; |
e088a685 | 630 | struct hns_roce_db rdb; |
0425e3e6 | 631 | struct hns_roce_db sdb; |
90ae0b57 | 632 | unsigned long en_flags; |
8b9b8d14 | 633 | u32 doorbell_qpn; |
bfe86035 | 634 | u32 sq_signal_bits; |
9a443537 | 635 | struct hns_roce_wq sq; |
636 | ||
8d18ad83 | 637 | struct hns_roce_mtr mtr; |
8d18ad83 | 638 | |
9a443537 | 639 | u32 buff_size; |
640 | struct mutex mutex; | |
641 | u8 port; | |
7716809e | 642 | u8 phy_port; |
9a443537 | 643 | u8 sl; |
644 | u8 resp_depth; | |
645 | u8 state; | |
646 | u32 access_flags; | |
ace1c541 | 647 | u32 atomic_rd_en; |
9a443537 | 648 | u32 pkey_index; |
0fa95a9a | 649 | u32 qkey; |
fd012f1c | 650 | void (*event)(struct hns_roce_qp *qp, |
651 | enum hns_roce_event event_type); | |
9a443537 | 652 | unsigned long qpn; |
653 | ||
654 | atomic_t refcount; | |
655 | struct completion free; | |
926a01dc WHX |
656 | |
657 | struct hns_roce_sge sge; | |
658 | u32 next_sge; | |
0009c2db | 659 | |
b5374286 YL |
660 | /* 0: flush needed, 1: unneeded */ |
661 | unsigned long flush_flag; | |
ffd541d4 | 662 | struct hns_roce_work flush_work; |
0009c2db | 663 | struct hns_roce_rinl_buf rq_inl_buf; |
626903e9 XW |
664 | struct list_head node; /* all qps are on a list */ |
665 | struct list_head rq_node; /* all recv qps are on a list */ | |
666 | struct list_head sq_node; /* all send qps are on a list */ | |
9a443537 | 667 | }; |
668 | ||
9a443537 | 669 | struct hns_roce_ib_iboe { |
670 | spinlock_t lock; | |
671 | struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; | |
672 | struct notifier_block nb; | |
9a443537 | 673 | u8 phy_port[HNS_ROCE_MAX_PORTS]; |
674 | }; | |
675 | ||
b16f8188 YL |
676 | enum { |
677 | HNS_ROCE_EQ_STAT_INVALID = 0, | |
678 | HNS_ROCE_EQ_STAT_VALID = 2, | |
679 | }; | |
680 | ||
681 | struct hns_roce_ceqe { | |
bfe86035 | 682 | __le32 comp; |
b16f8188 YL |
683 | }; |
684 | ||
685 | struct hns_roce_aeqe { | |
0576cbde | 686 | __le32 asyn; |
b16f8188 YL |
687 | union { |
688 | struct { | |
0576cbde | 689 | __le32 qp; |
b16f8188 YL |
690 | u32 rsv0; |
691 | u32 rsv1; | |
692 | } qp_event; | |
693 | ||
81fce629 LO |
694 | struct { |
695 | __le32 srq; | |
696 | u32 rsv0; | |
697 | u32 rsv1; | |
698 | } srq_event; | |
699 | ||
b16f8188 | 700 | struct { |
0576cbde | 701 | __le32 cq; |
b16f8188 YL |
702 | u32 rsv0; |
703 | u32 rsv1; | |
704 | } cq_event; | |
705 | ||
706 | struct { | |
0576cbde | 707 | __le32 ceqe; |
b16f8188 YL |
708 | u32 rsv0; |
709 | u32 rsv1; | |
710 | } ce_event; | |
711 | ||
712 | struct { | |
713 | __le64 out_param; | |
714 | __le16 token; | |
715 | u8 status; | |
716 | u8 rsv0; | |
717 | } __packed cmd; | |
718 | } event; | |
719 | }; | |
720 | ||
9a443537 | 721 | struct hns_roce_eq { |
722 | struct hns_roce_dev *hr_dev; | |
723 | void __iomem *doorbell; | |
724 | ||
6def7de6 | 725 | int type_flag; /* Aeq:1 ceq:0 */ |
9a443537 | 726 | int eqn; |
727 | u32 entries; | |
728 | int log_entries; | |
729 | int eqe_size; | |
730 | int irq; | |
731 | int log_page_size; | |
732 | int cons_index; | |
733 | struct hns_roce_buf_list *buf_list; | |
a5073d60 YL |
734 | int over_ignore; |
735 | int coalesce; | |
736 | int arm_st; | |
a5073d60 | 737 | int hop_num; |
d7e2d343 | 738 | struct hns_roce_mtr mtr; |
13aa13dd | 739 | u16 eq_max_cnt; |
a5073d60 YL |
740 | int eq_period; |
741 | int shift; | |
0425e3e6 YL |
742 | int event_type; |
743 | int sub_type; | |
9a443537 | 744 | }; |
745 | ||
746 | struct hns_roce_eq_table { | |
747 | struct hns_roce_eq *eq; | |
b16f8188 | 748 | void __iomem **eqc_base; /* only for hw v1 */ |
9a443537 | 749 | }; |
750 | ||
751 | struct hns_roce_caps { | |
3a63c964 | 752 | u64 fw_ver; |
9a443537 | 753 | u8 num_ports; |
754 | int gid_table_len[HNS_ROCE_MAX_PORTS]; | |
755 | int pkey_table_len[HNS_ROCE_MAX_PORTS]; | |
756 | int local_ca_ack_delay; | |
757 | int num_uars; | |
758 | u32 phy_num_uars; | |
6def7de6 LC |
759 | u32 max_sq_sg; |
760 | u32 max_sq_inline; | |
761 | u32 max_rq_sg; | |
05ad5482 | 762 | u32 max_extend_sg; |
6def7de6 | 763 | int num_qps; |
06ef0ee4 | 764 | int reserved_qps; |
0e40dc2f YL |
765 | int num_qpc_timer; |
766 | int num_cqc_timer; | |
5c1f167a | 767 | int num_srqs; |
6def7de6 | 768 | u32 max_wqes; |
d16da119 LO |
769 | u32 max_srq_wrs; |
770 | u32 max_srq_sges; | |
6def7de6 LC |
771 | u32 max_sq_desc_sz; |
772 | u32 max_rq_desc_sz; | |
cfc85f3e | 773 | u32 max_srq_desc_sz; |
9a443537 | 774 | int max_qp_init_rdma; |
775 | int max_qp_dest_rdma; | |
9a443537 | 776 | int num_cqs; |
e2b2744a YL |
777 | u32 max_cqes; |
778 | u32 min_cqes; | |
926a01dc | 779 | u32 min_wqes; |
9a443537 | 780 | int reserved_cqs; |
5c1f167a | 781 | int reserved_srqs; |
6def7de6 | 782 | int num_aeq_vectors; |
a5073d60 | 783 | int num_comp_vectors; |
9a443537 | 784 | int num_other_vectors; |
785 | int num_mtpts; | |
786 | u32 num_mtt_segs; | |
cfc85f3e | 787 | u32 num_cqe_segs; |
5c1f167a LO |
788 | u32 num_srqwqe_segs; |
789 | u32 num_idx_segs; | |
9a443537 | 790 | int reserved_mrws; |
791 | int reserved_uars; | |
792 | int num_pds; | |
793 | int reserved_pds; | |
794 | u32 mtt_entry_sz; | |
795 | u32 cq_entry_sz; | |
796 | u32 page_size_cap; | |
797 | u32 reserved_lkey; | |
798 | int mtpt_entry_sz; | |
799 | int qpc_entry_sz; | |
800 | int irrl_entry_sz; | |
e92f2c18 | 801 | int trrl_entry_sz; |
9a443537 | 802 | int cqc_entry_sz; |
6a157f7d | 803 | int sccc_entry_sz; |
0e40dc2f YL |
804 | int qpc_timer_entry_sz; |
805 | int cqc_timer_entry_sz; | |
5c1f167a LO |
806 | int srqc_entry_sz; |
807 | int idx_entry_sz; | |
ff795f71 WHX |
808 | u32 pbl_ba_pg_sz; |
809 | u32 pbl_buf_pg_sz; | |
810 | u32 pbl_hop_num; | |
9a443537 | 811 | int aeqe_depth; |
b16f8188 | 812 | int ceqe_depth; |
9a443537 | 813 | enum ib_mtu max_mtu; |
cfc85f3e | 814 | u32 qpc_bt_num; |
0e40dc2f | 815 | u32 qpc_timer_bt_num; |
cfc85f3e WHX |
816 | u32 srqc_bt_num; |
817 | u32 cqc_bt_num; | |
0e40dc2f | 818 | u32 cqc_timer_bt_num; |
cfc85f3e | 819 | u32 mpt_bt_num; |
6a157f7d | 820 | u32 sccc_bt_num; |
a25d13cb SX |
821 | u32 qpc_ba_pg_sz; |
822 | u32 qpc_buf_pg_sz; | |
823 | u32 qpc_hop_num; | |
824 | u32 srqc_ba_pg_sz; | |
825 | u32 srqc_buf_pg_sz; | |
826 | u32 srqc_hop_num; | |
827 | u32 cqc_ba_pg_sz; | |
828 | u32 cqc_buf_pg_sz; | |
829 | u32 cqc_hop_num; | |
830 | u32 mpt_ba_pg_sz; | |
831 | u32 mpt_buf_pg_sz; | |
832 | u32 mpt_hop_num; | |
6a93c77a SX |
833 | u32 mtt_ba_pg_sz; |
834 | u32 mtt_buf_pg_sz; | |
835 | u32 mtt_hop_num; | |
8d18ad83 LO |
836 | u32 wqe_sq_hop_num; |
837 | u32 wqe_sge_hop_num; | |
838 | u32 wqe_rq_hop_num; | |
6a157f7d YL |
839 | u32 sccc_ba_pg_sz; |
840 | u32 sccc_buf_pg_sz; | |
841 | u32 sccc_hop_num; | |
0e40dc2f YL |
842 | u32 qpc_timer_ba_pg_sz; |
843 | u32 qpc_timer_buf_pg_sz; | |
844 | u32 qpc_timer_hop_num; | |
845 | u32 cqc_timer_ba_pg_sz; | |
846 | u32 cqc_timer_buf_pg_sz; | |
847 | u32 cqc_timer_hop_num; | |
b14c95be | 848 | u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ |
6a93c77a SX |
849 | u32 cqe_buf_pg_sz; |
850 | u32 cqe_hop_num; | |
c7bcb134 LO |
851 | u32 srqwqe_ba_pg_sz; |
852 | u32 srqwqe_buf_pg_sz; | |
853 | u32 srqwqe_hop_num; | |
854 | u32 idx_ba_pg_sz; | |
855 | u32 idx_buf_pg_sz; | |
856 | u32 idx_hop_num; | |
a5073d60 YL |
857 | u32 eqe_ba_pg_sz; |
858 | u32 eqe_buf_pg_sz; | |
859 | u32 eqe_hop_num; | |
6b63597d | 860 | u32 sl_num; |
861 | u32 tsq_buf_pg_sz; | |
ded58ff9 | 862 | u32 tpq_buf_pg_sz; |
6def7de6 | 863 | u32 chunk_sz; /* chunk size in non multihop mode */ |
a2c80b7b | 864 | u64 flags; |
ba6bb7e9 LO |
865 | u16 default_ceq_max_cnt; |
866 | u16 default_ceq_period; | |
867 | u16 default_aeq_max_cnt; | |
868 | u16 default_aeq_period; | |
869 | u16 default_aeq_arm_st; | |
870 | u16 default_ceq_arm_st; | |
9a443537 | 871 | }; |
872 | ||
e1c9a0dc LO |
873 | struct hns_roce_dfx_hw { |
874 | int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn, | |
875 | int *buffer); | |
876 | }; | |
877 | ||
626903e9 XW |
878 | enum hns_roce_device_state { |
879 | HNS_ROCE_DEVICE_STATE_INITED, | |
880 | HNS_ROCE_DEVICE_STATE_RST_DOWN, | |
881 | HNS_ROCE_DEVICE_STATE_UNINIT, | |
882 | }; | |
883 | ||
9a443537 | 884 | struct hns_roce_hw { |
885 | int (*reset)(struct hns_roce_dev *hr_dev, bool enable); | |
a04ff739 WHX |
886 | int (*cmq_init)(struct hns_roce_dev *hr_dev); |
887 | void (*cmq_exit)(struct hns_roce_dev *hr_dev); | |
cfc85f3e | 888 | int (*hw_profile)(struct hns_roce_dev *hr_dev); |
9a443537 | 889 | int (*hw_init)(struct hns_roce_dev *hr_dev); |
890 | void (*hw_exit)(struct hns_roce_dev *hr_dev); | |
a680f2f3 WHX |
891 | int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param, |
892 | u64 out_param, u32 in_modifier, u8 op_modifier, u16 op, | |
893 | u16 token, int event); | |
894 | int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout); | |
6a04aed6 | 895 | int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev); |
b5ff0f61 | 896 | int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index, |
f4df9a7c | 897 | const union ib_gid *gid, const struct ib_gid_attr *attr); |
a74dc41d | 898 | int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr); |
9a443537 | 899 | void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port, |
900 | enum ib_mtu mtu); | |
98a61519 YL |
901 | int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, |
902 | struct hns_roce_mr *mr, unsigned long mtpt_idx); | |
a2c80b7b WHX |
903 | int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, |
904 | struct hns_roce_mr *mr, int flags, u32 pdn, | |
905 | int mr_access_flags, u64 iova, u64 size, | |
906 | void *mb_buf); | |
98a61519 YL |
907 | int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, |
908 | struct hns_roce_mr *mr); | |
c7c28191 | 909 | int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); |
9a443537 | 910 | void (*write_cqc)(struct hns_roce_dev *hr_dev, |
911 | struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, | |
e2b2744a | 912 | dma_addr_t dma_handle); |
a25d13cb SX |
913 | int (*set_hem)(struct hns_roce_dev *hr_dev, |
914 | struct hns_roce_hem_table *table, int obj, int step_idx); | |
97f0e39f | 915 | int (*clear_hem)(struct hns_roce_dev *hr_dev, |
a25d13cb SX |
916 | struct hns_roce_hem_table *table, int obj, |
917 | int step_idx); | |
9a443537 | 918 | int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, |
919 | int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr); | |
920 | int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, | |
921 | int attr_mask, enum ib_qp_state cur_state, | |
922 | enum ib_qp_state new_state); | |
c4367a26 | 923 | int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata); |
aa84fa18 YL |
924 | int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, |
925 | struct hns_roce_qp *hr_qp); | |
d34ac5cd BVA |
926 | int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
927 | const struct ib_send_wr **bad_wr); | |
928 | int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr, | |
929 | const struct ib_recv_wr **bad_recv_wr); | |
9a443537 | 930 | int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); |
931 | int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); | |
c4367a26 SR |
932 | int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, |
933 | struct ib_udata *udata); | |
a52c8e24 | 934 | void (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata); |
b156269d | 935 | int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period); |
b16f8188 YL |
936 | int (*init_eq)(struct hns_roce_dev *hr_dev); |
937 | void (*cleanup_eq)(struct hns_roce_dev *hr_dev); | |
c7bcb134 LO |
938 | void (*write_srqc)(struct hns_roce_dev *hr_dev, |
939 | struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn, | |
940 | void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx, | |
941 | dma_addr_t dma_handle_wqe, | |
942 | dma_addr_t dma_handle_idx); | |
943 | int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, | |
944 | enum ib_srq_attr_mask srq_attr_mask, | |
945 | struct ib_udata *udata); | |
946 | int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr); | |
947 | int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, | |
948 | const struct ib_recv_wr **bad_wr); | |
7f645a58 KH |
949 | const struct ib_device_ops *hns_roce_dev_ops; |
950 | const struct ib_device_ops *hns_roce_dev_srq_ops; | |
9a443537 | 951 | }; |
952 | ||
953 | struct hns_roce_dev { | |
954 | struct ib_device ib_dev; | |
955 | struct platform_device *pdev; | |
dd74282d WHX |
956 | struct pci_dev *pci_dev; |
957 | struct device *dev; | |
9a443537 | 958 | struct hns_roce_uar priv_uar; |
528f1deb | 959 | const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; |
9a443537 | 960 | spinlock_t sm_lock; |
9a443537 | 961 | spinlock_t bt_cmd_lock; |
cb7a94c9 WHX |
962 | bool active; |
963 | bool is_reset; | |
d3743fa9 | 964 | bool dis_db; |
d061effc | 965 | unsigned long reset_cnt; |
9a443537 | 966 | struct hns_roce_ib_iboe iboe; |
626903e9 XW |
967 | enum hns_roce_device_state state; |
968 | struct list_head qp_list; /* list of all qps on this dev */ | |
969 | spinlock_t qp_list_lock; /* protect qp_list */ | |
9a443537 | 970 | |
472bc0fb YL |
971 | struct list_head pgdir_list; |
972 | struct mutex pgdir_mutex; | |
9a443537 | 973 | int irq[HNS_ROCE_MAX_IRQ_NUM]; |
974 | u8 __iomem *reg_base; | |
975 | struct hns_roce_caps caps; | |
736b5a70 | 976 | struct xarray qp_table_xa; |
9a443537 | 977 | |
2a3d923f | 978 | unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; |
9a443537 | 979 | u64 sys_image_guid; |
980 | u32 vendor_id; | |
981 | u32 vendor_part_id; | |
982 | u32 hw_rev; | |
983 | void __iomem *priv_addr; | |
984 | ||
985 | struct hns_roce_cmdq cmd; | |
986 | struct hns_roce_bitmap pd_bitmap; | |
987 | struct hns_roce_uar_table uar_table; | |
988 | struct hns_roce_mr_table mr_table; | |
989 | struct hns_roce_cq_table cq_table; | |
5c1f167a | 990 | struct hns_roce_srq_table srq_table; |
9a443537 | 991 | struct hns_roce_qp_table qp_table; |
992 | struct hns_roce_eq_table eq_table; | |
0e40dc2f YL |
993 | struct hns_roce_hem_table qpc_timer_table; |
994 | struct hns_roce_hem_table cqc_timer_table; | |
9a443537 | 995 | |
996 | int cmd_mod; | |
997 | int loop_idc; | |
2d407888 WHX |
998 | u32 sdb_offset; |
999 | u32 odb_offset; | |
6def7de6 LC |
1000 | dma_addr_t tptr_dma_addr; /* only for hw v1 */ |
1001 | u32 tptr_size; /* only for hw v1 */ | |
08805fdb | 1002 | const struct hns_roce_hw *hw; |
016a0059 | 1003 | void *priv; |
0425e3e6 | 1004 | struct workqueue_struct *irq_workq; |
e1c9a0dc | 1005 | const struct hns_roce_dfx_hw *dfx; |
9a443537 | 1006 | }; |
1007 | ||
1008 | static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) | |
1009 | { | |
1010 | return container_of(ib_dev, struct hns_roce_dev, ib_dev); | |
1011 | } | |
1012 | ||
1013 | static inline struct hns_roce_ucontext | |
1014 | *to_hr_ucontext(struct ib_ucontext *ibucontext) | |
1015 | { | |
1016 | return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); | |
1017 | } | |
1018 | ||
1019 | static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) | |
1020 | { | |
1021 | return container_of(ibpd, struct hns_roce_pd, ibpd); | |
1022 | } | |
1023 | ||
1024 | static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) | |
1025 | { | |
1026 | return container_of(ibah, struct hns_roce_ah, ibah); | |
1027 | } | |
1028 | ||
1029 | static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) | |
1030 | { | |
1031 | return container_of(ibmr, struct hns_roce_mr, ibmr); | |
1032 | } | |
1033 | ||
c7c28191 YL |
1034 | static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) |
1035 | { | |
1036 | return container_of(ibmw, struct hns_roce_mw, ibmw); | |
1037 | } | |
1038 | ||
9a443537 | 1039 | static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) |
1040 | { | |
1041 | return container_of(ibqp, struct hns_roce_qp, ibqp); | |
1042 | } | |
1043 | ||
1044 | static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) | |
1045 | { | |
1046 | return container_of(ib_cq, struct hns_roce_cq, ib_cq); | |
1047 | } | |
1048 | ||
1049 | static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) | |
1050 | { | |
1051 | return container_of(ibsrq, struct hns_roce_srq, ibsrq); | |
1052 | } | |
1053 | ||
0576cbde | 1054 | static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) |
9a443537 | 1055 | { |
1056 | __raw_writeq(*(u64 *) val, dest); | |
1057 | } | |
1058 | ||
1059 | static inline struct hns_roce_qp | |
1060 | *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) | |
1061 | { | |
736b5a70 | 1062 | return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1)); |
9a443537 | 1063 | } |
1064 | ||
cc23267a XW |
1065 | static inline bool hns_roce_buf_is_direct(struct hns_roce_buf *buf) |
1066 | { | |
1067 | if (buf->page_list) | |
1068 | return false; | |
1069 | ||
1070 | return true; | |
1071 | } | |
1072 | ||
9a443537 | 1073 | static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset) |
1074 | { | |
cc23267a XW |
1075 | if (hns_roce_buf_is_direct(buf)) |
1076 | return (char *)(buf->direct.buf) + (offset & (buf->size - 1)); | |
9a443537 | 1077 | |
cc23267a XW |
1078 | return (char *)(buf->page_list[offset >> buf->page_shift].buf) + |
1079 | (offset & ((1 << buf->page_shift) - 1)); | |
1080 | } | |
1081 | ||
1082 | static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, int idx) | |
1083 | { | |
1084 | if (hns_roce_buf_is_direct(buf)) | |
1085 | return buf->direct.map + ((dma_addr_t)idx << buf->page_shift); | |
9a443537 | 1086 | else |
cc23267a | 1087 | return buf->page_list[idx].map; |
9a443537 | 1088 | } |
1089 | ||
9581a356 | 1090 | #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) |
54d66387 | 1091 | |
3c873161 XW |
1092 | static inline u64 to_hr_hw_page_addr(u64 addr) |
1093 | { | |
9581a356 | 1094 | return addr >> HNS_HW_PAGE_SHIFT; |
3c873161 XW |
1095 | } |
1096 | ||
1097 | static inline u32 to_hr_hw_page_shift(u32 page_shift) | |
1098 | { | |
9581a356 | 1099 | return page_shift - HNS_HW_PAGE_SHIFT; |
3c873161 XW |
1100 | } |
1101 | ||
54d66387 XW |
1102 | static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) |
1103 | { | |
1104 | if (count > 0) | |
1105 | return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | ||
1110 | static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) | |
1111 | { | |
1112 | return hr_hw_page_align(count << buf_shift); | |
1113 | } | |
1114 | ||
1115 | static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) | |
1116 | { | |
1117 | return hr_hw_page_align(count << buf_shift) >> buf_shift; | |
1118 | } | |
1119 | ||
1120 | static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) | |
1121 | { | |
d4d81387 WL |
1122 | if (!count) |
1123 | return 0; | |
1124 | ||
54d66387 XW |
1125 | return ilog2(to_hr_hem_entries_count(count, buf_shift)); |
1126 | } | |
1127 | ||
9a443537 | 1128 | int hns_roce_init_uar_table(struct hns_roce_dev *dev); |
1129 | int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); | |
1130 | void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar); | |
1131 | void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev); | |
1132 | ||
1133 | int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); | |
1134 | void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); | |
1135 | void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, | |
1136 | u64 out_param); | |
1137 | int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); | |
1138 | void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); | |
1139 | ||
38389eaa LO |
1140 | /* hns roce hw need current block and next block addr from mtt */ |
1141 | #define MTT_MIN_COUNT 2 | |
1142 | int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
1143 | int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr); | |
3c873161 | 1144 | int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, |
82d07a4e WL |
1145 | struct hns_roce_buf_attr *buf_attr, |
1146 | unsigned int page_shift, struct ib_udata *udata, | |
1147 | unsigned long user_addr); | |
3c873161 XW |
1148 | void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, |
1149 | struct hns_roce_mtr *mtr); | |
1150 | int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, | |
3c873161 | 1151 | dma_addr_t *pages, int page_cnt); |
38389eaa | 1152 | |
9a443537 | 1153 | int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); |
1154 | int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); | |
9a443537 | 1155 | int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); |
1156 | int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); | |
5c1f167a | 1157 | int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); |
9a443537 | 1158 | |
1159 | void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev); | |
1160 | void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev); | |
1161 | void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev); | |
1162 | void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); | |
1163 | void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); | |
5c1f167a | 1164 | void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev); |
9a443537 | 1165 | |
1166 | int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); | |
5e6ff78a WHX |
1167 | void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj, |
1168 | int rr); | |
9a443537 | 1169 | int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, |
1170 | u32 reserved_bot, u32 resetrved_top); | |
1171 | void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); | |
1172 | void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); | |
1173 | int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, | |
1174 | int align, unsigned long *obj); | |
1175 | void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, | |
5e6ff78a WHX |
1176 | unsigned long obj, int cnt, |
1177 | int rr); | |
9a443537 | 1178 | |
fa5d010c MG |
1179 | int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, |
1180 | struct ib_udata *udata); | |
90898850 | 1181 | int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); |
d3456914 | 1182 | void hns_roce_destroy_ah(struct ib_ah *ah, u32 flags); |
9a443537 | 1183 | |
ff23dfa1 | 1184 | int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); |
c4367a26 | 1185 | void hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); |
9a443537 | 1186 | |
1187 | struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); | |
1188 | struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |
1189 | u64 virt_addr, int access_flags, | |
1190 | struct ib_udata *udata); | |
a2c80b7b WHX |
1191 | int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length, |
1192 | u64 virt_addr, int mr_access_flags, struct ib_pd *pd, | |
1193 | struct ib_udata *udata); | |
68a997c5 | 1194 | struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, |
c4367a26 | 1195 | u32 max_num_sg, struct ib_udata *udata); |
68a997c5 YL |
1196 | int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, |
1197 | unsigned int *sg_offset); | |
c4367a26 | 1198 | int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); |
6eef5242 YL |
1199 | int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev, |
1200 | struct hns_roce_cmd_mailbox *mailbox, | |
1201 | unsigned long mpt_index); | |
bfcc681b | 1202 | unsigned long key_to_hw_index(u32 key); |
9a443537 | 1203 | |
c7c28191 YL |
1204 | struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type, |
1205 | struct ib_udata *udata); | |
1206 | int hns_roce_dealloc_mw(struct ib_mw *ibmw); | |
1207 | ||
cc23267a | 1208 | void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); |
9a443537 | 1209 | int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct, |
9a8982dc | 1210 | struct hns_roce_buf *buf, u32 page_shift); |
9a443537 | 1211 | |
2ac0bc5e LO |
1212 | int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, |
1213 | int buf_cnt, int start, struct hns_roce_buf *buf); | |
1214 | int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, | |
1215 | int buf_cnt, int start, struct ib_umem *umem, | |
82d07a4e | 1216 | unsigned int page_shift); |
2ac0bc5e | 1217 | |
68e326de LR |
1218 | int hns_roce_create_srq(struct ib_srq *srq, |
1219 | struct ib_srq_init_attr *srq_init_attr, | |
1220 | struct ib_udata *udata); | |
c7bcb134 LO |
1221 | int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, |
1222 | enum ib_srq_attr_mask srq_attr_mask, | |
1223 | struct ib_udata *udata); | |
68e326de | 1224 | void hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); |
c7bcb134 | 1225 | |
9a443537 | 1226 | struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd, |
1227 | struct ib_qp_init_attr *init_attr, | |
1228 | struct ib_udata *udata); | |
1229 | int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
1230 | int attr_mask, struct ib_udata *udata); | |
ffd541d4 | 1231 | void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); |
6c6e3921 XW |
1232 | void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n); |
1233 | void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n); | |
1234 | void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n); | |
9a443537 | 1235 | bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq, |
1236 | struct ib_cq *ib_cq); | |
1237 | enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state); | |
1238 | void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, | |
1239 | struct hns_roce_cq *recv_cq); | |
1240 | void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, | |
1241 | struct hns_roce_cq *recv_cq); | |
1242 | void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); | |
e365b26c XW |
1243 | void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, |
1244 | struct ib_udata *udata); | |
f696bf6d | 1245 | __be32 send_ieth(const struct ib_send_wr *wr); |
9a443537 | 1246 | int to_hr_qp_type(int qp_type); |
1247 | ||
707783ab YL |
1248 | int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, |
1249 | struct ib_udata *udata); | |
9a443537 | 1250 | |
707783ab | 1251 | void hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); |
b0ea0fa5 JG |
1252 | int hns_roce_db_map_user(struct hns_roce_ucontext *context, |
1253 | struct ib_udata *udata, unsigned long virt, | |
e088a685 YL |
1254 | struct hns_roce_db *db); |
1255 | void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, | |
1256 | struct hns_roce_db *db); | |
472bc0fb YL |
1257 | int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, |
1258 | int order); | |
1259 | void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); | |
1260 | ||
9a443537 | 1261 | void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); |
1262 | void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); | |
1263 | void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); | |
81fce629 | 1264 | void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); |
9a443537 | 1265 | int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index); |
626903e9 | 1266 | void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); |
08805fdb WHX |
1267 | int hns_roce_init(struct hns_roce_dev *hr_dev); |
1268 | void hns_roce_exit(struct hns_roce_dev *hr_dev); | |
9a443537 | 1269 | |
e1c9a0dc LO |
1270 | int hns_roce_fill_res_entry(struct sk_buff *msg, |
1271 | struct rdma_restrack_entry *res); | |
9a443537 | 1272 | #endif /* _HNS_ROCE_DEVICE_H */ |