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IB/hfi1: Add irq affinity notification handler
[linux-2.6-block.git] / drivers / infiniband / hw / hfi1 / sdma.c
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77241056 1/*
05d6ac1d 2 * Copyright(c) 2015, 2016 Intel Corporation.
77241056
MM		 3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
77241056
MM		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
77241056
MM		 20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48#include <linux/spinlock.h>
49#include <linux/seqlock.h>
50#include <linux/netdevice.h>
51#include <linux/moduleparam.h>
52#include <linux/bitops.h>
53#include <linux/timer.h>
54#include <linux/vmalloc.h>
f4d26d81 55#include <linux/highmem.h>
77241056
MM		 56
57#include "hfi.h"
58#include "common.h"
59#include "qp.h"
60#include "sdma.h"
61#include "iowait.h"
62#include "trace.h"
63
64/* must be a power of 2 >= 64 <= 32768 */
028d7254 65#define SDMA_DESCQ_CNT 2048
ee947859 66#define SDMA_DESC_INTR 64
77241056
MM		 67#define INVALID_TAIL 0xffff
68
69static uint sdma_descq_cnt = SDMA_DESCQ_CNT;
70module_param(sdma_descq_cnt, uint, S_IRUGO);
71MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries");
72
73static uint sdma_idle_cnt = 250;
74module_param(sdma_idle_cnt, uint, S_IRUGO);
75MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)");
76
77uint mod_num_sdma;
78module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO);
79MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");
80
ee947859
MH		 81static uint sdma_desct_intr = SDMA_DESC_INTR;
82module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR);
83MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt");
84
77241056
MM		 85#define SDMA_WAIT_BATCH_SIZE 20
86/* max wait time for a SDMA engine to indicate it has halted */
87#define SDMA_ERR_HALT_TIMEOUT 10 /* ms */
88/* all SDMA engine errors that cause a halt */
89
90#define SD(name) SEND_DMA_##name
91#define ALL_SDMA_ENG_HALT_ERRS \
92 (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \
93 | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \
94 | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \
95 | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \
96 | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \
97 | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \
98 | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \
99 | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \
100 | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \
101 | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \
102 | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \
103 | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \
104 | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \
105 | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \
106 | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \
107 | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \
108 | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \
109 | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK))
110
111/* sdma_sendctrl operations */
349ac71f 112#define SDMA_SENDCTRL_OP_ENABLE BIT(0)
113#define SDMA_SENDCTRL_OP_INTENABLE BIT(1)
114#define SDMA_SENDCTRL_OP_HALT BIT(2)
115#define SDMA_SENDCTRL_OP_CLEANUP BIT(3)
77241056
MM		 116
117/* handle long defines */
118#define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \
119SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK
120#define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \
121SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT
122
123static const char * const sdma_state_names[] = {
124 [sdma_state_s00_hw_down] = "s00_HwDown",
125 [sdma_state_s10_hw_start_up_halt_wait] = "s10_HwStartUpHaltWait",
126 [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait",
127 [sdma_state_s20_idle] = "s20_Idle",
128 [sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait",
129 [sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait",
130 [sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait",
131 [sdma_state_s60_idle_halt_wait] = "s60_IdleHaltWait",
132 [sdma_state_s80_hw_freeze] = "s80_HwFreeze",
133 [sdma_state_s82_freeze_sw_clean] = "s82_FreezeSwClean",
134 [sdma_state_s99_running] = "s99_Running",
135};
136
eac71936 137#ifdef CONFIG_SDMA_VERBOSITY
77241056
MM		 138static const char * const sdma_event_names[] = {
139 [sdma_event_e00_go_hw_down] = "e00_GoHwDown",
140 [sdma_event_e10_go_hw_start] = "e10_GoHwStart",
141 [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone",
142 [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone",
143 [sdma_event_e30_go_running] = "e30_GoRunning",
144 [sdma_event_e40_sw_cleaned] = "e40_SwCleaned",
145 [sdma_event_e50_hw_cleaned] = "e50_HwCleaned",
146 [sdma_event_e60_hw_halted] = "e60_HwHalted",
147 [sdma_event_e70_go_idle] = "e70_GoIdle",
148 [sdma_event_e80_hw_freeze] = "e80_HwFreeze",
149 [sdma_event_e81_hw_frozen] = "e81_HwFrozen",
150 [sdma_event_e82_hw_unfreeze] = "e82_HwUnfreeze",
151 [sdma_event_e85_link_down] = "e85_LinkDown",
152 [sdma_event_e90_sw_halted] = "e90_SwHalted",
153};
eac71936 154#endif
77241056
MM		 155
156static const struct sdma_set_state_action sdma_action_table[] = {
157 [sdma_state_s00_hw_down] = {
158 .go_s99_running_tofalse = 1,
159 .op_enable = 0,
160 .op_intenable = 0,
161 .op_halt = 0,
162 .op_cleanup = 0,
163 },
164 [sdma_state_s10_hw_start_up_halt_wait] = {
165 .op_enable = 0,
166 .op_intenable = 0,
167 .op_halt = 1,
168 .op_cleanup = 0,
169 },
170 [sdma_state_s15_hw_start_up_clean_wait] = {
171 .op_enable = 0,
172 .op_intenable = 1,
173 .op_halt = 0,
174 .op_cleanup = 1,
175 },
176 [sdma_state_s20_idle] = {
177 .op_enable = 0,
178 .op_intenable = 1,
179 .op_halt = 0,
180 .op_cleanup = 0,
181 },
182 [sdma_state_s30_sw_clean_up_wait] = {
183 .op_enable = 0,
184 .op_intenable = 0,
185 .op_halt = 0,
186 .op_cleanup = 0,
187 },
188 [sdma_state_s40_hw_clean_up_wait] = {
189 .op_enable = 0,
190 .op_intenable = 0,
191 .op_halt = 0,
192 .op_cleanup = 1,
193 },
194 [sdma_state_s50_hw_halt_wait] = {
195 .op_enable = 0,
196 .op_intenable = 0,
197 .op_halt = 0,
198 .op_cleanup = 0,
199 },
200 [sdma_state_s60_idle_halt_wait] = {
201 .go_s99_running_tofalse = 1,
202 .op_enable = 0,
203 .op_intenable = 0,
204 .op_halt = 1,
205 .op_cleanup = 0,
206 },
207 [sdma_state_s80_hw_freeze] = {
208 .op_enable = 0,
209 .op_intenable = 0,
210 .op_halt = 0,
211 .op_cleanup = 0,
212 },
213 [sdma_state_s82_freeze_sw_clean] = {
214 .op_enable = 0,
215 .op_intenable = 0,
216 .op_halt = 0,
217 .op_cleanup = 0,
218 },
219 [sdma_state_s99_running] = {
220 .op_enable = 1,
221 .op_intenable = 1,
222 .op_halt = 0,
223 .op_cleanup = 0,
224 .go_s99_running_totrue = 1,
225 },
226};
227
228#define SDMA_TAIL_UPDATE_THRESH 0x1F
229
230/* declare all statics here rather than keep sorting */
231static void sdma_complete(struct kref *);
232static void sdma_finalput(struct sdma_state *);
233static void sdma_get(struct sdma_state *);
234static void sdma_hw_clean_up_task(unsigned long);
235static void sdma_put(struct sdma_state *);
236static void sdma_set_state(struct sdma_engine *, enum sdma_states);
237static void sdma_start_hw_clean_up(struct sdma_engine *);
77241056
MM		 238static void sdma_sw_clean_up_task(unsigned long);
239static void sdma_sendctrl(struct sdma_engine *, unsigned);
240static void init_sdma_regs(struct sdma_engine *, u32, uint);
241static void sdma_process_event(
242 struct sdma_engine *sde,
243 enum sdma_events event);
244static void __sdma_process_event(
245 struct sdma_engine *sde,
246 enum sdma_events event);
247static void dump_sdma_state(struct sdma_engine *sde);
248static void sdma_make_progress(struct sdma_engine *sde, u64 status);
249static void sdma_desc_avail(struct sdma_engine *sde, unsigned avail);
250static void sdma_flush_descq(struct sdma_engine *sde);
251
252/**
253 * sdma_state_name() - return state string from enum
254 * @state: state
255 */
256static const char *sdma_state_name(enum sdma_states state)
257{
258 return sdma_state_names[state];
259}
260
261static void sdma_get(struct sdma_state *ss)
262{
263 kref_get(&ss->kref);
264}
265
266static void sdma_complete(struct kref *kref)
267{
268 struct sdma_state *ss =
269 container_of(kref, struct sdma_state, kref);
270
271 complete(&ss->comp);
272}
273
274static void sdma_put(struct sdma_state *ss)
275{
276 kref_put(&ss->kref, sdma_complete);
277}
278
279static void sdma_finalput(struct sdma_state *ss)
280{
281 sdma_put(ss);
282 wait_for_completion(&ss->comp);
283}
284
285static inline void write_sde_csr(
286 struct sdma_engine *sde,
287 u32 offset0,
288 u64 value)
289{
290 write_kctxt_csr(sde->dd, sde->this_idx, offset0, value);
291}
292
293static inline u64 read_sde_csr(
294 struct sdma_engine *sde,
295 u32 offset0)
296{
297 return read_kctxt_csr(sde->dd, sde->this_idx, offset0);
298}
299
300/*
301 * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for
302 * sdma engine 'sde' to drop to 0.
303 */
304static void sdma_wait_for_packet_egress(struct sdma_engine *sde,
305 int pause)
306{
307 u64 off = 8 * sde->this_idx;
308 struct hfi1_devdata *dd = sde->dd;
309 int lcnt = 0;
25d97dd5
VM		 310 u64 reg_prev;
311 u64 reg = 0;
77241056
MM		 312
313 while (1) {
25d97dd5
VM		 314 reg_prev = reg;
315 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS);
77241056
MM		 316
317 reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK;
318 reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT;
319 if (reg == 0)
320 break;
25d97dd5
VM		 321 /* counter is reest if accupancy count changes */
322 if (reg != reg_prev)
323 lcnt = 0;
324 if (lcnt++ > 500) {
325 /* timed out - bounce the link */
326 dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n",
17fb4f29 327 __func__, sde->this_idx, (u32)reg);
25d97dd5 328 queue_work(dd->pport->hfi1_wq,
17fb4f29 329 &dd->pport->link_bounce_work);
77241056
MM		 330 break;
331 }
332 udelay(1);
333 }
334}
335
336/*
337 * sdma_wait() - wait for packet egress to complete for all SDMA engines,
338 * and pause for credit return.
339 */
340void sdma_wait(struct hfi1_devdata *dd)
341{
342 int i;
343
344 for (i = 0; i < dd->num_sdma; i++) {
345 struct sdma_engine *sde = &dd->per_sdma[i];
346
347 sdma_wait_for_packet_egress(sde, 0);
348 }
349}
350
351static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt)
352{
353 u64 reg;
354
355 if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT))
356 return;
357 reg = cnt;
358 reg &= SD(DESC_CNT_CNT_MASK);
359 reg <<= SD(DESC_CNT_CNT_SHIFT);
360 write_sde_csr(sde, SD(DESC_CNT), reg);
361}
362
a545f530
MM		 363static inline void complete_tx(struct sdma_engine *sde,
364 struct sdma_txreq *tx,
365 int res)
366{
367 /* protect against complete modifying */
368 struct iowait *wait = tx->wait;
369 callback_t complete = tx->complete;
370
371#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
6b5c5213
MM		 372 trace_hfi1_sdma_out_sn(sde, tx->sn);
373 if (WARN_ON_ONCE(sde->head_sn != tx->sn))
a545f530 374 dd_dev_err(sde->dd, "expected %llu got %llu\n",
6b5c5213 375 sde->head_sn, tx->sn);
a545f530
MM		 376 sde->head_sn++;
377#endif
378 sdma_txclean(sde->dd, tx);
379 if (complete)
380 (*complete)(tx, res);
b96b0404 381 if (wait && iowait_sdma_dec(wait))
a545f530
MM		 382 iowait_drain_wakeup(wait);
383}
384
77241056
MM		 385/*
386 * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status
387 *
388 * Depending on timing there can be txreqs in two places:
389 * - in the descq ring
390 * - in the flush list
391 *
392 * To avoid ordering issues the descq ring needs to be flushed
393 * first followed by the flush list.
394 *
395 * This routine is called from two places
396 * - From a work queue item
397 * - Directly from the state machine just before setting the
398 * state to running
399 *
400 * Must be called with head_lock held
401 *
402 */
403static void sdma_flush(struct sdma_engine *sde)
404{
405 struct sdma_txreq *txp, *txp_next;
406 LIST_HEAD(flushlist);
b77d713a 407 unsigned long flags;
77241056
MM		 408
409 /* flush from head to tail */
410 sdma_flush_descq(sde);
b77d713a 411 spin_lock_irqsave(&sde->flushlist_lock, flags);
77241056
MM		 412 /* copy flush list */
413 list_for_each_entry_safe(txp, txp_next, &sde->flushlist, list) {
414 list_del_init(&txp->list);
415 list_add_tail(&txp->list, &flushlist);
416 }
b77d713a 417 spin_unlock_irqrestore(&sde->flushlist_lock, flags);
77241056 418 /* flush from flush list */
a545f530
MM		 419 list_for_each_entry_safe(txp, txp_next, &flushlist, list)
420 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
77241056
MM		 421}
422
423/*
424 * Fields a work request for flushing the descq ring
425 * and the flush list
426 *
427 * If the engine has been brought to running during
428 * the scheduling delay, the flush is ignored, assuming
429 * that the process of bringing the engine to running
430 * would have done this flush prior to going to running.
431 *
432 */
433static void sdma_field_flush(struct work_struct *work)
434{
435 unsigned long flags;
436 struct sdma_engine *sde =
437 container_of(work, struct sdma_engine, flush_worker);
438
439 write_seqlock_irqsave(&sde->head_lock, flags);
440 if (!__sdma_running(sde))
441 sdma_flush(sde);
442 write_sequnlock_irqrestore(&sde->head_lock, flags);
443}
444
445static void sdma_err_halt_wait(struct work_struct *work)
446{
447 struct sdma_engine *sde = container_of(work, struct sdma_engine,
448 err_halt_worker);
449 u64 statuscsr;
450 unsigned long timeout;
451
452 timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT);
453 while (1) {
454 statuscsr = read_sde_csr(sde, SD(STATUS));
455 statuscsr &= SD(STATUS_ENG_HALTED_SMASK);
456 if (statuscsr)
457 break;
458 if (time_after(jiffies, timeout)) {
459 dd_dev_err(sde->dd,
17fb4f29
JJ		 460 "SDMA engine %d - timeout waiting for engine to halt\n",
461 sde->this_idx);
77241056
MM		 462 /*
463 * Continue anyway. This could happen if there was
464 * an uncorrectable error in the wrong spot.
465 */
466 break;
467 }
468 usleep_range(80, 120);
469 }
470
471 sdma_process_event(sde, sdma_event_e15_hw_halt_done);
472}
473
77241056
MM		 474static void sdma_err_progress_check_schedule(struct sdma_engine *sde)
475{
476 if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) {
77241056
MM		 477 unsigned index;
478 struct hfi1_devdata *dd = sde->dd;
479
480 for (index = 0; index < dd->num_sdma; index++) {
481 struct sdma_engine *curr_sdma = &dd->per_sdma[index];
482
483 if (curr_sdma != sde)
484 curr_sdma->progress_check_head =
485 curr_sdma->descq_head;
486 }
487 dd_dev_err(sde->dd,
488 "SDMA engine %d - check scheduled\n",
489 sde->this_idx);
490 mod_timer(&sde->err_progress_check_timer, jiffies + 10);
491 }
492}
493
494static void sdma_err_progress_check(unsigned long data)
495{
496 unsigned index;
497 struct sdma_engine *sde = (struct sdma_engine *)data;
498
499 dd_dev_err(sde->dd, "SDE progress check event\n");
500 for (index = 0; index < sde->dd->num_sdma; index++) {
501 struct sdma_engine *curr_sde = &sde->dd->per_sdma[index];
502 unsigned long flags;
503
504 /* check progress on each engine except the current one */
505 if (curr_sde == sde)
506 continue;
507 /*
508 * We must lock interrupts when acquiring sde->lock,
509 * to avoid a deadlock if interrupt triggers and spins on
510 * the same lock on same CPU
511 */
512 spin_lock_irqsave(&curr_sde->tail_lock, flags);
513 write_seqlock(&curr_sde->head_lock);
514
515 /* skip non-running queues */
516 if (curr_sde->state.current_state != sdma_state_s99_running) {
517 write_sequnlock(&curr_sde->head_lock);
518 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
519 continue;
520 }
521
522 if ((curr_sde->descq_head != curr_sde->descq_tail) &&
523 (curr_sde->descq_head ==
524 curr_sde->progress_check_head))
525 __sdma_process_event(curr_sde,
526 sdma_event_e90_sw_halted);
527 write_sequnlock(&curr_sde->head_lock);
528 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
529 }
530 schedule_work(&sde->err_halt_worker);
531}
532
533static void sdma_hw_clean_up_task(unsigned long opaque)
534{
50e5dcbe 535 struct sdma_engine *sde = (struct sdma_engine *)opaque;
77241056
MM		 536 u64 statuscsr;
537
538 while (1) {
539#ifdef CONFIG_SDMA_VERBOSITY
540 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
541 sde->this_idx, slashstrip(__FILE__), __LINE__,
542 __func__);
543#endif
544 statuscsr = read_sde_csr(sde, SD(STATUS));
545 statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK);
546 if (statuscsr)
547 break;
548 udelay(10);
549 }
550
551 sdma_process_event(sde, sdma_event_e25_hw_clean_up_done);
552}
553
554static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde)
555{
556 smp_read_barrier_depends(); /* see sdma_update_tail() */
557 return sde->tx_ring[sde->tx_head & sde->sdma_mask];
558}
559
560/*
561 * flush ring for recovery
562 */
563static void sdma_flush_descq(struct sdma_engine *sde)
564{
565 u16 head, tail;
566 int progress = 0;
567 struct sdma_txreq *txp = get_txhead(sde);
568
569 /* The reason for some of the complexity of this code is that
570 * not all descriptors have corresponding txps. So, we have to
571 * be able to skip over descs until we wander into the range of
572 * the next txp on the list.
573 */
574 head = sde->descq_head & sde->sdma_mask;
575 tail = sde->descq_tail & sde->sdma_mask;
576 while (head != tail) {
577 /* advance head, wrap if needed */
578 head = ++sde->descq_head & sde->sdma_mask;
579 /* if now past this txp's descs, do the callback */
580 if (txp && txp->next_descq_idx == head) {
77241056
MM		 581 /* remove from list */
582 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
a545f530 583 complete_tx(sde, txp, SDMA_TXREQ_S_ABORTED);
77241056 584 trace_hfi1_sdma_progress(sde, head, tail, txp);
77241056
MM		 585 txp = get_txhead(sde);
586 }
587 progress++;
588 }
589 if (progress)
590 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
591}
592
593static void sdma_sw_clean_up_task(unsigned long opaque)
594{
50e5dcbe 595 struct sdma_engine *sde = (struct sdma_engine *)opaque;
77241056
MM		 596 unsigned long flags;
597
598 spin_lock_irqsave(&sde->tail_lock, flags);
599 write_seqlock(&sde->head_lock);
600
601 /*
602 * At this point, the following should always be true:
603 * - We are halted, so no more descriptors are getting retired.
604 * - We are not running, so no one is submitting new work.
605 * - Only we can send the e40_sw_cleaned, so we can't start
606 * running again until we say so. So, the active list and
607 * descq are ours to play with.
608 */
609
77241056
MM		 610 /*
611 * In the error clean up sequence, software clean must be called
612 * before the hardware clean so we can use the hardware head in
613 * the progress routine. A hardware clean or SPC unfreeze will
614 * reset the hardware head.
615 *
616 * Process all retired requests. The progress routine will use the
617 * latest physical hardware head - we are not running so speed does
618 * not matter.
619 */
620 sdma_make_progress(sde, 0);
621
622 sdma_flush(sde);
623
624 /*
625 * Reset our notion of head and tail.
626 * Note that the HW registers have been reset via an earlier
627 * clean up.
628 */
629 sde->descq_tail = 0;
630 sde->descq_head = 0;
631 sde->desc_avail = sdma_descq_freecnt(sde);
632 *sde->head_dma = 0;
633
634 __sdma_process_event(sde, sdma_event_e40_sw_cleaned);
635
636 write_sequnlock(&sde->head_lock);
637 spin_unlock_irqrestore(&sde->tail_lock, flags);
638}
639
640static void sdma_sw_tear_down(struct sdma_engine *sde)
641{
642 struct sdma_state *ss = &sde->state;
643
644 /* Releasing this reference means the state machine has stopped. */
645 sdma_put(ss);
646
647 /* stop waiting for all unfreeze events to complete */
648 atomic_set(&sde->dd->sdma_unfreeze_count, -1);
649 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
650}
651
652static void sdma_start_hw_clean_up(struct sdma_engine *sde)
653{
654 tasklet_hi_schedule(&sde->sdma_hw_clean_up_task);
655}
656
77241056 657static void sdma_set_state(struct sdma_engine *sde,
17fb4f29 658 enum sdma_states next_state)
77241056
MM		 659{
660 struct sdma_state *ss = &sde->state;
661 const struct sdma_set_state_action *action = sdma_action_table;
662 unsigned op = 0;
663
664 trace_hfi1_sdma_state(
665 sde,
666 sdma_state_names[ss->current_state],
667 sdma_state_names[next_state]);
668
669 /* debugging bookkeeping */
670 ss->previous_state = ss->current_state;
671 ss->previous_op = ss->current_op;
672 ss->current_state = next_state;
673
d0d236ea
JJ		 674 if (ss->previous_state != sdma_state_s99_running &&
675 next_state == sdma_state_s99_running)
77241056
MM		 676 sdma_flush(sde);
677
678 if (action[next_state].op_enable)
679 op |= SDMA_SENDCTRL_OP_ENABLE;
680
681 if (action[next_state].op_intenable)
682 op |= SDMA_SENDCTRL_OP_INTENABLE;
683
684 if (action[next_state].op_halt)
685 op |= SDMA_SENDCTRL_OP_HALT;
686
687 if (action[next_state].op_cleanup)
688 op |= SDMA_SENDCTRL_OP_CLEANUP;
689
690 if (action[next_state].go_s99_running_tofalse)
691 ss->go_s99_running = 0;
692
693 if (action[next_state].go_s99_running_totrue)
694 ss->go_s99_running = 1;
695
696 ss->current_op = op;
697 sdma_sendctrl(sde, ss->current_op);
698}
699
700/**
701 * sdma_get_descq_cnt() - called when device probed
702 *
703 * Return a validated descq count.
704 *
705 * This is currently only used in the verbs initialization to build the tx
706 * list.
707 *
708 * This will probably be deleted in favor of a more scalable approach to
709 * alloc tx's.
710 *
711 */
712u16 sdma_get_descq_cnt(void)
713{
714 u16 count = sdma_descq_cnt;
715
716 if (!count)
717 return SDMA_DESCQ_CNT;
718 /* count must be a power of 2 greater than 64 and less than
719 * 32768. Otherwise return default.
720 */
721 if (!is_power_of_2(count))
722 return SDMA_DESCQ_CNT;
aeef010a 723 if (count < 64 || count > 32768)
77241056
MM		 724 return SDMA_DESCQ_CNT;
725 return count;
726}
b91cc573 727
0cb2aa69
TS		 728/**
729 * sdma_engine_get_vl() - return vl for a given sdma engine
730 * @sde: sdma engine
731 *
732 * This function returns the vl mapped to a given engine, or an error if
733 * the mapping can't be found. The mapping fields are protected by RCU.
734 */
735int sdma_engine_get_vl(struct sdma_engine *sde)
736{
737 struct hfi1_devdata *dd = sde->dd;
738 struct sdma_vl_map *m;
739 u8 vl;
740
741 if (sde->this_idx >= TXE_NUM_SDMA_ENGINES)
742 return -EINVAL;
743
744 rcu_read_lock();
745 m = rcu_dereference(dd->sdma_map);
746 if (unlikely(!m)) {
747 rcu_read_unlock();
748 return -EINVAL;
749 }
750 vl = m->engine_to_vl[sde->this_idx];
751 rcu_read_unlock();
752
753 return vl;
754}
755
77241056
MM		 756/**
757 * sdma_select_engine_vl() - select sdma engine
758 * @dd: devdata
759 * @selector: a spreading factor
760 * @vl: this vl
761 *
762 *
763 * This function returns an engine based on the selector and a vl. The
764 * mapping fields are protected by RCU.
765 */
766struct sdma_engine *sdma_select_engine_vl(
767 struct hfi1_devdata *dd,
768 u32 selector,
769 u8 vl)
770{
771 struct sdma_vl_map *m;
772 struct sdma_map_elem *e;
773 struct sdma_engine *rval;
774
4be81991
IW		 775 /* NOTE This should only happen if SC->VL changed after the initial
776 * checks on the QP/AH
777 * Default will return engine 0 below
778 */
779 if (vl >= num_vls) {
780 rval = NULL;
781 goto done;
782 }
77241056
MM		 783
784 rcu_read_lock();
785 m = rcu_dereference(dd->sdma_map);
786 if (unlikely(!m)) {
787 rcu_read_unlock();
0a226edd 788 return &dd->per_sdma[0];
77241056
MM		 789 }
790 e = m->map[vl & m->mask];
791 rval = e->sde[selector & e->mask];
792 rcu_read_unlock();
793
4be81991 794done:
0a226edd 795 rval = !rval ? &dd->per_sdma[0] : rval;
77241056
MM		 796 trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx);
797 return rval;
798}
799
800/**
801 * sdma_select_engine_sc() - select sdma engine
802 * @dd: devdata
803 * @selector: a spreading factor
804 * @sc5: the 5 bit sc
805 *
806 *
807 * This function returns an engine based on the selector and an sc.
808 */
809struct sdma_engine *sdma_select_engine_sc(
810 struct hfi1_devdata *dd,
811 u32 selector,
812 u8 sc5)
813{
814 u8 vl = sc_to_vlt(dd, sc5);
815
816 return sdma_select_engine_vl(dd, selector, vl);
817}
818
0cb2aa69
TS		 819struct sdma_rht_map_elem {
820 u32 mask;
821 u8 ctr;
822 struct sdma_engine *sde[0];
823};
824
825struct sdma_rht_node {
826 unsigned long cpu_id;
827 struct sdma_rht_map_elem *map[HFI1_MAX_VLS_SUPPORTED];
828 struct rhash_head node;
829};
830
831#define NR_CPUS_HINT 192
832
833static const struct rhashtable_params sdma_rht_params = {
834 .nelem_hint = NR_CPUS_HINT,
835 .head_offset = offsetof(struct sdma_rht_node, node),
836 .key_offset = offsetof(struct sdma_rht_node, cpu_id),
837 .key_len = FIELD_SIZEOF(struct sdma_rht_node, cpu_id),
838 .max_size = NR_CPUS,
839 .min_size = 8,
840 .automatic_shrinking = true,
841};
842
843/*
844 * sdma_select_user_engine() - select sdma engine based on user setup
845 * @dd: devdata
846 * @selector: a spreading factor
847 * @vl: this vl
848 *
849 * This function returns an sdma engine for a user sdma request.
850 * User defined sdma engine affinity setting is honored when applicable,
851 * otherwise system default sdma engine mapping is used. To ensure correct
852 * ordering, the mapping from <selector, vl> to sde must remain unchanged.
853 */
854struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd,
855 u32 selector, u8 vl)
856{
857 struct sdma_rht_node *rht_node;
858 struct sdma_engine *sde = NULL;
859 const struct cpumask *current_mask = tsk_cpus_allowed(current);
860 unsigned long cpu_id;
861
862 /*
863 * To ensure that always the same sdma engine(s) will be
864 * selected make sure the process is pinned to this CPU only.
865 */
866 if (cpumask_weight(current_mask) != 1)
867 goto out;
868
869 cpu_id = smp_processor_id();
870 rcu_read_lock();
871 rht_node = rhashtable_lookup_fast(&dd->sdma_rht, &cpu_id,
872 sdma_rht_params);
873
874 if (rht_node && rht_node->map[vl]) {
875 struct sdma_rht_map_elem *map = rht_node->map[vl];
876
877 sde = map->sde[selector & map->mask];
878 }
879 rcu_read_unlock();
880
881 if (sde)
882 return sde;
883
884out:
885 return sdma_select_engine_vl(dd, selector, vl);
886}
887
888static void sdma_populate_sde_map(struct sdma_rht_map_elem *map)
889{
890 int i;
891
892 for (i = 0; i < roundup_pow_of_two(map->ctr ? : 1) - map->ctr; i++)
893 map->sde[map->ctr + i] = map->sde[i];
894}
895
896static void sdma_cleanup_sde_map(struct sdma_rht_map_elem *map,
897 struct sdma_engine *sde)
898{
899 unsigned int i, pow;
900
901 /* only need to check the first ctr entries for a match */
902 for (i = 0; i < map->ctr; i++) {
903 if (map->sde[i] == sde) {
904 memmove(&map->sde[i], &map->sde[i + 1],
905 (map->ctr - i - 1) * sizeof(map->sde[0]));
906 map->ctr--;
907 pow = roundup_pow_of_two(map->ctr ? : 1);
908 map->mask = pow - 1;
909 sdma_populate_sde_map(map);
910 break;
911 }
912 }
913}
914
915/*
916 * Prevents concurrent reads and writes of the sdma engine cpu_mask
917 */
918static DEFINE_MUTEX(process_to_sde_mutex);
919
920ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf,
921 size_t count)
922{
923 struct hfi1_devdata *dd = sde->dd;
924 cpumask_var_t mask, new_mask;
925 unsigned long cpu;
926 int ret, vl, sz;
927
928 vl = sdma_engine_get_vl(sde);
929 if (unlikely(vl < 0))
930 return -EINVAL;
931
932 ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
933 if (!ret)
934 return -ENOMEM;
935
936 ret = zalloc_cpumask_var(&new_mask, GFP_KERNEL);
937 if (!ret) {
938 free_cpumask_var(mask);
939 return -ENOMEM;
940 }
941 ret = cpulist_parse(buf, mask);
942 if (ret)
943 goto out_free;
944
945 if (!cpumask_subset(mask, cpu_online_mask)) {
946 dd_dev_warn(sde->dd, "Invalid CPU mask\n");
947 ret = -EINVAL;
948 goto out_free;
949 }
950
951 sz = sizeof(struct sdma_rht_map_elem) +
952 (TXE_NUM_SDMA_ENGINES * sizeof(struct sdma_engine *));
953
954 mutex_lock(&process_to_sde_mutex);
955
956 for_each_cpu(cpu, mask) {
957 struct sdma_rht_node *rht_node;
958
959 /* Check if we have this already mapped */
960 if (cpumask_test_cpu(cpu, &sde->cpu_mask)) {
961 cpumask_set_cpu(cpu, new_mask);
962 continue;
963 }
964
965 rht_node = rhashtable_lookup_fast(&dd->sdma_rht, &cpu,
966 sdma_rht_params);
967 if (!rht_node) {
968 rht_node = kzalloc(sizeof(*rht_node), GFP_KERNEL);
969 if (!rht_node) {
970 ret = -ENOMEM;
971 goto out;
972 }
973
974 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL);
975 if (!rht_node->map[vl]) {
976 kfree(rht_node);
977 ret = -ENOMEM;
978 goto out;
979 }
980 rht_node->cpu_id = cpu;
981 rht_node->map[vl]->mask = 0;
982 rht_node->map[vl]->ctr = 1;
983 rht_node->map[vl]->sde[0] = sde;
984
985 ret = rhashtable_insert_fast(&dd->sdma_rht,
986 &rht_node->node,
987 sdma_rht_params);
988 if (ret) {
989 kfree(rht_node->map[vl]);
990 kfree(rht_node);
991 dd_dev_err(sde->dd, "Failed to set process to sde affinity for cpu %lu\n",
992 cpu);
993 goto out;
994 }
995
996 } else {
997 int ctr, pow;
998
999 /* Add new user mappings */
1000 if (!rht_node->map[vl])
1001 rht_node->map[vl] = kzalloc(sz, GFP_KERNEL);
1002
1003 if (!rht_node->map[vl]) {
1004 ret = -ENOMEM;
1005 goto out;
1006 }
1007
1008 rht_node->map[vl]->ctr++;
1009 ctr = rht_node->map[vl]->ctr;
1010 rht_node->map[vl]->sde[ctr - 1] = sde;
1011 pow = roundup_pow_of_two(ctr);
1012 rht_node->map[vl]->mask = pow - 1;
1013
1014 /* Populate the sde map table */
1015 sdma_populate_sde_map(rht_node->map[vl]);
1016 }
1017 cpumask_set_cpu(cpu, new_mask);
1018 }
1019
1020 /* Clean up old mappings */
1021 for_each_cpu(cpu, cpu_online_mask) {
1022 struct sdma_rht_node *rht_node;
1023
1024 /* Don't cleanup sdes that are set in the new mask */
1025 if (cpumask_test_cpu(cpu, mask))
1026 continue;
1027
1028 rht_node = rhashtable_lookup_fast(&dd->sdma_rht, &cpu,
1029 sdma_rht_params);
1030 if (rht_node) {
1031 bool empty = true;
1032 int i;
1033
1034 /* Remove mappings for old sde */
1035 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1036 if (rht_node->map[i])
1037 sdma_cleanup_sde_map(rht_node->map[i],
1038 sde);
1039
1040 /* Free empty hash table entries */
1041 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++) {
1042 if (!rht_node->map[i])
1043 continue;
1044
1045 if (rht_node->map[i]->ctr) {
1046 empty = false;
1047 break;
1048 }
1049 }
1050
1051 if (empty) {
1052 ret = rhashtable_remove_fast(&dd->sdma_rht,
1053 &rht_node->node,
1054 sdma_rht_params);
1055 WARN_ON(ret);
1056
1057 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1058 kfree(rht_node->map[i]);
1059
1060 kfree(rht_node);
1061 }
1062 }
1063 }
1064
1065 cpumask_copy(&sde->cpu_mask, new_mask);
1066out:
1067 mutex_unlock(&process_to_sde_mutex);
1068out_free:
1069 free_cpumask_var(mask);
1070 free_cpumask_var(new_mask);
1071 return ret ? : strnlen(buf, PAGE_SIZE);
1072}
1073
1074ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf)
1075{
1076 mutex_lock(&process_to_sde_mutex);
1077 if (cpumask_empty(&sde->cpu_mask))
1078 snprintf(buf, PAGE_SIZE, "%s\n", "empty");
1079 else
1080 cpumap_print_to_pagebuf(true, buf, &sde->cpu_mask);
1081 mutex_unlock(&process_to_sde_mutex);
1082 return strnlen(buf, PAGE_SIZE);
1083}
1084
1085static void sdma_rht_free(void *ptr, void *arg)
1086{
1087 struct sdma_rht_node *rht_node = ptr;
1088 int i;
1089
1090 for (i = 0; i < HFI1_MAX_VLS_SUPPORTED; i++)
1091 kfree(rht_node->map[i]);
1092
1093 kfree(rht_node);
1094}
1095
77241056
MM		 1096/*
1097 * Free the indicated map struct
1098 */
1099static void sdma_map_free(struct sdma_vl_map *m)
1100{
1101 int i;
1102
1103 for (i = 0; m && i < m->actual_vls; i++)
1104 kfree(m->map[i]);
1105 kfree(m);
1106}
1107
1108/*
1109 * Handle RCU callback
1110 */
1111static void sdma_map_rcu_callback(struct rcu_head *list)
1112{
1113 struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list);
1114
1115 sdma_map_free(m);
1116}
1117
1118/**
1119 * sdma_map_init - called when # vls change
1120 * @dd: hfi1_devdata
1121 * @port: port number
1122 * @num_vls: number of vls
1123 * @vl_engines: per vl engine mapping (optional)
1124 *
1125 * This routine changes the mapping based on the number of vls.
1126 *
1127 * vl_engines is used to specify a non-uniform vl/engine loading. NULL
1128 * implies auto computing the loading and giving each VLs a uniform
1129 * distribution of engines per VL.
1130 *
1131 * The auto algorithm computes the sde_per_vl and the number of extra
1132 * engines. Any extra engines are added from the last VL on down.
1133 *
1134 * rcu locking is used here to control access to the mapping fields.
1135 *
1136 * If either the num_vls or num_sdma are non-power of 2, the array sizes
1137 * in the struct sdma_vl_map and the struct sdma_map_elem are rounded
1138 * up to the next highest power of 2 and the first entry is reused
1139 * in a round robin fashion.
1140 *
1141 * If an error occurs the map change is not done and the mapping is
1142 * not changed.
1143 *
1144 */
1145int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines)
1146{
1147 int i, j;
1148 int extra, sde_per_vl;
1149 int engine = 0;
1150 u8 lvl_engines[OPA_MAX_VLS];
1151 struct sdma_vl_map *oldmap, *newmap;
1152
1153 if (!(dd->flags & HFI1_HAS_SEND_DMA))
1154 return 0;
1155
1156 if (!vl_engines) {
1157 /* truncate divide */
1158 sde_per_vl = dd->num_sdma / num_vls;
1159 /* extras */
1160 extra = dd->num_sdma % num_vls;
1161 vl_engines = lvl_engines;
1162 /* add extras from last vl down */
1163 for (i = num_vls - 1; i >= 0; i--, extra--)
1164 vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0);
1165 }
1166 /* build new map */
1167 newmap = kzalloc(
1168 sizeof(struct sdma_vl_map) +
1169 roundup_pow_of_two(num_vls) *
1170 sizeof(struct sdma_map_elem *),
1171 GFP_KERNEL);
1172 if (!newmap)
1173 goto bail;
1174 newmap->actual_vls = num_vls;
1175 newmap->vls = roundup_pow_of_two(num_vls);
1176 newmap->mask = (1 << ilog2(newmap->vls)) - 1;
69a00b8e
MM		 1177 /* initialize back-map */
1178 for (i = 0; i < TXE_NUM_SDMA_ENGINES; i++)
1179 newmap->engine_to_vl[i] = -1;
77241056
MM		 1180 for (i = 0; i < newmap->vls; i++) {
1181 /* save for wrap around */
1182 int first_engine = engine;
1183
1184 if (i < newmap->actual_vls) {
1185 int sz = roundup_pow_of_two(vl_engines[i]);
1186
1187 /* only allocate once */
1188 newmap->map[i] = kzalloc(
1189 sizeof(struct sdma_map_elem) +
1190 sz * sizeof(struct sdma_engine *),
1191 GFP_KERNEL);
1192 if (!newmap->map[i])
1193 goto bail;
1194 newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
1195 /* assign engines */
1196 for (j = 0; j < sz; j++) {
1197 newmap->map[i]->sde[j] =
1198 &dd->per_sdma[engine];
1199 if (++engine >= first_engine + vl_engines[i])
1200 /* wrap back to first engine */
1201 engine = first_engine;
1202 }
69a00b8e
MM		 1203 /* assign back-map */
1204 for (j = 0; j < vl_engines[i]; j++)
1205 newmap->engine_to_vl[first_engine + j] = i;
77241056
MM		 1206 } else {
1207 /* just re-use entry without allocating */
1208 newmap->map[i] = newmap->map[i % num_vls];
1209 }
1210 engine = first_engine + vl_engines[i];
1211 }
1212 /* newmap in hand, save old map */
1213 spin_lock_irq(&dd->sde_map_lock);
1214 oldmap = rcu_dereference_protected(dd->sdma_map,
17fb4f29 1215 lockdep_is_held(&dd->sde_map_lock));
77241056
MM		 1216
1217 /* publish newmap */
1218 rcu_assign_pointer(dd->sdma_map, newmap);
1219
1220 spin_unlock_irq(&dd->sde_map_lock);
1221 /* success, free any old map after grace period */
1222 if (oldmap)
1223 call_rcu(&oldmap->list, sdma_map_rcu_callback);
1224 return 0;
1225bail:
1226 /* free any partial allocation */
1227 sdma_map_free(newmap);
1228 return -ENOMEM;
1229}
1230
1231/*
1232 * Clean up allocated memory.
1233 *
1234 * This routine is can be called regardless of the success of sdma_init()
1235 *
1236 */
1237static void sdma_clean(struct hfi1_devdata *dd, size_t num_engines)
1238{
1239 size_t i;
1240 struct sdma_engine *sde;
1241
1242 if (dd->sdma_pad_dma) {
1243 dma_free_coherent(&dd->pcidev->dev, 4,
1244 (void *)dd->sdma_pad_dma,
1245 dd->sdma_pad_phys);
1246 dd->sdma_pad_dma = NULL;
1247 dd->sdma_pad_phys = 0;
1248 }
1249 if (dd->sdma_heads_dma) {
1250 dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size,
1251 (void *)dd->sdma_heads_dma,
1252 dd->sdma_heads_phys);
1253 dd->sdma_heads_dma = NULL;
1254 dd->sdma_heads_phys = 0;
1255 }
1256 for (i = 0; dd->per_sdma && i < num_engines; ++i) {
1257 sde = &dd->per_sdma[i];
1258
1259 sde->head_dma = NULL;
1260 sde->head_phys = 0;
1261
1262 if (sde->descq) {
1263 dma_free_coherent(
1264 &dd->pcidev->dev,
1265 sde->descq_cnt * sizeof(u64[2]),
1266 sde->descq,
1267 sde->descq_phys
1268 );
1269 sde->descq = NULL;
1270 sde->descq_phys = 0;
1271 }
60f57ec2 1272 kvfree(sde->tx_ring);
77241056
MM		 1273 sde->tx_ring = NULL;
1274 }
1275 spin_lock_irq(&dd->sde_map_lock);
79d0c088 1276 sdma_map_free(rcu_access_pointer(dd->sdma_map));
77241056
MM		 1277 RCU_INIT_POINTER(dd->sdma_map, NULL);
1278 spin_unlock_irq(&dd->sde_map_lock);
1279 synchronize_rcu();
1280 kfree(dd->per_sdma);
1281 dd->per_sdma = NULL;
1282}
1283
1284/**
1285 * sdma_init() - called when device probed
1286 * @dd: hfi1_devdata
1287 * @port: port number (currently only zero)
1288 *
1289 * sdma_init initializes the specified number of engines.
1290 *
1291 * The code initializes each sde, its csrs. Interrupts
1292 * are not required to be enabled.
1293 *
1294 * Returns:
1295 * 0 - success, -errno on failure
1296 */
1297int sdma_init(struct hfi1_devdata *dd, u8 port)
1298{
1299 unsigned this_idx;
1300 struct sdma_engine *sde;
1301 u16 descq_cnt;
1302 void *curr_head;
1303 struct hfi1_pportdata *ppd = dd->pport + port;
1304 u32 per_sdma_credits;
1305 uint idle_cnt = sdma_idle_cnt;
1306 size_t num_engines = dd->chip_sdma_engines;
1307
1308 if (!HFI1_CAP_IS_KSET(SDMA)) {
1309 HFI1_CAP_CLEAR(SDMA_AHG);
1310 return 0;
1311 }
1312 if (mod_num_sdma &&
17fb4f29
JJ		 1313 /* can't exceed chip support */
1314 mod_num_sdma <= dd->chip_sdma_engines &&
1315 /* count must be >= vls */
1316 mod_num_sdma >= num_vls)
77241056
MM		 1317 num_engines = mod_num_sdma;
1318
1319 dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma);
1320 dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", dd->chip_sdma_engines);
1321 dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n",
17fb4f29 1322 dd->chip_sdma_mem_size);
77241056
MM		 1323
1324 per_sdma_credits =
8638b77f 1325 dd->chip_sdma_mem_size / (num_engines * SDMA_BLOCK_SIZE);
77241056
MM		 1326
1327 /* set up freeze waitqueue */
1328 init_waitqueue_head(&dd->sdma_unfreeze_wq);
1329 atomic_set(&dd->sdma_unfreeze_count, 0);
1330
1331 descq_cnt = sdma_get_descq_cnt();
1332 dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n",
17fb4f29 1333 num_engines, descq_cnt);
77241056
MM		 1334
1335 /* alloc memory for array of send engines */
1336 dd->per_sdma = kcalloc(num_engines, sizeof(*dd->per_sdma), GFP_KERNEL);
1337 if (!dd->per_sdma)
1338 return -ENOMEM;
1339
1340 idle_cnt = ns_to_cclock(dd, idle_cnt);
ee947859
MH		 1341 if (!sdma_desct_intr)
1342 sdma_desct_intr = SDMA_DESC_INTR;
1343
77241056
MM		 1344 /* Allocate memory for SendDMA descriptor FIFOs */
1345 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1346 sde = &dd->per_sdma[this_idx];
1347 sde->dd = dd;
1348 sde->ppd = ppd;
1349 sde->this_idx = this_idx;
1350 sde->descq_cnt = descq_cnt;
1351 sde->desc_avail = sdma_descq_freecnt(sde);
1352 sde->sdma_shift = ilog2(descq_cnt);
1353 sde->sdma_mask = (1 << sde->sdma_shift) - 1;
a699c6c2
VM		 1354
1355 /* Create a mask specifically for each interrupt source */
1356 sde->int_mask = (u64)1 << (0 * TXE_NUM_SDMA_ENGINES +
1357 this_idx);
1358 sde->progress_mask = (u64)1 << (1 * TXE_NUM_SDMA_ENGINES +
1359 this_idx);
1360 sde->idle_mask = (u64)1 << (2 * TXE_NUM_SDMA_ENGINES +
1361 this_idx);
1362 /* Create a combined mask to cover all 3 interrupt sources */
1363 sde->imask = sde->int_mask | sde->progress_mask |
1364 sde->idle_mask;
1365
77241056
MM		 1366 spin_lock_init(&sde->tail_lock);
1367 seqlock_init(&sde->head_lock);
1368 spin_lock_init(&sde->senddmactrl_lock);
1369 spin_lock_init(&sde->flushlist_lock);
1370 /* insure there is always a zero bit */
1371 sde->ahg_bits = 0xfffffffe00000000ULL;
1372
1373 sdma_set_state(sde, sdma_state_s00_hw_down);
1374
1375 /* set up reference counting */
1376 kref_init(&sde->state.kref);
1377 init_completion(&sde->state.comp);
1378
1379 INIT_LIST_HEAD(&sde->flushlist);
1380 INIT_LIST_HEAD(&sde->dmawait);
1381
1382 sde->tail_csr =
1383 get_kctxt_csr_addr(dd, this_idx, SD(TAIL));
1384
1385 if (idle_cnt)
1386 dd->default_desc1 =
1387 SDMA_DESC1_HEAD_TO_HOST_FLAG;
1388 else
1389 dd->default_desc1 =
1390 SDMA_DESC1_INT_REQ_FLAG;
1391
1392 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task,
17fb4f29 1393 (unsigned long)sde);
77241056
MM		 1394
1395 tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task,
17fb4f29 1396 (unsigned long)sde);
77241056
MM		 1397 INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait);
1398 INIT_WORK(&sde->flush_worker, sdma_field_flush);
1399
1400 sde->progress_check_head = 0;
1401
daac731b
MFW		 1402 setup_timer(&sde->err_progress_check_timer,
1403 sdma_err_progress_check, (unsigned long)sde);
77241056
MM		 1404
1405 sde->descq = dma_zalloc_coherent(
1406 &dd->pcidev->dev,
1407 descq_cnt * sizeof(u64[2]),
1408 &sde->descq_phys,
1409 GFP_KERNEL
1410 );
1411 if (!sde->descq)
1412 goto bail;
1413 sde->tx_ring =
1414 kcalloc(descq_cnt, sizeof(struct sdma_txreq *),
1415 GFP_KERNEL);
1416 if (!sde->tx_ring)
1417 sde->tx_ring =
1418 vzalloc(
1419 sizeof(struct sdma_txreq *) *
1420 descq_cnt);
1421 if (!sde->tx_ring)
1422 goto bail;
1423 }
1424
1425 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines;
1426 /* Allocate memory for DMA of head registers to memory */
1427 dd->sdma_heads_dma = dma_zalloc_coherent(
1428 &dd->pcidev->dev,
1429 dd->sdma_heads_size,
1430 &dd->sdma_heads_phys,
1431 GFP_KERNEL
1432 );
1433 if (!dd->sdma_heads_dma) {
1434 dd_dev_err(dd, "failed to allocate SendDMA head memory\n");
1435 goto bail;
1436 }
1437
1438 /* Allocate memory for pad */
1439 dd->sdma_pad_dma = dma_zalloc_coherent(
1440 &dd->pcidev->dev,
1441 sizeof(u32),
1442 &dd->sdma_pad_phys,
1443 GFP_KERNEL
1444 );
1445 if (!dd->sdma_pad_dma) {
1446 dd_dev_err(dd, "failed to allocate SendDMA pad memory\n");
1447 goto bail;
1448 }
1449
1450 /* assign each engine to different cacheline and init registers */
1451 curr_head = (void *)dd->sdma_heads_dma;
1452 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1453 unsigned long phys_offset;
1454
1455 sde = &dd->per_sdma[this_idx];
1456
1457 sde->head_dma = curr_head;
1458 curr_head += L1_CACHE_BYTES;
1459 phys_offset = (unsigned long)sde->head_dma -
1460 (unsigned long)dd->sdma_heads_dma;
1461 sde->head_phys = dd->sdma_heads_phys + phys_offset;
1462 init_sdma_regs(sde, per_sdma_credits, idle_cnt);
1463 }
1464 dd->flags |= HFI1_HAS_SEND_DMA;
1465 dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0;
1466 dd->num_sdma = num_engines;
1467 if (sdma_map_init(dd, port, ppd->vls_operational, NULL))
1468 goto bail;
0cb2aa69
TS		 1469
1470 if (rhashtable_init(&dd->sdma_rht, &sdma_rht_params))
1471 goto bail;
1472
77241056
MM		 1473 dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma);
1474 return 0;
1475
1476bail:
1477 sdma_clean(dd, num_engines);
1478 return -ENOMEM;
1479}
1480
1481/**
1482 * sdma_all_running() - called when the link goes up
1483 * @dd: hfi1_devdata
1484 *
1485 * This routine moves all engines to the running state.
1486 */
1487void sdma_all_running(struct hfi1_devdata *dd)
1488{
1489 struct sdma_engine *sde;
1490 unsigned int i;
1491
1492 /* move all engines to running */
1493 for (i = 0; i < dd->num_sdma; ++i) {
1494 sde = &dd->per_sdma[i];
1495 sdma_process_event(sde, sdma_event_e30_go_running);
1496 }
1497}
1498
1499/**
1500 * sdma_all_idle() - called when the link goes down
1501 * @dd: hfi1_devdata
1502 *
1503 * This routine moves all engines to the idle state.
1504 */
1505void sdma_all_idle(struct hfi1_devdata *dd)
1506{
1507 struct sdma_engine *sde;
1508 unsigned int i;
1509
1510 /* idle all engines */
1511 for (i = 0; i < dd->num_sdma; ++i) {
1512 sde = &dd->per_sdma[i];
1513 sdma_process_event(sde, sdma_event_e70_go_idle);
1514 }
1515}
1516
1517/**
1518 * sdma_start() - called to kick off state processing for all engines
1519 * @dd: hfi1_devdata
1520 *
1521 * This routine is for kicking off the state processing for all required
1522 * sdma engines. Interrupts need to be working at this point.
1523 *
1524 */
1525void sdma_start(struct hfi1_devdata *dd)
1526{
1527 unsigned i;
1528 struct sdma_engine *sde;
1529
1530 /* kick off the engines state processing */
1531 for (i = 0; i < dd->num_sdma; ++i) {
1532 sde = &dd->per_sdma[i];
1533 sdma_process_event(sde, sdma_event_e10_go_hw_start);
1534 }
1535}
1536
1537/**
1538 * sdma_exit() - used when module is removed
1539 * @dd: hfi1_devdata
1540 */
1541void sdma_exit(struct hfi1_devdata *dd)
1542{
1543 unsigned this_idx;
1544 struct sdma_engine *sde;
1545
1546 for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma;
1547 ++this_idx) {
77241056
MM		 1548 sde = &dd->per_sdma[this_idx];
1549 if (!list_empty(&sde->dmawait))
1550 dd_dev_err(dd, "sde %u: dmawait list not empty!\n",
17fb4f29 1551 sde->this_idx);
77241056
MM		 1552 sdma_process_event(sde, sdma_event_e00_go_hw_down);
1553
1554 del_timer_sync(&sde->err_progress_check_timer);
1555
1556 /*
1557 * This waits for the state machine to exit so it is not
1558 * necessary to kill the sdma_sw_clean_up_task to make sure
1559 * it is not running.
1560 */
1561 sdma_finalput(&sde->state);
1562 }
1563 sdma_clean(dd, dd->num_sdma);
0cb2aa69 1564 rhashtable_free_and_destroy(&dd->sdma_rht, sdma_rht_free, NULL);
77241056
MM		 1565}
1566
1567/*
1568 * unmap the indicated descriptor
1569 */
1570static inline void sdma_unmap_desc(
1571 struct hfi1_devdata *dd,
1572 struct sdma_desc *descp)
1573{
1574 switch (sdma_mapping_type(descp)) {
1575 case SDMA_MAP_SINGLE:
1576 dma_unmap_single(
1577 &dd->pcidev->dev,
1578 sdma_mapping_addr(descp),
1579 sdma_mapping_len(descp),
1580 DMA_TO_DEVICE);
1581 break;
1582 case SDMA_MAP_PAGE:
1583 dma_unmap_page(
1584 &dd->pcidev->dev,
1585 sdma_mapping_addr(descp),
1586 sdma_mapping_len(descp),
1587 DMA_TO_DEVICE);
1588 break;
1589 }
1590}
1591
1592/*
1593 * return the mode as indicated by the first
1594 * descriptor in the tx.
1595 */
1596static inline u8 ahg_mode(struct sdma_txreq *tx)
1597{
1598 return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1599 >> SDMA_DESC1_HEADER_MODE_SHIFT;
1600}
1601
1602/**
1603 * sdma_txclean() - clean tx of mappings, descp *kmalloc's
1604 * @dd: hfi1_devdata for unmapping
1605 * @tx: tx request to clean
1606 *
1607 * This is used in the progress routine to clean the tx or
1608 * by the ULP to toss an in-process tx build.
1609 *
1610 * The code can be called multiple times without issue.
1611 *
1612 */
1613void sdma_txclean(
1614 struct hfi1_devdata *dd,
1615 struct sdma_txreq *tx)
1616{
1617 u16 i;
1618
1619 if (tx->num_desc) {
1620 u8 skip = 0, mode = ahg_mode(tx);
1621
1622 /* unmap first */
1623 sdma_unmap_desc(dd, &tx->descp[0]);
1624 /* determine number of AHG descriptors to skip */
1625 if (mode > SDMA_AHG_APPLY_UPDATE1)
1626 skip = mode >> 1;
1627 for (i = 1 + skip; i < tx->num_desc; i++)
1628 sdma_unmap_desc(dd, &tx->descp[i]);
1629 tx->num_desc = 0;
1630 }
1631 kfree(tx->coalesce_buf);
1632 tx->coalesce_buf = NULL;
1633 /* kmalloc'ed descp */
1634 if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) {
1635 tx->desc_limit = ARRAY_SIZE(tx->descs);
1636 kfree(tx->descp);
1637 }
1638}
1639
1640static inline u16 sdma_gethead(struct sdma_engine *sde)
1641{
1642 struct hfi1_devdata *dd = sde->dd;
1643 int use_dmahead;
1644 u16 hwhead;
1645
1646#ifdef CONFIG_SDMA_VERBOSITY
1647 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1648 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1649#endif
1650
1651retry:
1652 use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) &&
1653 (dd->flags & HFI1_HAS_SDMA_TIMEOUT);
1654 hwhead = use_dmahead ?
50e5dcbe
JJ		 1655 (u16)le64_to_cpu(*sde->head_dma) :
1656 (u16)read_sde_csr(sde, SD(HEAD));
77241056
MM		 1657
1658 if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) {
1659 u16 cnt;
1660 u16 swtail;
1661 u16 swhead;
1662 int sane;
1663
1664 swhead = sde->descq_head & sde->sdma_mask;
1665 /* this code is really bad for cache line trading */
1666 swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
1667 cnt = sde->descq_cnt;
1668
1669 if (swhead < swtail)
1670 /* not wrapped */
1671 sane = (hwhead >= swhead) & (hwhead <= swtail);
1672 else if (swhead > swtail)
1673 /* wrapped around */
1674 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
1675 (hwhead <= swtail);
1676 else
1677 /* empty */
1678 sane = (hwhead == swhead);
1679
1680 if (unlikely(!sane)) {
1681 dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n",
17fb4f29
JJ		 1682 sde->this_idx,
1683 use_dmahead ? "dma" : "kreg",
1684 hwhead, swhead, swtail, cnt);
77241056
MM		 1685 if (use_dmahead) {
1686 /* try one more time, using csr */
1687 use_dmahead = 0;
1688 goto retry;
1689 }
1690 /* proceed as if no progress */
1691 hwhead = swhead;
1692 }
1693 }
1694 return hwhead;
1695}
1696
1697/*
1698 * This is called when there are send DMA descriptors that might be
1699 * available.
1700 *
1701 * This is called with head_lock held.
1702 */
1703static void sdma_desc_avail(struct sdma_engine *sde, unsigned avail)
1704{
1705 struct iowait *wait, *nw;
1706 struct iowait *waits[SDMA_WAIT_BATCH_SIZE];
1707 unsigned i, n = 0, seq;
1708 struct sdma_txreq *stx;
1709 struct hfi1_ibdev *dev = &sde->dd->verbs_dev;
1710
1711#ifdef CONFIG_SDMA_VERBOSITY
1712 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
1713 slashstrip(__FILE__), __LINE__, __func__);
1714 dd_dev_err(sde->dd, "avail: %u\n", avail);
1715#endif
1716
1717 do {
1718 seq = read_seqbegin(&dev->iowait_lock);
1719 if (!list_empty(&sde->dmawait)) {
1720 /* at least one item */
1721 write_seqlock(&dev->iowait_lock);
1722 /* Harvest waiters wanting DMA descriptors */
1723 list_for_each_entry_safe(
1724 wait,
1725 nw,
1726 &sde->dmawait,
1727 list) {
1728 u16 num_desc = 0;
1729
1730 if (!wait->wakeup)
1731 continue;
1732 if (n == ARRAY_SIZE(waits))
1733 break;
1734 if (!list_empty(&wait->tx_head)) {
1735 stx = list_first_entry(
1736 &wait->tx_head,
1737 struct sdma_txreq,
1738 list);
1739 num_desc = stx->num_desc;
1740 }
1741 if (num_desc > avail)
1742 break;
1743 avail -= num_desc;
1744 list_del_init(&wait->list);
1745 waits[n++] = wait;
1746 }
1747 write_sequnlock(&dev->iowait_lock);
1748 break;
1749 }
1750 } while (read_seqretry(&dev->iowait_lock, seq));
1751
1752 for (i = 0; i < n; i++)
1753 waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON);
1754}
1755
1756/* head_lock must be held */
1757static void sdma_make_progress(struct sdma_engine *sde, u64 status)
1758{
1759 struct sdma_txreq *txp = NULL;
1760 int progress = 0;
a545f530 1761 u16 hwhead, swhead;
77241056
MM		 1762 int idle_check_done = 0;
1763
1764 hwhead = sdma_gethead(sde);
1765
1766 /* The reason for some of the complexity of this code is that
1767 * not all descriptors have corresponding txps. So, we have to
1768 * be able to skip over descs until we wander into the range of
1769 * the next txp on the list.
1770 */
1771
1772retry:
1773 txp = get_txhead(sde);
1774 swhead = sde->descq_head & sde->sdma_mask;
1775 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1776 while (swhead != hwhead) {
1777 /* advance head, wrap if needed */
1778 swhead = ++sde->descq_head & sde->sdma_mask;
1779
1780 /* if now past this txp's descs, do the callback */
1781 if (txp && txp->next_descq_idx == swhead) {
77241056
MM		 1782 /* remove from list */
1783 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
a545f530 1784 complete_tx(sde, txp, SDMA_TXREQ_S_OK);
77241056
MM		 1785 /* see if there is another txp */
1786 txp = get_txhead(sde);
1787 }
1788 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1789 progress++;
1790 }
1791
1792 /*
1793 * The SDMA idle interrupt is not guaranteed to be ordered with respect
1794 * to updates to the the dma_head location in host memory. The head
1795 * value read might not be fully up to date. If there are pending
1796 * descriptors and the SDMA idle interrupt fired then read from the
1797 * CSR SDMA head instead to get the latest value from the hardware.
1798 * The hardware SDMA head should be read at most once in this invocation
1799 * of sdma_make_progress(..) which is ensured by idle_check_done flag
1800 */
1801 if ((status & sde->idle_mask) && !idle_check_done) {
a545f530
MM		 1802 u16 swtail;
1803
77241056
MM		 1804 swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
1805 if (swtail != hwhead) {
1806 hwhead = (u16)read_sde_csr(sde, SD(HEAD));
1807 idle_check_done = 1;
1808 goto retry;
1809 }
1810 }
1811
1812 sde->last_status = status;
1813 if (progress)
1814 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
1815}
1816
1817/*
1818 * sdma_engine_interrupt() - interrupt handler for engine
1819 * @sde: sdma engine
1820 * @status: sdma interrupt reason
1821 *
1822 * Status is a mask of the 3 possible interrupts for this engine. It will
1823 * contain bits _only_ for this SDMA engine. It will contain at least one
1824 * bit, it may contain more.
1825 */
1826void sdma_engine_interrupt(struct sdma_engine *sde, u64 status)
1827{
1828 trace_hfi1_sdma_engine_interrupt(sde, status);
1829 write_seqlock(&sde->head_lock);
ee947859 1830 sdma_set_desc_cnt(sde, sdma_desct_intr);
a699c6c2
VM		 1831 if (status & sde->idle_mask)
1832 sde->idle_int_cnt++;
1833 else if (status & sde->progress_mask)
1834 sde->progress_int_cnt++;
1835 else if (status & sde->int_mask)
1836 sde->sdma_int_cnt++;
77241056
MM		 1837 sdma_make_progress(sde, status);
1838 write_sequnlock(&sde->head_lock);
1839}
1840
1841/**
1842 * sdma_engine_error() - error handler for engine
1843 * @sde: sdma engine
1844 * @status: sdma interrupt reason
1845 */
1846void sdma_engine_error(struct sdma_engine *sde, u64 status)
1847{
1848 unsigned long flags;
1849
1850#ifdef CONFIG_SDMA_VERBOSITY
1851 dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n",
1852 sde->this_idx,
1853 (unsigned long long)status,
1854 sdma_state_names[sde->state.current_state]);
1855#endif
1856 spin_lock_irqsave(&sde->tail_lock, flags);
1857 write_seqlock(&sde->head_lock);
1858 if (status & ALL_SDMA_ENG_HALT_ERRS)
1859 __sdma_process_event(sde, sdma_event_e60_hw_halted);
1860 if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) {
1861 dd_dev_err(sde->dd,
17fb4f29
JJ		 1862 "SDMA (%u) engine error: 0x%llx state %s\n",
1863 sde->this_idx,
1864 (unsigned long long)status,
1865 sdma_state_names[sde->state.current_state]);
77241056
MM		 1866 dump_sdma_state(sde);
1867 }
1868 write_sequnlock(&sde->head_lock);
1869 spin_unlock_irqrestore(&sde->tail_lock, flags);
1870}
1871
1872static void sdma_sendctrl(struct sdma_engine *sde, unsigned op)
1873{
1874 u64 set_senddmactrl = 0;
1875 u64 clr_senddmactrl = 0;
1876 unsigned long flags;
1877
1878#ifdef CONFIG_SDMA_VERBOSITY
1879 dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n",
1880 sde->this_idx,
1881 (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0,
1882 (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0,
1883 (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0,
1884 (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0);
1885#endif
1886
1887 if (op & SDMA_SENDCTRL_OP_ENABLE)
1888 set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1889 else
1890 clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1891
1892 if (op & SDMA_SENDCTRL_OP_INTENABLE)
1893 set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1894 else
1895 clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1896
1897 if (op & SDMA_SENDCTRL_OP_HALT)
1898 set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1899 else
1900 clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1901
1902 spin_lock_irqsave(&sde->senddmactrl_lock, flags);
1903
1904 sde->p_senddmactrl |= set_senddmactrl;
1905 sde->p_senddmactrl &= ~clr_senddmactrl;
1906
1907 if (op & SDMA_SENDCTRL_OP_CLEANUP)
1908 write_sde_csr(sde, SD(CTRL),
17fb4f29
JJ		 1909 sde->p_senddmactrl |
1910 SD(CTRL_SDMA_CLEANUP_SMASK));
77241056
MM		 1911 else
1912 write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl);
1913
1914 spin_unlock_irqrestore(&sde->senddmactrl_lock, flags);
1915
1916#ifdef CONFIG_SDMA_VERBOSITY
1917 sdma_dumpstate(sde);
1918#endif
1919}
1920
1921static void sdma_setlengen(struct sdma_engine *sde)
1922{
1923#ifdef CONFIG_SDMA_VERBOSITY
1924 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1925 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1926#endif
1927
1928 /*
1929 * Set SendDmaLenGen and clear-then-set the MSB of the generation
1930 * count to enable generation checking and load the internal
1931 * generation counter.
1932 */
1933 write_sde_csr(sde, SD(LEN_GEN),
17fb4f29 1934 (sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT));
77241056 1935 write_sde_csr(sde, SD(LEN_GEN),
17fb4f29
JJ		 1936 ((sde->descq_cnt / 64) << SD(LEN_GEN_LENGTH_SHIFT)) |
1937 (4ULL << SD(LEN_GEN_GENERATION_SHIFT)));
77241056
MM		 1938}
1939
1940static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail)
1941{
1942 /* Commit writes to memory and advance the tail on the chip */
1943 smp_wmb(); /* see get_txhead() */
1944 writeq(tail, sde->tail_csr);
1945}
1946
1947/*
1948 * This is called when changing to state s10_hw_start_up_halt_wait as
1949 * a result of send buffer errors or send DMA descriptor errors.
1950 */
1951static void sdma_hw_start_up(struct sdma_engine *sde)
1952{
1953 u64 reg;
1954
1955#ifdef CONFIG_SDMA_VERBOSITY
1956 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1957 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1958#endif
1959
1960 sdma_setlengen(sde);
1961 sdma_update_tail(sde, 0); /* Set SendDmaTail */
1962 *sde->head_dma = 0;
1963
1964 reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) <<
1965 SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT);
1966 write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg);
1967}
1968
1969#define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
1970(r &= ~SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
1971
1972#define SET_STATIC_RATE_CONTROL_SMASK(r) \
1973(r |= SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
1974/*
1975 * set_sdma_integrity
1976 *
1977 * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'.
1978 */
1979static void set_sdma_integrity(struct sdma_engine *sde)
1980{
1981 struct hfi1_devdata *dd = sde->dd;
1982 u64 reg;
1983
1984 if (unlikely(HFI1_CAP_IS_KSET(NO_INTEGRITY)))
1985 return;
1986
1987 reg = hfi1_pkt_base_sdma_integrity(dd);
1988
1989 if (HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
1990 CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
1991 else
1992 SET_STATIC_RATE_CONTROL_SMASK(reg);
1993
1994 write_sde_csr(sde, SD(CHECK_ENABLE), reg);
1995}
1996
77241056
MM		 1997static void init_sdma_regs(
1998 struct sdma_engine *sde,
1999 u32 credits,
2000 uint idle_cnt)
2001{
2002 u8 opval, opmask;
2003#ifdef CONFIG_SDMA_VERBOSITY
2004 struct hfi1_devdata *dd = sde->dd;
2005
2006 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n",
2007 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
2008#endif
2009
2010 write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys);
2011 sdma_setlengen(sde);
2012 sdma_update_tail(sde, 0); /* Set SendDmaTail */
2013 write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt);
2014 write_sde_csr(sde, SD(DESC_CNT), 0);
2015 write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys);
2016 write_sde_csr(sde, SD(MEMORY),
17fb4f29
JJ		 2017 ((u64)credits << SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) |
2018 ((u64)(credits * sde->this_idx) <<
2019 SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT)));
77241056
MM		 2020 write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull);
2021 set_sdma_integrity(sde);
2022 opmask = OPCODE_CHECK_MASK_DISABLED;
2023 opval = OPCODE_CHECK_VAL_DISABLED;
2024 write_sde_csr(sde, SD(CHECK_OPCODE),
17fb4f29
JJ		 2025 (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) |
2026 (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT));
77241056
MM		 2027}
2028
2029#ifdef CONFIG_SDMA_VERBOSITY
2030
2031#define sdma_dumpstate_helper0(reg) do { \
2032 csr = read_csr(sde->dd, reg); \
2033 dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \
2034 } while (0)
2035
2036#define sdma_dumpstate_helper(reg) do { \
2037 csr = read_sde_csr(sde, reg); \
2038 dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \
2039 #reg, sde->this_idx, csr); \
2040 } while (0)
2041
2042#define sdma_dumpstate_helper2(reg) do { \
2043 csr = read_csr(sde->dd, reg + (8 * i)); \
2044 dd_dev_err(sde->dd, "%33s_%02u 0x%016llx\n", \
2045 #reg, i, csr); \
2046 } while (0)
2047
2048void sdma_dumpstate(struct sdma_engine *sde)
2049{
2050 u64 csr;
2051 unsigned i;
2052
2053 sdma_dumpstate_helper(SD(CTRL));
2054 sdma_dumpstate_helper(SD(STATUS));
2055 sdma_dumpstate_helper0(SD(ERR_STATUS));
2056 sdma_dumpstate_helper0(SD(ERR_MASK));
2057 sdma_dumpstate_helper(SD(ENG_ERR_STATUS));
2058 sdma_dumpstate_helper(SD(ENG_ERR_MASK));
2059
2060 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) {
6fd8edab 2061 sdma_dumpstate_helper2(CCE_INT_STATUS);
77241056
MM		 2062 sdma_dumpstate_helper2(CCE_INT_MASK);
2063 sdma_dumpstate_helper2(CCE_INT_BLOCKED);
2064 }
2065
2066 sdma_dumpstate_helper(SD(TAIL));
2067 sdma_dumpstate_helper(SD(HEAD));
2068 sdma_dumpstate_helper(SD(PRIORITY_THLD));
6fd8edab 2069 sdma_dumpstate_helper(SD(IDLE_CNT));
77241056
MM		 2070 sdma_dumpstate_helper(SD(RELOAD_CNT));
2071 sdma_dumpstate_helper(SD(DESC_CNT));
2072 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT));
2073 sdma_dumpstate_helper(SD(MEMORY));
2074 sdma_dumpstate_helper0(SD(ENGINES));
2075 sdma_dumpstate_helper0(SD(MEM_SIZE));
2076 /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS); */
2077 sdma_dumpstate_helper(SD(BASE_ADDR));
2078 sdma_dumpstate_helper(SD(LEN_GEN));
2079 sdma_dumpstate_helper(SD(HEAD_ADDR));
2080 sdma_dumpstate_helper(SD(CHECK_ENABLE));
2081 sdma_dumpstate_helper(SD(CHECK_VL));
2082 sdma_dumpstate_helper(SD(CHECK_JOB_KEY));
2083 sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY));
2084 sdma_dumpstate_helper(SD(CHECK_SLID));
2085 sdma_dumpstate_helper(SD(CHECK_OPCODE));
2086}
2087#endif
2088
2089static void dump_sdma_state(struct sdma_engine *sde)
2090{
2091 struct hw_sdma_desc *descq;
2092 struct hw_sdma_desc *descqp;
2093 u64 desc[2];
2094 u64 addr;
2095 u8 gen;
2096 u16 len;
2097 u16 head, tail, cnt;
2098
2099 head = sde->descq_head & sde->sdma_mask;
2100 tail = sde->descq_tail & sde->sdma_mask;
2101 cnt = sdma_descq_freecnt(sde);
2102 descq = sde->descq;
2103
2104 dd_dev_err(sde->dd,
17fb4f29
JJ		 2105 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n",
2106 sde->this_idx, head, tail, cnt,
2107 !list_empty(&sde->flushlist));
77241056
MM		 2108
2109 /* print info for each entry in the descriptor queue */
2110 while (head != tail) {
2111 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
2112
2113 descqp = &sde->descq[head];
2114 desc[0] = le64_to_cpu(descqp->qw[0]);
2115 desc[1] = le64_to_cpu(descqp->qw[1]);
2116 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
2117 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
2118 'H' : '-';
2119 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
2120 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
2121 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
2122 & SDMA_DESC0_PHY_ADDR_MASK;
2123 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
2124 & SDMA_DESC1_GENERATION_MASK;
2125 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
2126 & SDMA_DESC0_BYTE_COUNT_MASK;
2127 dd_dev_err(sde->dd,
17fb4f29
JJ		 2128 "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
2129 head, flags, addr, gen, len);
77241056 2130 dd_dev_err(sde->dd,
17fb4f29
JJ		 2131 "\tdesc0:0x%016llx desc1 0x%016llx\n",
2132 desc[0], desc[1]);
77241056
MM		 2133 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
2134 dd_dev_err(sde->dd,
17fb4f29
JJ		 2135 "\taidx: %u amode: %u alen: %u\n",
2136 (u8)((desc[1] &
2137 SDMA_DESC1_HEADER_INDEX_SMASK) >>
2138 SDMA_DESC1_HEADER_INDEX_SHIFT),
2139 (u8)((desc[1] &
2140 SDMA_DESC1_HEADER_MODE_SMASK) >>
2141 SDMA_DESC1_HEADER_MODE_SHIFT),
2142 (u8)((desc[1] &
2143 SDMA_DESC1_HEADER_DWS_SMASK) >>
2144 SDMA_DESC1_HEADER_DWS_SHIFT));
77241056
MM		 2145 head++;
2146 head &= sde->sdma_mask;
2147 }
2148}
2149
2150#define SDE_FMT \
0a226edd 2151 "SDE %u CPU %d STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n"
77241056
MM		 2152/**
2153 * sdma_seqfile_dump_sde() - debugfs dump of sde
2154 * @s: seq file
2155 * @sde: send dma engine to dump
2156 *
2157 * This routine dumps the sde to the indicated seq file.
2158 */
2159void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde)
2160{
2161 u16 head, tail;
2162 struct hw_sdma_desc *descqp;
2163 u64 desc[2];
2164 u64 addr;
2165 u8 gen;
2166 u16 len;
2167
2168 head = sde->descq_head & sde->sdma_mask;
2169 tail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
2170 seq_printf(s, SDE_FMT, sde->this_idx,
17fb4f29
JJ		 2171 sde->cpu,
2172 sdma_state_name(sde->state.current_state),
2173 (unsigned long long)read_sde_csr(sde, SD(CTRL)),
2174 (unsigned long long)read_sde_csr(sde, SD(STATUS)),
2175 (unsigned long long)read_sde_csr(sde, SD(ENG_ERR_STATUS)),
2176 (unsigned long long)read_sde_csr(sde, SD(TAIL)), tail,
2177 (unsigned long long)read_sde_csr(sde, SD(HEAD)), head,
2178 (unsigned long long)le64_to_cpu(*sde->head_dma),
2179 (unsigned long long)read_sde_csr(sde, SD(MEMORY)),
2180 (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)),
2181 (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)),
2182 (unsigned long long)sde->last_status,
2183 (unsigned long long)sde->ahg_bits,
2184 sde->tx_tail,
2185 sde->tx_head,
2186 sde->descq_tail,
2187 sde->descq_head,
77241056 2188 !list_empty(&sde->flushlist),
17fb4f29
JJ		 2189 sde->descq_full_count,
2190 (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID));
77241056
MM		 2191
2192 /* print info for each entry in the descriptor queue */
2193 while (head != tail) {
2194 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
2195
2196 descqp = &sde->descq[head];
2197 desc[0] = le64_to_cpu(descqp->qw[0]);
2198 desc[1] = le64_to_cpu(descqp->qw[1]);
2199 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
2200 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
2201 'H' : '-';
2202 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
2203 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
2204 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
2205 & SDMA_DESC0_PHY_ADDR_MASK;
2206 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
2207 & SDMA_DESC1_GENERATION_MASK;
2208 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
2209 & SDMA_DESC0_BYTE_COUNT_MASK;
2210 seq_printf(s,
17fb4f29
JJ		 2211 "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
2212 head, flags, addr, gen, len);
77241056
MM		 2213 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
2214 seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n",
17fb4f29
JJ		 2215 (u8)((desc[1] &
2216 SDMA_DESC1_HEADER_INDEX_SMASK) >>
2217 SDMA_DESC1_HEADER_INDEX_SHIFT),
2218 (u8)((desc[1] &
2219 SDMA_DESC1_HEADER_MODE_SMASK) >>
2220 SDMA_DESC1_HEADER_MODE_SHIFT));
77241056
MM		 2221 head = (head + 1) & sde->sdma_mask;
2222 }
2223}
2224
2225/*
2226 * add the generation number into
2227 * the qw1 and return
2228 */
2229static inline u64 add_gen(struct sdma_engine *sde, u64 qw1)
2230{
2231 u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3;
2232
2233 qw1 &= ~SDMA_DESC1_GENERATION_SMASK;
2234 qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK)
2235 << SDMA_DESC1_GENERATION_SHIFT;
2236 return qw1;
2237}
2238
2239/*
2240 * This routine submits the indicated tx
2241 *
2242 * Space has already been guaranteed and
2243 * tail side of ring is locked.
2244 *
2245 * The hardware tail update is done
2246 * in the caller and that is facilitated
2247 * by returning the new tail.
2248 *
2249 * There is special case logic for ahg
2250 * to not add the generation number for
2251 * up to 2 descriptors that follow the
2252 * first descriptor.
2253 *
2254 */
2255static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx)
2256{
2257 int i;
2258 u16 tail;
2259 struct sdma_desc *descp = tx->descp;
2260 u8 skip = 0, mode = ahg_mode(tx);
2261
2262 tail = sde->descq_tail & sde->sdma_mask;
2263 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2264 sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1]));
2265 trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1],
2266 tail, &sde->descq[tail]);
2267 tail = ++sde->descq_tail & sde->sdma_mask;
2268 descp++;
2269 if (mode > SDMA_AHG_APPLY_UPDATE1)
2270 skip = mode >> 1;
2271 for (i = 1; i < tx->num_desc; i++, descp++) {
2272 u64 qw1;
2273
2274 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2275 if (skip) {
2276 /* edits don't have generation */
2277 qw1 = descp->qw[1];
2278 skip--;
2279 } else {
2280 /* replace generation with real one for non-edits */
2281 qw1 = add_gen(sde, descp->qw[1]);
2282 }
2283 sde->descq[tail].qw[1] = cpu_to_le64(qw1);
2284 trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1,
2285 tail, &sde->descq[tail]);
2286 tail = ++sde->descq_tail & sde->sdma_mask;
2287 }
2288 tx->next_descq_idx = tail;
2289#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2290 tx->sn = sde->tail_sn++;
2291 trace_hfi1_sdma_in_sn(sde, tx->sn);
2292 WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]);
2293#endif
2294 sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx;
2295 sde->desc_avail -= tx->num_desc;
2296 return tail;
2297}
2298
2299/*
2300 * Check for progress
2301 */
2302static int sdma_check_progress(
2303 struct sdma_engine *sde,
2304 struct iowait *wait,
2305 struct sdma_txreq *tx)
2306{
2307 int ret;
2308
2309 sde->desc_avail = sdma_descq_freecnt(sde);
2310 if (tx->num_desc <= sde->desc_avail)
2311 return -EAGAIN;
2312 /* pulse the head_lock */
2313 if (wait && wait->sleep) {
2314 unsigned seq;
2315
2316 seq = raw_seqcount_begin(
2317 (const seqcount_t *)&sde->head_lock.seqcount);
2318 ret = wait->sleep(sde, wait, tx, seq);
2319 if (ret == -EAGAIN)
2320 sde->desc_avail = sdma_descq_freecnt(sde);
e490974e 2321 } else {
77241056 2322 ret = -EBUSY;
e490974e 2323 }
77241056
MM		 2324 return ret;
2325}
2326
2327/**
2328 * sdma_send_txreq() - submit a tx req to ring
2329 * @sde: sdma engine to use
2330 * @wait: wait structure to use when full (may be NULL)
2331 * @tx: sdma_txreq to submit
2332 *
2333 * The call submits the tx into the ring. If a iowait structure is non-NULL
2334 * the packet will be queued to the list in wait.
2335 *
2336 * Return:
2337 * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in
2338 * ring (wait == NULL)
2339 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2340 */
2341int sdma_send_txreq(struct sdma_engine *sde,
2342 struct iowait *wait,
2343 struct sdma_txreq *tx)
2344{
2345 int ret = 0;
2346 u16 tail;
2347 unsigned long flags;
2348
2349 /* user should have supplied entire packet */
2350 if (unlikely(tx->tlen))
2351 return -EINVAL;
2352 tx->wait = wait;
2353 spin_lock_irqsave(&sde->tail_lock, flags);
2354retry:
2355 if (unlikely(!__sdma_running(sde)))
2356 goto unlock_noconn;
2357 if (unlikely(tx->num_desc > sde->desc_avail))
2358 goto nodesc;
2359 tail = submit_tx(sde, tx);
2360 if (wait)
14553ca1 2361 iowait_sdma_inc(wait);
77241056
MM		 2362 sdma_update_tail(sde, tail);
2363unlock:
2364 spin_unlock_irqrestore(&sde->tail_lock, flags);
2365 return ret;
2366unlock_noconn:
2367 if (wait)
14553ca1 2368 iowait_sdma_inc(wait);
77241056
MM		 2369 tx->next_descq_idx = 0;
2370#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2371 tx->sn = sde->tail_sn++;
2372 trace_hfi1_sdma_in_sn(sde, tx->sn);
2373#endif
f4f30031 2374 spin_lock(&sde->flushlist_lock);
77241056 2375 list_add_tail(&tx->list, &sde->flushlist);
f4f30031 2376 spin_unlock(&sde->flushlist_lock);
77241056
MM		 2377 if (wait) {
2378 wait->tx_count++;
2379 wait->count += tx->num_desc;
2380 }
2381 schedule_work(&sde->flush_worker);
2382 ret = -ECOMM;
2383 goto unlock;
2384nodesc:
2385 ret = sdma_check_progress(sde, wait, tx);
2386 if (ret == -EAGAIN) {
2387 ret = 0;
2388 goto retry;
2389 }
2390 sde->descq_full_count++;
2391 goto unlock;
2392}
2393
2394/**
2395 * sdma_send_txlist() - submit a list of tx req to ring
2396 * @sde: sdma engine to use
2397 * @wait: wait structure to use when full (may be NULL)
2398 * @tx_list: list of sdma_txreqs to submit
0b115ef1
HC		 2399 * @count: pointer to a u32 which, after return will contain the total number of
2400 * sdma_txreqs removed from the tx_list. This will include sdma_txreqs
2401 * whose SDMA descriptors are submitted to the ring and the sdma_txreqs
2402 * which are added to SDMA engine flush list if the SDMA engine state is
2403 * not running.
77241056
MM		 2404 *
2405 * The call submits the list into the ring.
2406 *
2407 * If the iowait structure is non-NULL and not equal to the iowait list
2408 * the unprocessed part of the list will be appended to the list in wait.
2409 *
2410 * In all cases, the tx_list will be updated so the head of the tx_list is
2411 * the list of descriptors that have yet to be transmitted.
2412 *
2413 * The intent of this call is to provide a more efficient
2414 * way of submitting multiple packets to SDMA while holding the tail
2415 * side locking.
2416 *
2417 * Return:
0b115ef1 2418 * 0 - Success,
c7cbf2fa 2419 * -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring (wait == NULL)
77241056
MM		 2420 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2421 */
17fb4f29 2422int sdma_send_txlist(struct sdma_engine *sde, struct iowait *wait,
0b115ef1 2423 struct list_head *tx_list, u32 *count_out)
77241056
MM		 2424{
2425 struct sdma_txreq *tx, *tx_next;
2426 int ret = 0;
2427 unsigned long flags;
2428 u16 tail = INVALID_TAIL;
0b115ef1 2429 u32 submit_count = 0, flush_count = 0, total_count;
77241056
MM		 2430
2431 spin_lock_irqsave(&sde->tail_lock, flags);
2432retry:
2433 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2434 tx->wait = wait;
2435 if (unlikely(!__sdma_running(sde)))
2436 goto unlock_noconn;
2437 if (unlikely(tx->num_desc > sde->desc_avail))
2438 goto nodesc;
2439 if (unlikely(tx->tlen)) {
2440 ret = -EINVAL;
2441 goto update_tail;
2442 }
2443 list_del_init(&tx->list);
2444 tail = submit_tx(sde, tx);
0b115ef1 2445 submit_count++;
77241056 2446 if (tail != INVALID_TAIL &&
0b115ef1 2447 (submit_count & SDMA_TAIL_UPDATE_THRESH) == 0) {
77241056
MM		 2448 sdma_update_tail(sde, tail);
2449 tail = INVALID_TAIL;
2450 }
2451 }
2452update_tail:
0b115ef1 2453 total_count = submit_count + flush_count;
77241056 2454 if (wait)
0b115ef1 2455 iowait_sdma_add(wait, total_count);
77241056
MM		 2456 if (tail != INVALID_TAIL)
2457 sdma_update_tail(sde, tail);
2458 spin_unlock_irqrestore(&sde->tail_lock, flags);
0b115ef1
HC		 2459 *count_out = total_count;
2460 return ret;
77241056
MM		 2461unlock_noconn:
2462 spin_lock(&sde->flushlist_lock);
2463 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2464 tx->wait = wait;
2465 list_del_init(&tx->list);
77241056
MM		 2466 tx->next_descq_idx = 0;
2467#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2468 tx->sn = sde->tail_sn++;
2469 trace_hfi1_sdma_in_sn(sde, tx->sn);
2470#endif
2471 list_add_tail(&tx->list, &sde->flushlist);
0b115ef1 2472 flush_count++;
77241056
MM		 2473 if (wait) {
2474 wait->tx_count++;
2475 wait->count += tx->num_desc;
2476 }
2477 }
2478 spin_unlock(&sde->flushlist_lock);
2479 schedule_work(&sde->flush_worker);
2480 ret = -ECOMM;
2481 goto update_tail;
2482nodesc:
2483 ret = sdma_check_progress(sde, wait, tx);
2484 if (ret == -EAGAIN) {
2485 ret = 0;
2486 goto retry;
2487 }
2488 sde->descq_full_count++;
2489 goto update_tail;
2490}
2491
17fb4f29 2492static void sdma_process_event(struct sdma_engine *sde, enum sdma_events event)
77241056
MM		 2493{
2494 unsigned long flags;
2495
2496 spin_lock_irqsave(&sde->tail_lock, flags);
2497 write_seqlock(&sde->head_lock);
2498
2499 __sdma_process_event(sde, event);
2500
2501 if (sde->state.current_state == sdma_state_s99_running)
2502 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
2503
2504 write_sequnlock(&sde->head_lock);
2505 spin_unlock_irqrestore(&sde->tail_lock, flags);
2506}
2507
2508static void __sdma_process_event(struct sdma_engine *sde,
17fb4f29 2509 enum sdma_events event)
77241056
MM		 2510{
2511 struct sdma_state *ss = &sde->state;
2512 int need_progress = 0;
2513
2514 /* CONFIG SDMA temporary */
2515#ifdef CONFIG_SDMA_VERBOSITY
2516 dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx,
2517 sdma_state_names[ss->current_state],
2518 sdma_event_names[event]);
2519#endif
2520
2521 switch (ss->current_state) {
2522 case sdma_state_s00_hw_down:
2523 switch (event) {
2524 case sdma_event_e00_go_hw_down:
2525 break;
2526 case sdma_event_e30_go_running:
2527 /*
2528 * If down, but running requested (usually result
2529 * of link up, then we need to start up.
2530 * This can happen when hw down is requested while
2531 * bringing the link up with traffic active on
4d114fdd
JJ		 2532 * 7220, e.g.
2533 */
77241056
MM		 2534 ss->go_s99_running = 1;
2535 /* fall through and start dma engine */
2536 case sdma_event_e10_go_hw_start:
2537 /* This reference means the state machine is started */
2538 sdma_get(&sde->state);
2539 sdma_set_state(sde,
17fb4f29 2540 sdma_state_s10_hw_start_up_halt_wait);
77241056
MM		 2541 break;
2542 case sdma_event_e15_hw_halt_done:
2543 break;
2544 case sdma_event_e25_hw_clean_up_done:
2545 break;
2546 case sdma_event_e40_sw_cleaned:
2547 sdma_sw_tear_down(sde);
2548 break;
2549 case sdma_event_e50_hw_cleaned:
2550 break;
2551 case sdma_event_e60_hw_halted:
2552 break;
2553 case sdma_event_e70_go_idle:
2554 break;
2555 case sdma_event_e80_hw_freeze:
2556 break;
2557 case sdma_event_e81_hw_frozen:
2558 break;
2559 case sdma_event_e82_hw_unfreeze:
2560 break;
2561 case sdma_event_e85_link_down:
2562 break;
2563 case sdma_event_e90_sw_halted:
2564 break;
2565 }
2566 break;
2567
2568 case sdma_state_s10_hw_start_up_halt_wait:
2569 switch (event) {
2570 case sdma_event_e00_go_hw_down:
2571 sdma_set_state(sde, sdma_state_s00_hw_down);
2572 sdma_sw_tear_down(sde);
2573 break;
2574 case sdma_event_e10_go_hw_start:
2575 break;
2576 case sdma_event_e15_hw_halt_done:
2577 sdma_set_state(sde,
17fb4f29 2578 sdma_state_s15_hw_start_up_clean_wait);
77241056
MM		 2579 sdma_start_hw_clean_up(sde);
2580 break;
2581 case sdma_event_e25_hw_clean_up_done:
2582 break;
2583 case sdma_event_e30_go_running:
2584 ss->go_s99_running = 1;
2585 break;
2586 case sdma_event_e40_sw_cleaned:
2587 break;
2588 case sdma_event_e50_hw_cleaned:
2589 break;
2590 case sdma_event_e60_hw_halted:
8edf7502 2591 schedule_work(&sde->err_halt_worker);
77241056
MM		 2592 break;
2593 case sdma_event_e70_go_idle:
2594 ss->go_s99_running = 0;
2595 break;
2596 case sdma_event_e80_hw_freeze:
2597 break;
2598 case sdma_event_e81_hw_frozen:
2599 break;
2600 case sdma_event_e82_hw_unfreeze:
2601 break;
2602 case sdma_event_e85_link_down:
2603 break;
2604 case sdma_event_e90_sw_halted:
2605 break;
2606 }
2607 break;
2608
2609 case sdma_state_s15_hw_start_up_clean_wait:
2610 switch (event) {
2611 case sdma_event_e00_go_hw_down:
2612 sdma_set_state(sde, sdma_state_s00_hw_down);
2613 sdma_sw_tear_down(sde);
2614 break;
2615 case sdma_event_e10_go_hw_start:
2616 break;
2617 case sdma_event_e15_hw_halt_done:
2618 break;
2619 case sdma_event_e25_hw_clean_up_done:
2620 sdma_hw_start_up(sde);
2621 sdma_set_state(sde, ss->go_s99_running ?
2622 sdma_state_s99_running :
2623 sdma_state_s20_idle);
2624 break;
2625 case sdma_event_e30_go_running:
2626 ss->go_s99_running = 1;
2627 break;
2628 case sdma_event_e40_sw_cleaned:
2629 break;
2630 case sdma_event_e50_hw_cleaned:
2631 break;
2632 case sdma_event_e60_hw_halted:
2633 break;
2634 case sdma_event_e70_go_idle:
2635 ss->go_s99_running = 0;
2636 break;
2637 case sdma_event_e80_hw_freeze:
2638 break;
2639 case sdma_event_e81_hw_frozen:
2640 break;
2641 case sdma_event_e82_hw_unfreeze:
2642 break;
2643 case sdma_event_e85_link_down:
2644 break;
2645 case sdma_event_e90_sw_halted:
2646 break;
2647 }
2648 break;
2649
2650 case sdma_state_s20_idle:
2651 switch (event) {
2652 case sdma_event_e00_go_hw_down:
2653 sdma_set_state(sde, sdma_state_s00_hw_down);
2654 sdma_sw_tear_down(sde);
2655 break;
2656 case sdma_event_e10_go_hw_start:
2657 break;
2658 case sdma_event_e15_hw_halt_done:
2659 break;
2660 case sdma_event_e25_hw_clean_up_done:
2661 break;
2662 case sdma_event_e30_go_running:
2663 sdma_set_state(sde, sdma_state_s99_running);
2664 ss->go_s99_running = 1;
2665 break;
2666 case sdma_event_e40_sw_cleaned:
2667 break;
2668 case sdma_event_e50_hw_cleaned:
2669 break;
2670 case sdma_event_e60_hw_halted:
2671 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
8edf7502 2672 schedule_work(&sde->err_halt_worker);
77241056
MM		 2673 break;
2674 case sdma_event_e70_go_idle:
2675 break;
2676 case sdma_event_e85_link_down:
2677 /* fall through */
2678 case sdma_event_e80_hw_freeze:
2679 sdma_set_state(sde, sdma_state_s80_hw_freeze);
2680 atomic_dec(&sde->dd->sdma_unfreeze_count);
2681 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2682 break;
2683 case sdma_event_e81_hw_frozen:
2684 break;
2685 case sdma_event_e82_hw_unfreeze:
2686 break;
2687 case sdma_event_e90_sw_halted:
2688 break;
2689 }
2690 break;
2691
2692 case sdma_state_s30_sw_clean_up_wait:
2693 switch (event) {
2694 case sdma_event_e00_go_hw_down:
2695 sdma_set_state(sde, sdma_state_s00_hw_down);
2696 break;
2697 case sdma_event_e10_go_hw_start:
2698 break;
2699 case sdma_event_e15_hw_halt_done:
2700 break;
2701 case sdma_event_e25_hw_clean_up_done:
2702 break;
2703 case sdma_event_e30_go_running:
2704 ss->go_s99_running = 1;
2705 break;
2706 case sdma_event_e40_sw_cleaned:
2707 sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait);
2708 sdma_start_hw_clean_up(sde);
2709 break;
2710 case sdma_event_e50_hw_cleaned:
2711 break;
2712 case sdma_event_e60_hw_halted:
2713 break;
2714 case sdma_event_e70_go_idle:
2715 ss->go_s99_running = 0;
2716 break;
2717 case sdma_event_e80_hw_freeze:
2718 break;
2719 case sdma_event_e81_hw_frozen:
2720 break;
2721 case sdma_event_e82_hw_unfreeze:
2722 break;
2723 case sdma_event_e85_link_down:
2724 ss->go_s99_running = 0;
2725 break;
2726 case sdma_event_e90_sw_halted:
2727 break;
2728 }
2729 break;
2730
2731 case sdma_state_s40_hw_clean_up_wait:
2732 switch (event) {
2733 case sdma_event_e00_go_hw_down:
2734 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2735 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2736 break;
2737 case sdma_event_e10_go_hw_start:
2738 break;
2739 case sdma_event_e15_hw_halt_done:
2740 break;
2741 case sdma_event_e25_hw_clean_up_done:
2742 sdma_hw_start_up(sde);
2743 sdma_set_state(sde, ss->go_s99_running ?
2744 sdma_state_s99_running :
2745 sdma_state_s20_idle);
2746 break;
2747 case sdma_event_e30_go_running:
2748 ss->go_s99_running = 1;
2749 break;
2750 case sdma_event_e40_sw_cleaned:
2751 break;
2752 case sdma_event_e50_hw_cleaned:
2753 break;
2754 case sdma_event_e60_hw_halted:
2755 break;
2756 case sdma_event_e70_go_idle:
2757 ss->go_s99_running = 0;
2758 break;
2759 case sdma_event_e80_hw_freeze:
2760 break;
2761 case sdma_event_e81_hw_frozen:
2762 break;
2763 case sdma_event_e82_hw_unfreeze:
2764 break;
2765 case sdma_event_e85_link_down:
2766 ss->go_s99_running = 0;
2767 break;
2768 case sdma_event_e90_sw_halted:
2769 break;
2770 }
2771 break;
2772
2773 case sdma_state_s50_hw_halt_wait:
2774 switch (event) {
2775 case sdma_event_e00_go_hw_down:
2776 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2777 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2778 break;
2779 case sdma_event_e10_go_hw_start:
2780 break;
2781 case sdma_event_e15_hw_halt_done:
2782 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
8edf7502 2783 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2784 break;
2785 case sdma_event_e25_hw_clean_up_done:
2786 break;
2787 case sdma_event_e30_go_running:
2788 ss->go_s99_running = 1;
2789 break;
2790 case sdma_event_e40_sw_cleaned:
2791 break;
2792 case sdma_event_e50_hw_cleaned:
2793 break;
2794 case sdma_event_e60_hw_halted:
8edf7502 2795 schedule_work(&sde->err_halt_worker);
77241056
MM		 2796 break;
2797 case sdma_event_e70_go_idle:
2798 ss->go_s99_running = 0;
2799 break;
2800 case sdma_event_e80_hw_freeze:
2801 break;
2802 case sdma_event_e81_hw_frozen:
2803 break;
2804 case sdma_event_e82_hw_unfreeze:
2805 break;
2806 case sdma_event_e85_link_down:
2807 ss->go_s99_running = 0;
2808 break;
2809 case sdma_event_e90_sw_halted:
2810 break;
2811 }
2812 break;
2813
2814 case sdma_state_s60_idle_halt_wait:
2815 switch (event) {
2816 case sdma_event_e00_go_hw_down:
2817 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2818 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2819 break;
2820 case sdma_event_e10_go_hw_start:
2821 break;
2822 case sdma_event_e15_hw_halt_done:
2823 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
8edf7502 2824 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2825 break;
2826 case sdma_event_e25_hw_clean_up_done:
2827 break;
2828 case sdma_event_e30_go_running:
2829 ss->go_s99_running = 1;
2830 break;
2831 case sdma_event_e40_sw_cleaned:
2832 break;
2833 case sdma_event_e50_hw_cleaned:
2834 break;
2835 case sdma_event_e60_hw_halted:
8edf7502 2836 schedule_work(&sde->err_halt_worker);
77241056
MM		 2837 break;
2838 case sdma_event_e70_go_idle:
2839 ss->go_s99_running = 0;
2840 break;
2841 case sdma_event_e80_hw_freeze:
2842 break;
2843 case sdma_event_e81_hw_frozen:
2844 break;
2845 case sdma_event_e82_hw_unfreeze:
2846 break;
2847 case sdma_event_e85_link_down:
2848 break;
2849 case sdma_event_e90_sw_halted:
2850 break;
2851 }
2852 break;
2853
2854 case sdma_state_s80_hw_freeze:
2855 switch (event) {
2856 case sdma_event_e00_go_hw_down:
2857 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2858 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2859 break;
2860 case sdma_event_e10_go_hw_start:
2861 break;
2862 case sdma_event_e15_hw_halt_done:
2863 break;
2864 case sdma_event_e25_hw_clean_up_done:
2865 break;
2866 case sdma_event_e30_go_running:
2867 ss->go_s99_running = 1;
2868 break;
2869 case sdma_event_e40_sw_cleaned:
2870 break;
2871 case sdma_event_e50_hw_cleaned:
2872 break;
2873 case sdma_event_e60_hw_halted:
2874 break;
2875 case sdma_event_e70_go_idle:
2876 ss->go_s99_running = 0;
2877 break;
2878 case sdma_event_e80_hw_freeze:
2879 break;
2880 case sdma_event_e81_hw_frozen:
2881 sdma_set_state(sde, sdma_state_s82_freeze_sw_clean);
8edf7502 2882 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2883 break;
2884 case sdma_event_e82_hw_unfreeze:
2885 break;
2886 case sdma_event_e85_link_down:
2887 break;
2888 case sdma_event_e90_sw_halted:
2889 break;
2890 }
2891 break;
2892
2893 case sdma_state_s82_freeze_sw_clean:
2894 switch (event) {
2895 case sdma_event_e00_go_hw_down:
2896 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2897 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2898 break;
2899 case sdma_event_e10_go_hw_start:
2900 break;
2901 case sdma_event_e15_hw_halt_done:
2902 break;
2903 case sdma_event_e25_hw_clean_up_done:
2904 break;
2905 case sdma_event_e30_go_running:
2906 ss->go_s99_running = 1;
2907 break;
2908 case sdma_event_e40_sw_cleaned:
2909 /* notify caller this engine is done cleaning */
2910 atomic_dec(&sde->dd->sdma_unfreeze_count);
2911 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2912 break;
2913 case sdma_event_e50_hw_cleaned:
2914 break;
2915 case sdma_event_e60_hw_halted:
2916 break;
2917 case sdma_event_e70_go_idle:
2918 ss->go_s99_running = 0;
2919 break;
2920 case sdma_event_e80_hw_freeze:
2921 break;
2922 case sdma_event_e81_hw_frozen:
2923 break;
2924 case sdma_event_e82_hw_unfreeze:
2925 sdma_hw_start_up(sde);
2926 sdma_set_state(sde, ss->go_s99_running ?
2927 sdma_state_s99_running :
2928 sdma_state_s20_idle);
2929 break;
2930 case sdma_event_e85_link_down:
2931 break;
2932 case sdma_event_e90_sw_halted:
2933 break;
2934 }
2935 break;
2936
2937 case sdma_state_s99_running:
2938 switch (event) {
2939 case sdma_event_e00_go_hw_down:
2940 sdma_set_state(sde, sdma_state_s00_hw_down);
8edf7502 2941 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
77241056
MM		 2942 break;
2943 case sdma_event_e10_go_hw_start:
2944 break;
2945 case sdma_event_e15_hw_halt_done:
2946 break;
2947 case sdma_event_e25_hw_clean_up_done:
2948 break;
2949 case sdma_event_e30_go_running:
2950 break;
2951 case sdma_event_e40_sw_cleaned:
2952 break;
2953 case sdma_event_e50_hw_cleaned:
2954 break;
2955 case sdma_event_e60_hw_halted:
2956 need_progress = 1;
2957 sdma_err_progress_check_schedule(sde);
2958 case sdma_event_e90_sw_halted:
2959 /*
2960 * SW initiated halt does not perform engines
2961 * progress check
2962 */
2963 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
8edf7502 2964 schedule_work(&sde->err_halt_worker);
77241056
MM		 2965 break;
2966 case sdma_event_e70_go_idle:
2967 sdma_set_state(sde, sdma_state_s60_idle_halt_wait);
2968 break;
2969 case sdma_event_e85_link_down:
2970 ss->go_s99_running = 0;
2971 /* fall through */
2972 case sdma_event_e80_hw_freeze:
2973 sdma_set_state(sde, sdma_state_s80_hw_freeze);
2974 atomic_dec(&sde->dd->sdma_unfreeze_count);
2975 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2976 break;
2977 case sdma_event_e81_hw_frozen:
2978 break;
2979 case sdma_event_e82_hw_unfreeze:
2980 break;
2981 }
2982 break;
2983 }
2984
2985 ss->last_event = event;
2986 if (need_progress)
2987 sdma_make_progress(sde, 0);
2988}
2989
2990/*
2991 * _extend_sdma_tx_descs() - helper to extend txreq
2992 *
2993 * This is called once the initial nominal allocation
2994 * of descriptors in the sdma_txreq is exhausted.
2995 *
2996 * The code will bump the allocation up to the max
f4d26d81
NV		 2997 * of MAX_DESC (64) descriptors. There doesn't seem
2998 * much point in an interim step. The last descriptor
2999 * is reserved for coalesce buffer in order to support
3000 * cases where input packet has >MAX_DESC iovecs.
77241056
MM		 3001 *
3002 */
f4d26d81 3003static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
77241056
MM		 3004{
3005 int i;
3006
f4d26d81
NV		 3007 /* Handle last descriptor */
3008 if (unlikely((tx->num_desc == (MAX_DESC - 1)))) {
3009 /* if tlen is 0, it is for padding, release last descriptor */
3010 if (!tx->tlen) {
3011 tx->desc_limit = MAX_DESC;
3012 } else if (!tx->coalesce_buf) {
3013 /* allocate coalesce buffer with space for padding */
3014 tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32),
3015 GFP_ATOMIC);
3016 if (!tx->coalesce_buf)
a5a9e8cc 3017 goto enomem;
f4d26d81
NV		 3018 tx->coalesce_idx = 0;
3019 }
3020 return 0;
3021 }
3022
3023 if (unlikely(tx->num_desc == MAX_DESC))
a5a9e8cc 3024 goto enomem;
f4d26d81 3025
77241056
MM		 3026 tx->descp = kmalloc_array(
3027 MAX_DESC,
3028 sizeof(struct sdma_desc),
3029 GFP_ATOMIC);
3030 if (!tx->descp)
a5a9e8cc 3031 goto enomem;
f4d26d81
NV		 3032
3033 /* reserve last descriptor for coalescing */
3034 tx->desc_limit = MAX_DESC - 1;
77241056
MM		 3035 /* copy ones already built */
3036 for (i = 0; i < tx->num_desc; i++)
3037 tx->descp[i] = tx->descs[i];
3038 return 0;
a5a9e8cc
MM		 3039enomem:
3040 sdma_txclean(dd, tx);
3041 return -ENOMEM;
77241056
MM		 3042}
3043
f4d26d81
NV		 3044/*
3045 * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors
3046 *
3047 * This is called once the initial nominal allocation of descriptors
3048 * in the sdma_txreq is exhausted.
3049 *
3050 * This function calls _extend_sdma_tx_descs to extend or allocate
3051 * coalesce buffer. If there is a allocated coalesce buffer, it will
3052 * copy the input packet data into the coalesce buffer. It also adds
16733b88 3053 * coalesce buffer descriptor once when whole packet is received.
f4d26d81
NV		 3054 *
3055 * Return:
3056 * <0 - error
3057 * 0 - coalescing, don't populate descriptor
3058 * 1 - continue with populating descriptor
3059 */
3060int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
3061 int type, void *kvaddr, struct page *page,
3062 unsigned long offset, u16 len)
3063{
3064 int pad_len, rval;
3065 dma_addr_t addr;
3066
3067 rval = _extend_sdma_tx_descs(dd, tx);
3068 if (rval) {
3069 sdma_txclean(dd, tx);
3070 return rval;
3071 }
3072
3073 /* If coalesce buffer is allocated, copy data into it */
3074 if (tx->coalesce_buf) {
3075 if (type == SDMA_MAP_NONE) {
3076 sdma_txclean(dd, tx);
3077 return -EINVAL;
3078 }
3079
3080 if (type == SDMA_MAP_PAGE) {
3081 kvaddr = kmap(page);
3082 kvaddr += offset;
3083 } else if (WARN_ON(!kvaddr)) {
3084 sdma_txclean(dd, tx);
3085 return -EINVAL;
3086 }
3087
3088 memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len);
3089 tx->coalesce_idx += len;
3090 if (type == SDMA_MAP_PAGE)
3091 kunmap(page);
3092
3093 /* If there is more data, return */
3094 if (tx->tlen - tx->coalesce_idx)
3095 return 0;
3096
3097 /* Whole packet is received; add any padding */
3098 pad_len = tx->packet_len & (sizeof(u32) - 1);
3099 if (pad_len) {
3100 pad_len = sizeof(u32) - pad_len;
3101 memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len);
3102 /* padding is taken care of for coalescing case */
3103 tx->packet_len += pad_len;
3104 tx->tlen += pad_len;
3105 }
3106
3107 /* dma map the coalesce buffer */
3108 addr = dma_map_single(&dd->pcidev->dev,
3109 tx->coalesce_buf,
3110 tx->tlen,
3111 DMA_TO_DEVICE);
3112
3113 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
3114 sdma_txclean(dd, tx);
3115 return -ENOSPC;
3116 }
3117
3118 /* Add descriptor for coalesce buffer */
3119 tx->desc_limit = MAX_DESC;
3120 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx,
3121 addr, tx->tlen);
3122 }
3123
3124 return 1;
3125}
3126
77241056
MM		 3127/* Update sdes when the lmc changes */
3128void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid)
3129{
3130 struct sdma_engine *sde;
3131 int i;
3132 u64 sreg;
3133
3134 sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) <<
3135 SD(CHECK_SLID_MASK_SHIFT)) |
3136 (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) <<
3137 SD(CHECK_SLID_VALUE_SHIFT));
3138
3139 for (i = 0; i < dd->num_sdma; i++) {
3140 hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x",
3141 i, (u32)sreg);
3142 sde = &dd->per_sdma[i];
3143 write_sde_csr(sde, SD(CHECK_SLID), sreg);
3144 }
3145}
3146
3147/* tx not dword sized - pad */
3148int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3149{
3150 int rval = 0;
3151
f4d26d81 3152 tx->num_desc++;
77241056
MM		 3153 if ((unlikely(tx->num_desc == tx->desc_limit))) {
3154 rval = _extend_sdma_tx_descs(dd, tx);
f4d26d81
NV		 3155 if (rval) {
3156 sdma_txclean(dd, tx);
77241056 3157 return rval;
f4d26d81 3158 }
77241056 3159 }
f4d26d81 3160 /* finish the one just added */
77241056
MM		 3161 make_tx_sdma_desc(
3162 tx,
3163 SDMA_MAP_NONE,
3164 dd->sdma_pad_phys,
3165 sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1)));
3166 _sdma_close_tx(dd, tx);
3167 return rval;
3168}
3169
3170/*
3171 * Add ahg to the sdma_txreq
3172 *
3173 * The logic will consume up to 3
3174 * descriptors at the beginning of
3175 * sdma_txreq.
3176 */
3177void _sdma_txreq_ahgadd(
3178 struct sdma_txreq *tx,
3179 u8 num_ahg,
3180 u8 ahg_entry,
3181 u32 *ahg,
3182 u8 ahg_hlen)
3183{
3184 u32 i, shift = 0, desc = 0;
3185 u8 mode;
3186
3187 WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4);
3188 /* compute mode */
3189 if (num_ahg == 1)
3190 mode = SDMA_AHG_APPLY_UPDATE1;
3191 else if (num_ahg <= 5)
3192 mode = SDMA_AHG_APPLY_UPDATE2;
3193 else
3194 mode = SDMA_AHG_APPLY_UPDATE3;
3195 tx->num_desc++;
3196 /* initialize to consumed descriptors to zero */
3197 switch (mode) {
3198 case SDMA_AHG_APPLY_UPDATE3:
3199 tx->num_desc++;
3200 tx->descs[2].qw[0] = 0;
3201 tx->descs[2].qw[1] = 0;
3202 /* FALLTHROUGH */
3203 case SDMA_AHG_APPLY_UPDATE2:
3204 tx->num_desc++;
3205 tx->descs[1].qw[0] = 0;
3206 tx->descs[1].qw[1] = 0;
3207 break;
3208 }
3209 ahg_hlen >>= 2;
3210 tx->descs[0].qw[1] |=
3211 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK)
3212 << SDMA_DESC1_HEADER_INDEX_SHIFT) |
3213 (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK)
3214 << SDMA_DESC1_HEADER_DWS_SHIFT) |
3215 (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK)
3216 << SDMA_DESC1_HEADER_MODE_SHIFT) |
3217 (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK)
3218 << SDMA_DESC1_HEADER_UPDATE1_SHIFT);
3219 for (i = 0; i < (num_ahg - 1); i++) {
3220 if (!shift && !(i & 2))
3221 desc++;
3222 tx->descs[desc].qw[!!(i & 2)] |=
3223 (((u64)ahg[i + 1])
3224 << shift);
3225 shift = (shift + 32) & 63;
3226 }
3227}
3228
3229/**
3230 * sdma_ahg_alloc - allocate an AHG entry
3231 * @sde: engine to allocate from
3232 *
3233 * Return:
3234 * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled,
3235 * -ENOSPC if an entry is not available
3236 */
3237int sdma_ahg_alloc(struct sdma_engine *sde)
3238{
3239 int nr;
3240 int oldbit;
3241
3242 if (!sde) {
3243 trace_hfi1_ahg_allocate(sde, -EINVAL);
3244 return -EINVAL;
3245 }
3246 while (1) {
3247 nr = ffz(ACCESS_ONCE(sde->ahg_bits));
3248 if (nr > 31) {
3249 trace_hfi1_ahg_allocate(sde, -ENOSPC);
3250 return -ENOSPC;
3251 }
3252 oldbit = test_and_set_bit(nr, &sde->ahg_bits);
3253 if (!oldbit)
3254 break;
3255 cpu_relax();
3256 }
3257 trace_hfi1_ahg_allocate(sde, nr);
3258 return nr;
3259}
3260
3261/**
3262 * sdma_ahg_free - free an AHG entry
3263 * @sde: engine to return AHG entry
3264 * @ahg_index: index to free
3265 *
3266 * This routine frees the indicate AHG entry.
3267 */
3268void sdma_ahg_free(struct sdma_engine *sde, int ahg_index)
3269{
3270 if (!sde)
3271 return;
3272 trace_hfi1_ahg_deallocate(sde, ahg_index);
3273 if (ahg_index < 0 || ahg_index > 31)
3274 return;
3275 clear_bit(ahg_index, &sde->ahg_bits);
3276}
3277
3278/*
3279 * SPC freeze handling for SDMA engines. Called when the driver knows
3280 * the SPC is going into a freeze but before the freeze is fully
3281 * settled. Generally an error interrupt.
3282 *
3283 * This event will pull the engine out of running so no more entries can be
3284 * added to the engine's queue.
3285 */
3286void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down)
3287{
3288 int i;
3289 enum sdma_events event = link_down ? sdma_event_e85_link_down :
3290 sdma_event_e80_hw_freeze;
3291
3292 /* set up the wait but do not wait here */
3293 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3294
3295 /* tell all engines to stop running and wait */
3296 for (i = 0; i < dd->num_sdma; i++)
3297 sdma_process_event(&dd->per_sdma[i], event);
3298
3299 /* sdma_freeze() will wait for all engines to have stopped */
3300}
3301
3302/*
3303 * SPC freeze handling for SDMA engines. Called when the driver knows
3304 * the SPC is fully frozen.
3305 */
3306void sdma_freeze(struct hfi1_devdata *dd)
3307{
3308 int i;
3309 int ret;
3310
3311 /*
3312 * Make sure all engines have moved out of the running state before
3313 * continuing.
3314 */
3315 ret = wait_event_interruptible(dd->sdma_unfreeze_wq,
17fb4f29
JJ		 3316 atomic_read(&dd->sdma_unfreeze_count) <=
3317 0);
77241056
MM		 3318 /* interrupted or count is negative, then unloading - just exit */
3319 if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0)
3320 return;
3321
3322 /* set up the count for the next wait */
3323 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3324
3325 /* tell all engines that the SPC is frozen, they can start cleaning */
3326 for (i = 0; i < dd->num_sdma; i++)
3327 sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen);
3328
3329 /*
3330 * Wait for everyone to finish software clean before exiting. The
3331 * software clean will read engine CSRs, so must be completed before
3332 * the next step, which will clear the engine CSRs.
3333 */
50e5dcbe 3334 (void)wait_event_interruptible(dd->sdma_unfreeze_wq,
77241056
MM		 3335 atomic_read(&dd->sdma_unfreeze_count) <= 0);
3336 /* no need to check results - done no matter what */
3337}
3338
3339/*
3340 * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen.
3341 *
3342 * The SPC freeze acts like a SDMA halt and a hardware clean combined. All
3343 * that is left is a software clean. We could do it after the SPC is fully
3344 * frozen, but then we'd have to add another state to wait for the unfreeze.
3345 * Instead, just defer the software clean until the unfreeze step.
3346 */
3347void sdma_unfreeze(struct hfi1_devdata *dd)
3348{
3349 int i;
3350
3351 /* tell all engines start freeze clean up */
3352 for (i = 0; i < dd->num_sdma; i++)
3353 sdma_process_event(&dd->per_sdma[i],
17fb4f29 3354 sdma_event_e82_hw_unfreeze);
77241056
MM		 3355}
3356
3357/**
3358 * _sdma_engine_progress_schedule() - schedule progress on engine
3359 * @sde: sdma_engine to schedule progress
3360 *
3361 */
3362void _sdma_engine_progress_schedule(
3363 struct sdma_engine *sde)
3364{
3365 trace_hfi1_sdma_engine_progress(sde, sde->progress_mask);
3366 /* assume we have selected a good cpu */
3367 write_csr(sde->dd,
17fb4f29
JJ		 3368 CCE_INT_FORCE + (8 * (IS_SDMA_START / 64)),
3369 sde->progress_mask);
77241056 3370}
Linux 6.x block layer and io_uring tree(s)