Commit | Line | Data |
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77241056 | 1 | /* |
57f97e96 | 2 | * Copyright(c) 2015 - 2018 Intel Corporation. |
77241056 MM |
3 | * |
4 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
5 | * redistributing this file, you may do so under either license. | |
6 | * | |
7 | * GPL LICENSE SUMMARY | |
8 | * | |
77241056 MM |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * BSD LICENSE | |
19 | * | |
77241056 MM |
20 | * Redistribution and use in source and binary forms, with or without |
21 | * modification, are permitted provided that the following conditions | |
22 | * are met: | |
23 | * | |
24 | * - Redistributions of source code must retain the above copyright | |
25 | * notice, this list of conditions and the following disclaimer. | |
26 | * - Redistributions in binary form must reproduce the above copyright | |
27 | * notice, this list of conditions and the following disclaimer in | |
28 | * the documentation and/or other materials provided with the | |
29 | * distribution. | |
30 | * - Neither the name of Intel Corporation nor the names of its | |
31 | * contributors may be used to endorse or promote products derived | |
32 | * from this software without specific prior written permission. | |
33 | * | |
34 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
35 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
36 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
37 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
38 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
39 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
40 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
41 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
42 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
43 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
44 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
45 | * | |
46 | */ | |
47 | ||
48 | #include <linux/pci.h> | |
49 | #include <linux/io.h> | |
50 | #include <linux/delay.h> | |
51 | #include <linux/vmalloc.h> | |
52 | #include <linux/aer.h> | |
53 | #include <linux/module.h> | |
54 | ||
55 | #include "hfi.h" | |
56 | #include "chip_registers.h" | |
affa48de | 57 | #include "aspm.h" |
77241056 | 58 | |
77241056 MM |
59 | /* |
60 | * This file contains PCIe utility routines. | |
61 | */ | |
62 | ||
77241056 MM |
63 | /* |
64 | * Do all the common PCIe setup and initialization. | |
77241056 | 65 | */ |
57f97e96 | 66 | int hfi1_pcie_init(struct hfi1_devdata *dd) |
77241056 MM |
67 | { |
68 | int ret; | |
57f97e96 | 69 | struct pci_dev *pdev = dd->pcidev; |
77241056 MM |
70 | |
71 | ret = pci_enable_device(pdev); | |
72 | if (ret) { | |
73 | /* | |
74 | * This can happen (in theory) iff: | |
75 | * We did a chip reset, and then failed to reprogram the | |
76 | * BAR, or the chip reset due to an internal error. We then | |
77 | * unloaded the driver and reloaded it. | |
78 | * | |
79 | * Both reset cases set the BAR back to initial state. For | |
80 | * the latter case, the AER sticky error bit at offset 0x718 | |
81 | * should be set, but the Linux kernel doesn't yet know | |
82 | * about that, it appears. If the original BAR was retained | |
83 | * in the kernel data structures, this may be OK. | |
84 | */ | |
57f97e96 MR |
85 | dd_dev_err(dd, "pci enable failed: error %d\n", -ret); |
86 | return ret; | |
77241056 MM |
87 | } |
88 | ||
89 | ret = pci_request_regions(pdev, DRIVER_NAME); | |
90 | if (ret) { | |
57f97e96 | 91 | dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); |
77241056 MM |
92 | goto bail; |
93 | } | |
94 | ||
95 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
96 | if (ret) { | |
97 | /* | |
98 | * If the 64 bit setup fails, try 32 bit. Some systems | |
99 | * do not setup 64 bit maps on systems with 2GB or less | |
100 | * memory installed. | |
101 | */ | |
102 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
103 | if (ret) { | |
57f97e96 | 104 | dd_dev_err(dd, "Unable to set DMA mask: %d\n", ret); |
77241056 MM |
105 | goto bail; |
106 | } | |
107 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
e490974e | 108 | } else { |
77241056 | 109 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
e490974e | 110 | } |
77241056 | 111 | if (ret) { |
57f97e96 | 112 | dd_dev_err(dd, "Unable to set DMA consistent mask: %d\n", ret); |
77241056 MM |
113 | goto bail; |
114 | } | |
115 | ||
116 | pci_set_master(pdev); | |
0096765b | 117 | (void)pci_enable_pcie_error_reporting(pdev); |
57f97e96 | 118 | return 0; |
77241056 MM |
119 | |
120 | bail: | |
121 | hfi1_pcie_cleanup(pdev); | |
77241056 MM |
122 | return ret; |
123 | } | |
124 | ||
125 | /* | |
126 | * Clean what was done in hfi1_pcie_init() | |
127 | */ | |
128 | void hfi1_pcie_cleanup(struct pci_dev *pdev) | |
129 | { | |
130 | pci_disable_device(pdev); | |
131 | /* | |
132 | * Release regions should be called after the disable. OK to | |
133 | * call if request regions has not been called or failed. | |
134 | */ | |
135 | pci_release_regions(pdev); | |
136 | } | |
137 | ||
138 | /* | |
139 | * Do remaining PCIe setup, once dd is allocated, and save away | |
140 | * fields required to re-initialize after a chip reset, or for | |
141 | * various other purposes | |
142 | */ | |
26ea2544 | 143 | int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) |
77241056 MM |
144 | { |
145 | unsigned long len; | |
146 | resource_size_t addr; | |
c53df62c | 147 | int ret = 0; |
06e81e3e | 148 | u32 rcv_array_count; |
77241056 | 149 | |
77241056 MM |
150 | addr = pci_resource_start(pdev, 0); |
151 | len = pci_resource_len(pdev, 0); | |
152 | ||
153 | /* | |
154 | * The TXE PIO buffers are at the tail end of the chip space. | |
155 | * Cut them off and map them separately. | |
156 | */ | |
157 | ||
158 | /* sanity check vs expectations */ | |
159 | if (len != TXE_PIO_SEND + TXE_PIO_SIZE) { | |
160 | dd_dev_err(dd, "chip PIO range does not match\n"); | |
161 | return -EINVAL; | |
162 | } | |
163 | ||
cb51c5d2 MM |
164 | dd->kregbase1 = ioremap_nocache(addr, RCV_ARRAY); |
165 | if (!dd->kregbase1) { | |
166 | dd_dev_err(dd, "UC mapping of kregbase1 failed\n"); | |
77241056 | 167 | return -ENOMEM; |
cb51c5d2 MM |
168 | } |
169 | dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); | |
c872a1f9 KA |
170 | |
171 | /* verify that reads actually work, save revision for reset check */ | |
172 | dd->revision = readq(dd->kregbase1 + CCE_REVISION); | |
173 | if (dd->revision == ~(u64)0) { | |
174 | dd_dev_err(dd, "Cannot read chip CSRs\n"); | |
175 | goto nomem; | |
176 | } | |
177 | ||
06e81e3e MM |
178 | rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); |
179 | dd_dev_info(dd, "RcvArray count: %u\n", rcv_array_count); | |
180 | dd->base2_start = RCV_ARRAY + rcv_array_count * 8; | |
cb51c5d2 MM |
181 | |
182 | dd->kregbase2 = ioremap_nocache( | |
183 | addr + dd->base2_start, | |
184 | TXE_PIO_SEND - dd->base2_start); | |
185 | if (!dd->kregbase2) { | |
186 | dd_dev_err(dd, "UC mapping of kregbase2 failed\n"); | |
187 | goto nomem; | |
188 | } | |
189 | dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, | |
190 | TXE_PIO_SEND - dd->base2_start); | |
77241056 MM |
191 | |
192 | dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); | |
193 | if (!dd->piobase) { | |
cb51c5d2 MM |
194 | dd_dev_err(dd, "WC mapping of send buffers failed\n"); |
195 | goto nomem; | |
77241056 | 196 | } |
57f97e96 | 197 | dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE); |
77241056 | 198 | |
77241056 MM |
199 | dd->physaddr = addr; /* used for io_remap, etc. */ |
200 | ||
201 | /* | |
cb51c5d2 | 202 | * Map the chip's RcvArray as write-combining to allow us |
77241056 | 203 | * to write an entire cacheline worth of entries in one shot. |
77241056 | 204 | */ |
77241056 | 205 | dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, |
06e81e3e | 206 | rcv_array_count * 8); |
cb51c5d2 MM |
207 | if (!dd->rcvarray_wc) { |
208 | dd_dev_err(dd, "WC mapping of receive array failed\n"); | |
209 | goto nomem; | |
210 | } | |
211 | dd_dev_info(dd, "WC RcvArray: %p for %x\n", | |
06e81e3e | 212 | dd->rcvarray_wc, rcv_array_count * 8); |
77241056 | 213 | |
cb51c5d2 | 214 | dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ |
77241056 | 215 | return 0; |
cb51c5d2 MM |
216 | nomem: |
217 | ret = -ENOMEM; | |
cb51c5d2 | 218 | hfi1_pcie_ddcleanup(dd); |
c53df62c | 219 | return ret; |
77241056 MM |
220 | } |
221 | ||
222 | /* | |
223 | * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior | |
224 | * to releasing the dd memory. | |
225 | * Void because all of the core pcie cleanup functions are void. | |
226 | */ | |
227 | void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) | |
228 | { | |
77241056 | 229 | dd->flags &= ~HFI1_PRESENT; |
cb51c5d2 MM |
230 | if (dd->kregbase1) |
231 | iounmap(dd->kregbase1); | |
232 | dd->kregbase1 = NULL; | |
233 | if (dd->kregbase2) | |
234 | iounmap(dd->kregbase2); | |
235 | dd->kregbase2 = NULL; | |
77241056 MM |
236 | if (dd->rcvarray_wc) |
237 | iounmap(dd->rcvarray_wc); | |
cb51c5d2 | 238 | dd->rcvarray_wc = NULL; |
77241056 MM |
239 | if (dd->piobase) |
240 | iounmap(dd->piobase); | |
cb51c5d2 | 241 | dd->piobase = NULL; |
77241056 MM |
242 | } |
243 | ||
77241056 MM |
244 | /* return the PCIe link speed from the given link status */ |
245 | static u32 extract_speed(u16 linkstat) | |
246 | { | |
247 | u32 speed; | |
248 | ||
249 | switch (linkstat & PCI_EXP_LNKSTA_CLS) { | |
250 | default: /* not defined, assume Gen1 */ | |
251 | case PCI_EXP_LNKSTA_CLS_2_5GB: | |
252 | speed = 2500; /* Gen 1, 2.5GHz */ | |
253 | break; | |
254 | case PCI_EXP_LNKSTA_CLS_5_0GB: | |
255 | speed = 5000; /* Gen 2, 5GHz */ | |
256 | break; | |
8a7d1b16 | 257 | case PCI_EXP_LNKSTA_CLS_8_0GB: |
77241056 MM |
258 | speed = 8000; /* Gen 3, 8GHz */ |
259 | break; | |
260 | } | |
261 | return speed; | |
262 | } | |
263 | ||
264 | /* return the PCIe link speed from the given link status */ | |
265 | static u32 extract_width(u16 linkstat) | |
266 | { | |
267 | return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; | |
268 | } | |
269 | ||
270 | /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ | |
271 | static void update_lbus_info(struct hfi1_devdata *dd) | |
272 | { | |
273 | u16 linkstat; | |
c53df62c BD |
274 | int ret; |
275 | ||
276 | ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); | |
277 | if (ret) { | |
278 | dd_dev_err(dd, "Unable to read from PCI config\n"); | |
279 | return; | |
280 | } | |
77241056 | 281 | |
77241056 MM |
282 | dd->lbus_width = extract_width(linkstat); |
283 | dd->lbus_speed = extract_speed(linkstat); | |
284 | snprintf(dd->lbus_info, sizeof(dd->lbus_info), | |
285 | "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); | |
286 | } | |
287 | ||
288 | /* | |
289 | * Read in the current PCIe link width and speed. Find if the link is | |
290 | * Gen3 capable. | |
291 | */ | |
292 | int pcie_speeds(struct hfi1_devdata *dd) | |
293 | { | |
294 | u32 linkcap; | |
bf400235 | 295 | struct pci_dev *parent = dd->pcidev->bus->self; |
c53df62c | 296 | int ret; |
77241056 MM |
297 | |
298 | if (!pci_is_pcie(dd->pcidev)) { | |
299 | dd_dev_err(dd, "Can't find PCI Express capability!\n"); | |
300 | return -EINVAL; | |
301 | } | |
302 | ||
303 | /* find if our max speed is Gen3 and parent supports Gen3 speeds */ | |
304 | dd->link_gen3_capable = 1; | |
305 | ||
c53df62c BD |
306 | ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); |
307 | if (ret) { | |
308 | dd_dev_err(dd, "Unable to read from PCI config\n"); | |
309 | return ret; | |
310 | } | |
311 | ||
8a7d1b16 | 312 | if ((linkcap & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_8_0GB) { |
77241056 | 313 | dd_dev_info(dd, |
17fb4f29 JJ |
314 | "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n", |
315 | linkcap & PCI_EXP_LNKCAP_SLS); | |
77241056 MM |
316 | dd->link_gen3_capable = 0; |
317 | } | |
318 | ||
319 | /* | |
320 | * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed | |
321 | */ | |
bf400235 | 322 | if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) { |
77241056 MM |
323 | dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); |
324 | dd->link_gen3_capable = 0; | |
325 | } | |
326 | ||
327 | /* obtain the link width and current speed */ | |
328 | update_lbus_info(dd); | |
329 | ||
82ab09e1 | 330 | dd_dev_info(dd, "%s\n", dd->lbus_info); |
77241056 MM |
331 | |
332 | return 0; | |
333 | } | |
334 | ||
77241056 | 335 | /* restore command and BARs after a reset has wiped them out */ |
c53df62c | 336 | int restore_pci_variables(struct hfi1_devdata *dd) |
77241056 | 337 | { |
c53df62c BD |
338 | int ret = 0; |
339 | ||
340 | ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); | |
341 | if (ret) | |
342 | goto error; | |
343 | ||
344 | ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, | |
345 | dd->pcibar0); | |
346 | if (ret) | |
347 | goto error; | |
348 | ||
349 | ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, | |
350 | dd->pcibar1); | |
351 | if (ret) | |
352 | goto error; | |
353 | ||
354 | ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); | |
355 | if (ret) | |
356 | goto error; | |
357 | ||
358 | ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, | |
359 | dd->pcie_devctl); | |
360 | if (ret) | |
361 | goto error; | |
362 | ||
363 | ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, | |
364 | dd->pcie_lnkctl); | |
365 | if (ret) | |
366 | goto error; | |
367 | ||
368 | ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, | |
369 | dd->pcie_devctl2); | |
370 | if (ret) | |
371 | goto error; | |
372 | ||
373 | ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); | |
374 | if (ret) | |
375 | goto error; | |
376 | ||
4c009af4 MR |
377 | if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { |
378 | ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, | |
379 | dd->pci_tph2); | |
380 | if (ret) | |
381 | goto error; | |
382 | } | |
c53df62c BD |
383 | return 0; |
384 | ||
385 | error: | |
386 | dd_dev_err(dd, "Unable to write to PCI config\n"); | |
387 | return ret; | |
77241056 MM |
388 | } |
389 | ||
a618b7e4 BD |
390 | /* Save BARs and command to rewrite after device reset */ |
391 | int save_pci_variables(struct hfi1_devdata *dd) | |
392 | { | |
393 | int ret = 0; | |
394 | ||
395 | ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, | |
396 | &dd->pcibar0); | |
397 | if (ret) | |
398 | goto error; | |
399 | ||
400 | ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, | |
401 | &dd->pcibar1); | |
402 | if (ret) | |
403 | goto error; | |
404 | ||
405 | ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); | |
406 | if (ret) | |
407 | goto error; | |
408 | ||
409 | ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); | |
410 | if (ret) | |
411 | goto error; | |
412 | ||
413 | ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, | |
414 | &dd->pcie_devctl); | |
415 | if (ret) | |
416 | goto error; | |
417 | ||
418 | ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, | |
419 | &dd->pcie_lnkctl); | |
420 | if (ret) | |
421 | goto error; | |
422 | ||
423 | ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, | |
424 | &dd->pcie_devctl2); | |
425 | if (ret) | |
426 | goto error; | |
427 | ||
428 | ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); | |
429 | if (ret) | |
430 | goto error; | |
431 | ||
4c009af4 MR |
432 | if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { |
433 | ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, | |
434 | &dd->pci_tph2); | |
435 | if (ret) | |
436 | goto error; | |
437 | } | |
a618b7e4 BD |
438 | return 0; |
439 | ||
440 | error: | |
441 | dd_dev_err(dd, "Unable to read from PCI config\n"); | |
442 | return ret; | |
443 | } | |
444 | ||
77241056 MM |
445 | /* |
446 | * BIOS may not set PCIe bus-utilization parameters for best performance. | |
447 | * Check and optionally adjust them to maximize our throughput. | |
448 | */ | |
449 | static int hfi1_pcie_caps; | |
6a516bc9 | 450 | module_param_named(pcie_caps, hfi1_pcie_caps, int, 0444); |
77241056 MM |
451 | MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); |
452 | ||
affa48de | 453 | uint aspm_mode = ASPM_MODE_DISABLED; |
6a516bc9 | 454 | module_param_named(aspm, aspm_mode, uint, 0444); |
affa48de AD |
455 | MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic"); |
456 | ||
6a516bc9 MR |
457 | /** |
458 | * tune_pcie_caps() - Code to adjust PCIe capabilities. | |
459 | * @dd: Valid device data structure | |
460 | * | |
461 | */ | |
462 | void tune_pcie_caps(struct hfi1_devdata *dd) | |
77241056 MM |
463 | { |
464 | struct pci_dev *parent; | |
465 | u16 rc_mpss, rc_mps, ep_mpss, ep_mps; | |
bf70a775 | 466 | u16 rc_mrrs, ep_mrrs, max_mrrs, ectl; |
c53df62c | 467 | int ret; |
77241056 | 468 | |
bf70a775 VM |
469 | /* |
470 | * Turn on extended tags in DevCtl in case the BIOS has turned it off | |
471 | * to improve WFR SDMA bandwidth | |
472 | */ | |
828bcbdc HC |
473 | ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); |
474 | if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) { | |
bf70a775 VM |
475 | dd_dev_info(dd, "Enabling PCIe extended tags\n"); |
476 | ectl |= PCI_EXP_DEVCTL_EXT_TAG; | |
c53df62c BD |
477 | ret = pcie_capability_write_word(dd->pcidev, |
478 | PCI_EXP_DEVCTL, ectl); | |
828bcbdc HC |
479 | if (ret) |
480 | dd_dev_info(dd, "Unable to write to PCI config\n"); | |
bf70a775 | 481 | } |
77241056 MM |
482 | /* Find out supported and configured values for parent (root) */ |
483 | parent = dd->pcidev->bus->self; | |
bf400235 KW |
484 | /* |
485 | * The driver cannot perform the tuning if it does not have | |
486 | * access to the upstream component. | |
487 | */ | |
828bcbdc HC |
488 | if (!parent) { |
489 | dd_dev_info(dd, "Parent not found\n"); | |
490 | return; | |
491 | } | |
77241056 MM |
492 | if (!pci_is_root_bus(parent->bus)) { |
493 | dd_dev_info(dd, "Parent not root\n"); | |
828bcbdc HC |
494 | return; |
495 | } | |
496 | if (!pci_is_pcie(parent)) { | |
497 | dd_dev_info(dd, "Parent is not PCI Express capable\n"); | |
498 | return; | |
499 | } | |
500 | if (!pci_is_pcie(dd->pcidev)) { | |
501 | dd_dev_info(dd, "PCI device is not PCI Express capable\n"); | |
502 | return; | |
77241056 | 503 | } |
77241056 MM |
504 | rc_mpss = parent->pcie_mpss; |
505 | rc_mps = ffs(pcie_get_mps(parent)) - 8; | |
506 | /* Find out supported and configured values for endpoint (us) */ | |
507 | ep_mpss = dd->pcidev->pcie_mpss; | |
508 | ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; | |
509 | ||
510 | /* Find max payload supported by root, endpoint */ | |
511 | if (rc_mpss > ep_mpss) | |
512 | rc_mpss = ep_mpss; | |
513 | ||
514 | /* If Supported greater than limit in module param, limit it */ | |
515 | if (rc_mpss > (hfi1_pcie_caps & 7)) | |
516 | rc_mpss = hfi1_pcie_caps & 7; | |
517 | /* If less than (allowed, supported), bump root payload */ | |
518 | if (rc_mpss > rc_mps) { | |
519 | rc_mps = rc_mpss; | |
520 | pcie_set_mps(parent, 128 << rc_mps); | |
521 | } | |
522 | /* If less than (allowed, supported), bump endpoint payload */ | |
523 | if (rc_mpss > ep_mps) { | |
524 | ep_mps = rc_mpss; | |
525 | pcie_set_mps(dd->pcidev, 128 << ep_mps); | |
526 | } | |
527 | ||
528 | /* | |
529 | * Now the Read Request size. | |
530 | * No field for max supported, but PCIe spec limits it to 4096, | |
531 | * which is code '5' (log2(4096) - 7) | |
532 | */ | |
533 | max_mrrs = 5; | |
534 | if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7)) | |
535 | max_mrrs = (hfi1_pcie_caps >> 4) & 7; | |
536 | ||
537 | max_mrrs = 128 << max_mrrs; | |
538 | rc_mrrs = pcie_get_readrq(parent); | |
539 | ep_mrrs = pcie_get_readrq(dd->pcidev); | |
540 | ||
541 | if (max_mrrs > rc_mrrs) { | |
542 | rc_mrrs = max_mrrs; | |
543 | pcie_set_readrq(parent, rc_mrrs); | |
544 | } | |
545 | if (max_mrrs > ep_mrrs) { | |
546 | ep_mrrs = max_mrrs; | |
547 | pcie_set_readrq(dd->pcidev, ep_mrrs); | |
548 | } | |
549 | } | |
f4d507cd | 550 | |
77241056 MM |
551 | /* End of PCIe capability tuning */ |
552 | ||
553 | /* | |
554 | * From here through hfi1_pci_err_handler definition is invoked via | |
555 | * PCI error infrastructure, registered via pci | |
556 | */ | |
557 | static pci_ers_result_t | |
558 | pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
559 | { | |
560 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
561 | pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; | |
562 | ||
563 | switch (state) { | |
564 | case pci_channel_io_normal: | |
565 | dd_dev_info(dd, "State Normal, ignoring\n"); | |
566 | break; | |
567 | ||
568 | case pci_channel_io_frozen: | |
569 | dd_dev_info(dd, "State Frozen, requesting reset\n"); | |
570 | pci_disable_device(pdev); | |
571 | ret = PCI_ERS_RESULT_NEED_RESET; | |
572 | break; | |
573 | ||
574 | case pci_channel_io_perm_failure: | |
575 | if (dd) { | |
576 | dd_dev_info(dd, "State Permanent Failure, disabling\n"); | |
577 | /* no more register accesses! */ | |
578 | dd->flags &= ~HFI1_PRESENT; | |
579 | hfi1_disable_after_error(dd); | |
580 | } | |
581 | /* else early, or other problem */ | |
582 | ret = PCI_ERS_RESULT_DISCONNECT; | |
583 | break; | |
584 | ||
585 | default: /* shouldn't happen */ | |
586 | dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", | |
587 | state); | |
588 | break; | |
589 | } | |
590 | return ret; | |
591 | } | |
592 | ||
593 | static pci_ers_result_t | |
594 | pci_mmio_enabled(struct pci_dev *pdev) | |
595 | { | |
596 | u64 words = 0U; | |
597 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
598 | pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED; | |
599 | ||
600 | if (dd && dd->pport) { | |
601 | words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); | |
602 | if (words == ~0ULL) | |
603 | ret = PCI_ERS_RESULT_NEED_RESET; | |
604 | dd_dev_info(dd, | |
08af5916 | 605 | "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n", |
77241056 MM |
606 | words, ret); |
607 | } | |
608 | return ret; | |
609 | } | |
610 | ||
611 | static pci_ers_result_t | |
612 | pci_slot_reset(struct pci_dev *pdev) | |
613 | { | |
614 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
615 | ||
616 | dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); | |
617 | return PCI_ERS_RESULT_CAN_RECOVER; | |
618 | } | |
619 | ||
77241056 MM |
620 | static void |
621 | pci_resume(struct pci_dev *pdev) | |
622 | { | |
623 | struct hfi1_devdata *dd = pci_get_drvdata(pdev); | |
624 | ||
625 | dd_dev_info(dd, "HFI1 resume function called\n"); | |
626 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
627 | /* | |
628 | * Running jobs will fail, since it's asynchronous | |
629 | * unlike sysfs-requested reset. Better than | |
630 | * doing nothing. | |
631 | */ | |
632 | hfi1_init(dd, 1); /* same as re-init after reset */ | |
633 | } | |
634 | ||
635 | const struct pci_error_handlers hfi1_pci_err_handler = { | |
636 | .error_detected = pci_error_detected, | |
637 | .mmio_enabled = pci_mmio_enabled, | |
77241056 MM |
638 | .slot_reset = pci_slot_reset, |
639 | .resume = pci_resume, | |
640 | }; | |
641 | ||
642 | /*============================================================================*/ | |
643 | /* PCIe Gen3 support */ | |
644 | ||
645 | /* | |
646 | * This code is separated out because it is expected to be removed in the | |
647 | * final shipping product. If not, then it will be revisited and items | |
648 | * will be moved to more standard locations. | |
649 | */ | |
650 | ||
651 | /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */ | |
652 | #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */ | |
653 | #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */ | |
654 | #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */ | |
655 | ||
656 | /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */ | |
657 | #define DL_ERR_NONE 0x0 /* no error */ | |
658 | #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */ | |
659 | /* or response data */ | |
660 | #define DL_ERR_DISABLED 0x2 /* hfi disabled */ | |
661 | #define DL_ERR_SECURITY 0x3 /* security check failed */ | |
662 | #define DL_ERR_SBUS 0x4 /* SBus status error */ | |
663 | #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/ | |
664 | ||
665 | /* gasket block secondary bus reset delay */ | |
666 | #define SBR_DELAY_US 200000 /* 200ms */ | |
667 | ||
77241056 MM |
668 | static uint pcie_target = 3; |
669 | module_param(pcie_target, uint, S_IRUGO); | |
670 | MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)"); | |
671 | ||
672 | static uint pcie_force; | |
673 | module_param(pcie_force, uint, S_IRUGO); | |
674 | MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed"); | |
675 | ||
676 | static uint pcie_retry = 5; | |
677 | module_param(pcie_retry, uint, S_IRUGO); | |
678 | MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed"); | |
679 | ||
680 | #define UNSET_PSET 255 | |
681 | #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */ | |
39e2afa8 | 682 | #define DEFAULT_MCP_PSET 6 /* MCP HFI */ |
77241056 MM |
683 | static uint pcie_pset = UNSET_PSET; |
684 | module_param(pcie_pset, uint, S_IRUGO); | |
685 | MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10"); | |
686 | ||
39e2afa8 | 687 | static uint pcie_ctle = 3; /* discrete on, integrated on */ |
c3f8de0b DL |
688 | module_param(pcie_ctle, uint, S_IRUGO); |
689 | MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off"); | |
690 | ||
77241056 MM |
691 | /* equalization columns */ |
692 | #define PREC 0 | |
693 | #define ATTN 1 | |
694 | #define POST 2 | |
695 | ||
696 | /* discrete silicon preliminary equalization values */ | |
697 | static const u8 discrete_preliminary_eq[11][3] = { | |
698 | /* prec attn post */ | |
699 | { 0x00, 0x00, 0x12 }, /* p0 */ | |
700 | { 0x00, 0x00, 0x0c }, /* p1 */ | |
701 | { 0x00, 0x00, 0x0f }, /* p2 */ | |
702 | { 0x00, 0x00, 0x09 }, /* p3 */ | |
703 | { 0x00, 0x00, 0x00 }, /* p4 */ | |
704 | { 0x06, 0x00, 0x00 }, /* p5 */ | |
705 | { 0x09, 0x00, 0x00 }, /* p6 */ | |
706 | { 0x06, 0x00, 0x0f }, /* p7 */ | |
707 | { 0x09, 0x00, 0x09 }, /* p8 */ | |
708 | { 0x0c, 0x00, 0x00 }, /* p9 */ | |
709 | { 0x00, 0x00, 0x18 }, /* p10 */ | |
710 | }; | |
711 | ||
712 | /* integrated silicon preliminary equalization values */ | |
713 | static const u8 integrated_preliminary_eq[11][3] = { | |
714 | /* prec attn post */ | |
715 | { 0x00, 0x1e, 0x07 }, /* p0 */ | |
716 | { 0x00, 0x1e, 0x05 }, /* p1 */ | |
717 | { 0x00, 0x1e, 0x06 }, /* p2 */ | |
718 | { 0x00, 0x1e, 0x04 }, /* p3 */ | |
719 | { 0x00, 0x1e, 0x00 }, /* p4 */ | |
720 | { 0x03, 0x1e, 0x00 }, /* p5 */ | |
721 | { 0x04, 0x1e, 0x00 }, /* p6 */ | |
722 | { 0x03, 0x1e, 0x06 }, /* p7 */ | |
723 | { 0x03, 0x1e, 0x04 }, /* p8 */ | |
724 | { 0x05, 0x1e, 0x00 }, /* p9 */ | |
725 | { 0x00, 0x1e, 0x0a }, /* p10 */ | |
726 | }; | |
727 | ||
c3f8de0b DL |
728 | static const u8 discrete_ctle_tunings[11][4] = { |
729 | /* DC LF HF BW */ | |
730 | { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */ | |
731 | { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */ | |
732 | { 0x50, 0x09, 0x06, 0x06 }, /* p2 */ | |
733 | { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */ | |
734 | { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */ | |
735 | { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */ | |
736 | { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */ | |
737 | { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ | |
738 | { 0x48, 0x09, 0x06, 0x06 }, /* p8 */ | |
739 | { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */ | |
740 | { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */ | |
741 | }; | |
742 | ||
743 | static const u8 integrated_ctle_tunings[11][4] = { | |
744 | /* DC LF HF BW */ | |
745 | { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */ | |
746 | { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */ | |
747 | { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */ | |
748 | { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */ | |
749 | { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */ | |
750 | { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */ | |
751 | { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */ | |
752 | { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */ | |
753 | { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */ | |
754 | { 0x38, 0x09, 0x06, 0x06 }, /* p9 */ | |
755 | { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */ | |
756 | }; | |
757 | ||
77241056 MM |
758 | /* helper to format the value to write to hardware */ |
759 | #define eq_value(pre, curr, post) \ | |
760 | ((((u32)(pre)) << \ | |
761 | PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \ | |
762 | | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \ | |
763 | | (((u32)(post)) << \ | |
764 | PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT)) | |
765 | ||
766 | /* | |
767 | * Load the given EQ preset table into the PCIe hardware. | |
768 | */ | |
769 | static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, | |
770 | u8 div) | |
771 | { | |
772 | struct pci_dev *pdev = dd->pcidev; | |
773 | u32 hit_error = 0; | |
774 | u32 violation; | |
775 | u32 i; | |
776 | u8 c_minus1, c0, c_plus1; | |
c53df62c | 777 | int ret; |
77241056 MM |
778 | |
779 | for (i = 0; i < 11; i++) { | |
780 | /* set index */ | |
781 | pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i); | |
782 | /* write the value */ | |
783 | c_minus1 = eq[i][PREC] / div; | |
784 | c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); | |
785 | c_plus1 = eq[i][POST] / div; | |
786 | pci_write_config_dword(pdev, PCIE_CFG_REG_PL102, | |
17fb4f29 | 787 | eq_value(c_minus1, c0, c_plus1)); |
77241056 | 788 | /* check if these coefficients violate EQ rules */ |
c53df62c BD |
789 | ret = pci_read_config_dword(dd->pcidev, |
790 | PCIE_CFG_REG_PL105, &violation); | |
791 | if (ret) { | |
792 | dd_dev_err(dd, "Unable to read from PCI config\n"); | |
793 | hit_error = 1; | |
794 | break; | |
795 | } | |
796 | ||
77241056 MM |
797 | if (violation |
798 | & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){ | |
799 | if (hit_error == 0) { | |
800 | dd_dev_err(dd, | |
17fb4f29 | 801 | "Gen3 EQ Table Coefficient rule violations\n"); |
77241056 MM |
802 | dd_dev_err(dd, " prec attn post\n"); |
803 | } | |
804 | dd_dev_err(dd, " p%02d: %02x %02x %02x\n", | |
17fb4f29 JJ |
805 | i, (u32)eq[i][0], (u32)eq[i][1], |
806 | (u32)eq[i][2]); | |
77241056 | 807 | dd_dev_err(dd, " %02x %02x %02x\n", |
17fb4f29 | 808 | (u32)c_minus1, (u32)c0, (u32)c_plus1); |
77241056 MM |
809 | hit_error = 1; |
810 | } | |
811 | } | |
812 | if (hit_error) | |
813 | return -EINVAL; | |
814 | return 0; | |
815 | } | |
816 | ||
817 | /* | |
818 | * Steps to be done after the PCIe firmware is downloaded and | |
819 | * before the SBR for the Pcie Gen3. | |
576531fd | 820 | * The SBus resource is already being held. |
77241056 MM |
821 | */ |
822 | static void pcie_post_steps(struct hfi1_devdata *dd) | |
823 | { | |
824 | int i; | |
825 | ||
826 | set_sbus_fast_mode(dd); | |
827 | /* | |
828 | * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1. | |
829 | * This avoids a spurious framing error that can otherwise be | |
830 | * generated by the MAC layer. | |
831 | * | |
832 | * Use individual addresses since no broadcast is set up. | |
833 | */ | |
834 | for (i = 0; i < NUM_PCIE_SERDES; i++) { | |
835 | sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], | |
836 | 0x03, WRITE_SBUS_RECEIVER, 0x00022132); | |
837 | } | |
838 | ||
839 | clear_sbus_fast_mode(dd); | |
840 | } | |
841 | ||
842 | /* | |
843 | * Trigger a secondary bus reset (SBR) on ourselves using our parent. | |
844 | * | |
845 | * Based on pci_parent_bus_reset() which is not exported by the | |
846 | * kernel core. | |
847 | */ | |
848 | static int trigger_sbr(struct hfi1_devdata *dd) | |
849 | { | |
850 | struct pci_dev *dev = dd->pcidev; | |
851 | struct pci_dev *pdev; | |
852 | ||
853 | /* need a parent */ | |
854 | if (!dev->bus->self) { | |
855 | dd_dev_err(dd, "%s: no parent device\n", __func__); | |
856 | return -ENOTTY; | |
857 | } | |
858 | ||
859 | /* should not be anyone else on the bus */ | |
860 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
861 | if (pdev != dev) { | |
862 | dd_dev_err(dd, | |
17fb4f29 JJ |
863 | "%s: another device is on the same bus\n", |
864 | __func__); | |
77241056 MM |
865 | return -ENOTTY; |
866 | } | |
867 | ||
868 | /* | |
869 | * A secondary bus reset (SBR) issues a hot reset to our device. | |
870 | * The following routine does a 1s wait after the reset is dropped | |
871 | * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 - | |
872 | * Conventional Reset, paragraph 3, line 35 also says that a 1s | |
873 | * delay after a reset is required. Per spec requirements, | |
874 | * the link is either working or not after that point. | |
875 | */ | |
c6a44ba9 | 876 | return pci_reset_bus(dev); |
77241056 MM |
877 | } |
878 | ||
879 | /* | |
880 | * Write the given gasket interrupt register. | |
881 | */ | |
882 | static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, | |
883 | u16 code, u16 data) | |
884 | { | |
885 | write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), | |
17fb4f29 JJ |
886 | (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) | |
887 | ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT))); | |
77241056 MM |
888 | } |
889 | ||
890 | /* | |
891 | * Tell the gasket logic how to react to the reset. | |
892 | */ | |
893 | static void arm_gasket_logic(struct hfi1_devdata *dd) | |
894 | { | |
895 | u64 reg; | |
896 | ||
17fb4f29 JJ |
897 | reg = (((u64)1 << dd->hfi1_id) << |
898 | ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) | | |
899 | ((u64)pcie_serdes_broadcast[dd->hfi1_id] << | |
900 | ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT | | |
901 | ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK | | |
902 | ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) << | |
903 | ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT); | |
77241056 MM |
904 | write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); |
905 | /* read back to push the write */ | |
906 | read_csr(dd, ASIC_PCIE_SD_HOST_CMD); | |
907 | } | |
908 | ||
14d88ec5 DL |
909 | /* |
910 | * CCE_PCIE_CTRL long name helpers | |
911 | * We redefine these shorter macros to use in the code while leaving | |
912 | * chip_registers.h to be autogenerated from the hardware spec. | |
913 | */ | |
914 | #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK | |
915 | #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT | |
916 | #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK | |
917 | #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT | |
918 | #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT | |
919 | #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT | |
920 | #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK | |
921 | #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT | |
922 | #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK | |
923 | #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT | |
924 | ||
925 | /* | |
926 | * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C). | |
927 | */ | |
928 | static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) | |
929 | { | |
930 | u64 pcie_ctrl; | |
931 | u64 xmt_margin; | |
932 | u64 xmt_margin_oe; | |
933 | u64 lane_delay; | |
934 | u64 lane_bundle; | |
935 | ||
936 | pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); | |
937 | ||
938 | /* | |
939 | * For Discrete, use full-swing. | |
940 | * - PCIe TX defaults to full-swing. | |
941 | * Leave this register as default. | |
942 | * For Integrated, use half-swing | |
943 | * - Copy xmt_margin and xmt_margin_oe | |
944 | * from Gen1/Gen2 to Gen3. | |
945 | */ | |
946 | if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ | |
947 | /* extract initial fields */ | |
948 | xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT) | |
949 | & MARGIN_GEN1_GEN2_MASK; | |
950 | xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT) | |
951 | & MARGIN_G1_G2_OVERWRITE_MASK; | |
952 | lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK; | |
953 | lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT) | |
954 | & LANE_BUNDLE_MASK; | |
955 | ||
956 | /* | |
957 | * For A0, EFUSE values are not set. Override with the | |
958 | * correct values. | |
959 | */ | |
960 | if (is_ax(dd)) { | |
961 | /* | |
962 | * xmt_margin and OverwiteEnabel should be the | |
963 | * same for Gen1/Gen2 and Gen3 | |
964 | */ | |
965 | xmt_margin = 0x5; | |
966 | xmt_margin_oe = 0x1; | |
967 | lane_delay = 0xF; /* Delay 240ns. */ | |
968 | lane_bundle = 0x0; /* Set to 1 lane. */ | |
969 | } | |
970 | ||
971 | /* overwrite existing values */ | |
972 | pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT) | |
973 | | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT) | |
974 | | (xmt_margin << MARGIN_SHIFT) | |
975 | | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT) | |
976 | | (lane_delay << LANE_DELAY_SHIFT) | |
977 | | (lane_bundle << LANE_BUNDLE_SHIFT); | |
978 | ||
979 | write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); | |
980 | } | |
981 | ||
982 | dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", | |
983 | fname, pcie_ctrl); | |
984 | } | |
985 | ||
77241056 MM |
986 | /* |
987 | * Do all the steps needed to transition the PCIe link to Gen3 speed. | |
988 | */ | |
989 | int do_pcie_gen3_transition(struct hfi1_devdata *dd) | |
990 | { | |
bf400235 | 991 | struct pci_dev *parent = dd->pcidev->bus->self; |
77241056 MM |
992 | u64 fw_ctrl; |
993 | u64 reg, therm; | |
994 | u32 reg32, fs, lf; | |
995 | u32 status, err; | |
996 | int ret; | |
997 | int do_retry, retry_count = 0; | |
c3f8de0b | 998 | int intnum = 0; |
77241056 | 999 | uint default_pset; |
6391214f | 1000 | uint pset = pcie_pset; |
77241056 | 1001 | u16 target_vector, target_speed; |
affa48de | 1002 | u16 lnkctl2, vendor; |
77241056 MM |
1003 | u8 div; |
1004 | const u8 (*eq)[3]; | |
c3f8de0b DL |
1005 | const u8 (*ctle_tunings)[4]; |
1006 | uint static_ctle_mode; | |
77241056 MM |
1007 | int return_error = 0; |
1008 | ||
1009 | /* PCIe Gen3 is for the ASIC only */ | |
1010 | if (dd->icode != ICODE_RTL_SILICON) | |
1011 | return 0; | |
1012 | ||
1013 | if (pcie_target == 1) { /* target Gen1 */ | |
8a7d1b16 | 1014 | target_vector = PCI_EXP_LNKCTL2_TLS_2_5GT; |
77241056 MM |
1015 | target_speed = 2500; |
1016 | } else if (pcie_target == 2) { /* target Gen2 */ | |
8a7d1b16 | 1017 | target_vector = PCI_EXP_LNKCTL2_TLS_5_0GT; |
77241056 MM |
1018 | target_speed = 5000; |
1019 | } else if (pcie_target == 3) { /* target Gen3 */ | |
8a7d1b16 | 1020 | target_vector = PCI_EXP_LNKCTL2_TLS_8_0GT; |
77241056 MM |
1021 | target_speed = 8000; |
1022 | } else { | |
1023 | /* off or invalid target - skip */ | |
1024 | dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); | |
1025 | return 0; | |
1026 | } | |
1027 | ||
1028 | /* if already at target speed, done (unless forced) */ | |
1029 | if (dd->lbus_speed == target_speed) { | |
1030 | dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, | |
17fb4f29 JJ |
1031 | pcie_target, |
1032 | pcie_force ? "re-doing anyway" : "skipping"); | |
77241056 MM |
1033 | if (!pcie_force) |
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | /* | |
bf400235 KW |
1038 | * The driver cannot do the transition if it has no access to the |
1039 | * upstream component | |
77241056 | 1040 | */ |
bf400235 KW |
1041 | if (!parent) { |
1042 | dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", | |
1043 | __func__); | |
1044 | return 0; | |
1045 | } | |
77241056 MM |
1046 | |
1047 | /* | |
1048 | * Do the Gen3 transition. Steps are those of the PCIe Gen3 | |
1049 | * recipe. | |
1050 | */ | |
1051 | ||
1052 | /* step 1: pcie link working in gen1/gen2 */ | |
1053 | ||
1054 | /* step 2: if either side is not capable of Gen3, done */ | |
1055 | if (pcie_target == 3 && !dd->link_gen3_capable) { | |
1056 | dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); | |
1057 | ret = -ENOSYS; | |
1058 | goto done_no_mutex; | |
1059 | } | |
1060 | ||
576531fd DL |
1061 | /* hold the SBus resource across the firmware download and SBR */ |
1062 | ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); | |
1063 | if (ret) { | |
1064 | dd_dev_err(dd, "%s: unable to acquire SBus resource\n", | |
1065 | __func__); | |
77241056 | 1066 | return ret; |
576531fd | 1067 | } |
77241056 MM |
1068 | |
1069 | /* make sure thermal polling is not causing interrupts */ | |
1070 | therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); | |
1071 | if (therm) { | |
1072 | write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); | |
1073 | msleep(100); | |
1074 | dd_dev_info(dd, "%s: Disabled therm polling\n", | |
1075 | __func__); | |
1076 | } | |
1077 | ||
c91b4a12 | 1078 | retry: |
65fcf557 | 1079 | /* the SBus download will reset the spico for thermal */ |
c91b4a12 | 1080 | |
77241056 MM |
1081 | /* step 3: download SBus Master firmware */ |
1082 | /* step 4: download PCIe Gen3 SerDes firmware */ | |
77241056 MM |
1083 | dd_dev_info(dd, "%s: downloading firmware\n", __func__); |
1084 | ret = load_pcie_firmware(dd); | |
6b14e0ea DL |
1085 | if (ret) { |
1086 | /* do not proceed if the firmware cannot be downloaded */ | |
1087 | return_error = 1; | |
77241056 | 1088 | goto done; |
6b14e0ea | 1089 | } |
77241056 MM |
1090 | |
1091 | /* step 5: set up device parameter settings */ | |
1092 | dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); | |
1093 | ||
1094 | /* | |
1095 | * PcieCfgSpcie1 - Link Control 3 | |
1096 | * Leave at reset value. No need to set PerfEq - link equalization | |
1097 | * will be performed automatically after the SBR when the target | |
1098 | * speed is 8GT/s. | |
1099 | */ | |
1100 | ||
1101 | /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ | |
1102 | pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); | |
1103 | ||
1104 | /* step 5a: Set Synopsys Port Logic registers */ | |
1105 | ||
1106 | /* | |
1107 | * PcieCfgRegPl2 - Port Force Link | |
1108 | * | |
1109 | * Set the low power field to 0x10 to avoid unnecessary power | |
1110 | * management messages. All other fields are zero. | |
1111 | */ | |
1112 | reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; | |
1113 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); | |
1114 | ||
1115 | /* | |
1116 | * PcieCfgRegPl100 - Gen3 Control | |
1117 | * | |
1118 | * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl | |
80e4898e | 1119 | * turn on PcieCfgRegPl100.EqEieosCnt |
77241056 MM |
1120 | * Everything else zero. |
1121 | */ | |
1122 | reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; | |
1123 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); | |
1124 | ||
1125 | /* | |
1126 | * PcieCfgRegPl101 - Gen3 EQ FS and LF | |
1127 | * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping | |
1128 | * PcieCfgRegPl103 - Gen3 EQ Preset Index | |
1129 | * PcieCfgRegPl105 - Gen3 EQ Status | |
1130 | * | |
1131 | * Give initial EQ settings. | |
1132 | */ | |
1133 | if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ | |
1134 | /* 1000mV, FS=24, LF = 8 */ | |
1135 | fs = 24; | |
1136 | lf = 8; | |
1137 | div = 3; | |
1138 | eq = discrete_preliminary_eq; | |
1139 | default_pset = DEFAULT_DISCRETE_PSET; | |
c3f8de0b DL |
1140 | ctle_tunings = discrete_ctle_tunings; |
1141 | /* bit 0 - discrete on/off */ | |
1142 | static_ctle_mode = pcie_ctle & 0x1; | |
77241056 MM |
1143 | } else { |
1144 | /* 400mV, FS=29, LF = 9 */ | |
1145 | fs = 29; | |
1146 | lf = 9; | |
1147 | div = 1; | |
1148 | eq = integrated_preliminary_eq; | |
1149 | default_pset = DEFAULT_MCP_PSET; | |
c3f8de0b DL |
1150 | ctle_tunings = integrated_ctle_tunings; |
1151 | /* bit 1 - integrated on/off */ | |
1152 | static_ctle_mode = (pcie_ctle >> 1) & 0x1; | |
77241056 MM |
1153 | } |
1154 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, | |
17fb4f29 JJ |
1155 | (fs << |
1156 | PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) | | |
1157 | (lf << | |
1158 | PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT)); | |
77241056 MM |
1159 | ret = load_eq_table(dd, eq, fs, div); |
1160 | if (ret) | |
1161 | goto done; | |
1162 | ||
1163 | /* | |
1164 | * PcieCfgRegPl106 - Gen3 EQ Control | |
1165 | * | |
1166 | * Set Gen3EqPsetReqVec, leave other fields 0. | |
1167 | */ | |
6391214f BD |
1168 | if (pset == UNSET_PSET) |
1169 | pset = default_pset; | |
1170 | if (pset > 10) { /* valid range is 0-10, inclusive */ | |
77241056 | 1171 | dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", |
6391214f BD |
1172 | __func__, pset, default_pset); |
1173 | pset = default_pset; | |
77241056 | 1174 | } |
6391214f | 1175 | dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset); |
77241056 | 1176 | pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, |
6391214f | 1177 | ((1 << pset) << |
17fb4f29 JJ |
1178 | PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) | |
1179 | PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK | | |
1180 | PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK); | |
77241056 MM |
1181 | |
1182 | /* | |
1183 | * step 5b: Do post firmware download steps via SBus | |
1184 | */ | |
1185 | dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); | |
1186 | pcie_post_steps(dd); | |
1187 | ||
1188 | /* | |
1189 | * step 5c: Program gasket interrupts | |
1190 | */ | |
1191 | /* set the Rx Bit Rate to REFCLK ratio */ | |
c3f8de0b | 1192 | write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); |
77241056 | 1193 | /* disable pCal for PCIe Gen3 RX equalization */ |
c3f8de0b DL |
1194 | /* select adaptive or static CTLE */ |
1195 | write_gasket_interrupt(dd, intnum++, 0x0026, | |
1196 | 0x5b01 | (static_ctle_mode << 3)); | |
77241056 MM |
1197 | /* |
1198 | * Enable iCal for PCIe Gen3 RX equalization, and set which | |
1199 | * evaluation of RX_EQ_EVAL will launch the iCal procedure. | |
1200 | */ | |
c3f8de0b DL |
1201 | write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); |
1202 | ||
1203 | if (static_ctle_mode) { | |
1204 | /* apply static CTLE tunings */ | |
1205 | u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw; | |
1206 | ||
6391214f BD |
1207 | pcie_dc = ctle_tunings[pset][0]; |
1208 | pcie_lf = ctle_tunings[pset][1]; | |
1209 | pcie_hf = ctle_tunings[pset][2]; | |
1210 | pcie_bw = ctle_tunings[pset][3]; | |
c3f8de0b DL |
1211 | write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); |
1212 | write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); | |
1213 | write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); | |
1214 | write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); | |
1215 | } | |
1216 | ||
77241056 | 1217 | /* terminate list */ |
c3f8de0b | 1218 | write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); |
77241056 MM |
1219 | |
1220 | /* | |
1221 | * step 5d: program XMT margin | |
77241056 | 1222 | */ |
14d88ec5 | 1223 | write_xmt_margin(dd, __func__); |
77241056 | 1224 | |
affa48de AD |
1225 | /* |
1226 | * step 5e: disable active state power management (ASPM). It | |
1227 | * will be enabled if required later | |
1228 | */ | |
77241056 | 1229 | dd_dev_info(dd, "%s: clearing ASPM\n", __func__); |
affa48de | 1230 | aspm_hw_disable_l1(dd); |
77241056 MM |
1231 | |
1232 | /* | |
1233 | * step 5f: clear DirectSpeedChange | |
1234 | * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the | |
1235 | * change in the speed target from starting before we are ready. | |
1236 | * This field defaults to 0 and we are not changing it, so nothing | |
1237 | * needs to be done. | |
1238 | */ | |
1239 | ||
1240 | /* step 5g: Set target link speed */ | |
1241 | /* | |
1242 | * Set target link speed to be target on both device and parent. | |
1243 | * On setting the parent: Some system BIOSs "helpfully" set the | |
1244 | * parent target speed to Gen2 to match the ASIC's initial speed. | |
1245 | * We can set the target Gen3 because we have already checked | |
1246 | * that it is Gen3 capable earlier. | |
1247 | */ | |
1248 | dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); | |
c53df62c BD |
1249 | ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2); |
1250 | if (ret) { | |
1251 | dd_dev_err(dd, "Unable to read from PCI config\n"); | |
1252 | return_error = 1; | |
1253 | goto done; | |
1254 | } | |
1255 | ||
77241056 | 1256 | dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, |
17fb4f29 | 1257 | (u32)lnkctl2); |
77241056 | 1258 | /* only write to parent if target is not as high as ours */ |
8a7d1b16 FL |
1259 | if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) < target_vector) { |
1260 | lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; | |
77241056 MM |
1261 | lnkctl2 |= target_vector; |
1262 | dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, | |
17fb4f29 | 1263 | (u32)lnkctl2); |
c53df62c BD |
1264 | ret = pcie_capability_write_word(parent, |
1265 | PCI_EXP_LNKCTL2, lnkctl2); | |
1266 | if (ret) { | |
1267 | dd_dev_err(dd, "Unable to write to PCI config\n"); | |
1268 | return_error = 1; | |
1269 | goto done; | |
1270 | } | |
77241056 MM |
1271 | } else { |
1272 | dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); | |
1273 | } | |
1274 | ||
1275 | dd_dev_info(dd, "%s: setting target link speed\n", __func__); | |
c53df62c BD |
1276 | ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); |
1277 | if (ret) { | |
1278 | dd_dev_err(dd, "Unable to read from PCI config\n"); | |
1279 | return_error = 1; | |
1280 | goto done; | |
1281 | } | |
1282 | ||
77241056 | 1283 | dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, |
17fb4f29 | 1284 | (u32)lnkctl2); |
8a7d1b16 | 1285 | lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; |
77241056 MM |
1286 | lnkctl2 |= target_vector; |
1287 | dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, | |
17fb4f29 | 1288 | (u32)lnkctl2); |
c53df62c BD |
1289 | ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); |
1290 | if (ret) { | |
1291 | dd_dev_err(dd, "Unable to write to PCI config\n"); | |
1292 | return_error = 1; | |
1293 | goto done; | |
1294 | } | |
77241056 MM |
1295 | |
1296 | /* step 5h: arm gasket logic */ | |
1297 | /* hold DC in reset across the SBR */ | |
1298 | write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); | |
50e5dcbe | 1299 | (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ |
77241056 MM |
1300 | /* save firmware control across the SBR */ |
1301 | fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); | |
1302 | ||
1303 | dd_dev_info(dd, "%s: arming gasket logic\n", __func__); | |
1304 | arm_gasket_logic(dd); | |
1305 | ||
1306 | /* | |
1307 | * step 6: quiesce PCIe link | |
1308 | * The chip has already been reset, so there will be no traffic | |
1309 | * from the chip. Linux has no easy way to enforce that it will | |
1310 | * not try to access the device, so we just need to hope it doesn't | |
1311 | * do it while we are doing the reset. | |
1312 | */ | |
1313 | ||
1314 | /* | |
1315 | * step 7: initiate the secondary bus reset (SBR) | |
1316 | * step 8: hardware brings the links back up | |
1317 | * step 9: wait for link speed transition to be complete | |
1318 | */ | |
1319 | dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); | |
1320 | ret = trigger_sbr(dd); | |
1321 | if (ret) | |
1322 | goto done; | |
1323 | ||
1324 | /* step 10: decide what to do next */ | |
1325 | ||
1326 | /* check if we can read PCI space */ | |
1327 | ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); | |
1328 | if (ret) { | |
1329 | dd_dev_info(dd, | |
17fb4f29 JJ |
1330 | "%s: read of VendorID failed after SBR, err %d\n", |
1331 | __func__, ret); | |
77241056 MM |
1332 | return_error = 1; |
1333 | goto done; | |
1334 | } | |
1335 | if (vendor == 0xffff) { | |
1336 | dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); | |
1337 | return_error = 1; | |
1338 | ret = -EIO; | |
1339 | goto done; | |
1340 | } | |
1341 | ||
1342 | /* restore PCI space registers we know were reset */ | |
1343 | dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); | |
c53df62c BD |
1344 | ret = restore_pci_variables(dd); |
1345 | if (ret) { | |
1346 | dd_dev_err(dd, "%s: Could not restore PCI variables\n", | |
1347 | __func__); | |
1348 | return_error = 1; | |
1349 | goto done; | |
1350 | } | |
1351 | ||
77241056 MM |
1352 | /* restore firmware control */ |
1353 | write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); | |
1354 | ||
1355 | /* | |
1356 | * Check the gasket block status. | |
1357 | * | |
1358 | * This is the first CSR read after the SBR. If the read returns | |
1359 | * all 1s (fails), the link did not make it back. | |
1360 | * | |
1361 | * Once we're sure we can read and write, clear the DC reset after | |
1362 | * the SBR. Then check for any per-lane errors. Then look over | |
1363 | * the status. | |
1364 | */ | |
1365 | reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); | |
1366 | dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); | |
1367 | if (reg == ~0ull) { /* PCIe read failed/timeout */ | |
1368 | dd_dev_err(dd, "SBR failed - unable to read from device\n"); | |
1369 | return_error = 1; | |
1370 | ret = -ENOSYS; | |
1371 | goto done; | |
1372 | } | |
1373 | ||
1374 | /* clear the DC reset */ | |
1375 | write_csr(dd, CCE_DC_CTRL, 0); | |
abfc4459 | 1376 | |
77241056 | 1377 | /* Set the LED off */ |
773d0451 | 1378 | setextled(dd, 0); |
77241056 MM |
1379 | |
1380 | /* check for any per-lane errors */ | |
c53df62c BD |
1381 | ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); |
1382 | if (ret) { | |
1383 | dd_dev_err(dd, "Unable to read from PCI config\n"); | |
1384 | return_error = 1; | |
1385 | goto done; | |
1386 | } | |
1387 | ||
77241056 MM |
1388 | dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); |
1389 | ||
1390 | /* extract status, look for our HFI */ | |
1391 | status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) | |
1392 | & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK; | |
1393 | if ((status & (1 << dd->hfi1_id)) == 0) { | |
1394 | dd_dev_err(dd, | |
17fb4f29 JJ |
1395 | "%s: gasket status 0x%x, expecting 0x%x\n", |
1396 | __func__, status, 1 << dd->hfi1_id); | |
77241056 MM |
1397 | ret = -EIO; |
1398 | goto done; | |
1399 | } | |
1400 | ||
1401 | /* extract error */ | |
1402 | err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) | |
1403 | & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK; | |
1404 | if (err) { | |
1405 | dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); | |
1406 | ret = -EIO; | |
1407 | goto done; | |
1408 | } | |
1409 | ||
1410 | /* update our link information cache */ | |
1411 | update_lbus_info(dd); | |
1412 | dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, | |
17fb4f29 | 1413 | dd->lbus_info); |
77241056 MM |
1414 | |
1415 | if (dd->lbus_speed != target_speed) { /* not target */ | |
1416 | /* maybe retry */ | |
1417 | do_retry = retry_count < pcie_retry; | |
1418 | dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n", | |
17fb4f29 | 1419 | pcie_target, do_retry ? ", retrying" : ""); |
77241056 MM |
1420 | retry_count++; |
1421 | if (do_retry) { | |
1422 | msleep(100); /* allow time to settle */ | |
1423 | goto retry; | |
1424 | } | |
1425 | ret = -EIO; | |
1426 | } | |
1427 | ||
1428 | done: | |
1429 | if (therm) { | |
1430 | write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); | |
1431 | msleep(100); | |
1432 | dd_dev_info(dd, "%s: Re-enable therm polling\n", | |
1433 | __func__); | |
1434 | } | |
576531fd | 1435 | release_chip_resource(dd, CR_SBUS); |
77241056 MM |
1436 | done_no_mutex: |
1437 | /* return no error if it is OK to be at current speed */ | |
1438 | if (ret && !return_error) { | |
1439 | dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); | |
1440 | ret = 0; | |
1441 | } | |
1442 | ||
1443 | dd_dev_info(dd, "%s: done\n", __func__); | |
1444 | return ret; | |
1445 | } |