[linux-2.6-block.git] / drivers / infiniband / hw / ehca / hipz_hw.h

/*
 *  IBM eServer eHCA Infiniband device driver for Linux on POWER
 *
 *  eHCA register definitions
 *
 *  Authors: Waleri Fomin <fomin@de.ibm.com>
 *           Christoph Raisch <raisch@de.ibm.com>
 *           Reinhard Ernst <rernst@de.ibm.com>
 *
 *  Copyright (c) 2005 IBM Corporation
 *
 *  All rights reserved.
 *
 *  This source code is distributed under a dual license of GPL v2.0 and OpenIB
 *  BSD.
 *
 * OpenIB BSD License
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials
 * provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef __HIPZ_HW_H__
#define __HIPZ_HW_H__

#include "ehca_tools.h"

/* QP Table Entry Memory Map */
struct hipz_qptemm {
	u64 qpx_hcr;
	u64 qpx_c;
	u64 qpx_herr;
	u64 qpx_aer;
/* 0x20*/
	u64 qpx_sqa;
	u64 qpx_sqc;
	u64 qpx_rqa;
	u64 qpx_rqc;
/* 0x40*/
	u64 qpx_st;
	u64 qpx_pmstate;
	u64 qpx_pmfa;
	u64 qpx_pkey;
/* 0x60*/
	u64 qpx_pkeya;
	u64 qpx_pkeyb;
	u64 qpx_pkeyc;
	u64 qpx_pkeyd;
/* 0x80*/
	u64 qpx_qkey;
	u64 qpx_dqp;
	u64 qpx_dlidp;
	u64 qpx_portp;
/* 0xa0*/
	u64 qpx_slidp;
	u64 qpx_slidpp;
	u64 qpx_dlida;
	u64 qpx_porta;
/* 0xc0*/
	u64 qpx_slida;
	u64 qpx_slidpa;
	u64 qpx_slvl;
	u64 qpx_ipd;
/* 0xe0*/
	u64 qpx_mtu;
	u64 qpx_lato;
	u64 qpx_rlimit;
	u64 qpx_rnrlimit;
/* 0x100*/
	u64 qpx_t;
	u64 qpx_sqhp;
	u64 qpx_sqptp;
	u64 qpx_nspsn;
/* 0x120*/
	u64 qpx_nspsnhwm;
	u64 reserved1;
	u64 qpx_sdsi;
	u64 qpx_sdsbc;
/* 0x140*/
	u64 qpx_sqwsize;
	u64 qpx_sqwts;
	u64 qpx_lsn;
	u64 qpx_nssn;
/* 0x160 */
	u64 qpx_mor;
	u64 qpx_cor;
	u64 qpx_sqsize;
	u64 qpx_erc;
/* 0x180*/
	u64 qpx_rnrrc;
	u64 qpx_ernrwt;
	u64 qpx_rnrresp;
	u64 qpx_lmsna;
/* 0x1a0 */
	u64 qpx_sqhpc;
	u64 qpx_sqcptp;
	u64 qpx_sigt;
	u64 qpx_wqecnt;
/* 0x1c0*/
	u64 qpx_rqhp;
	u64 qpx_rqptp;
	u64 qpx_rqsize;
	u64 qpx_nrr;
/* 0x1e0*/
	u64 qpx_rdmac;
	u64 qpx_nrpsn;
	u64 qpx_lapsn;
	u64 qpx_lcr;
/* 0x200*/
	u64 qpx_rwc;
	u64 qpx_rwva;
	u64 qpx_rdsi;
	u64 qpx_rdsbc;
/* 0x220*/
	u64 qpx_rqwsize;
	u64 qpx_crmsn;
	u64 qpx_rdd;
	u64 qpx_larpsn;
/* 0x240*/
	u64 qpx_pd;
	u64 qpx_scqn;
	u64 qpx_rcqn;
	u64 qpx_aeqn;
/* 0x260*/
	u64 qpx_aaelog;
	u64 qpx_ram;
	u64 qpx_rdmaqe0;
	u64 qpx_rdmaqe1;
/* 0x280*/
	u64 qpx_rdmaqe2;
	u64 qpx_rdmaqe3;
	u64 qpx_nrpsnhwm;
/* 0x298*/
	u64 reserved[(0x400 - 0x298) / 8];
/* 0x400 extended data */
	u64 reserved_ext[(0x500 - 0x400) / 8];
/* 0x500 */
	u64 reserved2[(0x1000 - 0x500) / 8];
/* 0x1000      */
};

#define QPX_SQADDER EHCA_BMASK_IBM(48,63)
#define QPX_RQADDER EHCA_BMASK_IBM(48,63)

#define QPTEMM_OFFSET(x) offsetof(struct hipz_qptemm,x)

/* MRMWPT Entry Memory Map */
struct hipz_mrmwmm {
	/* 0x00 */
	u64 mrx_hcr;

	u64 mrx_c;
	u64 mrx_herr;
	u64 mrx_aer;
	/* 0x20 */
	u64 mrx_pp;
	u64 reserved1;
	u64 reserved2;
	u64 reserved3;
	/* 0x40 */
	u64 reserved4[(0x200 - 0x40) / 8];
	/* 0x200 */
	u64 mrx_ctl[64];

};

#define MRMWMM_OFFSET(x) offsetof(struct hipz_mrmwmm,x)

struct hipz_qpedmm {
	/* 0x00 */
	u64 reserved0[(0x400) / 8];
	/* 0x400 */
	u64 qpedx_phh;
	u64 qpedx_ppsgp;
	/* 0x410 */
	u64 qpedx_ppsgu;
	u64 qpedx_ppdgp;
	/* 0x420 */
	u64 qpedx_ppdgu;
	u64 qpedx_aph;
	/* 0x430 */
	u64 qpedx_apsgp;
	u64 qpedx_apsgu;
	/* 0x440 */
	u64 qpedx_apdgp;
	u64 qpedx_apdgu;
	/* 0x450 */
	u64 qpedx_apav;
	u64 qpedx_apsav;
	/* 0x460  */
	u64 qpedx_hcr;
	u64 reserved1[4];
	/* 0x488 */
	u64 qpedx_rrl0;
	/* 0x490 */
	u64 qpedx_rrrkey0;
	u64 qpedx_rrva0;
	/* 0x4a0 */
	u64 reserved2;
	u64 qpedx_rrl1;
	/* 0x4b0 */
	u64 qpedx_rrrkey1;
	u64 qpedx_rrva1;
	/* 0x4c0 */
	u64 reserved3;
	u64 qpedx_rrl2;
	/* 0x4d0 */
	u64 qpedx_rrrkey2;
	u64 qpedx_rrva2;
	/* 0x4e0 */
	u64 reserved4;
	u64 qpedx_rrl3;
	/* 0x4f0 */
	u64 qpedx_rrrkey3;
	u64 qpedx_rrva3;
};

#define QPEDMM_OFFSET(x) offsetof(struct hipz_qpedmm,x)

/* CQ Table Entry Memory Map */
struct hipz_cqtemm {
	u64 cqx_hcr;
	u64 cqx_c;
	u64 cqx_herr;
	u64 cqx_aer;
/* 0x20  */
	u64 cqx_ptp;
	u64 cqx_tp;
	u64 cqx_fec;
	u64 cqx_feca;
/* 0x40  */
	u64 cqx_ep;
	u64 cqx_eq;
/* 0x50  */
	u64 reserved1;
	u64 cqx_n0;
/* 0x60  */
	u64 cqx_n1;
	u64 reserved2[(0x1000 - 0x60) / 8];
/* 0x1000 */
};

#define CQX_FEC_CQE_CNT           EHCA_BMASK_IBM(32,63)
#define CQX_FECADDER              EHCA_BMASK_IBM(32,63)
#define CQX_N0_GENERATE_SOLICITED_COMP_EVENT EHCA_BMASK_IBM(0,0)
#define CQX_N1_GENERATE_COMP_EVENT EHCA_BMASK_IBM(0,0)

#define CQTEMM_OFFSET(x) offsetof(struct hipz_cqtemm,x)

/* EQ Table Entry Memory Map */
struct hipz_eqtemm {
	u64 eqx_hcr;
	u64 eqx_c;

	u64 eqx_herr;
	u64 eqx_aer;
/* 0x20 */
	u64 eqx_ptp;
	u64 eqx_tp;
	u64 eqx_ssba;
	u64 eqx_psba;

/* 0x40 */
	u64 eqx_cec;
	u64 eqx_meql;
	u64 eqx_xisbi;
	u64 eqx_xisc;
/* 0x60 */
	u64 eqx_it;

};

#define EQTEMM_OFFSET(x) offsetof(struct hipz_eqtemm,x)

/* access control defines for MR/MW */
#define HIPZ_ACCESSCTRL_L_WRITE  0x00800000
#define HIPZ_ACCESSCTRL_R_WRITE  0x00400000
#define HIPZ_ACCESSCTRL_R_READ   0x00200000
#define HIPZ_ACCESSCTRL_R_ATOMIC 0x00100000
#define HIPZ_ACCESSCTRL_MW_BIND  0x00080000

/* query hca response block */
struct hipz_query_hca {
	u32 cur_reliable_dg;
	u32 cur_qp;
	u32 cur_cq;
	u32 cur_eq;
	u32 cur_mr;
	u32 cur_mw;
	u32 cur_ee_context;
	u32 cur_mcast_grp;
	u32 cur_qp_attached_mcast_grp;
	u32 reserved1;
	u32 cur_ipv6_qp;
	u32 cur_eth_qp;
	u32 cur_hp_mr;
	u32 reserved2[3];
	u32 max_rd_domain;
	u32 max_qp;
	u32 max_cq;
	u32 max_eq;
	u32 max_mr;
	u32 max_hp_mr;
	u32 max_mw;
	u32 max_mrwpte;
	u32 max_special_mrwpte;
	u32 max_rd_ee_context;
	u32 max_mcast_grp;
	u32 max_total_mcast_qp_attach;
	u32 max_mcast_qp_attach;
	u32 max_raw_ipv6_qp;
	u32 max_raw_ethy_qp;
	u32 internal_clock_frequency;
	u32 max_pd;
	u32 max_ah;
	u32 max_cqe;
	u32 max_wqes_wq;
	u32 max_partitions;
	u32 max_rr_ee_context;
	u32 max_rr_qp;
	u32 max_rr_hca;
	u32 max_act_wqs_ee_context;
	u32 max_act_wqs_qp;
	u32 max_sge;
	u32 max_sge_rd;
	u32 memory_page_size_supported;
	u64 max_mr_size;
	u32 local_ca_ack_delay;
	u32 num_ports;
	u32 vendor_id;
	u32 vendor_part_id;
	u32 hw_ver;
	u64 node_guid;
	u64 hca_cap_indicators;
	u32 data_counter_register_size;
	u32 max_shared_rq;
	u32 max_isns_eq;
	u32 max_neq;
} __attribute__ ((packed));

/* query port response block */
struct hipz_query_port {
	u32 state;
	u32 bad_pkey_cntr;
	u32 lmc;
	u32 lid;
	u32 subnet_timeout;
	u32 qkey_viol_cntr;
	u32 sm_sl;
	u32 sm_lid;
	u32 capability_mask;
	u32 init_type_reply;
	u32 pkey_tbl_len;
	u32 gid_tbl_len;
	u64 gid_prefix;
	u32 port_nr;
	u16 pkey_entries[16];
	u8  reserved1[32];
	u32 trent_size;
	u32 trbuf_size;
	u64 max_msg_sz;
	u32 max_mtu;
	u32 vl_cap;
	u8  reserved2[1900];
	u64 guid_entries[255];
} __attribute__ ((packed));

#endif
Commit	Line	Data
fab97220 HS	1	/*
	2	* IBM eServer eHCA Infiniband device driver for Linux on POWER
	3	*
	4	* eHCA register definitions
	5	*
	6	* Authors: Waleri Fomin <fomin@de.ibm.com>
	7	* Christoph Raisch <raisch@de.ibm.com>
	8	* Reinhard Ernst <rernst@de.ibm.com>
	9	*
	10	* Copyright (c) 2005 IBM Corporation
	11	*
	12	* All rights reserved.
	13	*
	14	* This source code is distributed under a dual license of GPL v2.0 and OpenIB
	15	* BSD.
	16	*
	17	* OpenIB BSD License
	18	*
	19	* Redistribution and use in source and binary forms, with or without
	20	* modification, are permitted provided that the following conditions are met:
	21	*
	22	* Redistributions of source code must retain the above copyright notice, this
	23	* list of conditions and the following disclaimer.
	24	*
	25	* Redistributions in binary form must reproduce the above copyright notice,
	26	* this list of conditions and the following disclaimer in the documentation
	27	* and/or other materials
	28	* provided with the distribution.
	29	*
	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	33	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
	34	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	35	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	36	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	37	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
	38	* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	39	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	40	* POSSIBILITY OF SUCH DAMAGE.
	41	*/
	42
	43	#ifndef __HIPZ_HW_H__
	44	#define __HIPZ_HW_H__
	45
	46	#include "ehca_tools.h"
	47
	48	/* QP Table Entry Memory Map */
	49	struct hipz_qptemm {
	50	u64 qpx_hcr;
	51	u64 qpx_c;
	52	u64 qpx_herr;
	53	u64 qpx_aer;
	54	/* 0x20*/
	55	u64 qpx_sqa;
	56	u64 qpx_sqc;
	57	u64 qpx_rqa;
	58	u64 qpx_rqc;
	59	/* 0x40*/
	60	u64 qpx_st;
	61	u64 qpx_pmstate;
	62	u64 qpx_pmfa;
	63	u64 qpx_pkey;
	64	/* 0x60*/
65	u64 qpx_pkeya;
66	u64 qpx_pkeyb;
67	u64 qpx_pkeyc;
68	u64 qpx_pkeyd;
69	/* 0x80*/
70	u64 qpx_qkey;
71	u64 qpx_dqp;
72	u64 qpx_dlidp;
73	u64 qpx_portp;
74	/* 0xa0*/
75	u64 qpx_slidp;
76	u64 qpx_slidpp;
77	u64 qpx_dlida;
78	u64 qpx_porta;
79	/* 0xc0*/
80	u64 qpx_slida;
81	u64 qpx_slidpa;
82	u64 qpx_slvl;
83	u64 qpx_ipd;
84	/* 0xe0*/
85	u64 qpx_mtu;
86	u64 qpx_lato;
87	u64 qpx_rlimit;
88	u64 qpx_rnrlimit;
89	/* 0x100*/
90	u64 qpx_t;
91	u64 qpx_sqhp;
92	u64 qpx_sqptp;
93	u64 qpx_nspsn;
94	/* 0x120*/
95	u64 qpx_nspsnhwm;
96	u64 reserved1;
97	u64 qpx_sdsi;
98	u64 qpx_sdsbc;
99	/* 0x140*/
100	u64 qpx_sqwsize;
101	u64 qpx_sqwts;
102	u64 qpx_lsn;
103	u64 qpx_nssn;
104	/* 0x160 */
105	u64 qpx_mor;
106	u64 qpx_cor;
107	u64 qpx_sqsize;
108	u64 qpx_erc;
109	/* 0x180*/
110	u64 qpx_rnrrc;
111	u64 qpx_ernrwt;
112	u64 qpx_rnrresp;
113	u64 qpx_lmsna;
114	/* 0x1a0 */
115	u64 qpx_sqhpc;
116	u64 qpx_sqcptp;
117	u64 qpx_sigt;
118	u64 qpx_wqecnt;
119	/* 0x1c0*/
120	u64 qpx_rqhp;
121	u64 qpx_rqptp;
122	u64 qpx_rqsize;
123	u64 qpx_nrr;
124	/* 0x1e0*/
125	u64 qpx_rdmac;
126	u64 qpx_nrpsn;
127	u64 qpx_lapsn;
128	u64 qpx_lcr;
129	/* 0x200*/
130	u64 qpx_rwc;
131	u64 qpx_rwva;
132	u64 qpx_rdsi;
133	u64 qpx_rdsbc;
134	/* 0x220*/
135	u64 qpx_rqwsize;
136	u64 qpx_crmsn;
137	u64 qpx_rdd;
138	u64 qpx_larpsn;
139	/* 0x240*/
140	u64 qpx_pd;
141	u64 qpx_scqn;
142	u64 qpx_rcqn;
143	u64 qpx_aeqn;
144	/* 0x260*/
145	u64 qpx_aaelog;
146	u64 qpx_ram;
147	u64 qpx_rdmaqe0;
148	u64 qpx_rdmaqe1;
149	/* 0x280*/
150	u64 qpx_rdmaqe2;
151	u64 qpx_rdmaqe3;
152	u64 qpx_nrpsnhwm;
153	/* 0x298*/
154	u64 reserved[(0x400 - 0x298) / 8];
155	/* 0x400 extended data */
156	u64 reserved_ext[(0x500 - 0x400) / 8];
157	/* 0x500 */
158	u64 reserved2[(0x1000 - 0x500) / 8];
159	/* 0x1000 */
160	};
161
162	#define QPX_SQADDER EHCA_BMASK_IBM(48,63)
163	#define QPX_RQADDER EHCA_BMASK_IBM(48,63)
164
165	#define QPTEMM_OFFSET(x) offsetof(struct hipz_qptemm,x)
166
167	/* MRMWPT Entry Memory Map */
168	struct hipz_mrmwmm {
169	/* 0x00 */
170	u64 mrx_hcr;
171
172	u64 mrx_c;
173	u64 mrx_herr;
174	u64 mrx_aer;
175	/* 0x20 */
176	u64 mrx_pp;
177	u64 reserved1;
178	u64 reserved2;
179	u64 reserved3;
180	/* 0x40 */
181	u64 reserved4[(0x200 - 0x40) / 8];
182	/* 0x200 */
183	u64 mrx_ctl[64];
184
185	};
186
187	#define MRMWMM_OFFSET(x) offsetof(struct hipz_mrmwmm,x)
188
189	struct hipz_qpedmm {
190	/* 0x00 */
191	u64 reserved0[(0x400) / 8];
192	/* 0x400 */
193	u64 qpedx_phh;
194	u64 qpedx_ppsgp;
195	/* 0x410 */
196	u64 qpedx_ppsgu;
197	u64 qpedx_ppdgp;
198	/* 0x420 */
199	u64 qpedx_ppdgu;
200	u64 qpedx_aph;
201	/* 0x430 */
202	u64 qpedx_apsgp;
203	u64 qpedx_apsgu;
204	/* 0x440 */
205	u64 qpedx_apdgp;
206	u64 qpedx_apdgu;
207	/* 0x450 */
208	u64 qpedx_apav;
209	u64 qpedx_apsav;
210	/* 0x460 */
211	u64 qpedx_hcr;
212	u64 reserved1[4];
213	/* 0x488 */
214	u64 qpedx_rrl0;
215	/* 0x490 */
216	u64 qpedx_rrrkey0;
217	u64 qpedx_rrva0;
218	/* 0x4a0 */
219	u64 reserved2;
220	u64 qpedx_rrl1;
221	/* 0x4b0 */
222	u64 qpedx_rrrkey1;
223	u64 qpedx_rrva1;
224	/* 0x4c0 */
225	u64 reserved3;
226	u64 qpedx_rrl2;
227	/* 0x4d0 */
228	u64 qpedx_rrrkey2;
229	u64 qpedx_rrva2;
230	/* 0x4e0 */
231	u64 reserved4;
232	u64 qpedx_rrl3;
233	/* 0x4f0 */
234	u64 qpedx_rrrkey3;
235	u64 qpedx_rrva3;
236	};
237
238	#define QPEDMM_OFFSET(x) offsetof(struct hipz_qpedmm,x)
239
240	/* CQ Table Entry Memory Map */
241	struct hipz_cqtemm {
242	u64 cqx_hcr;
243	u64 cqx_c;
244	u64 cqx_herr;
245	u64 cqx_aer;
246	/* 0x20 */
247	u64 cqx_ptp;
248	u64 cqx_tp;
249	u64 cqx_fec;
250	u64 cqx_feca;
251	/* 0x40 */
252	u64 cqx_ep;
253	u64 cqx_eq;
254	/* 0x50 */
255	u64 reserved1;
256	u64 cqx_n0;
257	/* 0x60 */
258	u64 cqx_n1;
259	u64 reserved2[(0x1000 - 0x60) / 8];
260	/* 0x1000 */
261	};
262
263	#define CQX_FEC_CQE_CNT EHCA_BMASK_IBM(32,63)
264	#define CQX_FECADDER EHCA_BMASK_IBM(32,63)
265	#define CQX_N0_GENERATE_SOLICITED_COMP_EVENT EHCA_BMASK_IBM(0,0)
266	#define CQX_N1_GENERATE_COMP_EVENT EHCA_BMASK_IBM(0,0)
267
268	#define CQTEMM_OFFSET(x) offsetof(struct hipz_cqtemm,x)
269
270	/* EQ Table Entry Memory Map */
271	struct hipz_eqtemm {
272	u64 eqx_hcr;
273	u64 eqx_c;
274
275	u64 eqx_herr;
276	u64 eqx_aer;
277	/* 0x20 */
278	u64 eqx_ptp;
279	u64 eqx_tp;
280	u64 eqx_ssba;
281	u64 eqx_psba;
282
283	/* 0x40 */
284	u64 eqx_cec;
285	u64 eqx_meql;
286	u64 eqx_xisbi;
287	u64 eqx_xisc;
288	/* 0x60 */
289	u64 eqx_it;
290
291	};
292
293	#define EQTEMM_OFFSET(x) offsetof(struct hipz_eqtemm,x)
294
295	/* access control defines for MR/MW */
296	#define HIPZ_ACCESSCTRL_L_WRITE 0x00800000
297	#define HIPZ_ACCESSCTRL_R_WRITE 0x00400000
298	#define HIPZ_ACCESSCTRL_R_READ 0x00200000
299	#define HIPZ_ACCESSCTRL_R_ATOMIC 0x00100000
300	#define HIPZ_ACCESSCTRL_MW_BIND 0x00080000
301
302	/* query hca response block */
303	struct hipz_query_hca {
304	u32 cur_reliable_dg;
305	u32 cur_qp;
306	u32 cur_cq;
307	u32 cur_eq;
308	u32 cur_mr;
309	u32 cur_mw;
310	u32 cur_ee_context;
311	u32 cur_mcast_grp;
312	u32 cur_qp_attached_mcast_grp;
313	u32 reserved1;
314	u32 cur_ipv6_qp;
315	u32 cur_eth_qp;
316	u32 cur_hp_mr;
317	u32 reserved2[3];
318	u32 max_rd_domain;
319	u32 max_qp;
320	u32 max_cq;
321	u32 max_eq;
322	u32 max_mr;
323	u32 max_hp_mr;
324	u32 max_mw;
325	u32 max_mrwpte;
326	u32 max_special_mrwpte;
327	u32 max_rd_ee_context;
328	u32 max_mcast_grp;
329	u32 max_total_mcast_qp_attach;
330	u32 max_mcast_qp_attach;
331	u32 max_raw_ipv6_qp;
332	u32 max_raw_ethy_qp;
333	u32 internal_clock_frequency;
334	u32 max_pd;
335	u32 max_ah;
336	u32 max_cqe;
337	u32 max_wqes_wq;
338	u32 max_partitions;
339	u32 max_rr_ee_context;
340	u32 max_rr_qp;
341	u32 max_rr_hca;
342	u32 max_act_wqs_ee_context;
343	u32 max_act_wqs_qp;
344	u32 max_sge;
345	u32 max_sge_rd;
346	u32 memory_page_size_supported;
347	u64 max_mr_size;
348	u32 local_ca_ack_delay;
349	u32 num_ports;
350	u32 vendor_id;
351	u32 vendor_part_id;
352	u32 hw_ver;
353	u64 node_guid;
354	u64 hca_cap_indicators;
355	u32 data_counter_register_size;
356	u32 max_shared_rq;
357	u32 max_isns_eq;
358	u32 max_neq;
359	} __attribute__ ((packed));
360
361	/* query port response block */
362	struct hipz_query_port {
363	u32 state;
364	u32 bad_pkey_cntr;
365	u32 lmc;
366	u32 lid;
367	u32 subnet_timeout;
368	u32 qkey_viol_cntr;
369	u32 sm_sl;
370	u32 sm_lid;
371	u32 capability_mask;
372	u32 init_type_reply;
373	u32 pkey_tbl_len;
374	u32 gid_tbl_len;
375	u64 gid_prefix;
376	u32 port_nr;
377	u16 pkey_entries[16];
378	u8 reserved1[32];
379	u32 trent_size;
380	u32 trbuf_size;
381	u64 max_msg_sz;
382	u32 max_mtu;
383	u32 vl_cap;
384	u8 reserved2[1900];
385	u64 guid_entries[255];
386	} __attribute__ ((packed));
387
388	#endif