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fab97220 HS |
1 | /* |
2 | * IBM eServer eHCA Infiniband device driver for Linux on POWER | |
3 | * | |
4 | * QP functions | |
5 | * | |
6 | * Authors: Waleri Fomin <fomin@de.ibm.com> | |
7 | * Hoang-Nam Nguyen <hnguyen@de.ibm.com> | |
8 | * Reinhard Ernst <rernst@de.ibm.com> | |
9 | * Heiko J Schick <schickhj@de.ibm.com> | |
10 | * | |
11 | * Copyright (c) 2005 IBM Corporation | |
12 | * | |
13 | * All rights reserved. | |
14 | * | |
15 | * This source code is distributed under a dual license of GPL v2.0 and OpenIB | |
16 | * BSD. | |
17 | * | |
18 | * OpenIB BSD License | |
19 | * | |
20 | * Redistribution and use in source and binary forms, with or without | |
21 | * modification, are permitted provided that the following conditions are met: | |
22 | * | |
23 | * Redistributions of source code must retain the above copyright notice, this | |
24 | * list of conditions and the following disclaimer. | |
25 | * | |
26 | * Redistributions in binary form must reproduce the above copyright notice, | |
27 | * this list of conditions and the following disclaimer in the documentation | |
28 | * and/or other materials | |
29 | * provided with the distribution. | |
30 | * | |
31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
32 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
33 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
34 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
35 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
36 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
37 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | |
38 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER | |
39 | * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
40 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
41 | * POSSIBILITY OF SUCH DAMAGE. | |
42 | */ | |
43 | ||
44 | ||
45 | #include <asm/current.h> | |
46 | ||
47 | #include "ehca_classes.h" | |
48 | #include "ehca_tools.h" | |
49 | #include "ehca_qes.h" | |
50 | #include "ehca_iverbs.h" | |
51 | #include "hcp_if.h" | |
52 | #include "hipz_fns.h" | |
53 | ||
54 | static struct kmem_cache *qp_cache; | |
55 | ||
56 | /* | |
57 | * attributes not supported by query qp | |
58 | */ | |
59 | #define QP_ATTR_QUERY_NOT_SUPPORTED (IB_QP_MAX_DEST_RD_ATOMIC | \ | |
60 | IB_QP_MAX_QP_RD_ATOMIC | \ | |
61 | IB_QP_ACCESS_FLAGS | \ | |
62 | IB_QP_EN_SQD_ASYNC_NOTIFY) | |
63 | ||
64 | /* | |
65 | * ehca (internal) qp state values | |
66 | */ | |
67 | enum ehca_qp_state { | |
68 | EHCA_QPS_RESET = 1, | |
69 | EHCA_QPS_INIT = 2, | |
70 | EHCA_QPS_RTR = 3, | |
71 | EHCA_QPS_RTS = 5, | |
72 | EHCA_QPS_SQD = 6, | |
73 | EHCA_QPS_SQE = 8, | |
74 | EHCA_QPS_ERR = 128 | |
75 | }; | |
76 | ||
77 | /* | |
78 | * qp state transitions as defined by IB Arch Rel 1.1 page 431 | |
79 | */ | |
80 | enum ib_qp_statetrans { | |
81 | IB_QPST_ANY2RESET, | |
82 | IB_QPST_ANY2ERR, | |
83 | IB_QPST_RESET2INIT, | |
84 | IB_QPST_INIT2RTR, | |
85 | IB_QPST_INIT2INIT, | |
86 | IB_QPST_RTR2RTS, | |
87 | IB_QPST_RTS2SQD, | |
88 | IB_QPST_RTS2RTS, | |
89 | IB_QPST_SQD2RTS, | |
90 | IB_QPST_SQE2RTS, | |
91 | IB_QPST_SQD2SQD, | |
92 | IB_QPST_MAX /* nr of transitions, this must be last!!! */ | |
93 | }; | |
94 | ||
95 | /* | |
96 | * ib2ehca_qp_state maps IB to ehca qp_state | |
97 | * returns ehca qp state corresponding to given ib qp state | |
98 | */ | |
99 | static inline enum ehca_qp_state ib2ehca_qp_state(enum ib_qp_state ib_qp_state) | |
100 | { | |
101 | switch (ib_qp_state) { | |
102 | case IB_QPS_RESET: | |
103 | return EHCA_QPS_RESET; | |
104 | case IB_QPS_INIT: | |
105 | return EHCA_QPS_INIT; | |
106 | case IB_QPS_RTR: | |
107 | return EHCA_QPS_RTR; | |
108 | case IB_QPS_RTS: | |
109 | return EHCA_QPS_RTS; | |
110 | case IB_QPS_SQD: | |
111 | return EHCA_QPS_SQD; | |
112 | case IB_QPS_SQE: | |
113 | return EHCA_QPS_SQE; | |
114 | case IB_QPS_ERR: | |
115 | return EHCA_QPS_ERR; | |
116 | default: | |
117 | ehca_gen_err("invalid ib_qp_state=%x", ib_qp_state); | |
118 | return -EINVAL; | |
119 | } | |
120 | } | |
121 | ||
122 | /* | |
123 | * ehca2ib_qp_state maps ehca to IB qp_state | |
124 | * returns ib qp state corresponding to given ehca qp state | |
125 | */ | |
126 | static inline enum ib_qp_state ehca2ib_qp_state(enum ehca_qp_state | |
127 | ehca_qp_state) | |
128 | { | |
129 | switch (ehca_qp_state) { | |
130 | case EHCA_QPS_RESET: | |
131 | return IB_QPS_RESET; | |
132 | case EHCA_QPS_INIT: | |
133 | return IB_QPS_INIT; | |
134 | case EHCA_QPS_RTR: | |
135 | return IB_QPS_RTR; | |
136 | case EHCA_QPS_RTS: | |
137 | return IB_QPS_RTS; | |
138 | case EHCA_QPS_SQD: | |
139 | return IB_QPS_SQD; | |
140 | case EHCA_QPS_SQE: | |
141 | return IB_QPS_SQE; | |
142 | case EHCA_QPS_ERR: | |
143 | return IB_QPS_ERR; | |
144 | default: | |
145 | ehca_gen_err("invalid ehca_qp_state=%x", ehca_qp_state); | |
146 | return -EINVAL; | |
147 | } | |
148 | } | |
149 | ||
150 | /* | |
151 | * ehca_qp_type used as index for req_attr and opt_attr of | |
152 | * struct ehca_modqp_statetrans | |
153 | */ | |
154 | enum ehca_qp_type { | |
155 | QPT_RC = 0, | |
156 | QPT_UC = 1, | |
157 | QPT_UD = 2, | |
158 | QPT_SQP = 3, | |
159 | QPT_MAX | |
160 | }; | |
161 | ||
162 | /* | |
163 | * ib2ehcaqptype maps Ib to ehca qp_type | |
164 | * returns ehca qp type corresponding to ib qp type | |
165 | */ | |
166 | static inline enum ehca_qp_type ib2ehcaqptype(enum ib_qp_type ibqptype) | |
167 | { | |
168 | switch (ibqptype) { | |
169 | case IB_QPT_SMI: | |
170 | case IB_QPT_GSI: | |
171 | return QPT_SQP; | |
172 | case IB_QPT_RC: | |
173 | return QPT_RC; | |
174 | case IB_QPT_UC: | |
175 | return QPT_UC; | |
176 | case IB_QPT_UD: | |
177 | return QPT_UD; | |
178 | default: | |
179 | ehca_gen_err("Invalid ibqptype=%x", ibqptype); | |
180 | return -EINVAL; | |
181 | } | |
182 | } | |
183 | ||
184 | static inline enum ib_qp_statetrans get_modqp_statetrans(int ib_fromstate, | |
185 | int ib_tostate) | |
186 | { | |
187 | int index = -EINVAL; | |
188 | switch (ib_tostate) { | |
189 | case IB_QPS_RESET: | |
190 | index = IB_QPST_ANY2RESET; | |
191 | break; | |
192 | case IB_QPS_INIT: | |
193 | switch (ib_fromstate) { | |
194 | case IB_QPS_RESET: | |
195 | index = IB_QPST_RESET2INIT; | |
196 | break; | |
197 | case IB_QPS_INIT: | |
198 | index = IB_QPST_INIT2INIT; | |
199 | break; | |
200 | } | |
201 | break; | |
202 | case IB_QPS_RTR: | |
203 | if (ib_fromstate == IB_QPS_INIT) | |
204 | index = IB_QPST_INIT2RTR; | |
205 | break; | |
206 | case IB_QPS_RTS: | |
207 | switch (ib_fromstate) { | |
208 | case IB_QPS_RTR: | |
209 | index = IB_QPST_RTR2RTS; | |
210 | break; | |
211 | case IB_QPS_RTS: | |
212 | index = IB_QPST_RTS2RTS; | |
213 | break; | |
214 | case IB_QPS_SQD: | |
215 | index = IB_QPST_SQD2RTS; | |
216 | break; | |
217 | case IB_QPS_SQE: | |
218 | index = IB_QPST_SQE2RTS; | |
219 | break; | |
220 | } | |
221 | break; | |
222 | case IB_QPS_SQD: | |
223 | if (ib_fromstate == IB_QPS_RTS) | |
224 | index = IB_QPST_RTS2SQD; | |
225 | break; | |
226 | case IB_QPS_SQE: | |
227 | break; | |
228 | case IB_QPS_ERR: | |
229 | index = IB_QPST_ANY2ERR; | |
230 | break; | |
231 | default: | |
232 | break; | |
233 | } | |
234 | return index; | |
235 | } | |
236 | ||
237 | enum ehca_service_type { | |
238 | ST_RC = 0, | |
239 | ST_UC = 1, | |
240 | ST_RD = 2, | |
241 | ST_UD = 3 | |
242 | }; | |
243 | ||
244 | /* | |
245 | * ibqptype2servicetype returns hcp service type corresponding to given | |
246 | * ib qp type used by create_qp() | |
247 | */ | |
248 | static inline int ibqptype2servicetype(enum ib_qp_type ibqptype) | |
249 | { | |
250 | switch (ibqptype) { | |
251 | case IB_QPT_SMI: | |
252 | case IB_QPT_GSI: | |
253 | return ST_UD; | |
254 | case IB_QPT_RC: | |
255 | return ST_RC; | |
256 | case IB_QPT_UC: | |
257 | return ST_UC; | |
258 | case IB_QPT_UD: | |
259 | return ST_UD; | |
260 | case IB_QPT_RAW_IPV6: | |
261 | return -EINVAL; | |
262 | case IB_QPT_RAW_ETY: | |
263 | return -EINVAL; | |
264 | default: | |
265 | ehca_gen_err("Invalid ibqptype=%x", ibqptype); | |
266 | return -EINVAL; | |
267 | } | |
268 | } | |
269 | ||
270 | /* | |
271 | * init_qp_queues initializes/constructs r/squeue and registers queue pages. | |
272 | */ | |
273 | static inline int init_qp_queues(struct ehca_shca *shca, | |
274 | struct ehca_qp *my_qp, | |
275 | int nr_sq_pages, | |
276 | int nr_rq_pages, | |
277 | int swqe_size, | |
278 | int rwqe_size, | |
279 | int nr_send_sges, int nr_receive_sges) | |
280 | { | |
281 | int ret, cnt, ipz_rc; | |
282 | void *vpage; | |
283 | u64 rpage, h_ret; | |
284 | struct ib_device *ib_dev = &shca->ib_device; | |
285 | struct ipz_adapter_handle ipz_hca_handle = shca->ipz_hca_handle; | |
286 | ||
287 | ipz_rc = ipz_queue_ctor(&my_qp->ipz_squeue, | |
288 | nr_sq_pages, | |
289 | EHCA_PAGESIZE, swqe_size, nr_send_sges); | |
290 | if (!ipz_rc) { | |
291 | ehca_err(ib_dev,"Cannot allocate page for squeue. ipz_rc=%x", | |
292 | ipz_rc); | |
293 | return -EBUSY; | |
294 | } | |
295 | ||
296 | ipz_rc = ipz_queue_ctor(&my_qp->ipz_rqueue, | |
297 | nr_rq_pages, | |
298 | EHCA_PAGESIZE, rwqe_size, nr_receive_sges); | |
299 | if (!ipz_rc) { | |
300 | ehca_err(ib_dev, "Cannot allocate page for rqueue. ipz_rc=%x", | |
301 | ipz_rc); | |
302 | ret = -EBUSY; | |
303 | goto init_qp_queues0; | |
304 | } | |
305 | /* register SQ pages */ | |
306 | for (cnt = 0; cnt < nr_sq_pages; cnt++) { | |
307 | vpage = ipz_qpageit_get_inc(&my_qp->ipz_squeue); | |
308 | if (!vpage) { | |
309 | ehca_err(ib_dev, "SQ ipz_qpageit_get_inc() " | |
310 | "failed p_vpage= %p", vpage); | |
311 | ret = -EINVAL; | |
312 | goto init_qp_queues1; | |
313 | } | |
314 | rpage = virt_to_abs(vpage); | |
315 | ||
316 | h_ret = hipz_h_register_rpage_qp(ipz_hca_handle, | |
317 | my_qp->ipz_qp_handle, | |
318 | &my_qp->pf, 0, 0, | |
319 | rpage, 1, | |
320 | my_qp->galpas.kernel); | |
321 | if (h_ret < H_SUCCESS) { | |
322 | ehca_err(ib_dev, "SQ hipz_qp_register_rpage()" | |
323 | " failed rc=%lx", h_ret); | |
324 | ret = ehca2ib_return_code(h_ret); | |
325 | goto init_qp_queues1; | |
326 | } | |
327 | } | |
328 | ||
329 | ipz_qeit_reset(&my_qp->ipz_squeue); | |
330 | ||
331 | /* register RQ pages */ | |
332 | for (cnt = 0; cnt < nr_rq_pages; cnt++) { | |
333 | vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue); | |
334 | if (!vpage) { | |
335 | ehca_err(ib_dev, "RQ ipz_qpageit_get_inc() " | |
336 | "failed p_vpage = %p", vpage); | |
337 | ret = -EINVAL; | |
338 | goto init_qp_queues1; | |
339 | } | |
340 | ||
341 | rpage = virt_to_abs(vpage); | |
342 | ||
343 | h_ret = hipz_h_register_rpage_qp(ipz_hca_handle, | |
344 | my_qp->ipz_qp_handle, | |
345 | &my_qp->pf, 0, 1, | |
346 | rpage, 1,my_qp->galpas.kernel); | |
347 | if (h_ret < H_SUCCESS) { | |
348 | ehca_err(ib_dev, "RQ hipz_qp_register_rpage() failed " | |
349 | "rc=%lx", h_ret); | |
350 | ret = ehca2ib_return_code(h_ret); | |
351 | goto init_qp_queues1; | |
352 | } | |
353 | if (cnt == (nr_rq_pages - 1)) { /* last page! */ | |
354 | if (h_ret != H_SUCCESS) { | |
355 | ehca_err(ib_dev, "RQ hipz_qp_register_rpage() " | |
356 | "h_ret= %lx ", h_ret); | |
357 | ret = ehca2ib_return_code(h_ret); | |
358 | goto init_qp_queues1; | |
359 | } | |
360 | vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue); | |
361 | if (vpage) { | |
362 | ehca_err(ib_dev, "ipz_qpageit_get_inc() " | |
363 | "should not succeed vpage=%p", vpage); | |
364 | ret = -EINVAL; | |
365 | goto init_qp_queues1; | |
366 | } | |
367 | } else { | |
368 | if (h_ret != H_PAGE_REGISTERED) { | |
369 | ehca_err(ib_dev, "RQ hipz_qp_register_rpage() " | |
370 | "h_ret= %lx ", h_ret); | |
371 | ret = ehca2ib_return_code(h_ret); | |
372 | goto init_qp_queues1; | |
373 | } | |
374 | } | |
375 | } | |
376 | ||
377 | ipz_qeit_reset(&my_qp->ipz_rqueue); | |
378 | ||
379 | return 0; | |
380 | ||
381 | init_qp_queues1: | |
382 | ipz_queue_dtor(&my_qp->ipz_rqueue); | |
383 | init_qp_queues0: | |
384 | ipz_queue_dtor(&my_qp->ipz_squeue); | |
385 | return ret; | |
386 | } | |
387 | ||
388 | struct ib_qp *ehca_create_qp(struct ib_pd *pd, | |
389 | struct ib_qp_init_attr *init_attr, | |
390 | struct ib_udata *udata) | |
391 | { | |
392 | static int da_rc_msg_size[]={ 128, 256, 512, 1024, 2048, 4096 }; | |
393 | static int da_ud_sq_msg_size[]={ 128, 384, 896, 1920, 3968 }; | |
394 | struct ehca_qp *my_qp; | |
395 | struct ehca_pd *my_pd = container_of(pd, struct ehca_pd, ib_pd); | |
396 | struct ehca_shca *shca = container_of(pd->device, struct ehca_shca, | |
397 | ib_device); | |
398 | struct ib_ucontext *context = NULL; | |
399 | u64 h_ret; | |
400 | int max_send_sge, max_recv_sge, ret; | |
401 | ||
402 | /* h_call's out parameters */ | |
403 | struct ehca_alloc_qp_parms parms; | |
404 | u32 swqe_size = 0, rwqe_size = 0; | |
405 | u8 daqp_completion, isdaqp; | |
406 | unsigned long flags; | |
407 | ||
408 | if (init_attr->sq_sig_type != IB_SIGNAL_REQ_WR && | |
409 | init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) { | |
410 | ehca_err(pd->device, "init_attr->sg_sig_type=%x not allowed", | |
411 | init_attr->sq_sig_type); | |
412 | return ERR_PTR(-EINVAL); | |
413 | } | |
414 | ||
415 | /* save daqp completion bits */ | |
416 | daqp_completion = init_attr->qp_type & 0x60; | |
417 | /* save daqp bit */ | |
418 | isdaqp = (init_attr->qp_type & 0x80) ? 1 : 0; | |
419 | init_attr->qp_type = init_attr->qp_type & 0x1F; | |
420 | ||
421 | if (init_attr->qp_type != IB_QPT_UD && | |
422 | init_attr->qp_type != IB_QPT_SMI && | |
423 | init_attr->qp_type != IB_QPT_GSI && | |
424 | init_attr->qp_type != IB_QPT_UC && | |
425 | init_attr->qp_type != IB_QPT_RC) { | |
426 | ehca_err(pd->device, "wrong QP Type=%x", init_attr->qp_type); | |
427 | return ERR_PTR(-EINVAL); | |
428 | } | |
429 | if ((init_attr->qp_type != IB_QPT_RC && init_attr->qp_type != IB_QPT_UD) | |
430 | && isdaqp) { | |
431 | ehca_err(pd->device, "unsupported LL QP Type=%x", | |
432 | init_attr->qp_type); | |
433 | return ERR_PTR(-EINVAL); | |
434 | } else if (init_attr->qp_type == IB_QPT_RC && isdaqp && | |
435 | (init_attr->cap.max_send_wr > 255 || | |
436 | init_attr->cap.max_recv_wr > 255 )) { | |
437 | ehca_err(pd->device, "Invalid Number of max_sq_wr =%x " | |
438 | "or max_rq_wr=%x for QP Type=%x", | |
439 | init_attr->cap.max_send_wr, | |
440 | init_attr->cap.max_recv_wr,init_attr->qp_type); | |
441 | return ERR_PTR(-EINVAL); | |
442 | } else if (init_attr->qp_type == IB_QPT_UD && isdaqp && | |
443 | init_attr->cap.max_send_wr > 255) { | |
444 | ehca_err(pd->device, | |
445 | "Invalid Number of max_send_wr=%x for UD QP_TYPE=%x", | |
446 | init_attr->cap.max_send_wr, init_attr->qp_type); | |
447 | return ERR_PTR(-EINVAL); | |
448 | } | |
449 | ||
450 | if (pd->uobject && udata) | |
451 | context = pd->uobject->context; | |
452 | ||
453 | my_qp = kmem_cache_alloc(qp_cache, SLAB_KERNEL); | |
454 | if (!my_qp) { | |
455 | ehca_err(pd->device, "pd=%p not enough memory to alloc qp", pd); | |
456 | return ERR_PTR(-ENOMEM); | |
457 | } | |
458 | ||
459 | memset(my_qp, 0, sizeof(struct ehca_qp)); | |
460 | memset (&parms, 0, sizeof(struct ehca_alloc_qp_parms)); | |
461 | spin_lock_init(&my_qp->spinlock_s); | |
462 | spin_lock_init(&my_qp->spinlock_r); | |
463 | ||
464 | my_qp->recv_cq = | |
465 | container_of(init_attr->recv_cq, struct ehca_cq, ib_cq); | |
466 | my_qp->send_cq = | |
467 | container_of(init_attr->send_cq, struct ehca_cq, ib_cq); | |
468 | ||
469 | my_qp->init_attr = *init_attr; | |
470 | ||
471 | do { | |
472 | if (!idr_pre_get(&ehca_qp_idr, GFP_KERNEL)) { | |
473 | ret = -ENOMEM; | |
474 | ehca_err(pd->device, "Can't reserve idr resources."); | |
475 | goto create_qp_exit0; | |
476 | } | |
477 | ||
478 | spin_lock_irqsave(&ehca_qp_idr_lock, flags); | |
479 | ret = idr_get_new(&ehca_qp_idr, my_qp, &my_qp->token); | |
480 | spin_unlock_irqrestore(&ehca_qp_idr_lock, flags); | |
481 | ||
482 | } while (ret == -EAGAIN); | |
483 | ||
484 | if (ret) { | |
485 | ret = -ENOMEM; | |
486 | ehca_err(pd->device, "Can't allocate new idr entry."); | |
487 | goto create_qp_exit0; | |
488 | } | |
489 | ||
490 | parms.servicetype = ibqptype2servicetype(init_attr->qp_type); | |
491 | if (parms.servicetype < 0) { | |
492 | ret = -EINVAL; | |
493 | ehca_err(pd->device, "Invalid qp_type=%x", init_attr->qp_type); | |
494 | goto create_qp_exit0; | |
495 | } | |
496 | ||
497 | if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) | |
498 | parms.sigtype = HCALL_SIGT_EVERY; | |
499 | else | |
500 | parms.sigtype = HCALL_SIGT_BY_WQE; | |
501 | ||
502 | /* UD_AV CIRCUMVENTION */ | |
503 | max_send_sge = init_attr->cap.max_send_sge; | |
504 | max_recv_sge = init_attr->cap.max_recv_sge; | |
505 | if (IB_QPT_UD == init_attr->qp_type || | |
506 | IB_QPT_GSI == init_attr->qp_type || | |
507 | IB_QPT_SMI == init_attr->qp_type) { | |
508 | max_send_sge += 2; | |
509 | max_recv_sge += 2; | |
510 | } | |
511 | ||
512 | parms.ipz_eq_handle = shca->eq.ipz_eq_handle; | |
513 | parms.daqp_ctrl = isdaqp | daqp_completion; | |
514 | parms.pd = my_pd->fw_pd; | |
515 | parms.max_recv_sge = max_recv_sge; | |
516 | parms.max_send_sge = max_send_sge; | |
517 | ||
518 | h_ret = hipz_h_alloc_resource_qp(shca->ipz_hca_handle, my_qp, &parms); | |
519 | ||
520 | if (h_ret != H_SUCCESS) { | |
521 | ehca_err(pd->device, "h_alloc_resource_qp() failed h_ret=%lx", | |
522 | h_ret); | |
523 | ret = ehca2ib_return_code(h_ret); | |
524 | goto create_qp_exit1; | |
525 | } | |
526 | ||
527 | switch (init_attr->qp_type) { | |
528 | case IB_QPT_RC: | |
529 | if (isdaqp == 0) { | |
530 | swqe_size = offsetof(struct ehca_wqe, u.nud.sg_list[ | |
531 | (parms.act_nr_send_sges)]); | |
532 | rwqe_size = offsetof(struct ehca_wqe, u.nud.sg_list[ | |
533 | (parms.act_nr_recv_sges)]); | |
534 | } else { /* for daqp we need to use msg size, not wqe size */ | |
535 | swqe_size = da_rc_msg_size[max_send_sge]; | |
536 | rwqe_size = da_rc_msg_size[max_recv_sge]; | |
537 | parms.act_nr_send_sges = 1; | |
538 | parms.act_nr_recv_sges = 1; | |
539 | } | |
540 | break; | |
541 | case IB_QPT_UC: | |
542 | swqe_size = offsetof(struct ehca_wqe, | |
543 | u.nud.sg_list[parms.act_nr_send_sges]); | |
544 | rwqe_size = offsetof(struct ehca_wqe, | |
545 | u.nud.sg_list[parms.act_nr_recv_sges]); | |
546 | break; | |
547 | ||
548 | case IB_QPT_UD: | |
549 | case IB_QPT_GSI: | |
550 | case IB_QPT_SMI: | |
551 | /* UD circumvention */ | |
552 | parms.act_nr_recv_sges -= 2; | |
553 | parms.act_nr_send_sges -= 2; | |
554 | if (isdaqp) { | |
555 | swqe_size = da_ud_sq_msg_size[max_send_sge]; | |
556 | rwqe_size = da_rc_msg_size[max_recv_sge]; | |
557 | parms.act_nr_send_sges = 1; | |
558 | parms.act_nr_recv_sges = 1; | |
559 | } else { | |
560 | swqe_size = offsetof(struct ehca_wqe, | |
561 | u.ud_av.sg_list[parms.act_nr_send_sges]); | |
562 | rwqe_size = offsetof(struct ehca_wqe, | |
563 | u.ud_av.sg_list[parms.act_nr_recv_sges]); | |
564 | } | |
565 | ||
566 | if (IB_QPT_GSI == init_attr->qp_type || | |
567 | IB_QPT_SMI == init_attr->qp_type) { | |
568 | parms.act_nr_send_wqes = init_attr->cap.max_send_wr; | |
569 | parms.act_nr_recv_wqes = init_attr->cap.max_recv_wr; | |
570 | parms.act_nr_send_sges = init_attr->cap.max_send_sge; | |
571 | parms.act_nr_recv_sges = init_attr->cap.max_recv_sge; | |
572 | my_qp->real_qp_num = | |
573 | (init_attr->qp_type == IB_QPT_SMI) ? 0 : 1; | |
574 | } | |
575 | ||
576 | break; | |
577 | ||
578 | default: | |
579 | break; | |
580 | } | |
581 | ||
582 | /* initializes r/squeue and registers queue pages */ | |
583 | ret = init_qp_queues(shca, my_qp, | |
584 | parms.nr_sq_pages, parms.nr_rq_pages, | |
585 | swqe_size, rwqe_size, | |
586 | parms.act_nr_send_sges, parms.act_nr_recv_sges); | |
587 | if (ret) { | |
588 | ehca_err(pd->device, | |
589 | "Couldn't initialize r/squeue and pages ret=%x", ret); | |
590 | goto create_qp_exit2; | |
591 | } | |
592 | ||
593 | my_qp->ib_qp.pd = &my_pd->ib_pd; | |
594 | my_qp->ib_qp.device = my_pd->ib_pd.device; | |
595 | ||
596 | my_qp->ib_qp.recv_cq = init_attr->recv_cq; | |
597 | my_qp->ib_qp.send_cq = init_attr->send_cq; | |
598 | ||
599 | my_qp->ib_qp.qp_num = my_qp->real_qp_num; | |
600 | my_qp->ib_qp.qp_type = init_attr->qp_type; | |
601 | ||
602 | my_qp->qp_type = init_attr->qp_type; | |
603 | my_qp->ib_qp.srq = init_attr->srq; | |
604 | ||
605 | my_qp->ib_qp.qp_context = init_attr->qp_context; | |
606 | my_qp->ib_qp.event_handler = init_attr->event_handler; | |
607 | ||
608 | init_attr->cap.max_inline_data = 0; /* not supported yet */ | |
609 | init_attr->cap.max_recv_sge = parms.act_nr_recv_sges; | |
610 | init_attr->cap.max_recv_wr = parms.act_nr_recv_wqes; | |
611 | init_attr->cap.max_send_sge = parms.act_nr_send_sges; | |
612 | init_attr->cap.max_send_wr = parms.act_nr_send_wqes; | |
613 | ||
614 | /* NOTE: define_apq0() not supported yet */ | |
615 | if (init_attr->qp_type == IB_QPT_GSI) { | |
616 | h_ret = ehca_define_sqp(shca, my_qp, init_attr); | |
617 | if (h_ret != H_SUCCESS) { | |
618 | ehca_err(pd->device, "ehca_define_sqp() failed rc=%lx", | |
619 | h_ret); | |
620 | ret = ehca2ib_return_code(h_ret); | |
621 | goto create_qp_exit3; | |
622 | } | |
623 | } | |
624 | if (init_attr->send_cq) { | |
625 | struct ehca_cq *cq = container_of(init_attr->send_cq, | |
626 | struct ehca_cq, ib_cq); | |
627 | ret = ehca_cq_assign_qp(cq, my_qp); | |
628 | if (ret) { | |
629 | ehca_err(pd->device, "Couldn't assign qp to send_cq ret=%x", | |
630 | ret); | |
631 | goto create_qp_exit3; | |
632 | } | |
633 | my_qp->send_cq = cq; | |
634 | } | |
635 | /* copy queues, galpa data to user space */ | |
636 | if (context && udata) { | |
637 | struct ipz_queue *ipz_rqueue = &my_qp->ipz_rqueue; | |
638 | struct ipz_queue *ipz_squeue = &my_qp->ipz_squeue; | |
639 | struct ehca_create_qp_resp resp; | |
640 | struct vm_area_struct * vma; | |
641 | memset(&resp, 0, sizeof(resp)); | |
642 | ||
643 | resp.qp_num = my_qp->real_qp_num; | |
644 | resp.token = my_qp->token; | |
645 | resp.qp_type = my_qp->qp_type; | |
646 | resp.qkey = my_qp->qkey; | |
647 | resp.real_qp_num = my_qp->real_qp_num; | |
648 | /* rqueue properties */ | |
649 | resp.ipz_rqueue.qe_size = ipz_rqueue->qe_size; | |
650 | resp.ipz_rqueue.act_nr_of_sg = ipz_rqueue->act_nr_of_sg; | |
651 | resp.ipz_rqueue.queue_length = ipz_rqueue->queue_length; | |
652 | resp.ipz_rqueue.pagesize = ipz_rqueue->pagesize; | |
653 | resp.ipz_rqueue.toggle_state = ipz_rqueue->toggle_state; | |
654 | ret = ehca_mmap_nopage(((u64)(my_qp->token) << 32) | 0x22000000, | |
655 | ipz_rqueue->queue_length, | |
656 | (void**)&resp.ipz_rqueue.queue, | |
657 | &vma); | |
658 | if (ret) { | |
659 | ehca_err(pd->device, "Could not mmap rqueue pages"); | |
660 | goto create_qp_exit3; | |
661 | } | |
662 | my_qp->uspace_rqueue = resp.ipz_rqueue.queue; | |
663 | /* squeue properties */ | |
664 | resp.ipz_squeue.qe_size = ipz_squeue->qe_size; | |
665 | resp.ipz_squeue.act_nr_of_sg = ipz_squeue->act_nr_of_sg; | |
666 | resp.ipz_squeue.queue_length = ipz_squeue->queue_length; | |
667 | resp.ipz_squeue.pagesize = ipz_squeue->pagesize; | |
668 | resp.ipz_squeue.toggle_state = ipz_squeue->toggle_state; | |
669 | ret = ehca_mmap_nopage(((u64)(my_qp->token) << 32) | 0x23000000, | |
670 | ipz_squeue->queue_length, | |
671 | (void**)&resp.ipz_squeue.queue, | |
672 | &vma); | |
673 | if (ret) { | |
674 | ehca_err(pd->device, "Could not mmap squeue pages"); | |
675 | goto create_qp_exit4; | |
676 | } | |
677 | my_qp->uspace_squeue = resp.ipz_squeue.queue; | |
678 | /* fw_handle */ | |
679 | resp.galpas = my_qp->galpas; | |
680 | ret = ehca_mmap_register(my_qp->galpas.user.fw_handle, | |
681 | (void**)&resp.galpas.kernel.fw_handle, | |
682 | &vma); | |
683 | if (ret) { | |
684 | ehca_err(pd->device, "Could not mmap fw_handle"); | |
685 | goto create_qp_exit5; | |
686 | } | |
687 | my_qp->uspace_fwh = (u64)resp.galpas.kernel.fw_handle; | |
688 | ||
689 | if (ib_copy_to_udata(udata, &resp, sizeof resp)) { | |
690 | ehca_err(pd->device, "Copy to udata failed"); | |
691 | ret = -EINVAL; | |
692 | goto create_qp_exit6; | |
693 | } | |
694 | } | |
695 | ||
696 | return &my_qp->ib_qp; | |
697 | ||
698 | create_qp_exit6: | |
699 | ehca_munmap(my_qp->uspace_fwh, EHCA_PAGESIZE); | |
700 | ||
701 | create_qp_exit5: | |
702 | ehca_munmap(my_qp->uspace_squeue, my_qp->ipz_squeue.queue_length); | |
703 | ||
704 | create_qp_exit4: | |
705 | ehca_munmap(my_qp->uspace_rqueue, my_qp->ipz_rqueue.queue_length); | |
706 | ||
707 | create_qp_exit3: | |
708 | ipz_queue_dtor(&my_qp->ipz_rqueue); | |
709 | ipz_queue_dtor(&my_qp->ipz_squeue); | |
710 | ||
711 | create_qp_exit2: | |
712 | hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp); | |
713 | ||
714 | create_qp_exit1: | |
715 | spin_lock_irqsave(&ehca_qp_idr_lock, flags); | |
716 | idr_remove(&ehca_qp_idr, my_qp->token); | |
717 | spin_unlock_irqrestore(&ehca_qp_idr_lock, flags); | |
718 | ||
719 | create_qp_exit0: | |
720 | kmem_cache_free(qp_cache, my_qp); | |
721 | return ERR_PTR(ret); | |
722 | } | |
723 | ||
724 | /* | |
725 | * prepare_sqe_rts called by internal_modify_qp() at trans sqe -> rts | |
726 | * set purge bit of bad wqe and subsequent wqes to avoid reentering sqe | |
727 | * returns total number of bad wqes in bad_wqe_cnt | |
728 | */ | |
729 | static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca, | |
730 | int *bad_wqe_cnt) | |
731 | { | |
732 | u64 h_ret; | |
733 | struct ipz_queue *squeue; | |
734 | void *bad_send_wqe_p, *bad_send_wqe_v; | |
735 | void *squeue_start_p, *squeue_end_p; | |
736 | void *squeue_start_v, *squeue_end_v; | |
737 | struct ehca_wqe *wqe; | |
738 | int qp_num = my_qp->ib_qp.qp_num; | |
739 | ||
740 | /* get send wqe pointer */ | |
741 | h_ret = hipz_h_disable_and_get_wqe(shca->ipz_hca_handle, | |
742 | my_qp->ipz_qp_handle, &my_qp->pf, | |
743 | &bad_send_wqe_p, NULL, 2); | |
744 | if (h_ret != H_SUCCESS) { | |
745 | ehca_err(&shca->ib_device, "hipz_h_disable_and_get_wqe() failed" | |
746 | " ehca_qp=%p qp_num=%x h_ret=%lx", | |
747 | my_qp, qp_num, h_ret); | |
748 | return ehca2ib_return_code(h_ret); | |
749 | } | |
750 | bad_send_wqe_p = (void*)((u64)bad_send_wqe_p & (~(1L<<63))); | |
751 | ehca_dbg(&shca->ib_device, "qp_num=%x bad_send_wqe_p=%p", | |
752 | qp_num, bad_send_wqe_p); | |
753 | /* convert wqe pointer to vadr */ | |
754 | bad_send_wqe_v = abs_to_virt((u64)bad_send_wqe_p); | |
755 | if (ehca_debug_level) | |
756 | ehca_dmp(bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num); | |
757 | squeue = &my_qp->ipz_squeue; | |
758 | squeue_start_p = (void*)virt_to_abs(ipz_qeit_calc(squeue, 0L)); | |
759 | squeue_end_p = squeue_start_p+squeue->queue_length; | |
760 | squeue_start_v = abs_to_virt((u64)squeue_start_p); | |
761 | squeue_end_v = abs_to_virt((u64)squeue_end_p); | |
762 | ehca_dbg(&shca->ib_device, "qp_num=%x squeue_start_v=%p squeue_end_v=%p", | |
763 | qp_num, squeue_start_v, squeue_end_v); | |
764 | ||
765 | /* loop sets wqe's purge bit */ | |
766 | wqe = (struct ehca_wqe*)bad_send_wqe_v; | |
767 | *bad_wqe_cnt = 0; | |
768 | while (wqe->optype != 0xff && wqe->wqef != 0xff) { | |
769 | if (ehca_debug_level) | |
770 | ehca_dmp(wqe, 32, "qp_num=%x wqe", qp_num); | |
771 | wqe->nr_of_data_seg = 0; /* suppress data access */ | |
772 | wqe->wqef = WQEF_PURGE; /* WQE to be purged */ | |
773 | wqe = (struct ehca_wqe*)((u8*)wqe+squeue->qe_size); | |
774 | *bad_wqe_cnt = (*bad_wqe_cnt)+1; | |
775 | if ((void*)wqe >= squeue_end_v) { | |
776 | wqe = squeue_start_v; | |
777 | } | |
778 | } | |
779 | /* | |
780 | * bad wqe will be reprocessed and ignored when pol_cq() is called, | |
781 | * i.e. nr of wqes with flush error status is one less | |
782 | */ | |
783 | ehca_dbg(&shca->ib_device, "qp_num=%x flusherr_wqe_cnt=%x", | |
784 | qp_num, (*bad_wqe_cnt)-1); | |
785 | wqe->wqef = 0; | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | /* | |
791 | * internal_modify_qp with circumvention to handle aqp0 properly | |
792 | * smi_reset2init indicates if this is an internal reset-to-init-call for | |
793 | * smi. This flag must always be zero if called from ehca_modify_qp()! | |
794 | * This internal func was intorduced to avoid recursion of ehca_modify_qp()! | |
795 | */ | |
796 | static int internal_modify_qp(struct ib_qp *ibqp, | |
797 | struct ib_qp_attr *attr, | |
798 | int attr_mask, int smi_reset2init) | |
799 | { | |
800 | enum ib_qp_state qp_cur_state, qp_new_state; | |
801 | int cnt, qp_attr_idx, ret = 0; | |
802 | enum ib_qp_statetrans statetrans; | |
803 | struct hcp_modify_qp_control_block *mqpcb; | |
804 | struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp); | |
805 | struct ehca_shca *shca = | |
806 | container_of(ibqp->pd->device, struct ehca_shca, ib_device); | |
807 | u64 update_mask; | |
808 | u64 h_ret; | |
809 | int bad_wqe_cnt = 0; | |
810 | int squeue_locked = 0; | |
811 | unsigned long spl_flags = 0; | |
812 | ||
813 | /* do query_qp to obtain current attr values */ | |
814 | mqpcb = kzalloc(H_CB_ALIGNMENT, GFP_KERNEL); | |
815 | if (mqpcb == NULL) { | |
816 | ehca_err(ibqp->device, "Could not get zeroed page for mqpcb " | |
817 | "ehca_qp=%p qp_num=%x ", my_qp, ibqp->qp_num); | |
818 | return -ENOMEM; | |
819 | } | |
820 | ||
821 | h_ret = hipz_h_query_qp(shca->ipz_hca_handle, | |
822 | my_qp->ipz_qp_handle, | |
823 | &my_qp->pf, | |
824 | mqpcb, my_qp->galpas.kernel); | |
825 | if (h_ret != H_SUCCESS) { | |
826 | ehca_err(ibqp->device, "hipz_h_query_qp() failed " | |
827 | "ehca_qp=%p qp_num=%x h_ret=%lx", | |
828 | my_qp, ibqp->qp_num, h_ret); | |
829 | ret = ehca2ib_return_code(h_ret); | |
830 | goto modify_qp_exit1; | |
831 | } | |
832 | ||
833 | qp_cur_state = ehca2ib_qp_state(mqpcb->qp_state); | |
834 | ||
835 | if (qp_cur_state == -EINVAL) { /* invalid qp state */ | |
836 | ret = -EINVAL; | |
837 | ehca_err(ibqp->device, "Invalid current ehca_qp_state=%x " | |
838 | "ehca_qp=%p qp_num=%x", | |
839 | mqpcb->qp_state, my_qp, ibqp->qp_num); | |
840 | goto modify_qp_exit1; | |
841 | } | |
842 | /* | |
843 | * circumvention to set aqp0 initial state to init | |
844 | * as expected by IB spec | |
845 | */ | |
846 | if (smi_reset2init == 0 && | |
847 | ibqp->qp_type == IB_QPT_SMI && | |
848 | qp_cur_state == IB_QPS_RESET && | |
849 | (attr_mask & IB_QP_STATE) && | |
850 | attr->qp_state == IB_QPS_INIT) { /* RESET -> INIT */ | |
851 | struct ib_qp_attr smiqp_attr = { | |
852 | .qp_state = IB_QPS_INIT, | |
853 | .port_num = my_qp->init_attr.port_num, | |
854 | .pkey_index = 0, | |
855 | .qkey = 0 | |
856 | }; | |
857 | int smiqp_attr_mask = IB_QP_STATE | IB_QP_PORT | | |
858 | IB_QP_PKEY_INDEX | IB_QP_QKEY; | |
859 | int smirc = internal_modify_qp( | |
860 | ibqp, &smiqp_attr, smiqp_attr_mask, 1); | |
861 | if (smirc) { | |
862 | ehca_err(ibqp->device, "SMI RESET -> INIT failed. " | |
863 | "ehca_modify_qp() rc=%x", smirc); | |
864 | ret = H_PARAMETER; | |
865 | goto modify_qp_exit1; | |
866 | } | |
867 | qp_cur_state = IB_QPS_INIT; | |
868 | ehca_dbg(ibqp->device, "SMI RESET -> INIT succeeded"); | |
869 | } | |
870 | /* is transmitted current state equal to "real" current state */ | |
871 | if ((attr_mask & IB_QP_CUR_STATE) && | |
872 | qp_cur_state != attr->cur_qp_state) { | |
873 | ret = -EINVAL; | |
874 | ehca_err(ibqp->device, | |
875 | "Invalid IB_QP_CUR_STATE attr->curr_qp_state=%x <>" | |
876 | " actual cur_qp_state=%x. ehca_qp=%p qp_num=%x", | |
877 | attr->cur_qp_state, qp_cur_state, my_qp, ibqp->qp_num); | |
878 | goto modify_qp_exit1; | |
879 | } | |
880 | ||
881 | ehca_dbg(ibqp->device,"ehca_qp=%p qp_num=%x current qp_state=%x " | |
882 | "new qp_state=%x attribute_mask=%x", | |
883 | my_qp, ibqp->qp_num, qp_cur_state, attr->qp_state, attr_mask); | |
884 | ||
885 | qp_new_state = attr_mask & IB_QP_STATE ? attr->qp_state : qp_cur_state; | |
886 | if (!smi_reset2init && | |
887 | !ib_modify_qp_is_ok(qp_cur_state, qp_new_state, ibqp->qp_type, | |
888 | attr_mask)) { | |
889 | ret = -EINVAL; | |
890 | ehca_err(ibqp->device, | |
891 | "Invalid qp transition new_state=%x cur_state=%x " | |
892 | "ehca_qp=%p qp_num=%x attr_mask=%x", qp_new_state, | |
893 | qp_cur_state, my_qp, ibqp->qp_num, attr_mask); | |
894 | goto modify_qp_exit1; | |
895 | } | |
896 | ||
897 | if ((mqpcb->qp_state = ib2ehca_qp_state(qp_new_state))) | |
898 | update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1); | |
899 | else { | |
900 | ret = -EINVAL; | |
901 | ehca_err(ibqp->device, "Invalid new qp state=%x " | |
902 | "ehca_qp=%p qp_num=%x", | |
903 | qp_new_state, my_qp, ibqp->qp_num); | |
904 | goto modify_qp_exit1; | |
905 | } | |
906 | ||
907 | /* retrieve state transition struct to get req and opt attrs */ | |
908 | statetrans = get_modqp_statetrans(qp_cur_state, qp_new_state); | |
909 | if (statetrans < 0) { | |
910 | ret = -EINVAL; | |
911 | ehca_err(ibqp->device, "<INVALID STATE CHANGE> qp_cur_state=%x " | |
912 | "new_qp_state=%x State_xsition=%x ehca_qp=%p " | |
913 | "qp_num=%x", qp_cur_state, qp_new_state, | |
914 | statetrans, my_qp, ibqp->qp_num); | |
915 | goto modify_qp_exit1; | |
916 | } | |
917 | ||
918 | qp_attr_idx = ib2ehcaqptype(ibqp->qp_type); | |
919 | ||
920 | if (qp_attr_idx < 0) { | |
921 | ret = qp_attr_idx; | |
922 | ehca_err(ibqp->device, | |
923 | "Invalid QP type=%x ehca_qp=%p qp_num=%x", | |
924 | ibqp->qp_type, my_qp, ibqp->qp_num); | |
925 | goto modify_qp_exit1; | |
926 | } | |
927 | ||
928 | ehca_dbg(ibqp->device, | |
929 | "ehca_qp=%p qp_num=%x <VALID STATE CHANGE> qp_state_xsit=%x", | |
930 | my_qp, ibqp->qp_num, statetrans); | |
931 | ||
932 | /* sqe -> rts: set purge bit of bad wqe before actual trans */ | |
933 | if ((my_qp->qp_type == IB_QPT_UD || | |
934 | my_qp->qp_type == IB_QPT_GSI || | |
935 | my_qp->qp_type == IB_QPT_SMI) && | |
936 | statetrans == IB_QPST_SQE2RTS) { | |
937 | /* mark next free wqe if kernel */ | |
938 | if (my_qp->uspace_squeue == 0) { | |
939 | struct ehca_wqe *wqe; | |
940 | /* lock send queue */ | |
941 | spin_lock_irqsave(&my_qp->spinlock_s, spl_flags); | |
942 | squeue_locked = 1; | |
943 | /* mark next free wqe */ | |
944 | wqe = (struct ehca_wqe*) | |
945 | ipz_qeit_get(&my_qp->ipz_squeue); | |
946 | wqe->optype = wqe->wqef = 0xff; | |
947 | ehca_dbg(ibqp->device, "qp_num=%x next_free_wqe=%p", | |
948 | ibqp->qp_num, wqe); | |
949 | } | |
950 | ret = prepare_sqe_rts(my_qp, shca, &bad_wqe_cnt); | |
951 | if (ret) { | |
952 | ehca_err(ibqp->device, "prepare_sqe_rts() failed " | |
953 | "ehca_qp=%p qp_num=%x ret=%x", | |
954 | my_qp, ibqp->qp_num, ret); | |
955 | goto modify_qp_exit2; | |
956 | } | |
957 | } | |
958 | ||
959 | /* | |
960 | * enable RDMA_Atomic_Control if reset->init und reliable con | |
961 | * this is necessary since gen2 does not provide that flag, | |
962 | * but pHyp requires it | |
963 | */ | |
964 | if (statetrans == IB_QPST_RESET2INIT && | |
965 | (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_UC)) { | |
966 | mqpcb->rdma_atomic_ctrl = 3; | |
967 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RDMA_ATOMIC_CTRL, 1); | |
968 | } | |
969 | /* circ. pHyp requires #RDMA/Atomic Resp Res for UC INIT -> RTR */ | |
970 | if (statetrans == IB_QPST_INIT2RTR && | |
971 | (ibqp->qp_type == IB_QPT_UC) && | |
972 | !(attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)) { | |
973 | mqpcb->rdma_nr_atomic_resp_res = 1; /* default to 1 */ | |
974 | update_mask |= | |
975 | EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1); | |
976 | } | |
977 | ||
978 | if (attr_mask & IB_QP_PKEY_INDEX) { | |
979 | mqpcb->prim_p_key_idx = attr->pkey_index; | |
980 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_P_KEY_IDX, 1); | |
981 | } | |
982 | if (attr_mask & IB_QP_PORT) { | |
983 | if (attr->port_num < 1 || attr->port_num > shca->num_ports) { | |
984 | ret = -EINVAL; | |
985 | ehca_err(ibqp->device, "Invalid port=%x. " | |
986 | "ehca_qp=%p qp_num=%x num_ports=%x", | |
987 | attr->port_num, my_qp, ibqp->qp_num, | |
988 | shca->num_ports); | |
989 | goto modify_qp_exit2; | |
990 | } | |
991 | mqpcb->prim_phys_port = attr->port_num; | |
992 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_PHYS_PORT, 1); | |
993 | } | |
994 | if (attr_mask & IB_QP_QKEY) { | |
995 | mqpcb->qkey = attr->qkey; | |
996 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_QKEY, 1); | |
997 | } | |
998 | if (attr_mask & IB_QP_AV) { | |
999 | int ah_mult = ib_rate_to_mult(attr->ah_attr.static_rate); | |
1000 | int ehca_mult = ib_rate_to_mult(shca->sport[my_qp-> | |
1001 | init_attr.port_num].rate); | |
1002 | ||
1003 | mqpcb->dlid = attr->ah_attr.dlid; | |
1004 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID, 1); | |
1005 | mqpcb->source_path_bits = attr->ah_attr.src_path_bits; | |
1006 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS, 1); | |
1007 | mqpcb->service_level = attr->ah_attr.sl; | |
1008 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL, 1); | |
1009 | ||
1010 | if (ah_mult < ehca_mult) | |
1011 | mqpcb->max_static_rate = (ah_mult > 0) ? | |
1012 | ((ehca_mult - 1) / ah_mult) : 0; | |
1013 | else | |
1014 | mqpcb->max_static_rate = 0; | |
1015 | ||
1016 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE, 1); | |
1017 | ||
1018 | /* | |
1019 | * only if GRH is TRUE we might consider SOURCE_GID_IDX | |
1020 | * and DEST_GID otherwise phype will return H_ATTR_PARM!!! | |
1021 | */ | |
1022 | if (attr->ah_attr.ah_flags == IB_AH_GRH) { | |
1023 | mqpcb->send_grh_flag = 1 << 31; | |
1024 | update_mask |= | |
1025 | EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1); | |
1026 | mqpcb->source_gid_idx = attr->ah_attr.grh.sgid_index; | |
1027 | update_mask |= | |
1028 | EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX, 1); | |
1029 | ||
1030 | for (cnt = 0; cnt < 16; cnt++) | |
1031 | mqpcb->dest_gid.byte[cnt] = | |
1032 | attr->ah_attr.grh.dgid.raw[cnt]; | |
1033 | ||
1034 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_GID, 1); | |
1035 | mqpcb->flow_label = attr->ah_attr.grh.flow_label; | |
1036 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL, 1); | |
1037 | mqpcb->hop_limit = attr->ah_attr.grh.hop_limit; | |
1038 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT, 1); | |
1039 | mqpcb->traffic_class = attr->ah_attr.grh.traffic_class; | |
1040 | update_mask |= | |
1041 | EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS, 1); | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | if (attr_mask & IB_QP_PATH_MTU) { | |
1046 | mqpcb->path_mtu = attr->path_mtu; | |
1047 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PATH_MTU, 1); | |
1048 | } | |
1049 | if (attr_mask & IB_QP_TIMEOUT) { | |
1050 | mqpcb->timeout = attr->timeout; | |
1051 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT, 1); | |
1052 | } | |
1053 | if (attr_mask & IB_QP_RETRY_CNT) { | |
1054 | mqpcb->retry_count = attr->retry_cnt; | |
1055 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT, 1); | |
1056 | } | |
1057 | if (attr_mask & IB_QP_RNR_RETRY) { | |
1058 | mqpcb->rnr_retry_count = attr->rnr_retry; | |
1059 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT, 1); | |
1060 | } | |
1061 | if (attr_mask & IB_QP_RQ_PSN) { | |
1062 | mqpcb->receive_psn = attr->rq_psn; | |
1063 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RECEIVE_PSN, 1); | |
1064 | } | |
1065 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { | |
1066 | mqpcb->rdma_nr_atomic_resp_res = attr->max_dest_rd_atomic < 3 ? | |
1067 | attr->max_dest_rd_atomic : 2; | |
1068 | update_mask |= | |
1069 | EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1); | |
1070 | } | |
1071 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { | |
1072 | mqpcb->rdma_atomic_outst_dest_qp = attr->max_rd_atomic < 3 ? | |
1073 | attr->max_rd_atomic : 2; | |
1074 | update_mask |= | |
1075 | EHCA_BMASK_SET | |
1076 | (MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP, 1); | |
1077 | } | |
1078 | if (attr_mask & IB_QP_ALT_PATH) { | |
1079 | int ah_mult = ib_rate_to_mult(attr->alt_ah_attr.static_rate); | |
1080 | int ehca_mult = ib_rate_to_mult( | |
1081 | shca->sport[my_qp->init_attr.port_num].rate); | |
1082 | ||
1083 | mqpcb->dlid_al = attr->alt_ah_attr.dlid; | |
1084 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID_AL, 1); | |
1085 | mqpcb->source_path_bits_al = attr->alt_ah_attr.src_path_bits; | |
1086 | update_mask |= | |
1087 | EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS_AL, 1); | |
1088 | mqpcb->service_level_al = attr->alt_ah_attr.sl; | |
1089 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL_AL, 1); | |
1090 | ||
1091 | if (ah_mult < ehca_mult) | |
1092 | mqpcb->max_static_rate = (ah_mult > 0) ? | |
1093 | ((ehca_mult - 1) / ah_mult) : 0; | |
1094 | else | |
1095 | mqpcb->max_static_rate_al = 0; | |
1096 | ||
1097 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE_AL, 1); | |
1098 | ||
1099 | /* | |
1100 | * only if GRH is TRUE we might consider SOURCE_GID_IDX | |
1101 | * and DEST_GID otherwise phype will return H_ATTR_PARM!!! | |
1102 | */ | |
1103 | if (attr->alt_ah_attr.ah_flags == IB_AH_GRH) { | |
1104 | mqpcb->send_grh_flag_al = 1 << 31; | |
1105 | update_mask |= | |
1106 | EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG_AL, 1); | |
1107 | mqpcb->source_gid_idx_al = | |
1108 | attr->alt_ah_attr.grh.sgid_index; | |
1109 | update_mask |= | |
1110 | EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX_AL, 1); | |
1111 | ||
1112 | for (cnt = 0; cnt < 16; cnt++) | |
1113 | mqpcb->dest_gid_al.byte[cnt] = | |
1114 | attr->alt_ah_attr.grh.dgid.raw[cnt]; | |
1115 | ||
1116 | update_mask |= | |
1117 | EHCA_BMASK_SET(MQPCB_MASK_DEST_GID_AL, 1); | |
1118 | mqpcb->flow_label_al = attr->alt_ah_attr.grh.flow_label; | |
1119 | update_mask |= | |
1120 | EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL_AL, 1); | |
1121 | mqpcb->hop_limit_al = attr->alt_ah_attr.grh.hop_limit; | |
1122 | update_mask |= | |
1123 | EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT_AL, 1); | |
1124 | mqpcb->traffic_class_al = | |
1125 | attr->alt_ah_attr.grh.traffic_class; | |
1126 | update_mask |= | |
1127 | EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS_AL, 1); | |
1128 | } | |
1129 | } | |
1130 | ||
1131 | if (attr_mask & IB_QP_MIN_RNR_TIMER) { | |
1132 | mqpcb->min_rnr_nak_timer_field = attr->min_rnr_timer; | |
1133 | update_mask |= | |
1134 | EHCA_BMASK_SET(MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD, 1); | |
1135 | } | |
1136 | ||
1137 | if (attr_mask & IB_QP_SQ_PSN) { | |
1138 | mqpcb->send_psn = attr->sq_psn; | |
1139 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_PSN, 1); | |
1140 | } | |
1141 | ||
1142 | if (attr_mask & IB_QP_DEST_QPN) { | |
1143 | mqpcb->dest_qp_nr = attr->dest_qp_num; | |
1144 | update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_QP_NR, 1); | |
1145 | } | |
1146 | ||
1147 | if (attr_mask & IB_QP_PATH_MIG_STATE) { | |
1148 | mqpcb->path_migration_state = attr->path_mig_state; | |
1149 | update_mask |= | |
1150 | EHCA_BMASK_SET(MQPCB_MASK_PATH_MIGRATION_STATE, 1); | |
1151 | } | |
1152 | ||
1153 | if (attr_mask & IB_QP_CAP) { | |
1154 | mqpcb->max_nr_outst_send_wr = attr->cap.max_send_wr+1; | |
1155 | update_mask |= | |
1156 | EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_SEND_WR, 1); | |
1157 | mqpcb->max_nr_outst_recv_wr = attr->cap.max_recv_wr+1; | |
1158 | update_mask |= | |
1159 | EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_RECV_WR, 1); | |
1160 | /* no support for max_send/recv_sge yet */ | |
1161 | } | |
1162 | ||
1163 | if (ehca_debug_level) | |
1164 | ehca_dmp(mqpcb, 4*70, "qp_num=%x", ibqp->qp_num); | |
1165 | ||
1166 | h_ret = hipz_h_modify_qp(shca->ipz_hca_handle, | |
1167 | my_qp->ipz_qp_handle, | |
1168 | &my_qp->pf, | |
1169 | update_mask, | |
1170 | mqpcb, my_qp->galpas.kernel); | |
1171 | ||
1172 | if (h_ret != H_SUCCESS) { | |
1173 | ret = ehca2ib_return_code(h_ret); | |
1174 | ehca_err(ibqp->device, "hipz_h_modify_qp() failed rc=%lx " | |
1175 | "ehca_qp=%p qp_num=%x",h_ret, my_qp, ibqp->qp_num); | |
1176 | goto modify_qp_exit2; | |
1177 | } | |
1178 | ||
1179 | if ((my_qp->qp_type == IB_QPT_UD || | |
1180 | my_qp->qp_type == IB_QPT_GSI || | |
1181 | my_qp->qp_type == IB_QPT_SMI) && | |
1182 | statetrans == IB_QPST_SQE2RTS) { | |
1183 | /* doorbell to reprocessing wqes */ | |
1184 | iosync(); /* serialize GAL register access */ | |
1185 | hipz_update_sqa(my_qp, bad_wqe_cnt-1); | |
1186 | ehca_gen_dbg("doorbell for %x wqes", bad_wqe_cnt); | |
1187 | } | |
1188 | ||
1189 | if (statetrans == IB_QPST_RESET2INIT || | |
1190 | statetrans == IB_QPST_INIT2INIT) { | |
1191 | mqpcb->qp_enable = 1; | |
1192 | mqpcb->qp_state = EHCA_QPS_INIT; | |
1193 | update_mask = 0; | |
1194 | update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1); | |
1195 | ||
1196 | h_ret = hipz_h_modify_qp(shca->ipz_hca_handle, | |
1197 | my_qp->ipz_qp_handle, | |
1198 | &my_qp->pf, | |
1199 | update_mask, | |
1200 | mqpcb, | |
1201 | my_qp->galpas.kernel); | |
1202 | ||
1203 | if (h_ret != H_SUCCESS) { | |
1204 | ret = ehca2ib_return_code(h_ret); | |
1205 | ehca_err(ibqp->device, "ENABLE in context of " | |
1206 | "RESET_2_INIT failed! Maybe you didn't get " | |
1207 | "a LID h_ret=%lx ehca_qp=%p qp_num=%x", | |
1208 | h_ret, my_qp, ibqp->qp_num); | |
1209 | goto modify_qp_exit2; | |
1210 | } | |
1211 | } | |
1212 | ||
1213 | if (statetrans == IB_QPST_ANY2RESET) { | |
1214 | ipz_qeit_reset(&my_qp->ipz_rqueue); | |
1215 | ipz_qeit_reset(&my_qp->ipz_squeue); | |
1216 | } | |
1217 | ||
1218 | if (attr_mask & IB_QP_QKEY) | |
1219 | my_qp->qkey = attr->qkey; | |
1220 | ||
1221 | modify_qp_exit2: | |
1222 | if (squeue_locked) { /* this means: sqe -> rts */ | |
1223 | spin_unlock_irqrestore(&my_qp->spinlock_s, spl_flags); | |
1224 | my_qp->sqerr_purgeflag = 1; | |
1225 | } | |
1226 | ||
1227 | modify_qp_exit1: | |
1228 | kfree(mqpcb); | |
1229 | ||
1230 | return ret; | |
1231 | } | |
1232 | ||
1233 | int ehca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask) | |
1234 | { | |
1235 | struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp); | |
1236 | struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd, | |
1237 | ib_pd); | |
1238 | u32 cur_pid = current->tgid; | |
1239 | ||
1240 | if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context && | |
1241 | my_pd->ownpid != cur_pid) { | |
1242 | ehca_err(ibqp->pd->device, "Invalid caller pid=%x ownpid=%x", | |
1243 | cur_pid, my_pd->ownpid); | |
1244 | return -EINVAL; | |
1245 | } | |
1246 | ||
1247 | return internal_modify_qp(ibqp, attr, attr_mask, 0); | |
1248 | } | |
1249 | ||
1250 | int ehca_query_qp(struct ib_qp *qp, | |
1251 | struct ib_qp_attr *qp_attr, | |
1252 | int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) | |
1253 | { | |
1254 | struct ehca_qp *my_qp = container_of(qp, struct ehca_qp, ib_qp); | |
1255 | struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd, | |
1256 | ib_pd); | |
1257 | struct ehca_shca *shca = container_of(qp->device, struct ehca_shca, | |
1258 | ib_device); | |
1259 | struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle; | |
1260 | struct hcp_modify_qp_control_block *qpcb; | |
1261 | u32 cur_pid = current->tgid; | |
1262 | int cnt, ret = 0; | |
1263 | u64 h_ret; | |
1264 | ||
1265 | if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context && | |
1266 | my_pd->ownpid != cur_pid) { | |
1267 | ehca_err(qp->device, "Invalid caller pid=%x ownpid=%x", | |
1268 | cur_pid, my_pd->ownpid); | |
1269 | return -EINVAL; | |
1270 | } | |
1271 | ||
1272 | if (qp_attr_mask & QP_ATTR_QUERY_NOT_SUPPORTED) { | |
1273 | ehca_err(qp->device,"Invalid attribute mask " | |
1274 | "ehca_qp=%p qp_num=%x qp_attr_mask=%x ", | |
1275 | my_qp, qp->qp_num, qp_attr_mask); | |
1276 | return -EINVAL; | |
1277 | } | |
1278 | ||
1279 | qpcb = kzalloc(H_CB_ALIGNMENT, GFP_KERNEL ); | |
1280 | if (!qpcb) { | |
1281 | ehca_err(qp->device,"Out of memory for qpcb " | |
1282 | "ehca_qp=%p qp_num=%x", my_qp, qp->qp_num); | |
1283 | return -ENOMEM; | |
1284 | } | |
1285 | ||
1286 | h_ret = hipz_h_query_qp(adapter_handle, | |
1287 | my_qp->ipz_qp_handle, | |
1288 | &my_qp->pf, | |
1289 | qpcb, my_qp->galpas.kernel); | |
1290 | ||
1291 | if (h_ret != H_SUCCESS) { | |
1292 | ret = ehca2ib_return_code(h_ret); | |
1293 | ehca_err(qp->device,"hipz_h_query_qp() failed " | |
1294 | "ehca_qp=%p qp_num=%x h_ret=%lx", | |
1295 | my_qp, qp->qp_num, h_ret); | |
1296 | goto query_qp_exit1; | |
1297 | } | |
1298 | ||
1299 | qp_attr->cur_qp_state = ehca2ib_qp_state(qpcb->qp_state); | |
1300 | qp_attr->qp_state = qp_attr->cur_qp_state; | |
1301 | ||
1302 | if (qp_attr->cur_qp_state == -EINVAL) { | |
1303 | ret = -EINVAL; | |
1304 | ehca_err(qp->device,"Got invalid ehca_qp_state=%x " | |
1305 | "ehca_qp=%p qp_num=%x", | |
1306 | qpcb->qp_state, my_qp, qp->qp_num); | |
1307 | goto query_qp_exit1; | |
1308 | } | |
1309 | ||
1310 | if (qp_attr->qp_state == IB_QPS_SQD) | |
1311 | qp_attr->sq_draining = 1; | |
1312 | ||
1313 | qp_attr->qkey = qpcb->qkey; | |
1314 | qp_attr->path_mtu = qpcb->path_mtu; | |
1315 | qp_attr->path_mig_state = qpcb->path_migration_state; | |
1316 | qp_attr->rq_psn = qpcb->receive_psn; | |
1317 | qp_attr->sq_psn = qpcb->send_psn; | |
1318 | qp_attr->min_rnr_timer = qpcb->min_rnr_nak_timer_field; | |
1319 | qp_attr->cap.max_send_wr = qpcb->max_nr_outst_send_wr-1; | |
1320 | qp_attr->cap.max_recv_wr = qpcb->max_nr_outst_recv_wr-1; | |
1321 | /* UD_AV CIRCUMVENTION */ | |
1322 | if (my_qp->qp_type == IB_QPT_UD) { | |
1323 | qp_attr->cap.max_send_sge = | |
1324 | qpcb->actual_nr_sges_in_sq_wqe - 2; | |
1325 | qp_attr->cap.max_recv_sge = | |
1326 | qpcb->actual_nr_sges_in_rq_wqe - 2; | |
1327 | } else { | |
1328 | qp_attr->cap.max_send_sge = | |
1329 | qpcb->actual_nr_sges_in_sq_wqe; | |
1330 | qp_attr->cap.max_recv_sge = | |
1331 | qpcb->actual_nr_sges_in_rq_wqe; | |
1332 | } | |
1333 | ||
1334 | qp_attr->cap.max_inline_data = my_qp->sq_max_inline_data_size; | |
1335 | qp_attr->dest_qp_num = qpcb->dest_qp_nr; | |
1336 | ||
1337 | qp_attr->pkey_index = | |
1338 | EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->prim_p_key_idx); | |
1339 | ||
1340 | qp_attr->port_num = | |
1341 | EHCA_BMASK_GET(MQPCB_PRIM_PHYS_PORT, qpcb->prim_phys_port); | |
1342 | ||
1343 | qp_attr->timeout = qpcb->timeout; | |
1344 | qp_attr->retry_cnt = qpcb->retry_count; | |
1345 | qp_attr->rnr_retry = qpcb->rnr_retry_count; | |
1346 | ||
1347 | qp_attr->alt_pkey_index = | |
1348 | EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->alt_p_key_idx); | |
1349 | ||
1350 | qp_attr->alt_port_num = qpcb->alt_phys_port; | |
1351 | qp_attr->alt_timeout = qpcb->timeout_al; | |
1352 | ||
1353 | /* primary av */ | |
1354 | qp_attr->ah_attr.sl = qpcb->service_level; | |
1355 | ||
1356 | if (qpcb->send_grh_flag) { | |
1357 | qp_attr->ah_attr.ah_flags = IB_AH_GRH; | |
1358 | } | |
1359 | ||
1360 | qp_attr->ah_attr.static_rate = qpcb->max_static_rate; | |
1361 | qp_attr->ah_attr.dlid = qpcb->dlid; | |
1362 | qp_attr->ah_attr.src_path_bits = qpcb->source_path_bits; | |
1363 | qp_attr->ah_attr.port_num = qp_attr->port_num; | |
1364 | ||
1365 | /* primary GRH */ | |
1366 | qp_attr->ah_attr.grh.traffic_class = qpcb->traffic_class; | |
1367 | qp_attr->ah_attr.grh.hop_limit = qpcb->hop_limit; | |
1368 | qp_attr->ah_attr.grh.sgid_index = qpcb->source_gid_idx; | |
1369 | qp_attr->ah_attr.grh.flow_label = qpcb->flow_label; | |
1370 | ||
1371 | for (cnt = 0; cnt < 16; cnt++) | |
1372 | qp_attr->ah_attr.grh.dgid.raw[cnt] = | |
1373 | qpcb->dest_gid.byte[cnt]; | |
1374 | ||
1375 | /* alternate AV */ | |
1376 | qp_attr->alt_ah_attr.sl = qpcb->service_level_al; | |
1377 | if (qpcb->send_grh_flag_al) { | |
1378 | qp_attr->alt_ah_attr.ah_flags = IB_AH_GRH; | |
1379 | } | |
1380 | ||
1381 | qp_attr->alt_ah_attr.static_rate = qpcb->max_static_rate_al; | |
1382 | qp_attr->alt_ah_attr.dlid = qpcb->dlid_al; | |
1383 | qp_attr->alt_ah_attr.src_path_bits = qpcb->source_path_bits_al; | |
1384 | ||
1385 | /* alternate GRH */ | |
1386 | qp_attr->alt_ah_attr.grh.traffic_class = qpcb->traffic_class_al; | |
1387 | qp_attr->alt_ah_attr.grh.hop_limit = qpcb->hop_limit_al; | |
1388 | qp_attr->alt_ah_attr.grh.sgid_index = qpcb->source_gid_idx_al; | |
1389 | qp_attr->alt_ah_attr.grh.flow_label = qpcb->flow_label_al; | |
1390 | ||
1391 | for (cnt = 0; cnt < 16; cnt++) | |
1392 | qp_attr->alt_ah_attr.grh.dgid.raw[cnt] = | |
1393 | qpcb->dest_gid_al.byte[cnt]; | |
1394 | ||
1395 | /* return init attributes given in ehca_create_qp */ | |
1396 | if (qp_init_attr) | |
1397 | *qp_init_attr = my_qp->init_attr; | |
1398 | ||
1399 | if (ehca_debug_level) | |
1400 | ehca_dmp(qpcb, 4*70, "qp_num=%x", qp->qp_num); | |
1401 | ||
1402 | query_qp_exit1: | |
1403 | kfree(qpcb); | |
1404 | ||
1405 | return ret; | |
1406 | } | |
1407 | ||
1408 | int ehca_destroy_qp(struct ib_qp *ibqp) | |
1409 | { | |
1410 | struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp); | |
1411 | struct ehca_shca *shca = container_of(ibqp->device, struct ehca_shca, | |
1412 | ib_device); | |
1413 | struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd, | |
1414 | ib_pd); | |
1415 | u32 cur_pid = current->tgid; | |
1416 | u32 qp_num = ibqp->qp_num; | |
1417 | int ret; | |
1418 | u64 h_ret; | |
1419 | u8 port_num; | |
1420 | enum ib_qp_type qp_type; | |
1421 | unsigned long flags; | |
1422 | ||
1423 | if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context && | |
1424 | my_pd->ownpid != cur_pid) { | |
1425 | ehca_err(ibqp->device, "Invalid caller pid=%x ownpid=%x", | |
1426 | cur_pid, my_pd->ownpid); | |
1427 | return -EINVAL; | |
1428 | } | |
1429 | ||
1430 | if (my_qp->send_cq) { | |
1431 | ret = ehca_cq_unassign_qp(my_qp->send_cq, | |
1432 | my_qp->real_qp_num); | |
1433 | if (ret) { | |
1434 | ehca_err(ibqp->device, "Couldn't unassign qp from " | |
1435 | "send_cq ret=%x qp_num=%x cq_num=%x", ret, | |
1436 | my_qp->ib_qp.qp_num, my_qp->send_cq->cq_number); | |
1437 | return ret; | |
1438 | } | |
1439 | } | |
1440 | ||
1441 | spin_lock_irqsave(&ehca_qp_idr_lock, flags); | |
1442 | idr_remove(&ehca_qp_idr, my_qp->token); | |
1443 | spin_unlock_irqrestore(&ehca_qp_idr_lock, flags); | |
1444 | ||
1445 | /* un-mmap if vma alloc */ | |
1446 | if (my_qp->uspace_rqueue) { | |
1447 | ret = ehca_munmap(my_qp->uspace_rqueue, | |
1448 | my_qp->ipz_rqueue.queue_length); | |
1449 | if (ret) | |
1450 | ehca_err(ibqp->device, "Could not munmap rqueue " | |
1451 | "qp_num=%x", qp_num); | |
1452 | ret = ehca_munmap(my_qp->uspace_squeue, | |
1453 | my_qp->ipz_squeue.queue_length); | |
1454 | if (ret) | |
1455 | ehca_err(ibqp->device, "Could not munmap squeue " | |
1456 | "qp_num=%x", qp_num); | |
1457 | ret = ehca_munmap(my_qp->uspace_fwh, EHCA_PAGESIZE); | |
1458 | if (ret) | |
1459 | ehca_err(ibqp->device, "Could not munmap fwh qp_num=%x", | |
1460 | qp_num); | |
1461 | } | |
1462 | ||
1463 | h_ret = hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp); | |
1464 | if (h_ret != H_SUCCESS) { | |
1465 | ehca_err(ibqp->device, "hipz_h_destroy_qp() failed rc=%lx " | |
1466 | "ehca_qp=%p qp_num=%x", h_ret, my_qp, qp_num); | |
1467 | return ehca2ib_return_code(h_ret); | |
1468 | } | |
1469 | ||
1470 | port_num = my_qp->init_attr.port_num; | |
1471 | qp_type = my_qp->init_attr.qp_type; | |
1472 | ||
1473 | /* no support for IB_QPT_SMI yet */ | |
1474 | if (qp_type == IB_QPT_GSI) { | |
1475 | struct ib_event event; | |
1476 | ehca_info(ibqp->device, "device %s: port %x is inactive.", | |
1477 | shca->ib_device.name, port_num); | |
1478 | event.device = &shca->ib_device; | |
1479 | event.event = IB_EVENT_PORT_ERR; | |
1480 | event.element.port_num = port_num; | |
1481 | shca->sport[port_num - 1].port_state = IB_PORT_DOWN; | |
1482 | ib_dispatch_event(&event); | |
1483 | } | |
1484 | ||
1485 | ipz_queue_dtor(&my_qp->ipz_rqueue); | |
1486 | ipz_queue_dtor(&my_qp->ipz_squeue); | |
1487 | kmem_cache_free(qp_cache, my_qp); | |
1488 | return 0; | |
1489 | } | |
1490 | ||
1491 | int ehca_init_qp_cache(void) | |
1492 | { | |
1493 | qp_cache = kmem_cache_create("ehca_cache_qp", | |
1494 | sizeof(struct ehca_qp), 0, | |
1495 | SLAB_HWCACHE_ALIGN, | |
1496 | NULL, NULL); | |
1497 | if (!qp_cache) | |
1498 | return -ENOMEM; | |
1499 | return 0; | |
1500 | } | |
1501 | ||
1502 | void ehca_cleanup_qp_cache(void) | |
1503 | { | |
1504 | if (qp_cache) | |
1505 | kmem_cache_destroy(qp_cache); | |
1506 | } |