[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / t4.h

/*
 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __T4_H__
#define __T4_H__

#include "t4_hw.h"
#include "t4_regs.h"
#include "t4_msg.h"
#include "t4fw_ri_api.h"

#define T4_MAX_NUM_QP 65536
#define T4_MAX_NUM_CQ 65536
#define T4_MAX_NUM_PD 65536
#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
#define T4_MAX_IQ_SIZE (65520 - 1)
#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
#define T4_MAX_NUM_STAG (1<<15)
#define T4_MAX_MR_SIZE (~0ULL)
#define T4_PAGESIZE_MASK 0xffff000  /* 4KB-128MB */
#define T4_STAG_UNSET 0xffffffff
#define T4_FW_MAJ 0
#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
#define A_PCIE_MA_SYNC 0x30b4

struct t4_status_page {
	__be32 rsvd1;	/* flit 0 - hw owns */
	__be16 rsvd2;
	__be16 qid;
	__be16 cidx;
	__be16 pidx;
	u8 qp_err;	/* flit 1 - sw owns */
	u8 db_off;
	u8 pad;
	u16 host_wq_pidx;
	u16 host_cidx;
	u16 host_pidx;
};

#define T4_EQ_ENTRY_SIZE 64

#define T4_SQ_NUM_SLOTS 5
#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
			sizeof(struct fw_ri_rdma_write_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
			sizeof(struct fw_ri_rdma_write_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
			sizeof(struct fw_ri_immd)) & ~31UL)
#define T4_MAX_FR_DEPTH (1024 / sizeof(u64))

#define T4_RQ_NUM_SLOTS 2
#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
#define T4_MAX_RECV_SGE 4

union t4_wr {
	struct fw_ri_res_wr res;
	struct fw_ri_wr ri;
	struct fw_ri_rdma_write_wr write;
	struct fw_ri_send_wr send;
	struct fw_ri_rdma_read_wr read;
	struct fw_ri_bind_mw_wr bind;
	struct fw_ri_fr_nsmr_wr fr;
	struct fw_ri_inv_lstag_wr inv;
	struct t4_status_page status;
	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
};

union t4_recv_wr {
	struct fw_ri_recv_wr recv;
	struct t4_status_page status;
	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
};

static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
			       enum fw_wr_opcodes opcode, u8 flags, u8 len16)
{
	wqe->send.opcode = (u8)opcode;
	wqe->send.flags = flags;
	wqe->send.wrid = wrid;
	wqe->send.r1[0] = 0;
	wqe->send.r1[1] = 0;
	wqe->send.r1[2] = 0;
	wqe->send.len16 = len16;
}

/* CQE/AE status codes */
#define T4_ERR_SUCCESS                     0x0
#define T4_ERR_STAG                        0x1	/* STAG invalid: either the */
						/* STAG is offlimt, being 0, */
						/* or STAG_key mismatch */
#define T4_ERR_PDID                        0x2	/* PDID mismatch */
#define T4_ERR_QPID                        0x3	/* QPID mismatch */
#define T4_ERR_ACCESS                      0x4	/* Invalid access right */
#define T4_ERR_WRAP                        0x5	/* Wrap error */
#define T4_ERR_BOUND                       0x6	/* base and bounds voilation */
#define T4_ERR_INVALIDATE_SHARED_MR        0x7	/* attempt to invalidate a  */
						/* shared memory region */
#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8	/* attempt to invalidate a  */
						/* shared memory region */
#define T4_ERR_ECC                         0x9	/* ECC error detected */
#define T4_ERR_ECC_PSTAG                   0xA	/* ECC error detected when  */
						/* reading PSTAG for a MW  */
						/* Invalidate */
#define T4_ERR_PBL_ADDR_BOUND              0xB	/* pbl addr out of bounds:  */
						/* software error */
#define T4_ERR_SWFLUSH			   0xC	/* SW FLUSHED */
#define T4_ERR_CRC                         0x10 /* CRC error */
#define T4_ERR_MARKER                      0x11 /* Marker error */
#define T4_ERR_PDU_LEN_ERR                 0x12 /* invalid PDU length */
#define T4_ERR_OUT_OF_RQE                  0x13 /* out of RQE */
#define T4_ERR_DDP_VERSION                 0x14 /* wrong DDP version */
#define T4_ERR_RDMA_VERSION                0x15 /* wrong RDMA version */
#define T4_ERR_OPCODE                      0x16 /* invalid rdma opcode */
#define T4_ERR_DDP_QUEUE_NUM               0x17 /* invalid ddp queue number */
#define T4_ERR_MSN                         0x18 /* MSN error */
#define T4_ERR_TBIT                        0x19 /* tag bit not set correctly */
#define T4_ERR_MO                          0x1A /* MO not 0 for TERMINATE  */
						/* or READ_REQ */
#define T4_ERR_MSN_GAP                     0x1B
#define T4_ERR_MSN_RANGE                   0x1C
#define T4_ERR_IRD_OVERFLOW                0x1D
#define T4_ERR_RQE_ADDR_BOUND              0x1E /* RQE addr out of bounds:  */
						/* software error */
#define T4_ERR_INTERNAL_ERR                0x1F /* internal error (opcode  */
						/* mismatch) */
/*
 * CQE defs
 */
struct t4_cqe {
	__be32 header;
	__be32 len;
	union {
		struct {
			__be32 stag;
			__be32 msn;
		} rcqe;
		struct {
			u32 nada1;
			u16 nada2;
			u16 cidx;
		} scqe;
		struct {
			__be32 wrid_hi;
			__be32 wrid_low;
		} gen;
	} u;
	__be64 reserved;
	__be64 bits_type_ts;
};

/* macros for flit 0 of the cqe */

#define S_CQE_QPID        12
#define M_CQE_QPID        0xFFFFF
#define G_CQE_QPID(x)     ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
#define V_CQE_QPID(x)	  ((x)<<S_CQE_QPID)

#define S_CQE_SWCQE       11
#define M_CQE_SWCQE       0x1
#define G_CQE_SWCQE(x)    ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
#define V_CQE_SWCQE(x)	  ((x)<<S_CQE_SWCQE)

#define S_CQE_STATUS      5
#define M_CQE_STATUS      0x1F
#define G_CQE_STATUS(x)   ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
#define V_CQE_STATUS(x)   ((x)<<S_CQE_STATUS)

#define S_CQE_TYPE        4
#define M_CQE_TYPE        0x1
#define G_CQE_TYPE(x)     ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
#define V_CQE_TYPE(x)     ((x)<<S_CQE_TYPE)

#define S_CQE_OPCODE      0
#define M_CQE_OPCODE      0xF
#define G_CQE_OPCODE(x)   ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
#define V_CQE_OPCODE(x)   ((x)<<S_CQE_OPCODE)

#define SW_CQE(x)         (G_CQE_SWCQE(be32_to_cpu((x)->header)))
#define CQE_QPID(x)       (G_CQE_QPID(be32_to_cpu((x)->header)))
#define CQE_TYPE(x)       (G_CQE_TYPE(be32_to_cpu((x)->header)))
#define SQ_TYPE(x)	  (CQE_TYPE((x)))
#define RQ_TYPE(x)	  (!CQE_TYPE((x)))
#define CQE_STATUS(x)     (G_CQE_STATUS(be32_to_cpu((x)->header)))
#define CQE_OPCODE(x)     (G_CQE_OPCODE(be32_to_cpu((x)->header)))

#define CQE_SEND_OPCODE(x)( \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))

#define CQE_LEN(x)        (be32_to_cpu((x)->len))

/* used for RQ completion processing */
#define CQE_WRID_STAG(x)  (be32_to_cpu((x)->u.rcqe.stag))
#define CQE_WRID_MSN(x)   (be32_to_cpu((x)->u.rcqe.msn))

/* used for SQ completion processing */
#define CQE_WRID_SQ_IDX(x)	((x)->u.scqe.cidx)

/* generic accessor macros */
#define CQE_WRID_HI(x)		((x)->u.gen.wrid_hi)
#define CQE_WRID_LOW(x)		((x)->u.gen.wrid_low)

/* macros for flit 3 of the cqe */
#define S_CQE_GENBIT	63
#define M_CQE_GENBIT	0x1
#define G_CQE_GENBIT(x)	(((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)

#define S_CQE_OVFBIT	62
#define M_CQE_OVFBIT	0x1
#define G_CQE_OVFBIT(x)	((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)

#define S_CQE_IQTYPE	60
#define M_CQE_IQTYPE	0x3
#define G_CQE_IQTYPE(x)	((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)

#define M_CQE_TS	0x0fffffffffffffffULL
#define G_CQE_TS(x)	((x) & M_CQE_TS)

#define CQE_OVFBIT(x)	((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
#define CQE_GENBIT(x)	((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
#define CQE_TS(x)	(G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))

struct t4_swsqe {
	u64			wr_id;
	struct t4_cqe		cqe;
	int			read_len;
	int			opcode;
	int			complete;
	int			signaled;
	u16			idx;
	int                     flushed;
};

static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
{
#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
	return pgprot_writecombine(prot);
#else
	return pgprot_noncached(prot);
#endif
}

enum {
	T4_SQ_ONCHIP = (1<<0),
};

struct t4_sq {
	union t4_wr *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	unsigned long phys_addr;
	struct t4_swsqe *sw_sq;
	struct t4_swsqe *oldest_read;
	u64 __iomem *udb;
	size_t memsize;
	u32 qid;
	u16 in_use;
	u16 size;
	u16 cidx;
	u16 pidx;
	u16 wq_pidx;
	u16 wq_pidx_inc;
	u16 flags;
	short flush_cidx;
};

struct t4_swrqe {
	u64 wr_id;
};

struct t4_rq {
	union  t4_recv_wr *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	struct t4_swrqe *sw_rq;
	u64 __iomem *udb;
	size_t memsize;
	u32 qid;
	u32 msn;
	u32 rqt_hwaddr;
	u16 rqt_size;
	u16 in_use;
	u16 size;
	u16 cidx;
	u16 pidx;
	u16 wq_pidx;
	u16 wq_pidx_inc;
};

struct t4_wq {
	struct t4_sq sq;
	struct t4_rq rq;
	void __iomem *db;
	void __iomem *gts;
	struct c4iw_rdev *rdev;
	int flushed;
};

static inline int t4_rqes_posted(struct t4_wq *wq)
{
	return wq->rq.in_use;
}

static inline int t4_rq_empty(struct t4_wq *wq)
{
	return wq->rq.in_use == 0;
}

static inline int t4_rq_full(struct t4_wq *wq)
{
	return wq->rq.in_use == (wq->rq.size - 1);
}

static inline u32 t4_rq_avail(struct t4_wq *wq)
{
	return wq->rq.size - 1 - wq->rq.in_use;
}

static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
{
	wq->rq.in_use++;
	if (++wq->rq.pidx == wq->rq.size)
		wq->rq.pidx = 0;
	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
		wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
}

static inline void t4_rq_consume(struct t4_wq *wq)
{
	wq->rq.in_use--;
	wq->rq.msn++;
	if (++wq->rq.cidx == wq->rq.size)
		wq->rq.cidx = 0;
}

static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
{
	return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
}

static inline u16 t4_rq_wq_size(struct t4_wq *wq)
{
		return wq->rq.size * T4_RQ_NUM_SLOTS;
}

static inline int t4_sq_onchip(struct t4_sq *sq)
{
	return sq->flags & T4_SQ_ONCHIP;
}

static inline int t4_sq_empty(struct t4_wq *wq)
{
	return wq->sq.in_use == 0;
}

static inline int t4_sq_full(struct t4_wq *wq)
{
	return wq->sq.in_use == (wq->sq.size - 1);
}

static inline u32 t4_sq_avail(struct t4_wq *wq)
{
	return wq->sq.size - 1 - wq->sq.in_use;
}

static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
{
	wq->sq.in_use++;
	if (++wq->sq.pidx == wq->sq.size)
		wq->sq.pidx = 0;
	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
		wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
}

static inline void t4_sq_consume(struct t4_wq *wq)
{
	BUG_ON(wq->sq.in_use < 1);
	if (wq->sq.cidx == wq->sq.flush_cidx)
		wq->sq.flush_cidx = -1;
	wq->sq.in_use--;
	if (++wq->sq.cidx == wq->sq.size)
		wq->sq.cidx = 0;
}

static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
{
	return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
}

static inline u16 t4_sq_wq_size(struct t4_wq *wq)
{
		return wq->sq.size * T4_SQ_NUM_SLOTS;
}

/* This function copies 64 byte coalesced work request to memory
 * mapped BAR2 space. For coalesced WRs, the SGE fetches data
 * from the FIFO instead of from Host.
 */
static inline void pio_copy(u64 __iomem *dst, u64 *src)
{
	int count = 8;

	while (count) {
		writeq(*src, dst);
		src++;
		dst++;
		count--;
	}
}

static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
				 union t4_wr *wqe)
{

	/* Flush host queue memory writes. */
	wmb();
	if (t5) {
		if (inc == 1 && wqe) {
			PDBG("%s: WC wq->sq.pidx = %d\n",
			     __func__, wq->sq.pidx);
			pio_copy(wq->sq.udb + 7, (void *)wqe);
		} else {
			PDBG("%s: DB wq->sq.pidx = %d\n",
			     __func__, wq->sq.pidx);
			writel(PIDX_T5(inc), wq->sq.udb);
		}

		/* Flush user doorbell area writes. */
		wmb();
		return;
	}
	writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
}

static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
				 union t4_recv_wr *wqe)
{

	/* Flush host queue memory writes. */
	wmb();
	if (t5) {
		if (inc == 1 && wqe) {
			PDBG("%s: WC wq->rq.pidx = %d\n",
			     __func__, wq->rq.pidx);
			pio_copy(wq->rq.udb + 7, (void *)wqe);
		} else {
			PDBG("%s: DB wq->rq.pidx = %d\n",
			     __func__, wq->rq.pidx);
			writel(PIDX_T5(inc), wq->rq.udb);
		}

		/* Flush user doorbell area writes. */
		wmb();
		return;
	}
	writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
}

static inline int t4_wq_in_error(struct t4_wq *wq)
{
	return wq->rq.queue[wq->rq.size].status.qp_err;
}

static inline void t4_set_wq_in_error(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.qp_err = 1;
}

static inline void t4_disable_wq_db(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.db_off = 1;
}

static inline void t4_enable_wq_db(struct t4_wq *wq)
{
	wq->rq.queue[wq->rq.size].status.db_off = 0;
}

static inline int t4_wq_db_enabled(struct t4_wq *wq)
{
	return !wq->rq.queue[wq->rq.size].status.db_off;
}

struct t4_cq {
	struct t4_cqe *queue;
	dma_addr_t dma_addr;
	DEFINE_DMA_UNMAP_ADDR(mapping);
	struct t4_cqe *sw_queue;
	void __iomem *gts;
	struct c4iw_rdev *rdev;
	u64 ugts;
	size_t memsize;
	__be64 bits_type_ts;
	u32 cqid;
	u16 size; /* including status page */
	u16 cidx;
	u16 sw_pidx;
	u16 sw_cidx;
	u16 sw_in_use;
	u16 cidx_inc;
	u8 gen;
	u8 error;
};

static inline int t4_arm_cq(struct t4_cq *cq, int se)
{
	u32 val;

	while (cq->cidx_inc > CIDXINC_MASK) {
		val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |
		      INGRESSQID(cq->cqid);
		writel(val, cq->gts);
		cq->cidx_inc -= CIDXINC_MASK;
	}
	val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |
	      INGRESSQID(cq->cqid);
	writel(val, cq->gts);
	cq->cidx_inc = 0;
	return 0;
}

static inline void t4_swcq_produce(struct t4_cq *cq)
{
	cq->sw_in_use++;
	if (cq->sw_in_use == cq->size) {
		PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
		cq->error = 1;
		BUG_ON(1);
	}
	if (++cq->sw_pidx == cq->size)
		cq->sw_pidx = 0;
}

static inline void t4_swcq_consume(struct t4_cq *cq)
{
	BUG_ON(cq->sw_in_use < 1);
	cq->sw_in_use--;
	if (++cq->sw_cidx == cq->size)
		cq->sw_cidx = 0;
}

static inline void t4_hwcq_consume(struct t4_cq *cq)
{
	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
	if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_MASK) {
		u32 val;

		val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) |
		      INGRESSQID(cq->cqid);
		writel(val, cq->gts);
		cq->cidx_inc = 0;
	}
	if (++cq->cidx == cq->size) {
		cq->cidx = 0;
		cq->gen ^= 1;
	}
}

static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
{
	return (CQE_GENBIT(cqe) == cq->gen);
}

static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
{
	int ret;
	u16 prev_cidx;

	if (cq->cidx == 0)
		prev_cidx = cq->size - 1;
	else
		prev_cidx = cq->cidx - 1;

	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
		ret = -EOVERFLOW;
		cq->error = 1;
		printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
		BUG_ON(1);
	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {

		/* Ensure CQE is flushed to memory */
		rmb();
		*cqe = &cq->queue[cq->cidx];
		ret = 0;
	} else
		ret = -ENODATA;
	return ret;
}

static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
{
	if (cq->sw_in_use == cq->size) {
		PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
		cq->error = 1;
		BUG_ON(1);
		return NULL;
	}
	if (cq->sw_in_use)
		return &cq->sw_queue[cq->sw_cidx];
	return NULL;
}

static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
{
	int ret = 0;

	if (cq->error)
		ret = -ENODATA;
	else if (cq->sw_in_use)
		*cqe = &cq->sw_queue[cq->sw_cidx];
	else
		ret = t4_next_hw_cqe(cq, cqe);
	return ret;
}

static inline int t4_cq_in_error(struct t4_cq *cq)
{
	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
}

static inline void t4_set_cq_in_error(struct t4_cq *cq)
{
	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
}
#endif

struct t4_dev_status_page {
	u8 db_off;
};
Commit	Line	Data
cfdda9d7 SW	1	/*
	2	* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	* - Redistributions in binary form must reproduce the above
	18	* copyright notice, this list of conditions and the following
	19	* disclaimer in the documentation and/or other materials
	20	* provided with the distribution.
	21	*
	22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	23	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	24	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	25	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	26	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	27	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	28	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	29	* SOFTWARE.
	30	*/
	31	#ifndef __T4_H__
	32	#define __T4_H__
	33
	34	#include "t4_hw.h"
	35	#include "t4_regs.h"
	36	#include "t4_msg.h"
	37	#include "t4fw_ri_api.h"
	38
1cf24dce SW	39	#define T4_MAX_NUM_QP 65536
	40	#define T4_MAX_NUM_CQ 65536
	41	#define T4_MAX_NUM_PD 65536
f64b8843 SW	42	#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
	43	#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
	44	#define T4_MAX_IQ_SIZE (65520 - 1)
	45	#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
	46	#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
	47	#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
	48	#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
cfdda9d7	49	#define T4_MAX_NUM_STAG (1<<15)
a2de1499	50	#define T4_MAX_MR_SIZE (~0ULL)
cfdda9d7 SW	51	#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
	52	#define T4_STAG_UNSET 0xffffffff
	53	#define T4_FW_MAJ 0
	54	#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
c6d7b267	55	#define A_PCIE_MA_SYNC 0x30b4
cfdda9d7 SW	56
	57	struct t4_status_page {
	58	__be32 rsvd1; /* flit 0 - hw owns */
	59	__be16 rsvd2;
	60	__be16 qid;
	61	__be16 cidx;
	62	__be16 pidx;
	63	u8 qp_err; /* flit 1 - sw owns */
	64	u8 db_off;
422eea0a VP	65	u8 pad;
	66	u16 host_wq_pidx;
	67	u16 host_cidx;
	68	u16 host_pidx;
cfdda9d7 SW	69	};
cfdda9d7 SW	70
d37ac31d	71	#define T4_EQ_ENTRY_SIZE 64
cfdda9d7	72
40dbf6ee	73	#define T4_SQ_NUM_SLOTS 5
d37ac31d	74	#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
cfdda9d7 SW	75	#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
	76	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	77	#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
	78	sizeof(struct fw_ri_immd)))
	79	#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
	80	sizeof(struct fw_ri_rdma_write_wr) - \
	81	sizeof(struct fw_ri_immd)))
	82	#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
	83	sizeof(struct fw_ri_rdma_write_wr) - \
	84	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	85	#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
40dbf6ee	86	sizeof(struct fw_ri_immd)) & ~31UL)
42b6a949	87	#define T4_MAX_FR_DEPTH (1024 / sizeof(u64))
cfdda9d7 SW	88
cfdda9d7 SW	89	#define T4_RQ_NUM_SLOTS 2
d37ac31d	90	#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
f64b8843	91	#define T4_MAX_RECV_SGE 4
cfdda9d7 SW	92
	93	union t4_wr {
	94	struct fw_ri_res_wr res;
	95	struct fw_ri_wr ri;
	96	struct fw_ri_rdma_write_wr write;
	97	struct fw_ri_send_wr send;
	98	struct fw_ri_rdma_read_wr read;
	99	struct fw_ri_bind_mw_wr bind;
	100	struct fw_ri_fr_nsmr_wr fr;
	101	struct fw_ri_inv_lstag_wr inv;
	102	struct t4_status_page status;
d37ac31d	103	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
cfdda9d7 SW	104	};
	105
	106	union t4_recv_wr {
	107	struct fw_ri_recv_wr recv;
	108	struct t4_status_page status;
d37ac31d	109	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
cfdda9d7 SW	110	};
	111
	112	static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
	113	enum fw_wr_opcodes opcode, u8 flags, u8 len16)
	114	{
cfdda9d7 SW	115	wqe->send.opcode = (u8)opcode;
	116	wqe->send.flags = flags;
	117	wqe->send.wrid = wrid;
	118	wqe->send.r1[0] = 0;
	119	wqe->send.r1[1] = 0;
	120	wqe->send.r1[2] = 0;
	121	wqe->send.len16 = len16;
cfdda9d7 SW	122	}
	123
	124	/* CQE/AE status codes */
	125	#define T4_ERR_SUCCESS 0x0
	126	#define T4_ERR_STAG 0x1 /* STAG invalid: either the */
	127	/* STAG is offlimt, being 0, */
	128	/* or STAG_key mismatch */
	129	#define T4_ERR_PDID 0x2 /* PDID mismatch */
	130	#define T4_ERR_QPID 0x3 /* QPID mismatch */
	131	#define T4_ERR_ACCESS 0x4 /* Invalid access right */
	132	#define T4_ERR_WRAP 0x5 /* Wrap error */
	133	#define T4_ERR_BOUND 0x6 /* base and bounds voilation */
	134	#define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
	135	/* shared memory region */
	136	#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
	137	/* shared memory region */
	138	#define T4_ERR_ECC 0x9 /* ECC error detected */
	139	#define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
	140	/* reading PSTAG for a MW */
	141	/* Invalidate */
	142	#define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
	143	/* software error */
	144	#define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
	145	#define T4_ERR_CRC 0x10 /* CRC error */
	146	#define T4_ERR_MARKER 0x11 /* Marker error */
	147	#define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
	148	#define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
	149	#define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
	150	#define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
	151	#define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
	152	#define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
	153	#define T4_ERR_MSN 0x18 /* MSN error */
	154	#define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
	155	#define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
	156	/* or READ_REQ */
	157	#define T4_ERR_MSN_GAP 0x1B
	158	#define T4_ERR_MSN_RANGE 0x1C
	159	#define T4_ERR_IRD_OVERFLOW 0x1D
	160	#define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
	161	/* software error */
	162	#define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
	163	/* mismatch) */
	164	/*
	165	* CQE defs
	166	*/
	167	struct t4_cqe {
	168	__be32 header;
	169	__be32 len;
	170	union {
	171	struct {
	172	__be32 stag;
	173	__be32 msn;
	174	} rcqe;
	175	struct {
	176	u32 nada1;
	177	u16 nada2;
	178	u16 cidx;
	179	} scqe;
	180	struct {
	181	__be32 wrid_hi;
	182	__be32 wrid_low;
	183	} gen;
	184	} u;
	185	__be64 reserved;
186	__be64 bits_type_ts;
187	};
188
189	/* macros for flit 0 of the cqe */
190
191	#define S_CQE_QPID 12
192	#define M_CQE_QPID 0xFFFFF
193	#define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
194	#define V_CQE_QPID(x) ((x)<<S_CQE_QPID)
195
196	#define S_CQE_SWCQE 11
197	#define M_CQE_SWCQE 0x1
198	#define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
199	#define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE)
200
201	#define S_CQE_STATUS 5
202	#define M_CQE_STATUS 0x1F
203	#define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
204	#define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS)
205
206	#define S_CQE_TYPE 4
207	#define M_CQE_TYPE 0x1
208	#define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
209	#define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE)
210
211	#define S_CQE_OPCODE 0
212	#define M_CQE_OPCODE 0xF
213	#define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
214	#define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE)
215
216	#define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header)))
217	#define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header)))
218	#define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header)))
219	#define SQ_TYPE(x) (CQE_TYPE((x)))
220	#define RQ_TYPE(x) (!CQE_TYPE((x)))
221	#define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header)))
222	#define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header)))
223
224	#define CQE_SEND_OPCODE(x)( \
225	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) \|\| \
226	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) \|\| \
227	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) \|\| \
228	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
229
230	#define CQE_LEN(x) (be32_to_cpu((x)->len))
231
232	/* used for RQ completion processing */
233	#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
234	#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
235
236	/* used for SQ completion processing */
237	#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
238
239	/* generic accessor macros */
240	#define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi)
241	#define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low)
242
243	/* macros for flit 3 of the cqe */
244	#define S_CQE_GENBIT 63
245	#define M_CQE_GENBIT 0x1
246	#define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
247	#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
248
249	#define S_CQE_OVFBIT 62
250	#define M_CQE_OVFBIT 0x1
251	#define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
252
253	#define S_CQE_IQTYPE 60
254	#define M_CQE_IQTYPE 0x3
255	#define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
256
257	#define M_CQE_TS 0x0fffffffffffffffULL
258	#define G_CQE_TS(x) ((x) & M_CQE_TS)
259
260	#define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
261	#define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
262	#define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
263
264	struct t4_swsqe {
265	u64 wr_id;
266	struct t4_cqe cqe;
267	int read_len;
268	int opcode;
269	int complete;
270	int signaled;
271	u16 idx;
1cf24dce	272	int flushed;
cfdda9d7 SW	273	};
cfdda9d7 SW	274
c6d7b267 SW	275	static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
c6d7b267 SW	276	{
e297d9dd	277	#if defined(__i386__) \|\| defined(__x86_64__) \|\| defined(CONFIG_PPC64)
c6d7b267	278	return pgprot_writecombine(prot);
c6d7b267 SW	279	#else
	280	return pgprot_noncached(prot);
	281	#endif
	282	}
	283
c6d7b267 SW	284	enum {
	285	T4_SQ_ONCHIP = (1<<0),
	286	};
	287
cfdda9d7 SW	288	struct t4_sq {
	289	union t4_wr *queue;
	290	dma_addr_t dma_addr;
f38926aa	291	DEFINE_DMA_UNMAP_ADDR(mapping);
c6d7b267	292	unsigned long phys_addr;
cfdda9d7 SW	293	struct t4_swsqe *sw_sq;
cfdda9d7 SW	294	struct t4_swsqe *oldest_read;
fa658a98	295	u64 __iomem *udb;
cfdda9d7 SW	296	size_t memsize;
	297	u32 qid;
	298	u16 in_use;
	299	u16 size;
	300	u16 cidx;
	301	u16 pidx;
d37ac31d	302	u16 wq_pidx;
05eb2389	303	u16 wq_pidx_inc;
c6d7b267	304	u16 flags;
1cf24dce	305	short flush_cidx;
cfdda9d7 SW	306	};
	307
	308	struct t4_swrqe {
	309	u64 wr_id;
	310	};
	311
	312	struct t4_rq {
	313	union t4_recv_wr *queue;
	314	dma_addr_t dma_addr;
f38926aa	315	DEFINE_DMA_UNMAP_ADDR(mapping);
cfdda9d7	316	struct t4_swrqe *sw_rq;
fa658a98	317	u64 __iomem *udb;
cfdda9d7 SW	318	size_t memsize;
	319	u32 qid;
	320	u32 msn;
	321	u32 rqt_hwaddr;
	322	u16 rqt_size;
	323	u16 in_use;
	324	u16 size;
	325	u16 cidx;
	326	u16 pidx;
d37ac31d	327	u16 wq_pidx;
05eb2389	328	u16 wq_pidx_inc;
cfdda9d7 SW	329	};
	330
	331	struct t4_wq {
	332	struct t4_sq sq;
	333	struct t4_rq rq;
	334	void __iomem *db;
	335	void __iomem *gts;
	336	struct c4iw_rdev *rdev;
1cf24dce	337	int flushed;
cfdda9d7 SW	338	};
	339
	340	static inline int t4_rqes_posted(struct t4_wq *wq)
	341	{
	342	return wq->rq.in_use;
	343	}
	344
	345	static inline int t4_rq_empty(struct t4_wq *wq)
	346	{
	347	return wq->rq.in_use == 0;
	348	}
	349
	350	static inline int t4_rq_full(struct t4_wq *wq)
	351	{
	352	return wq->rq.in_use == (wq->rq.size - 1);
	353	}
	354
	355	static inline u32 t4_rq_avail(struct t4_wq *wq)
	356	{
	357	return wq->rq.size - 1 - wq->rq.in_use;
	358	}
	359
d37ac31d	360	static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
cfdda9d7 SW	361	{
	362	wq->rq.in_use++;
	363	if (++wq->rq.pidx == wq->rq.size)
	364	wq->rq.pidx = 0;
d37ac31d SW	365	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	366	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
	367	wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
cfdda9d7 SW	368	}
	369
	370	static inline void t4_rq_consume(struct t4_wq *wq)
	371	{
	372	wq->rq.in_use--;
	373	wq->rq.msn++;
	374	if (++wq->rq.cidx == wq->rq.size)
	375	wq->rq.cidx = 0;
	376	}
	377
422eea0a VP	378	static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
	379	{
	380	return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
	381	}
	382
	383	static inline u16 t4_rq_wq_size(struct t4_wq *wq)
	384	{
	385	return wq->rq.size * T4_RQ_NUM_SLOTS;
	386	}
	387
c6d7b267 SW	388	static inline int t4_sq_onchip(struct t4_sq *sq)
	389	{
	390	return sq->flags & T4_SQ_ONCHIP;
	391	}
	392
cfdda9d7 SW	393	static inline int t4_sq_empty(struct t4_wq *wq)
	394	{
	395	return wq->sq.in_use == 0;
	396	}
	397
	398	static inline int t4_sq_full(struct t4_wq *wq)
	399	{
	400	return wq->sq.in_use == (wq->sq.size - 1);
	401	}
	402
	403	static inline u32 t4_sq_avail(struct t4_wq *wq)
	404	{
	405	return wq->sq.size - 1 - wq->sq.in_use;
	406	}
	407
d37ac31d	408	static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
cfdda9d7 SW	409	{
	410	wq->sq.in_use++;
	411	if (++wq->sq.pidx == wq->sq.size)
	412	wq->sq.pidx = 0;
d37ac31d SW	413	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
	414	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
	415	wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
cfdda9d7 SW	416	}
	417
	418	static inline void t4_sq_consume(struct t4_wq *wq)
	419	{
1cf24dce SW	420	BUG_ON(wq->sq.in_use < 1);
	421	if (wq->sq.cidx == wq->sq.flush_cidx)
	422	wq->sq.flush_cidx = -1;
cfdda9d7 SW	423	wq->sq.in_use--;
	424	if (++wq->sq.cidx == wq->sq.size)
	425	wq->sq.cidx = 0;
	426	}
	427
422eea0a VP	428	static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
	429	{
	430	return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
	431	}
	432
	433	static inline u16 t4_sq_wq_size(struct t4_wq *wq)
	434	{
	435	return wq->sq.size * T4_SQ_NUM_SLOTS;
	436	}
	437
fa658a98 SW	438	/* This function copies 64 byte coalesced work request to memory
	439	* mapped BAR2 space. For coalesced WRs, the SGE fetches data
	440	* from the FIFO instead of from Host.
	441	*/
	442	static inline void pio_copy(u64 __iomem dst, u64 src)
	443	{
	444	int count = 8;
	445
	446	while (count) {
	447	writeq(*src, dst);
	448	src++;
	449	dst++;
	450	count--;
	451	}
	452	}
	453
	454	static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
	455	union t4_wr *wqe)
cfdda9d7	456	{
fa658a98 SW	457
fa658a98 SW	458	/* Flush host queue memory writes. */
cfdda9d7	459	wmb();
fa658a98 SW	460	if (t5) {
	461	if (inc == 1 && wqe) {
	462	PDBG("%s: WC wq->sq.pidx = %d\n",
	463	__func__, wq->sq.pidx);
	464	pio_copy(wq->sq.udb + 7, (void *)wqe);
	465	} else {
	466	PDBG("%s: DB wq->sq.pidx = %d\n",
	467	__func__, wq->sq.pidx);
	468	writel(PIDX_T5(inc), wq->sq.udb);
	469	}
	470
	471	/* Flush user doorbell area writes. */
	472	wmb();
	473	return;
	474	}
cfdda9d7 SW	475	writel(QID(wq->sq.qid) \| PIDX(inc), wq->db);
	476	}
	477
fa658a98 SW	478	static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
fa658a98 SW	479	union t4_recv_wr *wqe)
cfdda9d7	480	{
fa658a98 SW	481
fa658a98 SW	482	/* Flush host queue memory writes. */
cfdda9d7	483	wmb();
fa658a98 SW	484	if (t5) {
	485	if (inc == 1 && wqe) {
	486	PDBG("%s: WC wq->rq.pidx = %d\n",
	487	__func__, wq->rq.pidx);
	488	pio_copy(wq->rq.udb + 7, (void *)wqe);
	489	} else {
	490	PDBG("%s: DB wq->rq.pidx = %d\n",
	491	__func__, wq->rq.pidx);
	492	writel(PIDX_T5(inc), wq->rq.udb);
	493	}
	494
	495	/* Flush user doorbell area writes. */
	496	wmb();
	497	return;
	498	}
cfdda9d7 SW	499	writel(QID(wq->rq.qid) \| PIDX(inc), wq->db);
	500	}
	501
	502	static inline int t4_wq_in_error(struct t4_wq *wq)
	503	{
c6d7b267	504	return wq->rq.queue[wq->rq.size].status.qp_err;
cfdda9d7 SW	505	}
	506
	507	static inline void t4_set_wq_in_error(struct t4_wq *wq)
	508	{
cfdda9d7 SW	509	wq->rq.queue[wq->rq.size].status.qp_err = 1;
	510	}
	511
	512	static inline void t4_disable_wq_db(struct t4_wq *wq)
	513	{
cfdda9d7 SW	514	wq->rq.queue[wq->rq.size].status.db_off = 1;
	515	}
	516
	517	static inline void t4_enable_wq_db(struct t4_wq *wq)
	518	{
cfdda9d7 SW	519	wq->rq.queue[wq->rq.size].status.db_off = 0;
	520	}
	521
	522	static inline int t4_wq_db_enabled(struct t4_wq *wq)
	523	{
c6d7b267	524	return !wq->rq.queue[wq->rq.size].status.db_off;
cfdda9d7 SW	525	}
	526
	527	struct t4_cq {
	528	struct t4_cqe *queue;
	529	dma_addr_t dma_addr;
f38926aa	530	DEFINE_DMA_UNMAP_ADDR(mapping);
cfdda9d7 SW	531	struct t4_cqe *sw_queue;
	532	void __iomem *gts;
	533	struct c4iw_rdev *rdev;
	534	u64 ugts;
	535	size_t memsize;
84172dee	536	__be64 bits_type_ts;
cfdda9d7 SW	537	u32 cqid;
	538	u16 size; /* including status page */
	539	u16 cidx;
	540	u16 sw_pidx;
	541	u16 sw_cidx;
	542	u16 sw_in_use;
	543	u16 cidx_inc;
	544	u8 gen;
	545	u8 error;
	546	};
	547
	548	static inline int t4_arm_cq(struct t4_cq *cq, int se)
	549	{
	550	u32 val;
7ec45b92 SW	551
	552	while (cq->cidx_inc > CIDXINC_MASK) {
	553	val = SEINTARM(0) \| CIDXINC(CIDXINC_MASK) \| TIMERREG(7) \|
	554	INGRESSQID(cq->cqid);
be4c9bad	555	writel(val, cq->gts);
7ec45b92 SW	556	cq->cidx_inc -= CIDXINC_MASK;
	557	}
	558	val = SEINTARM(se) \| CIDXINC(cq->cidx_inc) \| TIMERREG(6) \|
	559	INGRESSQID(cq->cqid);
	560	writel(val, cq->gts);
	561	cq->cidx_inc = 0;
cfdda9d7 SW	562	return 0;
	563	}
	564
	565	static inline void t4_swcq_produce(struct t4_cq *cq)
	566	{
	567	cq->sw_in_use++;
1cf24dce SW	568	if (cq->sw_in_use == cq->size) {
	569	PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
	570	cq->error = 1;
	571	BUG_ON(1);
	572	}
cfdda9d7 SW	573	if (++cq->sw_pidx == cq->size)
	574	cq->sw_pidx = 0;
	575	}
	576
	577	static inline void t4_swcq_consume(struct t4_cq *cq)
	578	{
1cf24dce	579	BUG_ON(cq->sw_in_use < 1);
cfdda9d7 SW	580	cq->sw_in_use--;
	581	if (++cq->sw_cidx == cq->size)
	582	cq->sw_cidx = 0;
	583	}
	584
	585	static inline void t4_hwcq_consume(struct t4_cq *cq)
	586	{
84172dee	587	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
b298881f	588	if (++cq->cidx_inc == (cq->size >> 4) \|\| cq->cidx_inc == CIDXINC_MASK) {
ffc3f748 SW	589	u32 val;
	590
	591	val = SEINTARM(0) \| CIDXINC(cq->cidx_inc) \| TIMERREG(7) \|
	592	INGRESSQID(cq->cqid);
	593	writel(val, cq->gts);
7ec45b92	594	cq->cidx_inc = 0;
ffc3f748	595	}
cfdda9d7 SW	596	if (++cq->cidx == cq->size) {
	597	cq->cidx = 0;
	598	cq->gen ^= 1;
	599	}
	600	}
	601
	602	static inline int t4_valid_cqe(struct t4_cq cq, struct t4_cqe cqe)
	603	{
	604	return (CQE_GENBIT(cqe) == cq->gen);
	605	}
	606
	607	static inline int t4_next_hw_cqe(struct t4_cq cq, struct t4_cqe *cqe)
	608	{
84172dee SW	609	int ret;
84172dee SW	610	u16 prev_cidx;
cfdda9d7	611
84172dee SW	612	if (cq->cidx == 0)
84172dee SW	613	prev_cidx = cq->size - 1;
cfdda9d7	614	else
84172dee SW	615	prev_cidx = cq->cidx - 1;
	616
	617	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
	618	ret = -EOVERFLOW;
cfdda9d7	619	cq->error = 1;
84172dee	620	printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
1cf24dce	621	BUG_ON(1);
84172dee	622	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
def4771f SW	623
	624	/* Ensure CQE is flushed to memory */
	625	rmb();
84172dee SW	626	*cqe = &cq->queue[cq->cidx];
	627	ret = 0;
	628	} else
	629	ret = -ENODATA;
cfdda9d7 SW	630	return ret;
	631	}
	632
	633	static inline struct t4_cqe t4_next_sw_cqe(struct t4_cq cq)
	634	{
1cf24dce SW	635	if (cq->sw_in_use == cq->size) {
	636	PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid);
	637	cq->error = 1;
	638	BUG_ON(1);
	639	return NULL;
	640	}
cfdda9d7 SW	641	if (cq->sw_in_use)
	642	return &cq->sw_queue[cq->sw_cidx];
	643	return NULL;
	644	}
	645
	646	static inline int t4_next_cqe(struct t4_cq cq, struct t4_cqe *cqe)
	647	{
	648	int ret = 0;
	649
	650	if (cq->error)
	651	ret = -ENODATA;
	652	else if (cq->sw_in_use)
	653	*cqe = &cq->sw_queue[cq->sw_cidx];
	654	else
	655	ret = t4_next_hw_cqe(cq, cqe);
	656	return ret;
	657	}
	658
	659	static inline int t4_cq_in_error(struct t4_cq *cq)
	660	{
	661	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
	662	}
	663
	664	static inline void t4_set_cq_in_error(struct t4_cq *cq)
	665	{
	666	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
	667	}
	668	#endif
05eb2389 SW	669
	670	struct t4_dev_status_page {
	671	u8 db_off;
	672	};