[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / t4.h

/*
 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __T4_H__
#define __T4_H__

#include "t4_hw.h"
#include "t4_regs.h"
#include "t4_msg.h"
#include "t4fw_ri_api.h"

#define T4_QID_BASE 1024
#define T4_MAX_QIDS 256
#define T4_MAX_NUM_QP (1<<16)
#define T4_MAX_NUM_CQ (1<<15)
#define T4_MAX_NUM_PD (1<<15)
#define T4_MAX_PBL_SIZE 256
#define T4_MAX_RQ_SIZE 1024
#define T4_MAX_SQ_SIZE 1024
#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE-1)
#define T4_MAX_CQ_DEPTH 8192
#define T4_MAX_NUM_STAG (1<<15)
#define T4_MAX_MR_SIZE (~0ULL - 1)
#define T4_PAGESIZE_MASK 0xffff000  /* 4KB-128MB */
#define T4_STAG_UNSET 0xffffffff
#define T4_FW_MAJ 0
#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)

struct t4_status_page {
	__be32 rsvd1;	/* flit 0 - hw owns */
	__be16 rsvd2;
	__be16 qid;
	__be16 cidx;
	__be16 pidx;
	u8 qp_err;	/* flit 1 - sw owns */
	u8 db_off;
};

#define T4_EQ_SIZE 64

#define T4_SQ_NUM_SLOTS 4
#define T4_SQ_NUM_BYTES (T4_EQ_SIZE * T4_SQ_NUM_SLOTS)
#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
			sizeof(struct fw_ri_rdma_write_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
			sizeof(struct fw_ri_rdma_write_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
			sizeof(struct fw_ri_immd)))
#define T4_MAX_FR_DEPTH 255

#define T4_RQ_NUM_SLOTS 2
#define T4_RQ_NUM_BYTES (T4_EQ_SIZE * T4_RQ_NUM_SLOTS)
#define T4_MAX_RECV_SGE ((T4_RQ_NUM_BYTES - sizeof(struct fw_ri_recv_wr) - \
			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))

union t4_wr {
	struct fw_ri_res_wr res;
	struct fw_ri_wr ri;
	struct fw_ri_rdma_write_wr write;
	struct fw_ri_send_wr send;
	struct fw_ri_rdma_read_wr read;
	struct fw_ri_bind_mw_wr bind;
	struct fw_ri_fr_nsmr_wr fr;
	struct fw_ri_inv_lstag_wr inv;
	struct t4_status_page status;
	__be64 flits[T4_EQ_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
};

union t4_recv_wr {
	struct fw_ri_recv_wr recv;
	struct t4_status_page status;
	__be64 flits[T4_EQ_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
};

static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
			       enum fw_wr_opcodes opcode, u8 flags, u8 len16)
{
	int slots_used;

	wqe->send.opcode = (u8)opcode;
	wqe->send.flags = flags;
	wqe->send.wrid = wrid;
	wqe->send.r1[0] = 0;
	wqe->send.r1[1] = 0;
	wqe->send.r1[2] = 0;
	wqe->send.len16 = len16;

	slots_used = DIV_ROUND_UP(len16*16, T4_EQ_SIZE);
	while (slots_used < T4_SQ_NUM_SLOTS) {
		wqe->flits[slots_used * T4_EQ_SIZE / sizeof(__be64)] = 0;
		slots_used++;
	}
}

/* CQE/AE status codes */
#define T4_ERR_SUCCESS                     0x0
#define T4_ERR_STAG                        0x1	/* STAG invalid: either the */
						/* STAG is offlimt, being 0, */
						/* or STAG_key mismatch */
#define T4_ERR_PDID                        0x2	/* PDID mismatch */
#define T4_ERR_QPID                        0x3	/* QPID mismatch */
#define T4_ERR_ACCESS                      0x4	/* Invalid access right */
#define T4_ERR_WRAP                        0x5	/* Wrap error */
#define T4_ERR_BOUND                       0x6	/* base and bounds voilation */
#define T4_ERR_INVALIDATE_SHARED_MR        0x7	/* attempt to invalidate a  */
						/* shared memory region */
#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8	/* attempt to invalidate a  */
						/* shared memory region */
#define T4_ERR_ECC                         0x9	/* ECC error detected */
#define T4_ERR_ECC_PSTAG                   0xA	/* ECC error detected when  */
						/* reading PSTAG for a MW  */
						/* Invalidate */
#define T4_ERR_PBL_ADDR_BOUND              0xB	/* pbl addr out of bounds:  */
						/* software error */
#define T4_ERR_SWFLUSH			   0xC	/* SW FLUSHED */
#define T4_ERR_CRC                         0x10 /* CRC error */
#define T4_ERR_MARKER                      0x11 /* Marker error */
#define T4_ERR_PDU_LEN_ERR                 0x12 /* invalid PDU length */
#define T4_ERR_OUT_OF_RQE                  0x13 /* out of RQE */
#define T4_ERR_DDP_VERSION                 0x14 /* wrong DDP version */
#define T4_ERR_RDMA_VERSION                0x15 /* wrong RDMA version */
#define T4_ERR_OPCODE                      0x16 /* invalid rdma opcode */
#define T4_ERR_DDP_QUEUE_NUM               0x17 /* invalid ddp queue number */
#define T4_ERR_MSN                         0x18 /* MSN error */
#define T4_ERR_TBIT                        0x19 /* tag bit not set correctly */
#define T4_ERR_MO                          0x1A /* MO not 0 for TERMINATE  */
						/* or READ_REQ */
#define T4_ERR_MSN_GAP                     0x1B
#define T4_ERR_MSN_RANGE                   0x1C
#define T4_ERR_IRD_OVERFLOW                0x1D
#define T4_ERR_RQE_ADDR_BOUND              0x1E /* RQE addr out of bounds:  */
						/* software error */
#define T4_ERR_INTERNAL_ERR                0x1F /* internal error (opcode  */
						/* mismatch) */
/*
 * CQE defs
 */
struct t4_cqe {
	__be32 header;
	__be32 len;
	union {
		struct {
			__be32 stag;
			__be32 msn;
		} rcqe;
		struct {
			u32 nada1;
			u16 nada2;
			u16 cidx;
		} scqe;
		struct {
			__be32 wrid_hi;
			__be32 wrid_low;
		} gen;
	} u;
	__be64 reserved;
	__be64 bits_type_ts;
};

/* macros for flit 0 of the cqe */

#define S_CQE_QPID        12
#define M_CQE_QPID        0xFFFFF
#define G_CQE_QPID(x)     ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
#define V_CQE_QPID(x)	  ((x)<<S_CQE_QPID)

#define S_CQE_SWCQE       11
#define M_CQE_SWCQE       0x1
#define G_CQE_SWCQE(x)    ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
#define V_CQE_SWCQE(x)	  ((x)<<S_CQE_SWCQE)

#define S_CQE_STATUS      5
#define M_CQE_STATUS      0x1F
#define G_CQE_STATUS(x)   ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
#define V_CQE_STATUS(x)   ((x)<<S_CQE_STATUS)

#define S_CQE_TYPE        4
#define M_CQE_TYPE        0x1
#define G_CQE_TYPE(x)     ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
#define V_CQE_TYPE(x)     ((x)<<S_CQE_TYPE)

#define S_CQE_OPCODE      0
#define M_CQE_OPCODE      0xF
#define G_CQE_OPCODE(x)   ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
#define V_CQE_OPCODE(x)   ((x)<<S_CQE_OPCODE)

#define SW_CQE(x)         (G_CQE_SWCQE(be32_to_cpu((x)->header)))
#define CQE_QPID(x)       (G_CQE_QPID(be32_to_cpu((x)->header)))
#define CQE_TYPE(x)       (G_CQE_TYPE(be32_to_cpu((x)->header)))
#define SQ_TYPE(x)	  (CQE_TYPE((x)))
#define RQ_TYPE(x)	  (!CQE_TYPE((x)))
#define CQE_STATUS(x)     (G_CQE_STATUS(be32_to_cpu((x)->header)))
#define CQE_OPCODE(x)     (G_CQE_OPCODE(be32_to_cpu((x)->header)))

#define CQE_SEND_OPCODE(x)( \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))

#define CQE_LEN(x)        (be32_to_cpu((x)->len))

/* used for RQ completion processing */
#define CQE_WRID_STAG(x)  (be32_to_cpu((x)->u.rcqe.stag))
#define CQE_WRID_MSN(x)   (be32_to_cpu((x)->u.rcqe.msn))

/* used for SQ completion processing */
#define CQE_WRID_SQ_IDX(x)	((x)->u.scqe.cidx)

/* generic accessor macros */
#define CQE_WRID_HI(x)		((x)->u.gen.wrid_hi)
#define CQE_WRID_LOW(x)		((x)->u.gen.wrid_low)

/* macros for flit 3 of the cqe */
#define S_CQE_GENBIT	63
#define M_CQE_GENBIT	0x1
#define G_CQE_GENBIT(x)	(((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)

#define S_CQE_OVFBIT	62
#define M_CQE_OVFBIT	0x1
#define G_CQE_OVFBIT(x)	((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)

#define S_CQE_IQTYPE	60
#define M_CQE_IQTYPE	0x3
#define G_CQE_IQTYPE(x)	((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)

#define M_CQE_TS	0x0fffffffffffffffULL
#define G_CQE_TS(x)	((x) & M_CQE_TS)

#define CQE_OVFBIT(x)	((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
#define CQE_GENBIT(x)	((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
#define CQE_TS(x)	(G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))

struct t4_swsqe {
	u64			wr_id;
	struct t4_cqe		cqe;
	int			read_len;
	int			opcode;
	int			complete;
	int			signaled;
	u16			idx;
};

struct t4_sq {
	union t4_wr *queue;
	dma_addr_t dma_addr;
	DECLARE_PCI_UNMAP_ADDR(mapping);
	struct t4_swsqe *sw_sq;
	struct t4_swsqe *oldest_read;
	u64 udb;
	size_t memsize;
	u32 qid;
	u16 in_use;
	u16 size;
	u16 cidx;
	u16 pidx;
};

struct t4_swrqe {
	u64 wr_id;
};

struct t4_rq {
	union  t4_recv_wr *queue;
	dma_addr_t dma_addr;
	DECLARE_PCI_UNMAP_ADDR(mapping);
	struct t4_swrqe *sw_rq;
	u64 udb;
	size_t memsize;
	u32 qid;
	u32 msn;
	u32 rqt_hwaddr;
	u16 rqt_size;
	u16 in_use;
	u16 size;
	u16 cidx;
	u16 pidx;
};

struct t4_wq {
	struct t4_sq sq;
	struct t4_rq rq;
	void __iomem *db;
	void __iomem *gts;
	struct c4iw_rdev *rdev;
};

static inline int t4_rqes_posted(struct t4_wq *wq)
{
	return wq->rq.in_use;
}

static inline int t4_rq_empty(struct t4_wq *wq)
{
	return wq->rq.in_use == 0;
}

static inline int t4_rq_full(struct t4_wq *wq)
{
	return wq->rq.in_use == (wq->rq.size - 1);
}

static inline u32 t4_rq_avail(struct t4_wq *wq)
{
	return wq->rq.size - 1 - wq->rq.in_use;
}

static inline void t4_rq_produce(struct t4_wq *wq)
{
	wq->rq.in_use++;
	if (++wq->rq.pidx == wq->rq.size)
		wq->rq.pidx = 0;
}

static inline void t4_rq_consume(struct t4_wq *wq)
{
	wq->rq.in_use--;
	wq->rq.msn++;
	if (++wq->rq.cidx == wq->rq.size)
		wq->rq.cidx = 0;
}

static inline int t4_sq_empty(struct t4_wq *wq)
{
	return wq->sq.in_use == 0;
}

static inline int t4_sq_full(struct t4_wq *wq)
{
	return wq->sq.in_use == (wq->sq.size - 1);
}

static inline u32 t4_sq_avail(struct t4_wq *wq)
{
	return wq->sq.size - 1 - wq->sq.in_use;
}

static inline void t4_sq_produce(struct t4_wq *wq)
{
	wq->sq.in_use++;
	if (++wq->sq.pidx == wq->sq.size)
		wq->sq.pidx = 0;
}

static inline void t4_sq_consume(struct t4_wq *wq)
{
	wq->sq.in_use--;
	if (++wq->sq.cidx == wq->sq.size)
		wq->sq.cidx = 0;
}

static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc)
{
	inc *= T4_SQ_NUM_SLOTS;
	wmb();
	writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
}

static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc)
{
	inc *= T4_RQ_NUM_SLOTS;
	wmb();
	writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
}

static inline int t4_wq_in_error(struct t4_wq *wq)
{
	return wq->sq.queue[wq->sq.size].status.qp_err;
}

static inline void t4_set_wq_in_error(struct t4_wq *wq)
{
	wq->sq.queue[wq->sq.size].status.qp_err = 1;
	wq->rq.queue[wq->rq.size].status.qp_err = 1;
}

static inline void t4_disable_wq_db(struct t4_wq *wq)
{
	wq->sq.queue[wq->sq.size].status.db_off = 1;
	wq->rq.queue[wq->rq.size].status.db_off = 1;
}

static inline void t4_enable_wq_db(struct t4_wq *wq)
{
	wq->sq.queue[wq->sq.size].status.db_off = 0;
	wq->rq.queue[wq->rq.size].status.db_off = 0;
}

static inline int t4_wq_db_enabled(struct t4_wq *wq)
{
	return !wq->sq.queue[wq->sq.size].status.db_off;
}

struct t4_cq {
	struct t4_cqe *queue;
	dma_addr_t dma_addr;
	DECLARE_PCI_UNMAP_ADDR(mapping);
	struct t4_cqe *sw_queue;
	void __iomem *gts;
	struct c4iw_rdev *rdev;
	u64 ugts;
	size_t memsize;
	u64 timestamp;
	u32 cqid;
	u16 size; /* including status page */
	u16 cidx;
	u16 sw_pidx;
	u16 sw_cidx;
	u16 sw_in_use;
	u16 cidx_inc;
	u8 gen;
	u8 error;
};

static inline int t4_arm_cq(struct t4_cq *cq, int se)
{
	u32 val;
	u16 inc;

	do {
		/*
		 * inc must be less the both the max update value -and-
		 * the size of the CQ.
		 */
		inc = cq->cidx_inc <= CIDXINC_MASK ? cq->cidx_inc :
						     CIDXINC_MASK;
		inc = inc <= (cq->size - 1) ? inc : (cq->size - 1);
		if (inc == cq->cidx_inc)
			val = SEINTARM(se) | CIDXINC(inc) | TIMERREG(6) |
			      INGRESSQID(cq->cqid);
		else
			val = SEINTARM(0) | CIDXINC(inc) | TIMERREG(7) |
			      INGRESSQID(cq->cqid);
		cq->cidx_inc -= inc;
		writel(val, cq->gts);
	} while (cq->cidx_inc);
	return 0;
}

static inline void t4_swcq_produce(struct t4_cq *cq)
{
	cq->sw_in_use++;
	if (++cq->sw_pidx == cq->size)
		cq->sw_pidx = 0;
}

static inline void t4_swcq_consume(struct t4_cq *cq)
{
	cq->sw_in_use--;
	if (++cq->sw_cidx == cq->size)
		cq->sw_cidx = 0;
}

static inline void t4_hwcq_consume(struct t4_cq *cq)
{
	cq->cidx_inc++;
	if (++cq->cidx == cq->size) {
		cq->cidx = 0;
		cq->gen ^= 1;
	}
}

static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
{
	return (CQE_GENBIT(cqe) == cq->gen);
}

static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
{
	int ret = 0;
	u64 bits_type_ts = be64_to_cpu(cq->queue[cq->cidx].bits_type_ts);

	if (G_CQE_GENBIT(bits_type_ts) == cq->gen) {
		*cqe = &cq->queue[cq->cidx];
		cq->timestamp = G_CQE_TS(bits_type_ts);
	} else if (G_CQE_TS(bits_type_ts) > cq->timestamp)
		ret = -EOVERFLOW;
	else
		ret = -ENODATA;
	if (ret == -EOVERFLOW) {
		printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
		cq->error = 1;
	}
	return ret;
}

static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
{
	if (cq->sw_in_use)
		return &cq->sw_queue[cq->sw_cidx];
	return NULL;
}

static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
{
	int ret = 0;

	if (cq->error)
		ret = -ENODATA;
	else if (cq->sw_in_use)
		*cqe = &cq->sw_queue[cq->sw_cidx];
	else
		ret = t4_next_hw_cqe(cq, cqe);
	return ret;
}

static inline int t4_cq_in_error(struct t4_cq *cq)
{
	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
}

static inline void t4_set_cq_in_error(struct t4_cq *cq)
{
	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
}
#endif
Commit	Line	Data
cfdda9d7 SW	1	/*
	2	* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	* - Redistributions in binary form must reproduce the above
	18	* copyright notice, this list of conditions and the following
	19	* disclaimer in the documentation and/or other materials
	20	* provided with the distribution.
	21	*
	22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	23	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	24	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	25	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	26	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	27	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	28	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	29	* SOFTWARE.
	30	*/
	31	#ifndef __T4_H__
	32	#define __T4_H__
	33
	34	#include "t4_hw.h"
	35	#include "t4_regs.h"
	36	#include "t4_msg.h"
	37	#include "t4fw_ri_api.h"
	38
cfdda9d7 SW	39	#define T4_QID_BASE 1024
	40	#define T4_MAX_QIDS 256
	41	#define T4_MAX_NUM_QP (1<<16)
	42	#define T4_MAX_NUM_CQ (1<<15)
	43	#define T4_MAX_NUM_PD (1<<15)
	44	#define T4_MAX_PBL_SIZE 256
	45	#define T4_MAX_RQ_SIZE 1024
	46	#define T4_MAX_SQ_SIZE 1024
	47	#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE-1)
	48	#define T4_MAX_CQ_DEPTH 8192
	49	#define T4_MAX_NUM_STAG (1<<15)
	50	#define T4_MAX_MR_SIZE (~0ULL - 1)
	51	#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
	52	#define T4_STAG_UNSET 0xffffffff
	53	#define T4_FW_MAJ 0
	54	#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
	55
	56	struct t4_status_page {
	57	__be32 rsvd1; /* flit 0 - hw owns */
	58	__be16 rsvd2;
	59	__be16 qid;
	60	__be16 cidx;
	61	__be16 pidx;
	62	u8 qp_err; /* flit 1 - sw owns */
	63	u8 db_off;
	64	};
	65
	66	#define T4_EQ_SIZE 64
	67
	68	#define T4_SQ_NUM_SLOTS 4
	69	#define T4_SQ_NUM_BYTES (T4_EQ_SIZE * T4_SQ_NUM_SLOTS)
	70	#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
	71	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	72	#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
	73	sizeof(struct fw_ri_immd)))
	74	#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
	75	sizeof(struct fw_ri_rdma_write_wr) - \
	76	sizeof(struct fw_ri_immd)))
	77	#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
	78	sizeof(struct fw_ri_rdma_write_wr) - \
	79	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	80	#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
	81	sizeof(struct fw_ri_immd)))
	82	#define T4_MAX_FR_DEPTH 255
	83
	84	#define T4_RQ_NUM_SLOTS 2
	85	#define T4_RQ_NUM_BYTES (T4_EQ_SIZE * T4_RQ_NUM_SLOTS)
	86	#define T4_MAX_RECV_SGE ((T4_RQ_NUM_BYTES - sizeof(struct fw_ri_recv_wr) - \
	87	sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
	88
	89	union t4_wr {
	90	struct fw_ri_res_wr res;
	91	struct fw_ri_wr ri;
	92	struct fw_ri_rdma_write_wr write;
	93	struct fw_ri_send_wr send;
	94	struct fw_ri_rdma_read_wr read;
	95	struct fw_ri_bind_mw_wr bind;
	96	struct fw_ri_fr_nsmr_wr fr;
	97	struct fw_ri_inv_lstag_wr inv;
	98	struct t4_status_page status;
	99	__be64 flits[T4_EQ_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
	100	};
	101
	102	union t4_recv_wr {
103	struct fw_ri_recv_wr recv;
104	struct t4_status_page status;
105	__be64 flits[T4_EQ_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
106	};
107
108	static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
109	enum fw_wr_opcodes opcode, u8 flags, u8 len16)
110	{
111	int slots_used;
112
113	wqe->send.opcode = (u8)opcode;
114	wqe->send.flags = flags;
115	wqe->send.wrid = wrid;
116	wqe->send.r1[0] = 0;
117	wqe->send.r1[1] = 0;
118	wqe->send.r1[2] = 0;
119	wqe->send.len16 = len16;
120
121	slots_used = DIV_ROUND_UP(len16*16, T4_EQ_SIZE);
122	while (slots_used < T4_SQ_NUM_SLOTS) {
123	wqe->flits[slots_used * T4_EQ_SIZE / sizeof(__be64)] = 0;
124	slots_used++;
125	}
126	}
127
128	/* CQE/AE status codes */
129	#define T4_ERR_SUCCESS 0x0
130	#define T4_ERR_STAG 0x1 /* STAG invalid: either the */
131	/* STAG is offlimt, being 0, */
132	/* or STAG_key mismatch */
133	#define T4_ERR_PDID 0x2 /* PDID mismatch */
134	#define T4_ERR_QPID 0x3 /* QPID mismatch */
135	#define T4_ERR_ACCESS 0x4 /* Invalid access right */
136	#define T4_ERR_WRAP 0x5 /* Wrap error */
137	#define T4_ERR_BOUND 0x6 /* base and bounds voilation */
138	#define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
139	/* shared memory region */
140	#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
141	/* shared memory region */
142	#define T4_ERR_ECC 0x9 /* ECC error detected */
143	#define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
144	/* reading PSTAG for a MW */
145	/* Invalidate */
146	#define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
147	/* software error */
148	#define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
149	#define T4_ERR_CRC 0x10 /* CRC error */
150	#define T4_ERR_MARKER 0x11 /* Marker error */
151	#define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
152	#define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
153	#define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
154	#define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
155	#define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
156	#define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
157	#define T4_ERR_MSN 0x18 /* MSN error */
158	#define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
159	#define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
160	/* or READ_REQ */
161	#define T4_ERR_MSN_GAP 0x1B
162	#define T4_ERR_MSN_RANGE 0x1C
163	#define T4_ERR_IRD_OVERFLOW 0x1D
164	#define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
165	/* software error */
166	#define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
167	/* mismatch) */
168	/*
169	* CQE defs
170	*/
171	struct t4_cqe {
172	__be32 header;
173	__be32 len;
174	union {
175	struct {
176	__be32 stag;
177	__be32 msn;
178	} rcqe;
179	struct {
180	u32 nada1;
181	u16 nada2;
182	u16 cidx;
183	} scqe;
184	struct {
185	__be32 wrid_hi;
186	__be32 wrid_low;
187	} gen;
188	} u;
189	__be64 reserved;
190	__be64 bits_type_ts;
191	};
192
193	/* macros for flit 0 of the cqe */
194
195	#define S_CQE_QPID 12
196	#define M_CQE_QPID 0xFFFFF
197	#define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
198	#define V_CQE_QPID(x) ((x)<<S_CQE_QPID)
199
200	#define S_CQE_SWCQE 11
201	#define M_CQE_SWCQE 0x1
202	#define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
203	#define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE)
204
205	#define S_CQE_STATUS 5
206	#define M_CQE_STATUS 0x1F
207	#define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
208	#define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS)
209
210	#define S_CQE_TYPE 4
211	#define M_CQE_TYPE 0x1
212	#define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
213	#define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE)
214
215	#define S_CQE_OPCODE 0
216	#define M_CQE_OPCODE 0xF
217	#define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
218	#define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE)
219
220	#define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header)))
221	#define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header)))
222	#define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header)))
223	#define SQ_TYPE(x) (CQE_TYPE((x)))
224	#define RQ_TYPE(x) (!CQE_TYPE((x)))
225	#define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header)))
226	#define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header)))
227
228	#define CQE_SEND_OPCODE(x)( \
229	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) \|\| \
230	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) \|\| \
231	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) \|\| \
232	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
233
234	#define CQE_LEN(x) (be32_to_cpu((x)->len))
235
236	/* used for RQ completion processing */
237	#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
238	#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
239
240	/* used for SQ completion processing */
241	#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
242
243	/* generic accessor macros */
244	#define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi)
245	#define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low)
246
247	/* macros for flit 3 of the cqe */
248	#define S_CQE_GENBIT 63
249	#define M_CQE_GENBIT 0x1
250	#define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
251	#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
252
253	#define S_CQE_OVFBIT 62
254	#define M_CQE_OVFBIT 0x1
255	#define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
256
257	#define S_CQE_IQTYPE 60
258	#define M_CQE_IQTYPE 0x3
259	#define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
260
261	#define M_CQE_TS 0x0fffffffffffffffULL
262	#define G_CQE_TS(x) ((x) & M_CQE_TS)
263
264	#define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
265	#define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
266	#define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
267
268	struct t4_swsqe {
269	u64 wr_id;
270	struct t4_cqe cqe;
271	int read_len;
272	int opcode;
273	int complete;
274	int signaled;
275	u16 idx;
276	};
277
278	struct t4_sq {
279	union t4_wr *queue;
280	dma_addr_t dma_addr;
281	DECLARE_PCI_UNMAP_ADDR(mapping);
282	struct t4_swsqe *sw_sq;
283	struct t4_swsqe *oldest_read;
284	u64 udb;
285	size_t memsize;
286	u32 qid;
287	u16 in_use;
288	u16 size;
289	u16 cidx;
290	u16 pidx;
291	};
292
293	struct t4_swrqe {
294	u64 wr_id;
295	};
296
297	struct t4_rq {
298	union t4_recv_wr *queue;
299	dma_addr_t dma_addr;
300	DECLARE_PCI_UNMAP_ADDR(mapping);
301	struct t4_swrqe *sw_rq;
302	u64 udb;
303	size_t memsize;
304	u32 qid;
305	u32 msn;
306	u32 rqt_hwaddr;
307	u16 rqt_size;
308	u16 in_use;
309	u16 size;
310	u16 cidx;
311	u16 pidx;
312	};
313
314	struct t4_wq {
315	struct t4_sq sq;
316	struct t4_rq rq;
317	void __iomem *db;
318	void __iomem *gts;
319	struct c4iw_rdev *rdev;
320	};
321
322	static inline int t4_rqes_posted(struct t4_wq *wq)
323	{
324	return wq->rq.in_use;
325	}
326
327	static inline int t4_rq_empty(struct t4_wq *wq)
328	{
329	return wq->rq.in_use == 0;
330	}
331
332	static inline int t4_rq_full(struct t4_wq *wq)
333	{
334	return wq->rq.in_use == (wq->rq.size - 1);
335	}
336
337	static inline u32 t4_rq_avail(struct t4_wq *wq)
338	{
339	return wq->rq.size - 1 - wq->rq.in_use;
340	}
341
342	static inline void t4_rq_produce(struct t4_wq *wq)
343	{
344	wq->rq.in_use++;
345	if (++wq->rq.pidx == wq->rq.size)
346	wq->rq.pidx = 0;
347	}
348
349	static inline void t4_rq_consume(struct t4_wq *wq)
350	{
351	wq->rq.in_use--;
352	wq->rq.msn++;
353	if (++wq->rq.cidx == wq->rq.size)
354	wq->rq.cidx = 0;
355	}
356
357	static inline int t4_sq_empty(struct t4_wq *wq)
358	{
359	return wq->sq.in_use == 0;
360	}
361
362	static inline int t4_sq_full(struct t4_wq *wq)
363	{
364	return wq->sq.in_use == (wq->sq.size - 1);
365	}
366
367	static inline u32 t4_sq_avail(struct t4_wq *wq)
368	{
369	return wq->sq.size - 1 - wq->sq.in_use;
370	}
371
372	static inline void t4_sq_produce(struct t4_wq *wq)
373	{
374	wq->sq.in_use++;
375	if (++wq->sq.pidx == wq->sq.size)
376	wq->sq.pidx = 0;
377	}
378
379	static inline void t4_sq_consume(struct t4_wq *wq)
380	{
381	wq->sq.in_use--;
382	if (++wq->sq.cidx == wq->sq.size)
383	wq->sq.cidx = 0;
384	}
385
386	static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc)
387	{
388	inc *= T4_SQ_NUM_SLOTS;
389	wmb();
390	writel(QID(wq->sq.qid) \| PIDX(inc), wq->db);
391	}
392
393	static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc)
394	{
395	inc *= T4_RQ_NUM_SLOTS;
396	wmb();
397	writel(QID(wq->rq.qid) \| PIDX(inc), wq->db);
398	}
399
400	static inline int t4_wq_in_error(struct t4_wq *wq)
401	{
402	return wq->sq.queue[wq->sq.size].status.qp_err;
403	}
404
405	static inline void t4_set_wq_in_error(struct t4_wq *wq)
406	{
407	wq->sq.queue[wq->sq.size].status.qp_err = 1;
408	wq->rq.queue[wq->rq.size].status.qp_err = 1;
409	}
410
411	static inline void t4_disable_wq_db(struct t4_wq *wq)
412	{
413	wq->sq.queue[wq->sq.size].status.db_off = 1;
414	wq->rq.queue[wq->rq.size].status.db_off = 1;
415	}
416
417	static inline void t4_enable_wq_db(struct t4_wq *wq)
418	{
419	wq->sq.queue[wq->sq.size].status.db_off = 0;
420	wq->rq.queue[wq->rq.size].status.db_off = 0;
421	}
422
423	static inline int t4_wq_db_enabled(struct t4_wq *wq)
424	{
425	return !wq->sq.queue[wq->sq.size].status.db_off;
426	}
427
428	struct t4_cq {
429	struct t4_cqe *queue;
430	dma_addr_t dma_addr;
431	DECLARE_PCI_UNMAP_ADDR(mapping);
432	struct t4_cqe *sw_queue;
433	void __iomem *gts;
434	struct c4iw_rdev *rdev;
435	u64 ugts;
436	size_t memsize;
437	u64 timestamp;
438	u32 cqid;
439	u16 size; /* including status page */
440	u16 cidx;
441	u16 sw_pidx;
442	u16 sw_cidx;
443	u16 sw_in_use;
444	u16 cidx_inc;
445	u8 gen;
446	u8 error;
447	};
448
449	static inline int t4_arm_cq(struct t4_cq *cq, int se)
450	{
451	u32 val;
be4c9bad RD	452	u16 inc;
	453
	454	do {
	455	/*
	456	* inc must be less the both the max update value -and-
	457	* the size of the CQ.
	458	*/
	459	inc = cq->cidx_inc <= CIDXINC_MASK ? cq->cidx_inc :
	460	CIDXINC_MASK;
	461	inc = inc <= (cq->size - 1) ? inc : (cq->size - 1);
	462	if (inc == cq->cidx_inc)
	463	val = SEINTARM(se) \| CIDXINC(inc) \| TIMERREG(6) \|
	464	INGRESSQID(cq->cqid);
	465	else
	466	val = SEINTARM(0) \| CIDXINC(inc) \| TIMERREG(7) \|
	467	INGRESSQID(cq->cqid);
	468	cq->cidx_inc -= inc;
	469	writel(val, cq->gts);
	470	} while (cq->cidx_inc);
cfdda9d7 SW	471	return 0;
	472	}
	473
	474	static inline void t4_swcq_produce(struct t4_cq *cq)
	475	{
	476	cq->sw_in_use++;
	477	if (++cq->sw_pidx == cq->size)
	478	cq->sw_pidx = 0;
	479	}
	480
	481	static inline void t4_swcq_consume(struct t4_cq *cq)
	482	{
	483	cq->sw_in_use--;
	484	if (++cq->sw_cidx == cq->size)
	485	cq->sw_cidx = 0;
	486	}
	487
	488	static inline void t4_hwcq_consume(struct t4_cq *cq)
	489	{
	490	cq->cidx_inc++;
	491	if (++cq->cidx == cq->size) {
	492	cq->cidx = 0;
	493	cq->gen ^= 1;
	494	}
	495	}
	496
	497	static inline int t4_valid_cqe(struct t4_cq cq, struct t4_cqe cqe)
	498	{
	499	return (CQE_GENBIT(cqe) == cq->gen);
	500	}
	501
	502	static inline int t4_next_hw_cqe(struct t4_cq cq, struct t4_cqe *cqe)
	503	{
	504	int ret = 0;
be4c9bad	505	u64 bits_type_ts = be64_to_cpu(cq->queue[cq->cidx].bits_type_ts);
cfdda9d7	506
be4c9bad	507	if (G_CQE_GENBIT(bits_type_ts) == cq->gen) {
cfdda9d7	508	*cqe = &cq->queue[cq->cidx];
be4c9bad RD	509	cq->timestamp = G_CQE_TS(bits_type_ts);
be4c9bad RD	510	} else if (G_CQE_TS(bits_type_ts) > cq->timestamp)
cfdda9d7 SW	511	ret = -EOVERFLOW;
	512	else
	513	ret = -ENODATA;
	514	if (ret == -EOVERFLOW) {
	515	printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
	516	cq->error = 1;
	517	}
	518	return ret;
	519	}
	520
	521	static inline struct t4_cqe t4_next_sw_cqe(struct t4_cq cq)
	522	{
	523	if (cq->sw_in_use)
	524	return &cq->sw_queue[cq->sw_cidx];
	525	return NULL;
	526	}
	527
	528	static inline int t4_next_cqe(struct t4_cq cq, struct t4_cqe *cqe)
	529	{
	530	int ret = 0;
	531
	532	if (cq->error)
	533	ret = -ENODATA;
	534	else if (cq->sw_in_use)
	535	*cqe = &cq->sw_queue[cq->sw_cidx];
	536	else
	537	ret = t4_next_hw_cqe(cq, cqe);
	538	return ret;
	539	}
	540
	541	static inline int t4_cq_in_error(struct t4_cq *cq)
	542	{
	543	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
	544	}
	545
	546	static inline void t4_set_cq_in_error(struct t4_cq *cq)
	547	{
	548	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
	549	}
	550	#endif