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cfdda9d7 SW |
1 | /* |
2 | * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
e4dd23d7 PG |
32 | |
33 | #include <linux/module.h> | |
34 | ||
cfdda9d7 SW |
35 | #include "iw_cxgb4.h" |
36 | ||
2c974781 VP |
37 | static int db_delay_usecs = 1; |
38 | module_param(db_delay_usecs, int, 0644); | |
39 | MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain"); | |
40 | ||
a9c77198 | 41 | static int ocqp_support = 1; |
c6d7b267 | 42 | module_param(ocqp_support, int, 0644); |
a9c77198 | 43 | MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)"); |
c6d7b267 | 44 | |
3cbdb928 | 45 | int db_fc_threshold = 1000; |
422eea0a | 46 | module_param(db_fc_threshold, int, 0644); |
3cbdb928 VP |
47 | MODULE_PARM_DESC(db_fc_threshold, |
48 | "QP count/threshold that triggers" | |
49 | " automatic db flow control mode (default = 1000)"); | |
50 | ||
51 | int db_coalescing_threshold; | |
52 | module_param(db_coalescing_threshold, int, 0644); | |
53 | MODULE_PARM_DESC(db_coalescing_threshold, | |
54 | "QP count/threshold that triggers" | |
55 | " disabling db coalescing (default = 0)"); | |
422eea0a | 56 | |
42b6a949 VP |
57 | static int max_fr_immd = T4_MAX_FR_IMMD; |
58 | module_param(max_fr_immd, int, 0644); | |
59 | MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate"); | |
60 | ||
2f5b48c3 SW |
61 | static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) |
62 | { | |
63 | unsigned long flag; | |
64 | spin_lock_irqsave(&qhp->lock, flag); | |
65 | qhp->attr.state = state; | |
66 | spin_unlock_irqrestore(&qhp->lock, flag); | |
67 | } | |
68 | ||
c6d7b267 SW |
69 | static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) |
70 | { | |
71 | c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize); | |
72 | } | |
73 | ||
74 | static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) | |
75 | { | |
76 | dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue, | |
77 | pci_unmap_addr(sq, mapping)); | |
78 | } | |
79 | ||
80 | static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) | |
81 | { | |
82 | if (t4_sq_onchip(sq)) | |
83 | dealloc_oc_sq(rdev, sq); | |
84 | else | |
85 | dealloc_host_sq(rdev, sq); | |
86 | } | |
87 | ||
88 | static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) | |
89 | { | |
f079af7a | 90 | if (!ocqp_support || !ocqp_supported(&rdev->lldi)) |
c6d7b267 SW |
91 | return -ENOSYS; |
92 | sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize); | |
93 | if (!sq->dma_addr) | |
94 | return -ENOMEM; | |
95 | sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr - | |
96 | rdev->lldi.vr->ocq.start; | |
97 | sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr - | |
98 | rdev->lldi.vr->ocq.start); | |
99 | sq->flags |= T4_SQ_ONCHIP; | |
100 | return 0; | |
101 | } | |
102 | ||
103 | static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) | |
104 | { | |
105 | sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize, | |
106 | &(sq->dma_addr), GFP_KERNEL); | |
107 | if (!sq->queue) | |
108 | return -ENOMEM; | |
109 | sq->phys_addr = virt_to_phys(sq->queue); | |
110 | pci_unmap_addr_set(sq, mapping, sq->dma_addr); | |
111 | return 0; | |
112 | } | |
113 | ||
5b0c2759 TLSC |
114 | static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user) |
115 | { | |
116 | int ret = -ENOSYS; | |
117 | if (user) | |
118 | ret = alloc_oc_sq(rdev, sq); | |
119 | if (ret) | |
120 | ret = alloc_host_sq(rdev, sq); | |
121 | return ret; | |
122 | } | |
123 | ||
cfdda9d7 SW |
124 | static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, |
125 | struct c4iw_dev_ucontext *uctx) | |
126 | { | |
127 | /* | |
128 | * uP clears EQ contexts when the connection exits rdma mode, | |
129 | * so no need to post a RESET WR for these EQs. | |
130 | */ | |
131 | dma_free_coherent(&(rdev->lldi.pdev->dev), | |
132 | wq->rq.memsize, wq->rq.queue, | |
f38926aa | 133 | dma_unmap_addr(&wq->rq, mapping)); |
c6d7b267 | 134 | dealloc_sq(rdev, &wq->sq); |
cfdda9d7 SW |
135 | c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); |
136 | kfree(wq->rq.sw_rq); | |
137 | kfree(wq->sq.sw_sq); | |
138 | c4iw_put_qpid(rdev, wq->rq.qid, uctx); | |
139 | c4iw_put_qpid(rdev, wq->sq.qid, uctx); | |
140 | return 0; | |
141 | } | |
142 | ||
143 | static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, | |
144 | struct t4_cq *rcq, struct t4_cq *scq, | |
145 | struct c4iw_dev_ucontext *uctx) | |
146 | { | |
147 | int user = (uctx != &rdev->uctx); | |
148 | struct fw_ri_res_wr *res_wr; | |
149 | struct fw_ri_res *res; | |
150 | int wr_len; | |
151 | struct c4iw_wr_wait wr_wait; | |
152 | struct sk_buff *skb; | |
9919d5bd | 153 | int ret = 0; |
cfdda9d7 SW |
154 | int eqsize; |
155 | ||
156 | wq->sq.qid = c4iw_get_qpid(rdev, uctx); | |
157 | if (!wq->sq.qid) | |
158 | return -ENOMEM; | |
159 | ||
160 | wq->rq.qid = c4iw_get_qpid(rdev, uctx); | |
c079c287 EG |
161 | if (!wq->rq.qid) { |
162 | ret = -ENOMEM; | |
163 | goto free_sq_qid; | |
164 | } | |
cfdda9d7 SW |
165 | |
166 | if (!user) { | |
167 | wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, | |
168 | GFP_KERNEL); | |
c079c287 EG |
169 | if (!wq->sq.sw_sq) { |
170 | ret = -ENOMEM; | |
171 | goto free_rq_qid; | |
172 | } | |
cfdda9d7 SW |
173 | |
174 | wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, | |
175 | GFP_KERNEL); | |
c079c287 EG |
176 | if (!wq->rq.sw_rq) { |
177 | ret = -ENOMEM; | |
178 | goto free_sw_sq; | |
179 | } | |
cfdda9d7 SW |
180 | } |
181 | ||
182 | /* | |
183 | * RQT must be a power of 2. | |
184 | */ | |
185 | wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size); | |
186 | wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); | |
c079c287 EG |
187 | if (!wq->rq.rqt_hwaddr) { |
188 | ret = -ENOMEM; | |
189 | goto free_sw_rq; | |
190 | } | |
cfdda9d7 | 191 | |
5b0c2759 TLSC |
192 | ret = alloc_sq(rdev, &wq->sq, user); |
193 | if (ret) | |
194 | goto free_hwaddr; | |
cfdda9d7 | 195 | memset(wq->sq.queue, 0, wq->sq.memsize); |
f38926aa | 196 | dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); |
cfdda9d7 SW |
197 | |
198 | wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), | |
199 | wq->rq.memsize, &(wq->rq.dma_addr), | |
200 | GFP_KERNEL); | |
55e57a78 WY |
201 | if (!wq->rq.queue) { |
202 | ret = -ENOMEM; | |
c079c287 | 203 | goto free_sq; |
55e57a78 | 204 | } |
cfdda9d7 SW |
205 | PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n", |
206 | __func__, wq->sq.queue, | |
207 | (unsigned long long)virt_to_phys(wq->sq.queue), | |
208 | wq->rq.queue, | |
209 | (unsigned long long)virt_to_phys(wq->rq.queue)); | |
210 | memset(wq->rq.queue, 0, wq->rq.memsize); | |
f38926aa | 211 | dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); |
cfdda9d7 SW |
212 | |
213 | wq->db = rdev->lldi.db_reg; | |
214 | wq->gts = rdev->lldi.gts_reg; | |
fa658a98 SW |
215 | if (user || is_t5(rdev->lldi.adapter_type)) { |
216 | u32 off; | |
217 | ||
218 | off = (wq->sq.qid << rdev->qpshift) & PAGE_MASK; | |
219 | if (user) { | |
220 | wq->sq.udb = (u64 __iomem *)(rdev->bar2_pa + off); | |
221 | } else { | |
222 | off += 128 * (wq->sq.qid & rdev->qpmask) + 8; | |
223 | wq->sq.udb = (u64 __iomem *)(rdev->bar2_kva + off); | |
224 | } | |
225 | off = (wq->rq.qid << rdev->qpshift) & PAGE_MASK; | |
226 | if (user) { | |
227 | wq->rq.udb = (u64 __iomem *)(rdev->bar2_pa + off); | |
228 | } else { | |
229 | off += 128 * (wq->rq.qid & rdev->qpmask) + 8; | |
230 | wq->rq.udb = (u64 __iomem *)(rdev->bar2_kva + off); | |
231 | } | |
cfdda9d7 SW |
232 | } |
233 | wq->rdev = rdev; | |
234 | wq->rq.msn = 1; | |
235 | ||
236 | /* build fw_ri_res_wr */ | |
237 | wr_len = sizeof *res_wr + 2 * sizeof *res; | |
238 | ||
d3c814e8 | 239 | skb = alloc_skb(wr_len, GFP_KERNEL); |
cfdda9d7 SW |
240 | if (!skb) { |
241 | ret = -ENOMEM; | |
c079c287 | 242 | goto free_dma; |
cfdda9d7 SW |
243 | } |
244 | set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); | |
245 | ||
246 | res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len); | |
247 | memset(res_wr, 0, wr_len); | |
248 | res_wr->op_nres = cpu_to_be32( | |
249 | FW_WR_OP(FW_RI_RES_WR) | | |
250 | V_FW_RI_RES_WR_NRES(2) | | |
251 | FW_WR_COMPL(1)); | |
252 | res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); | |
c8e081a1 | 253 | res_wr->cookie = (unsigned long) &wr_wait; |
cfdda9d7 SW |
254 | res = res_wr->res; |
255 | res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; | |
256 | res->u.sqrq.op = FW_RI_RES_OP_WRITE; | |
257 | ||
258 | /* | |
259 | * eqsize is the number of 64B entries plus the status page size. | |
260 | */ | |
261 | eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES; | |
262 | ||
263 | res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( | |
264 | V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ | |
265 | V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ | |
266 | V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ | |
85d215b0 | 267 | (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) | |
cfdda9d7 SW |
268 | V_FW_RI_RES_WR_IQID(scq->cqid)); |
269 | res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( | |
270 | V_FW_RI_RES_WR_DCAEN(0) | | |
271 | V_FW_RI_RES_WR_DCACPU(0) | | |
d37ac31d | 272 | V_FW_RI_RES_WR_FBMIN(2) | |
6a09a9d6 | 273 | V_FW_RI_RES_WR_FBMAX(2) | |
cfdda9d7 SW |
274 | V_FW_RI_RES_WR_CIDXFTHRESHO(0) | |
275 | V_FW_RI_RES_WR_CIDXFTHRESH(0) | | |
276 | V_FW_RI_RES_WR_EQSIZE(eqsize)); | |
277 | res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); | |
278 | res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); | |
279 | res++; | |
280 | res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; | |
281 | res->u.sqrq.op = FW_RI_RES_OP_WRITE; | |
282 | ||
283 | /* | |
284 | * eqsize is the number of 64B entries plus the status page size. | |
285 | */ | |
286 | eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES; | |
287 | res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( | |
288 | V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ | |
289 | V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ | |
290 | V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ | |
291 | V_FW_RI_RES_WR_IQID(rcq->cqid)); | |
292 | res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( | |
293 | V_FW_RI_RES_WR_DCAEN(0) | | |
294 | V_FW_RI_RES_WR_DCACPU(0) | | |
d37ac31d | 295 | V_FW_RI_RES_WR_FBMIN(2) | |
6a09a9d6 | 296 | V_FW_RI_RES_WR_FBMAX(2) | |
cfdda9d7 SW |
297 | V_FW_RI_RES_WR_CIDXFTHRESHO(0) | |
298 | V_FW_RI_RES_WR_CIDXFTHRESH(0) | | |
299 | V_FW_RI_RES_WR_EQSIZE(eqsize)); | |
300 | res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); | |
301 | res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); | |
302 | ||
303 | c4iw_init_wr_wait(&wr_wait); | |
304 | ||
305 | ret = c4iw_ofld_send(rdev, skb); | |
306 | if (ret) | |
c079c287 | 307 | goto free_dma; |
aadc4df3 | 308 | ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__); |
cfdda9d7 | 309 | if (ret) |
c079c287 | 310 | goto free_dma; |
cfdda9d7 | 311 | |
fa658a98 | 312 | PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%lx rqudb 0x%lx\n", |
cfdda9d7 | 313 | __func__, wq->sq.qid, wq->rq.qid, wq->db, |
fa658a98 SW |
314 | (__force unsigned long) wq->sq.udb, |
315 | (__force unsigned long) wq->rq.udb); | |
cfdda9d7 SW |
316 | |
317 | return 0; | |
c079c287 | 318 | free_dma: |
cfdda9d7 SW |
319 | dma_free_coherent(&(rdev->lldi.pdev->dev), |
320 | wq->rq.memsize, wq->rq.queue, | |
f38926aa | 321 | dma_unmap_addr(&wq->rq, mapping)); |
c079c287 | 322 | free_sq: |
c6d7b267 | 323 | dealloc_sq(rdev, &wq->sq); |
c079c287 | 324 | free_hwaddr: |
cfdda9d7 | 325 | c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); |
c079c287 | 326 | free_sw_rq: |
cfdda9d7 | 327 | kfree(wq->rq.sw_rq); |
c079c287 | 328 | free_sw_sq: |
cfdda9d7 | 329 | kfree(wq->sq.sw_sq); |
c079c287 | 330 | free_rq_qid: |
cfdda9d7 | 331 | c4iw_put_qpid(rdev, wq->rq.qid, uctx); |
c079c287 | 332 | free_sq_qid: |
cfdda9d7 | 333 | c4iw_put_qpid(rdev, wq->sq.qid, uctx); |
c079c287 | 334 | return ret; |
cfdda9d7 SW |
335 | } |
336 | ||
d37ac31d SW |
337 | static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, |
338 | struct ib_send_wr *wr, int max, u32 *plenp) | |
cfdda9d7 | 339 | { |
d37ac31d SW |
340 | u8 *dstp, *srcp; |
341 | u32 plen = 0; | |
cfdda9d7 | 342 | int i; |
d37ac31d SW |
343 | int rem, len; |
344 | ||
345 | dstp = (u8 *)immdp->data; | |
346 | for (i = 0; i < wr->num_sge; i++) { | |
347 | if ((plen + wr->sg_list[i].length) > max) | |
348 | return -EMSGSIZE; | |
349 | srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; | |
350 | plen += wr->sg_list[i].length; | |
351 | rem = wr->sg_list[i].length; | |
352 | while (rem) { | |
353 | if (dstp == (u8 *)&sq->queue[sq->size]) | |
354 | dstp = (u8 *)sq->queue; | |
355 | if (rem <= (u8 *)&sq->queue[sq->size] - dstp) | |
356 | len = rem; | |
357 | else | |
358 | len = (u8 *)&sq->queue[sq->size] - dstp; | |
359 | memcpy(dstp, srcp, len); | |
360 | dstp += len; | |
361 | srcp += len; | |
362 | rem -= len; | |
363 | } | |
364 | } | |
13fecb83 SW |
365 | len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); |
366 | if (len) | |
367 | memset(dstp, 0, len); | |
d37ac31d SW |
368 | immdp->op = FW_RI_DATA_IMMD; |
369 | immdp->r1 = 0; | |
370 | immdp->r2 = 0; | |
371 | immdp->immdlen = cpu_to_be32(plen); | |
372 | *plenp = plen; | |
373 | return 0; | |
374 | } | |
375 | ||
376 | static int build_isgl(__be64 *queue_start, __be64 *queue_end, | |
377 | struct fw_ri_isgl *isglp, struct ib_sge *sg_list, | |
378 | int num_sge, u32 *plenp) | |
379 | ||
380 | { | |
381 | int i; | |
382 | u32 plen = 0; | |
383 | __be64 *flitp = (__be64 *)isglp->sge; | |
384 | ||
385 | for (i = 0; i < num_sge; i++) { | |
386 | if ((plen + sg_list[i].length) < plen) | |
387 | return -EMSGSIZE; | |
388 | plen += sg_list[i].length; | |
389 | *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | | |
390 | sg_list[i].length); | |
391 | if (++flitp == queue_end) | |
392 | flitp = queue_start; | |
393 | *flitp = cpu_to_be64(sg_list[i].addr); | |
394 | if (++flitp == queue_end) | |
395 | flitp = queue_start; | |
396 | } | |
13fecb83 | 397 | *flitp = (__force __be64)0; |
d37ac31d SW |
398 | isglp->op = FW_RI_DATA_ISGL; |
399 | isglp->r1 = 0; | |
400 | isglp->nsge = cpu_to_be16(num_sge); | |
401 | isglp->r2 = 0; | |
402 | if (plenp) | |
403 | *plenp = plen; | |
404 | return 0; | |
405 | } | |
406 | ||
407 | static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, | |
408 | struct ib_send_wr *wr, u8 *len16) | |
409 | { | |
cfdda9d7 SW |
410 | u32 plen; |
411 | int size; | |
d37ac31d | 412 | int ret; |
cfdda9d7 SW |
413 | |
414 | if (wr->num_sge > T4_MAX_SEND_SGE) | |
415 | return -EINVAL; | |
416 | switch (wr->opcode) { | |
417 | case IB_WR_SEND: | |
418 | if (wr->send_flags & IB_SEND_SOLICITED) | |
419 | wqe->send.sendop_pkd = cpu_to_be32( | |
420 | V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE)); | |
421 | else | |
422 | wqe->send.sendop_pkd = cpu_to_be32( | |
423 | V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND)); | |
424 | wqe->send.stag_inv = 0; | |
425 | break; | |
426 | case IB_WR_SEND_WITH_INV: | |
427 | if (wr->send_flags & IB_SEND_SOLICITED) | |
428 | wqe->send.sendop_pkd = cpu_to_be32( | |
429 | V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV)); | |
430 | else | |
431 | wqe->send.sendop_pkd = cpu_to_be32( | |
432 | V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV)); | |
433 | wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); | |
434 | break; | |
435 | ||
436 | default: | |
437 | return -EINVAL; | |
438 | } | |
c3f98fa2 SW |
439 | wqe->send.r3 = 0; |
440 | wqe->send.r4 = 0; | |
d37ac31d | 441 | |
cfdda9d7 SW |
442 | plen = 0; |
443 | if (wr->num_sge) { | |
444 | if (wr->send_flags & IB_SEND_INLINE) { | |
d37ac31d SW |
445 | ret = build_immd(sq, wqe->send.u.immd_src, wr, |
446 | T4_MAX_SEND_INLINE, &plen); | |
447 | if (ret) | |
448 | return ret; | |
cfdda9d7 SW |
449 | size = sizeof wqe->send + sizeof(struct fw_ri_immd) + |
450 | plen; | |
451 | } else { | |
d37ac31d SW |
452 | ret = build_isgl((__be64 *)sq->queue, |
453 | (__be64 *)&sq->queue[sq->size], | |
454 | wqe->send.u.isgl_src, | |
455 | wr->sg_list, wr->num_sge, &plen); | |
456 | if (ret) | |
457 | return ret; | |
cfdda9d7 SW |
458 | size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + |
459 | wr->num_sge * sizeof(struct fw_ri_sge); | |
460 | } | |
461 | } else { | |
462 | wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; | |
463 | wqe->send.u.immd_src[0].r1 = 0; | |
464 | wqe->send.u.immd_src[0].r2 = 0; | |
465 | wqe->send.u.immd_src[0].immdlen = 0; | |
466 | size = sizeof wqe->send + sizeof(struct fw_ri_immd); | |
d37ac31d | 467 | plen = 0; |
cfdda9d7 SW |
468 | } |
469 | *len16 = DIV_ROUND_UP(size, 16); | |
470 | wqe->send.plen = cpu_to_be32(plen); | |
471 | return 0; | |
472 | } | |
473 | ||
d37ac31d SW |
474 | static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, |
475 | struct ib_send_wr *wr, u8 *len16) | |
cfdda9d7 | 476 | { |
cfdda9d7 SW |
477 | u32 plen; |
478 | int size; | |
d37ac31d | 479 | int ret; |
cfdda9d7 | 480 | |
d37ac31d | 481 | if (wr->num_sge > T4_MAX_SEND_SGE) |
cfdda9d7 SW |
482 | return -EINVAL; |
483 | wqe->write.r2 = 0; | |
484 | wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey); | |
485 | wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr); | |
cfdda9d7 SW |
486 | if (wr->num_sge) { |
487 | if (wr->send_flags & IB_SEND_INLINE) { | |
d37ac31d SW |
488 | ret = build_immd(sq, wqe->write.u.immd_src, wr, |
489 | T4_MAX_WRITE_INLINE, &plen); | |
490 | if (ret) | |
491 | return ret; | |
cfdda9d7 SW |
492 | size = sizeof wqe->write + sizeof(struct fw_ri_immd) + |
493 | plen; | |
494 | } else { | |
d37ac31d SW |
495 | ret = build_isgl((__be64 *)sq->queue, |
496 | (__be64 *)&sq->queue[sq->size], | |
497 | wqe->write.u.isgl_src, | |
498 | wr->sg_list, wr->num_sge, &plen); | |
499 | if (ret) | |
500 | return ret; | |
cfdda9d7 SW |
501 | size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + |
502 | wr->num_sge * sizeof(struct fw_ri_sge); | |
503 | } | |
504 | } else { | |
505 | wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; | |
506 | wqe->write.u.immd_src[0].r1 = 0; | |
507 | wqe->write.u.immd_src[0].r2 = 0; | |
508 | wqe->write.u.immd_src[0].immdlen = 0; | |
509 | size = sizeof wqe->write + sizeof(struct fw_ri_immd); | |
d37ac31d | 510 | plen = 0; |
cfdda9d7 SW |
511 | } |
512 | *len16 = DIV_ROUND_UP(size, 16); | |
513 | wqe->write.plen = cpu_to_be32(plen); | |
514 | return 0; | |
515 | } | |
516 | ||
517 | static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) | |
518 | { | |
519 | if (wr->num_sge > 1) | |
520 | return -EINVAL; | |
521 | if (wr->num_sge) { | |
522 | wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey); | |
523 | wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr | |
524 | >> 32)); | |
525 | wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr); | |
526 | wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); | |
527 | wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); | |
528 | wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr | |
529 | >> 32)); | |
530 | wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); | |
531 | } else { | |
532 | wqe->read.stag_src = cpu_to_be32(2); | |
533 | wqe->read.to_src_hi = 0; | |
534 | wqe->read.to_src_lo = 0; | |
535 | wqe->read.stag_sink = cpu_to_be32(2); | |
536 | wqe->read.plen = 0; | |
537 | wqe->read.to_sink_hi = 0; | |
538 | wqe->read.to_sink_lo = 0; | |
539 | } | |
540 | wqe->read.r2 = 0; | |
541 | wqe->read.r5 = 0; | |
542 | *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); | |
543 | return 0; | |
544 | } | |
545 | ||
546 | static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, | |
547 | struct ib_recv_wr *wr, u8 *len16) | |
548 | { | |
d37ac31d | 549 | int ret; |
cfdda9d7 | 550 | |
d37ac31d SW |
551 | ret = build_isgl((__be64 *)qhp->wq.rq.queue, |
552 | (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], | |
553 | &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); | |
554 | if (ret) | |
555 | return ret; | |
cfdda9d7 SW |
556 | *len16 = DIV_ROUND_UP(sizeof wqe->recv + |
557 | wr->num_sge * sizeof(struct fw_ri_sge), 16); | |
558 | return 0; | |
559 | } | |
560 | ||
40dbf6ee | 561 | static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, |
42b6a949 | 562 | struct ib_send_wr *wr, u8 *len16, u8 t5dev) |
cfdda9d7 SW |
563 | { |
564 | ||
565 | struct fw_ri_immd *imdp; | |
566 | __be64 *p; | |
567 | int i; | |
568 | int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32); | |
40dbf6ee | 569 | int rem; |
cfdda9d7 | 570 | |
a03d9f94 SW |
571 | if (wr->wr.fast_reg.page_list_len > |
572 | t4_max_fr_depth(use_dsgl)) | |
cfdda9d7 SW |
573 | return -EINVAL; |
574 | ||
575 | wqe->fr.qpbinde_to_dcacpu = 0; | |
576 | wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12; | |
577 | wqe->fr.addr_type = FW_RI_VA_BASED_TO; | |
578 | wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags); | |
579 | wqe->fr.len_hi = 0; | |
580 | wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length); | |
581 | wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey); | |
582 | wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32); | |
583 | wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start & | |
584 | 0xffffffff); | |
42b6a949 VP |
585 | |
586 | if (t5dev && use_dsgl && (pbllen > max_fr_immd)) { | |
587 | struct c4iw_fr_page_list *c4pl = | |
588 | to_c4iw_fr_page_list(wr->wr.fast_reg.page_list); | |
589 | struct fw_ri_dsgl *sglp; | |
590 | ||
591 | for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { | |
592 | wr->wr.fast_reg.page_list->page_list[i] = (__force u64) | |
593 | cpu_to_be64((u64) | |
594 | wr->wr.fast_reg.page_list->page_list[i]); | |
595 | } | |
596 | ||
597 | sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1); | |
598 | sglp->op = FW_RI_DATA_DSGL; | |
599 | sglp->r1 = 0; | |
600 | sglp->nsge = cpu_to_be16(1); | |
601 | sglp->addr0 = cpu_to_be64(c4pl->dma_addr); | |
602 | sglp->len0 = cpu_to_be32(pbllen); | |
603 | ||
604 | *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16); | |
605 | } else { | |
606 | imdp = (struct fw_ri_immd *)(&wqe->fr + 1); | |
607 | imdp->op = FW_RI_DATA_IMMD; | |
608 | imdp->r1 = 0; | |
609 | imdp->r2 = 0; | |
610 | imdp->immdlen = cpu_to_be32(pbllen); | |
611 | p = (__be64 *)(imdp + 1); | |
612 | rem = pbllen; | |
613 | for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { | |
614 | *p = cpu_to_be64( | |
615 | (u64)wr->wr.fast_reg.page_list->page_list[i]); | |
616 | rem -= sizeof(*p); | |
617 | if (++p == (__be64 *)&sq->queue[sq->size]) | |
618 | p = (__be64 *)sq->queue; | |
619 | } | |
620 | BUG_ON(rem < 0); | |
621 | while (rem) { | |
622 | *p = 0; | |
623 | rem -= sizeof(*p); | |
624 | if (++p == (__be64 *)&sq->queue[sq->size]) | |
625 | p = (__be64 *)sq->queue; | |
626 | } | |
627 | *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp) | |
628 | + pbllen, 16); | |
cfdda9d7 SW |
629 | } |
630 | return 0; | |
631 | } | |
632 | ||
633 | static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, | |
634 | u8 *len16) | |
635 | { | |
636 | wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); | |
637 | wqe->inv.r2 = 0; | |
638 | *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); | |
639 | return 0; | |
640 | } | |
641 | ||
642 | void c4iw_qp_add_ref(struct ib_qp *qp) | |
643 | { | |
644 | PDBG("%s ib_qp %p\n", __func__, qp); | |
645 | atomic_inc(&(to_c4iw_qp(qp)->refcnt)); | |
646 | } | |
647 | ||
648 | void c4iw_qp_rem_ref(struct ib_qp *qp) | |
649 | { | |
650 | PDBG("%s ib_qp %p\n", __func__, qp); | |
651 | if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt))) | |
652 | wake_up(&(to_c4iw_qp(qp)->wait)); | |
653 | } | |
654 | ||
05eb2389 SW |
655 | static void add_to_fc_list(struct list_head *head, struct list_head *entry) |
656 | { | |
657 | if (list_empty(entry)) | |
658 | list_add_tail(entry, head); | |
659 | } | |
660 | ||
661 | static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc) | |
662 | { | |
663 | unsigned long flags; | |
664 | ||
665 | spin_lock_irqsave(&qhp->rhp->lock, flags); | |
666 | spin_lock(&qhp->lock); | |
fa658a98 SW |
667 | if (qhp->rhp->db_state == NORMAL) |
668 | t4_ring_sq_db(&qhp->wq, inc, | |
669 | is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL); | |
670 | else { | |
05eb2389 SW |
671 | add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry); |
672 | qhp->wq.sq.wq_pidx_inc += inc; | |
673 | } | |
674 | spin_unlock(&qhp->lock); | |
675 | spin_unlock_irqrestore(&qhp->rhp->lock, flags); | |
676 | return 0; | |
677 | } | |
678 | ||
679 | static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc) | |
680 | { | |
681 | unsigned long flags; | |
682 | ||
683 | spin_lock_irqsave(&qhp->rhp->lock, flags); | |
684 | spin_lock(&qhp->lock); | |
fa658a98 SW |
685 | if (qhp->rhp->db_state == NORMAL) |
686 | t4_ring_rq_db(&qhp->wq, inc, | |
687 | is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL); | |
688 | else { | |
05eb2389 SW |
689 | add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry); |
690 | qhp->wq.rq.wq_pidx_inc += inc; | |
691 | } | |
692 | spin_unlock(&qhp->lock); | |
693 | spin_unlock_irqrestore(&qhp->rhp->lock, flags); | |
694 | return 0; | |
695 | } | |
696 | ||
cfdda9d7 SW |
697 | int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, |
698 | struct ib_send_wr **bad_wr) | |
699 | { | |
700 | int err = 0; | |
701 | u8 len16 = 0; | |
702 | enum fw_wr_opcodes fw_opcode = 0; | |
703 | enum fw_ri_wr_flags fw_flags; | |
704 | struct c4iw_qp *qhp; | |
fa658a98 | 705 | union t4_wr *wqe = NULL; |
cfdda9d7 SW |
706 | u32 num_wrs; |
707 | struct t4_swsqe *swsqe; | |
708 | unsigned long flag; | |
709 | u16 idx = 0; | |
710 | ||
711 | qhp = to_c4iw_qp(ibqp); | |
712 | spin_lock_irqsave(&qhp->lock, flag); | |
713 | if (t4_wq_in_error(&qhp->wq)) { | |
714 | spin_unlock_irqrestore(&qhp->lock, flag); | |
715 | return -EINVAL; | |
716 | } | |
717 | num_wrs = t4_sq_avail(&qhp->wq); | |
718 | if (num_wrs == 0) { | |
719 | spin_unlock_irqrestore(&qhp->lock, flag); | |
720 | return -ENOMEM; | |
721 | } | |
722 | while (wr) { | |
723 | if (num_wrs == 0) { | |
724 | err = -ENOMEM; | |
725 | *bad_wr = wr; | |
726 | break; | |
727 | } | |
d37ac31d SW |
728 | wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + |
729 | qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); | |
730 | ||
cfdda9d7 SW |
731 | fw_flags = 0; |
732 | if (wr->send_flags & IB_SEND_SOLICITED) | |
733 | fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; | |
ba32de9d | 734 | if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all) |
cfdda9d7 SW |
735 | fw_flags |= FW_RI_COMPLETION_FLAG; |
736 | swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; | |
737 | switch (wr->opcode) { | |
738 | case IB_WR_SEND_WITH_INV: | |
739 | case IB_WR_SEND: | |
740 | if (wr->send_flags & IB_SEND_FENCE) | |
741 | fw_flags |= FW_RI_READ_FENCE_FLAG; | |
742 | fw_opcode = FW_RI_SEND_WR; | |
743 | if (wr->opcode == IB_WR_SEND) | |
744 | swsqe->opcode = FW_RI_SEND; | |
745 | else | |
746 | swsqe->opcode = FW_RI_SEND_WITH_INV; | |
d37ac31d | 747 | err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); |
cfdda9d7 SW |
748 | break; |
749 | case IB_WR_RDMA_WRITE: | |
750 | fw_opcode = FW_RI_RDMA_WRITE_WR; | |
751 | swsqe->opcode = FW_RI_RDMA_WRITE; | |
d37ac31d | 752 | err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); |
cfdda9d7 SW |
753 | break; |
754 | case IB_WR_RDMA_READ: | |
2f1fb507 | 755 | case IB_WR_RDMA_READ_WITH_INV: |
cfdda9d7 SW |
756 | fw_opcode = FW_RI_RDMA_READ_WR; |
757 | swsqe->opcode = FW_RI_READ_REQ; | |
2f1fb507 | 758 | if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) |
410ade4c | 759 | fw_flags = FW_RI_RDMA_READ_INVALIDATE; |
2f1fb507 SW |
760 | else |
761 | fw_flags = 0; | |
cfdda9d7 SW |
762 | err = build_rdma_read(wqe, wr, &len16); |
763 | if (err) | |
764 | break; | |
765 | swsqe->read_len = wr->sg_list[0].length; | |
766 | if (!qhp->wq.sq.oldest_read) | |
767 | qhp->wq.sq.oldest_read = swsqe; | |
768 | break; | |
769 | case IB_WR_FAST_REG_MR: | |
770 | fw_opcode = FW_RI_FR_NSMR_WR; | |
771 | swsqe->opcode = FW_RI_FAST_REGISTER; | |
42b6a949 VP |
772 | err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16, |
773 | is_t5( | |
774 | qhp->rhp->rdev.lldi.adapter_type) ? | |
775 | 1 : 0); | |
cfdda9d7 SW |
776 | break; |
777 | case IB_WR_LOCAL_INV: | |
4ab1eb9c SW |
778 | if (wr->send_flags & IB_SEND_FENCE) |
779 | fw_flags |= FW_RI_LOCAL_FENCE_FLAG; | |
cfdda9d7 SW |
780 | fw_opcode = FW_RI_INV_LSTAG_WR; |
781 | swsqe->opcode = FW_RI_LOCAL_INV; | |
782 | err = build_inv_stag(wqe, wr, &len16); | |
783 | break; | |
784 | default: | |
785 | PDBG("%s post of type=%d TBD!\n", __func__, | |
786 | wr->opcode); | |
787 | err = -EINVAL; | |
788 | } | |
789 | if (err) { | |
790 | *bad_wr = wr; | |
791 | break; | |
792 | } | |
793 | swsqe->idx = qhp->wq.sq.pidx; | |
794 | swsqe->complete = 0; | |
ba32de9d SW |
795 | swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) || |
796 | qhp->sq_sig_all; | |
1cf24dce | 797 | swsqe->flushed = 0; |
cfdda9d7 SW |
798 | swsqe->wr_id = wr->wr_id; |
799 | ||
800 | init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); | |
801 | ||
802 | PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n", | |
803 | __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, | |
804 | swsqe->opcode, swsqe->read_len); | |
805 | wr = wr->next; | |
806 | num_wrs--; | |
d37ac31d SW |
807 | t4_sq_produce(&qhp->wq, len16); |
808 | idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); | |
cfdda9d7 | 809 | } |
05eb2389 | 810 | if (!qhp->rhp->rdev.status_page->db_off) { |
fa658a98 SW |
811 | t4_ring_sq_db(&qhp->wq, idx, |
812 | is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe); | |
05eb2389 SW |
813 | spin_unlock_irqrestore(&qhp->lock, flag); |
814 | } else { | |
815 | spin_unlock_irqrestore(&qhp->lock, flag); | |
816 | ring_kernel_sq_db(qhp, idx); | |
817 | } | |
cfdda9d7 SW |
818 | return err; |
819 | } | |
820 | ||
821 | int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, | |
822 | struct ib_recv_wr **bad_wr) | |
823 | { | |
824 | int err = 0; | |
825 | struct c4iw_qp *qhp; | |
fa658a98 | 826 | union t4_recv_wr *wqe = NULL; |
cfdda9d7 SW |
827 | u32 num_wrs; |
828 | u8 len16 = 0; | |
829 | unsigned long flag; | |
830 | u16 idx = 0; | |
831 | ||
832 | qhp = to_c4iw_qp(ibqp); | |
833 | spin_lock_irqsave(&qhp->lock, flag); | |
834 | if (t4_wq_in_error(&qhp->wq)) { | |
835 | spin_unlock_irqrestore(&qhp->lock, flag); | |
836 | return -EINVAL; | |
837 | } | |
838 | num_wrs = t4_rq_avail(&qhp->wq); | |
839 | if (num_wrs == 0) { | |
840 | spin_unlock_irqrestore(&qhp->lock, flag); | |
841 | return -ENOMEM; | |
842 | } | |
843 | while (wr) { | |
844 | if (wr->num_sge > T4_MAX_RECV_SGE) { | |
845 | err = -EINVAL; | |
846 | *bad_wr = wr; | |
847 | break; | |
848 | } | |
d37ac31d SW |
849 | wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + |
850 | qhp->wq.rq.wq_pidx * | |
851 | T4_EQ_ENTRY_SIZE); | |
cfdda9d7 SW |
852 | if (num_wrs) |
853 | err = build_rdma_recv(qhp, wqe, wr, &len16); | |
854 | else | |
855 | err = -ENOMEM; | |
856 | if (err) { | |
857 | *bad_wr = wr; | |
858 | break; | |
859 | } | |
860 | ||
861 | qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; | |
862 | ||
863 | wqe->recv.opcode = FW_RI_RECV_WR; | |
864 | wqe->recv.r1 = 0; | |
865 | wqe->recv.wrid = qhp->wq.rq.pidx; | |
866 | wqe->recv.r2[0] = 0; | |
867 | wqe->recv.r2[1] = 0; | |
868 | wqe->recv.r2[2] = 0; | |
869 | wqe->recv.len16 = len16; | |
cfdda9d7 SW |
870 | PDBG("%s cookie 0x%llx pidx %u\n", __func__, |
871 | (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); | |
d37ac31d SW |
872 | t4_rq_produce(&qhp->wq, len16); |
873 | idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); | |
cfdda9d7 SW |
874 | wr = wr->next; |
875 | num_wrs--; | |
cfdda9d7 | 876 | } |
05eb2389 | 877 | if (!qhp->rhp->rdev.status_page->db_off) { |
fa658a98 SW |
878 | t4_ring_rq_db(&qhp->wq, idx, |
879 | is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe); | |
05eb2389 SW |
880 | spin_unlock_irqrestore(&qhp->lock, flag); |
881 | } else { | |
882 | spin_unlock_irqrestore(&qhp->lock, flag); | |
883 | ring_kernel_rq_db(qhp, idx); | |
884 | } | |
cfdda9d7 SW |
885 | return err; |
886 | } | |
887 | ||
888 | int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind) | |
889 | { | |
890 | return -ENOSYS; | |
891 | } | |
892 | ||
893 | static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, | |
894 | u8 *ecode) | |
895 | { | |
896 | int status; | |
897 | int tagged; | |
898 | int opcode; | |
899 | int rqtype; | |
900 | int send_inv; | |
901 | ||
902 | if (!err_cqe) { | |
903 | *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; | |
904 | *ecode = 0; | |
905 | return; | |
906 | } | |
907 | ||
908 | status = CQE_STATUS(err_cqe); | |
909 | opcode = CQE_OPCODE(err_cqe); | |
910 | rqtype = RQ_TYPE(err_cqe); | |
911 | send_inv = (opcode == FW_RI_SEND_WITH_INV) || | |
912 | (opcode == FW_RI_SEND_WITH_SE_INV); | |
913 | tagged = (opcode == FW_RI_RDMA_WRITE) || | |
914 | (rqtype && (opcode == FW_RI_READ_RESP)); | |
915 | ||
916 | switch (status) { | |
917 | case T4_ERR_STAG: | |
918 | if (send_inv) { | |
919 | *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; | |
920 | *ecode = RDMAP_CANT_INV_STAG; | |
921 | } else { | |
922 | *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; | |
923 | *ecode = RDMAP_INV_STAG; | |
924 | } | |
925 | break; | |
926 | case T4_ERR_PDID: | |
927 | *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; | |
928 | if ((opcode == FW_RI_SEND_WITH_INV) || | |
929 | (opcode == FW_RI_SEND_WITH_SE_INV)) | |
930 | *ecode = RDMAP_CANT_INV_STAG; | |
931 | else | |
932 | *ecode = RDMAP_STAG_NOT_ASSOC; | |
933 | break; | |
934 | case T4_ERR_QPID: | |
935 | *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; | |
936 | *ecode = RDMAP_STAG_NOT_ASSOC; | |
937 | break; | |
938 | case T4_ERR_ACCESS: | |
939 | *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; | |
940 | *ecode = RDMAP_ACC_VIOL; | |
941 | break; | |
942 | case T4_ERR_WRAP: | |
943 | *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; | |
944 | *ecode = RDMAP_TO_WRAP; | |
945 | break; | |
946 | case T4_ERR_BOUND: | |
947 | if (tagged) { | |
948 | *layer_type = LAYER_DDP|DDP_TAGGED_ERR; | |
949 | *ecode = DDPT_BASE_BOUNDS; | |
950 | } else { | |
951 | *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; | |
952 | *ecode = RDMAP_BASE_BOUNDS; | |
953 | } | |
954 | break; | |
955 | case T4_ERR_INVALIDATE_SHARED_MR: | |
956 | case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: | |
957 | *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; | |
958 | *ecode = RDMAP_CANT_INV_STAG; | |
959 | break; | |
960 | case T4_ERR_ECC: | |
961 | case T4_ERR_ECC_PSTAG: | |
962 | case T4_ERR_INTERNAL_ERR: | |
963 | *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; | |
964 | *ecode = 0; | |
965 | break; | |
966 | case T4_ERR_OUT_OF_RQE: | |
967 | *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; | |
968 | *ecode = DDPU_INV_MSN_NOBUF; | |
969 | break; | |
970 | case T4_ERR_PBL_ADDR_BOUND: | |
971 | *layer_type = LAYER_DDP|DDP_TAGGED_ERR; | |
972 | *ecode = DDPT_BASE_BOUNDS; | |
973 | break; | |
974 | case T4_ERR_CRC: | |
975 | *layer_type = LAYER_MPA|DDP_LLP; | |
976 | *ecode = MPA_CRC_ERR; | |
977 | break; | |
978 | case T4_ERR_MARKER: | |
979 | *layer_type = LAYER_MPA|DDP_LLP; | |
980 | *ecode = MPA_MARKER_ERR; | |
981 | break; | |
982 | case T4_ERR_PDU_LEN_ERR: | |
983 | *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; | |
984 | *ecode = DDPU_MSG_TOOBIG; | |
985 | break; | |
986 | case T4_ERR_DDP_VERSION: | |
987 | if (tagged) { | |
988 | *layer_type = LAYER_DDP|DDP_TAGGED_ERR; | |
989 | *ecode = DDPT_INV_VERS; | |
990 | } else { | |
991 | *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; | |
992 | *ecode = DDPU_INV_VERS; | |
993 | } | |
994 | break; | |
995 | case T4_ERR_RDMA_VERSION: | |
996 | *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; | |
997 | *ecode = RDMAP_INV_VERS; | |
998 | break; | |
999 | case T4_ERR_OPCODE: | |
1000 | *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; | |
1001 | *ecode = RDMAP_INV_OPCODE; | |
1002 | break; | |
1003 | case T4_ERR_DDP_QUEUE_NUM: | |
1004 | *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; | |
1005 | *ecode = DDPU_INV_QN; | |
1006 | break; | |
1007 | case T4_ERR_MSN: | |
1008 | case T4_ERR_MSN_GAP: | |
1009 | case T4_ERR_MSN_RANGE: | |
1010 | case T4_ERR_IRD_OVERFLOW: | |
1011 | *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; | |
1012 | *ecode = DDPU_INV_MSN_RANGE; | |
1013 | break; | |
1014 | case T4_ERR_TBIT: | |
1015 | *layer_type = LAYER_DDP|DDP_LOCAL_CATA; | |
1016 | *ecode = 0; | |
1017 | break; | |
1018 | case T4_ERR_MO: | |
1019 | *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; | |
1020 | *ecode = DDPU_INV_MO; | |
1021 | break; | |
1022 | default: | |
1023 | *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; | |
1024 | *ecode = 0; | |
1025 | break; | |
1026 | } | |
1027 | } | |
1028 | ||
be4c9bad RD |
1029 | static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, |
1030 | gfp_t gfp) | |
cfdda9d7 SW |
1031 | { |
1032 | struct fw_ri_wr *wqe; | |
1033 | struct sk_buff *skb; | |
1034 | struct terminate_message *term; | |
1035 | ||
1036 | PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, | |
1037 | qhp->ep->hwtid); | |
1038 | ||
be4c9bad | 1039 | skb = alloc_skb(sizeof *wqe, gfp); |
cfdda9d7 | 1040 | if (!skb) |
be4c9bad | 1041 | return; |
cfdda9d7 SW |
1042 | set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); |
1043 | ||
1044 | wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); | |
1045 | memset(wqe, 0, sizeof *wqe); | |
1046 | wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR)); | |
1047 | wqe->flowid_len16 = cpu_to_be32( | |
1048 | FW_WR_FLOWID(qhp->ep->hwtid) | | |
1049 | FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); | |
1050 | ||
1051 | wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; | |
1052 | wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); | |
1053 | term = (struct terminate_message *)wqe->u.terminate.termmsg; | |
d2fe99e8 KS |
1054 | if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { |
1055 | term->layer_etype = qhp->attr.layer_etype; | |
1056 | term->ecode = qhp->attr.ecode; | |
1057 | } else | |
1058 | build_term_codes(err_cqe, &term->layer_etype, &term->ecode); | |
be4c9bad | 1059 | c4iw_ofld_send(&qhp->rhp->rdev, skb); |
cfdda9d7 SW |
1060 | } |
1061 | ||
1062 | /* | |
1063 | * Assumes qhp lock is held. | |
1064 | */ | |
1065 | static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, | |
2f5b48c3 | 1066 | struct c4iw_cq *schp) |
cfdda9d7 SW |
1067 | { |
1068 | int count; | |
1069 | int flushed; | |
2f5b48c3 | 1070 | unsigned long flag; |
cfdda9d7 SW |
1071 | |
1072 | PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp); | |
cfdda9d7 | 1073 | |
732bee7a | 1074 | /* locking hierarchy: cq lock first, then qp lock. */ |
2f5b48c3 | 1075 | spin_lock_irqsave(&rchp->lock, flag); |
cfdda9d7 | 1076 | spin_lock(&qhp->lock); |
1cf24dce SW |
1077 | |
1078 | if (qhp->wq.flushed) { | |
1079 | spin_unlock(&qhp->lock); | |
1080 | spin_unlock_irqrestore(&rchp->lock, flag); | |
1081 | return; | |
1082 | } | |
1083 | qhp->wq.flushed = 1; | |
1084 | ||
1085 | c4iw_flush_hw_cq(rchp); | |
cfdda9d7 SW |
1086 | c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); |
1087 | flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); | |
1088 | spin_unlock(&qhp->lock); | |
2f5b48c3 | 1089 | spin_unlock_irqrestore(&rchp->lock, flag); |
581bbe2c KS |
1090 | if (flushed) { |
1091 | spin_lock_irqsave(&rchp->comp_handler_lock, flag); | |
cfdda9d7 | 1092 | (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); |
581bbe2c KS |
1093 | spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); |
1094 | } | |
cfdda9d7 | 1095 | |
732bee7a | 1096 | /* locking hierarchy: cq lock first, then qp lock. */ |
2f5b48c3 | 1097 | spin_lock_irqsave(&schp->lock, flag); |
cfdda9d7 | 1098 | spin_lock(&qhp->lock); |
1cf24dce SW |
1099 | if (schp != rchp) |
1100 | c4iw_flush_hw_cq(schp); | |
1101 | flushed = c4iw_flush_sq(qhp); | |
cfdda9d7 | 1102 | spin_unlock(&qhp->lock); |
2f5b48c3 | 1103 | spin_unlock_irqrestore(&schp->lock, flag); |
581bbe2c KS |
1104 | if (flushed) { |
1105 | spin_lock_irqsave(&schp->comp_handler_lock, flag); | |
cfdda9d7 | 1106 | (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context); |
581bbe2c KS |
1107 | spin_unlock_irqrestore(&schp->comp_handler_lock, flag); |
1108 | } | |
cfdda9d7 SW |
1109 | } |
1110 | ||
2f5b48c3 | 1111 | static void flush_qp(struct c4iw_qp *qhp) |
cfdda9d7 SW |
1112 | { |
1113 | struct c4iw_cq *rchp, *schp; | |
581bbe2c | 1114 | unsigned long flag; |
cfdda9d7 | 1115 | |
1cf24dce SW |
1116 | rchp = to_c4iw_cq(qhp->ibqp.recv_cq); |
1117 | schp = to_c4iw_cq(qhp->ibqp.send_cq); | |
cfdda9d7 | 1118 | |
1cf24dce | 1119 | t4_set_wq_in_error(&qhp->wq); |
cfdda9d7 | 1120 | if (qhp->ibqp.uobject) { |
cfdda9d7 | 1121 | t4_set_cq_in_error(&rchp->cq); |
581bbe2c | 1122 | spin_lock_irqsave(&rchp->comp_handler_lock, flag); |
01e7da6b | 1123 | (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); |
581bbe2c | 1124 | spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); |
01e7da6b | 1125 | if (schp != rchp) { |
cfdda9d7 | 1126 | t4_set_cq_in_error(&schp->cq); |
581bbe2c | 1127 | spin_lock_irqsave(&schp->comp_handler_lock, flag); |
01e7da6b KS |
1128 | (*schp->ibcq.comp_handler)(&schp->ibcq, |
1129 | schp->ibcq.cq_context); | |
581bbe2c | 1130 | spin_unlock_irqrestore(&schp->comp_handler_lock, flag); |
01e7da6b | 1131 | } |
cfdda9d7 SW |
1132 | return; |
1133 | } | |
2f5b48c3 | 1134 | __flush_qp(qhp, rchp, schp); |
cfdda9d7 SW |
1135 | } |
1136 | ||
73d6fcad SW |
1137 | static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, |
1138 | struct c4iw_ep *ep) | |
cfdda9d7 SW |
1139 | { |
1140 | struct fw_ri_wr *wqe; | |
1141 | int ret; | |
cfdda9d7 SW |
1142 | struct sk_buff *skb; |
1143 | ||
1144 | PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, | |
73d6fcad | 1145 | ep->hwtid); |
cfdda9d7 | 1146 | |
d3c814e8 | 1147 | skb = alloc_skb(sizeof *wqe, GFP_KERNEL); |
cfdda9d7 SW |
1148 | if (!skb) |
1149 | return -ENOMEM; | |
73d6fcad | 1150 | set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx); |
cfdda9d7 SW |
1151 | |
1152 | wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); | |
1153 | memset(wqe, 0, sizeof *wqe); | |
1154 | wqe->op_compl = cpu_to_be32( | |
1155 | FW_WR_OP(FW_RI_INIT_WR) | | |
1156 | FW_WR_COMPL(1)); | |
1157 | wqe->flowid_len16 = cpu_to_be32( | |
73d6fcad | 1158 | FW_WR_FLOWID(ep->hwtid) | |
cfdda9d7 | 1159 | FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); |
2f5b48c3 | 1160 | wqe->cookie = (unsigned long) &ep->com.wr_wait; |
cfdda9d7 SW |
1161 | |
1162 | wqe->u.fini.type = FW_RI_TYPE_FINI; | |
cfdda9d7 SW |
1163 | ret = c4iw_ofld_send(&rhp->rdev, skb); |
1164 | if (ret) | |
1165 | goto out; | |
1166 | ||
2f5b48c3 | 1167 | ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid, |
aadc4df3 | 1168 | qhp->wq.sq.qid, __func__); |
cfdda9d7 SW |
1169 | out: |
1170 | PDBG("%s ret %d\n", __func__, ret); | |
1171 | return ret; | |
1172 | } | |
1173 | ||
1174 | static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) | |
1175 | { | |
d2fe99e8 | 1176 | PDBG("%s p2p_type = %d\n", __func__, p2p_type); |
cfdda9d7 SW |
1177 | memset(&init->u, 0, sizeof init->u); |
1178 | switch (p2p_type) { | |
1179 | case FW_RI_INIT_P2PTYPE_RDMA_WRITE: | |
1180 | init->u.write.opcode = FW_RI_RDMA_WRITE_WR; | |
1181 | init->u.write.stag_sink = cpu_to_be32(1); | |
1182 | init->u.write.to_sink = cpu_to_be64(1); | |
1183 | init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; | |
1184 | init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + | |
1185 | sizeof(struct fw_ri_immd), | |
1186 | 16); | |
1187 | break; | |
1188 | case FW_RI_INIT_P2PTYPE_READ_REQ: | |
1189 | init->u.write.opcode = FW_RI_RDMA_READ_WR; | |
1190 | init->u.read.stag_src = cpu_to_be32(1); | |
1191 | init->u.read.to_src_lo = cpu_to_be32(1); | |
1192 | init->u.read.stag_sink = cpu_to_be32(1); | |
1193 | init->u.read.to_sink_lo = cpu_to_be32(1); | |
1194 | init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); | |
1195 | break; | |
1196 | } | |
1197 | } | |
1198 | ||
1199 | static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) | |
1200 | { | |
1201 | struct fw_ri_wr *wqe; | |
1202 | int ret; | |
cfdda9d7 SW |
1203 | struct sk_buff *skb; |
1204 | ||
1205 | PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid, | |
1206 | qhp->ep->hwtid); | |
1207 | ||
d3c814e8 | 1208 | skb = alloc_skb(sizeof *wqe, GFP_KERNEL); |
cfdda9d7 SW |
1209 | if (!skb) |
1210 | return -ENOMEM; | |
1211 | set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); | |
1212 | ||
1213 | wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); | |
1214 | memset(wqe, 0, sizeof *wqe); | |
1215 | wqe->op_compl = cpu_to_be32( | |
1216 | FW_WR_OP(FW_RI_INIT_WR) | | |
1217 | FW_WR_COMPL(1)); | |
1218 | wqe->flowid_len16 = cpu_to_be32( | |
1219 | FW_WR_FLOWID(qhp->ep->hwtid) | | |
1220 | FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); | |
1221 | ||
2f5b48c3 | 1222 | wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait; |
cfdda9d7 SW |
1223 | |
1224 | wqe->u.init.type = FW_RI_TYPE_INIT; | |
1225 | wqe->u.init.mpareqbit_p2ptype = | |
1226 | V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) | | |
1227 | V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type); | |
1228 | wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; | |
1229 | if (qhp->attr.mpa_attr.recv_marker_enabled) | |
1230 | wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; | |
1231 | if (qhp->attr.mpa_attr.xmit_marker_enabled) | |
1232 | wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; | |
1233 | if (qhp->attr.mpa_attr.crc_enabled) | |
1234 | wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; | |
1235 | ||
1236 | wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | | |
1237 | FW_RI_QP_RDMA_WRITE_ENABLE | | |
1238 | FW_RI_QP_BIND_ENABLE; | |
1239 | if (!qhp->ibqp.uobject) | |
1240 | wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | | |
1241 | FW_RI_QP_STAG0_ENABLE; | |
1242 | wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); | |
1243 | wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); | |
1244 | wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); | |
1245 | wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); | |
1246 | wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); | |
1247 | wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); | |
1248 | wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); | |
1249 | wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); | |
1250 | wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); | |
1251 | wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq); | |
1252 | wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq); | |
1253 | wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); | |
1254 | wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - | |
1255 | rhp->rdev.lldi.vr->rq.start); | |
1256 | if (qhp->attr.mpa_attr.initiator) | |
1257 | build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); | |
1258 | ||
cfdda9d7 SW |
1259 | ret = c4iw_ofld_send(&rhp->rdev, skb); |
1260 | if (ret) | |
1261 | goto out; | |
1262 | ||
2f5b48c3 SW |
1263 | ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait, |
1264 | qhp->ep->hwtid, qhp->wq.sq.qid, __func__); | |
cfdda9d7 SW |
1265 | out: |
1266 | PDBG("%s ret %d\n", __func__, ret); | |
1267 | return ret; | |
1268 | } | |
1269 | ||
1270 | int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, | |
1271 | enum c4iw_qp_attr_mask mask, | |
1272 | struct c4iw_qp_attributes *attrs, | |
1273 | int internal) | |
1274 | { | |
1275 | int ret = 0; | |
1276 | struct c4iw_qp_attributes newattr = qhp->attr; | |
cfdda9d7 SW |
1277 | int disconnect = 0; |
1278 | int terminate = 0; | |
1279 | int abort = 0; | |
1280 | int free = 0; | |
1281 | struct c4iw_ep *ep = NULL; | |
1282 | ||
1283 | PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__, | |
1284 | qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state, | |
1285 | (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); | |
1286 | ||
2f5b48c3 | 1287 | mutex_lock(&qhp->mutex); |
cfdda9d7 SW |
1288 | |
1289 | /* Process attr changes if in IDLE */ | |
1290 | if (mask & C4IW_QP_ATTR_VALID_MODIFY) { | |
1291 | if (qhp->attr.state != C4IW_QP_STATE_IDLE) { | |
1292 | ret = -EIO; | |
1293 | goto out; | |
1294 | } | |
1295 | if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) | |
1296 | newattr.enable_rdma_read = attrs->enable_rdma_read; | |
1297 | if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) | |
1298 | newattr.enable_rdma_write = attrs->enable_rdma_write; | |
1299 | if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) | |
1300 | newattr.enable_bind = attrs->enable_bind; | |
1301 | if (mask & C4IW_QP_ATTR_MAX_ORD) { | |
be4c9bad | 1302 | if (attrs->max_ord > c4iw_max_read_depth) { |
cfdda9d7 SW |
1303 | ret = -EINVAL; |
1304 | goto out; | |
1305 | } | |
1306 | newattr.max_ord = attrs->max_ord; | |
1307 | } | |
1308 | if (mask & C4IW_QP_ATTR_MAX_IRD) { | |
be4c9bad | 1309 | if (attrs->max_ird > c4iw_max_read_depth) { |
cfdda9d7 SW |
1310 | ret = -EINVAL; |
1311 | goto out; | |
1312 | } | |
1313 | newattr.max_ird = attrs->max_ird; | |
1314 | } | |
1315 | qhp->attr = newattr; | |
1316 | } | |
1317 | ||
2c974781 | 1318 | if (mask & C4IW_QP_ATTR_SQ_DB) { |
05eb2389 | 1319 | ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc); |
2c974781 VP |
1320 | goto out; |
1321 | } | |
1322 | if (mask & C4IW_QP_ATTR_RQ_DB) { | |
05eb2389 | 1323 | ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc); |
2c974781 VP |
1324 | goto out; |
1325 | } | |
1326 | ||
cfdda9d7 SW |
1327 | if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) |
1328 | goto out; | |
1329 | if (qhp->attr.state == attrs->next_state) | |
1330 | goto out; | |
1331 | ||
1332 | switch (qhp->attr.state) { | |
1333 | case C4IW_QP_STATE_IDLE: | |
1334 | switch (attrs->next_state) { | |
1335 | case C4IW_QP_STATE_RTS: | |
1336 | if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { | |
1337 | ret = -EINVAL; | |
1338 | goto out; | |
1339 | } | |
1340 | if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { | |
1341 | ret = -EINVAL; | |
1342 | goto out; | |
1343 | } | |
1344 | qhp->attr.mpa_attr = attrs->mpa_attr; | |
1345 | qhp->attr.llp_stream_handle = attrs->llp_stream_handle; | |
1346 | qhp->ep = qhp->attr.llp_stream_handle; | |
2f5b48c3 | 1347 | set_state(qhp, C4IW_QP_STATE_RTS); |
cfdda9d7 SW |
1348 | |
1349 | /* | |
1350 | * Ref the endpoint here and deref when we | |
1351 | * disassociate the endpoint from the QP. This | |
1352 | * happens in CLOSING->IDLE transition or *->ERROR | |
1353 | * transition. | |
1354 | */ | |
1355 | c4iw_get_ep(&qhp->ep->com); | |
cfdda9d7 | 1356 | ret = rdma_init(rhp, qhp); |
cfdda9d7 SW |
1357 | if (ret) |
1358 | goto err; | |
1359 | break; | |
1360 | case C4IW_QP_STATE_ERROR: | |
2f5b48c3 SW |
1361 | set_state(qhp, C4IW_QP_STATE_ERROR); |
1362 | flush_qp(qhp); | |
cfdda9d7 SW |
1363 | break; |
1364 | default: | |
1365 | ret = -EINVAL; | |
1366 | goto out; | |
1367 | } | |
1368 | break; | |
1369 | case C4IW_QP_STATE_RTS: | |
1370 | switch (attrs->next_state) { | |
1371 | case C4IW_QP_STATE_CLOSING: | |
1372 | BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2); | |
b4e2901c | 1373 | t4_set_wq_in_error(&qhp->wq); |
2f5b48c3 | 1374 | set_state(qhp, C4IW_QP_STATE_CLOSING); |
73d6fcad | 1375 | ep = qhp->ep; |
cfdda9d7 SW |
1376 | if (!internal) { |
1377 | abort = 0; | |
1378 | disconnect = 1; | |
2f5b48c3 | 1379 | c4iw_get_ep(&qhp->ep->com); |
cfdda9d7 | 1380 | } |
73d6fcad | 1381 | ret = rdma_fini(rhp, qhp, ep); |
8da7e7a5 | 1382 | if (ret) |
cfdda9d7 | 1383 | goto err; |
cfdda9d7 SW |
1384 | break; |
1385 | case C4IW_QP_STATE_TERMINATE: | |
b4e2901c | 1386 | t4_set_wq_in_error(&qhp->wq); |
2f5b48c3 | 1387 | set_state(qhp, C4IW_QP_STATE_TERMINATE); |
d2fe99e8 KS |
1388 | qhp->attr.layer_etype = attrs->layer_etype; |
1389 | qhp->attr.ecode = attrs->ecode; | |
be4c9bad | 1390 | ep = qhp->ep; |
cc18b939 SW |
1391 | if (!internal) { |
1392 | c4iw_get_ep(&qhp->ep->com); | |
0e42c1f4 | 1393 | terminate = 1; |
cc18b939 SW |
1394 | disconnect = 1; |
1395 | } else { | |
1396 | terminate = qhp->attr.send_term; | |
09992579 SW |
1397 | ret = rdma_fini(rhp, qhp, ep); |
1398 | if (ret) | |
1399 | goto err; | |
1400 | } | |
cfdda9d7 SW |
1401 | break; |
1402 | case C4IW_QP_STATE_ERROR: | |
1cf24dce | 1403 | t4_set_wq_in_error(&qhp->wq); |
b4e2901c | 1404 | set_state(qhp, C4IW_QP_STATE_ERROR); |
cfdda9d7 SW |
1405 | if (!internal) { |
1406 | abort = 1; | |
1407 | disconnect = 1; | |
1408 | ep = qhp->ep; | |
2f5b48c3 | 1409 | c4iw_get_ep(&qhp->ep->com); |
cfdda9d7 SW |
1410 | } |
1411 | goto err; | |
1412 | break; | |
1413 | default: | |
1414 | ret = -EINVAL; | |
1415 | goto out; | |
1416 | } | |
1417 | break; | |
1418 | case C4IW_QP_STATE_CLOSING: | |
1419 | if (!internal) { | |
1420 | ret = -EINVAL; | |
1421 | goto out; | |
1422 | } | |
1423 | switch (attrs->next_state) { | |
1424 | case C4IW_QP_STATE_IDLE: | |
2f5b48c3 SW |
1425 | flush_qp(qhp); |
1426 | set_state(qhp, C4IW_QP_STATE_IDLE); | |
cfdda9d7 SW |
1427 | qhp->attr.llp_stream_handle = NULL; |
1428 | c4iw_put_ep(&qhp->ep->com); | |
1429 | qhp->ep = NULL; | |
1430 | wake_up(&qhp->wait); | |
1431 | break; | |
1432 | case C4IW_QP_STATE_ERROR: | |
1433 | goto err; | |
1434 | default: | |
1435 | ret = -EINVAL; | |
1436 | goto err; | |
1437 | } | |
1438 | break; | |
1439 | case C4IW_QP_STATE_ERROR: | |
1440 | if (attrs->next_state != C4IW_QP_STATE_IDLE) { | |
1441 | ret = -EINVAL; | |
1442 | goto out; | |
1443 | } | |
1444 | if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { | |
1445 | ret = -EINVAL; | |
1446 | goto out; | |
1447 | } | |
2f5b48c3 | 1448 | set_state(qhp, C4IW_QP_STATE_IDLE); |
cfdda9d7 SW |
1449 | break; |
1450 | case C4IW_QP_STATE_TERMINATE: | |
1451 | if (!internal) { | |
1452 | ret = -EINVAL; | |
1453 | goto out; | |
1454 | } | |
1455 | goto err; | |
1456 | break; | |
1457 | default: | |
1458 | printk(KERN_ERR "%s in a bad state %d\n", | |
1459 | __func__, qhp->attr.state); | |
1460 | ret = -EINVAL; | |
1461 | goto err; | |
1462 | break; | |
1463 | } | |
1464 | goto out; | |
1465 | err: | |
1466 | PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep, | |
1467 | qhp->wq.sq.qid); | |
1468 | ||
1469 | /* disassociate the LLP connection */ | |
1470 | qhp->attr.llp_stream_handle = NULL; | |
af93fb5d SW |
1471 | if (!ep) |
1472 | ep = qhp->ep; | |
cfdda9d7 | 1473 | qhp->ep = NULL; |
2f5b48c3 | 1474 | set_state(qhp, C4IW_QP_STATE_ERROR); |
cfdda9d7 | 1475 | free = 1; |
91e9c071 | 1476 | abort = 1; |
cfdda9d7 SW |
1477 | wake_up(&qhp->wait); |
1478 | BUG_ON(!ep); | |
2f5b48c3 | 1479 | flush_qp(qhp); |
cfdda9d7 | 1480 | out: |
2f5b48c3 | 1481 | mutex_unlock(&qhp->mutex); |
cfdda9d7 SW |
1482 | |
1483 | if (terminate) | |
be4c9bad | 1484 | post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); |
cfdda9d7 SW |
1485 | |
1486 | /* | |
1487 | * If disconnect is 1, then we need to initiate a disconnect | |
1488 | * on the EP. This can be a normal close (RTS->CLOSING) or | |
1489 | * an abnormal close (RTS/CLOSING->ERROR). | |
1490 | */ | |
1491 | if (disconnect) { | |
be4c9bad RD |
1492 | c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : |
1493 | GFP_KERNEL); | |
cfdda9d7 SW |
1494 | c4iw_put_ep(&ep->com); |
1495 | } | |
1496 | ||
1497 | /* | |
1498 | * If free is 1, then we've disassociated the EP from the QP | |
1499 | * and we need to dereference the EP. | |
1500 | */ | |
1501 | if (free) | |
1502 | c4iw_put_ep(&ep->com); | |
cfdda9d7 SW |
1503 | PDBG("%s exit state %d\n", __func__, qhp->attr.state); |
1504 | return ret; | |
1505 | } | |
1506 | ||
1507 | int c4iw_destroy_qp(struct ib_qp *ib_qp) | |
1508 | { | |
1509 | struct c4iw_dev *rhp; | |
1510 | struct c4iw_qp *qhp; | |
1511 | struct c4iw_qp_attributes attrs; | |
1512 | struct c4iw_ucontext *ucontext; | |
1513 | ||
1514 | qhp = to_c4iw_qp(ib_qp); | |
1515 | rhp = qhp->rhp; | |
1516 | ||
1517 | attrs.next_state = C4IW_QP_STATE_ERROR; | |
d2fe99e8 KS |
1518 | if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) |
1519 | c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); | |
1520 | else | |
1521 | c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); | |
cfdda9d7 SW |
1522 | wait_event(qhp->wait, !qhp->ep); |
1523 | ||
05eb2389 | 1524 | remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); |
cfdda9d7 SW |
1525 | atomic_dec(&qhp->refcnt); |
1526 | wait_event(qhp->wait, !atomic_read(&qhp->refcnt)); | |
1527 | ||
05eb2389 SW |
1528 | spin_lock_irq(&rhp->lock); |
1529 | if (!list_empty(&qhp->db_fc_entry)) | |
1530 | list_del_init(&qhp->db_fc_entry); | |
1531 | spin_unlock_irq(&rhp->lock); | |
1532 | ||
cfdda9d7 SW |
1533 | ucontext = ib_qp->uobject ? |
1534 | to_c4iw_ucontext(ib_qp->uobject->context) : NULL; | |
1535 | destroy_qp(&rhp->rdev, &qhp->wq, | |
1536 | ucontext ? &ucontext->uctx : &rhp->rdev.uctx); | |
1537 | ||
1538 | PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid); | |
1539 | kfree(qhp); | |
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, | |
1544 | struct ib_udata *udata) | |
1545 | { | |
1546 | struct c4iw_dev *rhp; | |
1547 | struct c4iw_qp *qhp; | |
1548 | struct c4iw_pd *php; | |
1549 | struct c4iw_cq *schp; | |
1550 | struct c4iw_cq *rchp; | |
1551 | struct c4iw_create_qp_resp uresp; | |
ff1706f4 | 1552 | unsigned int sqsize, rqsize; |
cfdda9d7 SW |
1553 | struct c4iw_ucontext *ucontext; |
1554 | int ret; | |
c6d7b267 | 1555 | struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL; |
cfdda9d7 SW |
1556 | |
1557 | PDBG("%s ib_pd %p\n", __func__, pd); | |
1558 | ||
1559 | if (attrs->qp_type != IB_QPT_RC) | |
1560 | return ERR_PTR(-EINVAL); | |
1561 | ||
1562 | php = to_c4iw_pd(pd); | |
1563 | rhp = php->rhp; | |
1564 | schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); | |
1565 | rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); | |
1566 | if (!schp || !rchp) | |
1567 | return ERR_PTR(-EINVAL); | |
1568 | ||
1569 | if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) | |
1570 | return ERR_PTR(-EINVAL); | |
1571 | ||
1572 | rqsize = roundup(attrs->cap.max_recv_wr + 1, 16); | |
1573 | if (rqsize > T4_MAX_RQ_SIZE) | |
1574 | return ERR_PTR(-E2BIG); | |
1575 | ||
1576 | sqsize = roundup(attrs->cap.max_send_wr + 1, 16); | |
1577 | if (sqsize > T4_MAX_SQ_SIZE) | |
1578 | return ERR_PTR(-E2BIG); | |
1579 | ||
1580 | ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; | |
1581 | ||
cfdda9d7 SW |
1582 | qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); |
1583 | if (!qhp) | |
1584 | return ERR_PTR(-ENOMEM); | |
1585 | qhp->wq.sq.size = sqsize; | |
1586 | qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue; | |
1cf24dce | 1587 | qhp->wq.sq.flush_cidx = -1; |
cfdda9d7 SW |
1588 | qhp->wq.rq.size = rqsize; |
1589 | qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue; | |
1590 | ||
1591 | if (ucontext) { | |
1592 | qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); | |
1593 | qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); | |
1594 | } | |
1595 | ||
1596 | PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n", | |
1597 | __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize); | |
1598 | ||
1599 | ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, | |
1600 | ucontext ? &ucontext->uctx : &rhp->rdev.uctx); | |
1601 | if (ret) | |
1602 | goto err1; | |
1603 | ||
1604 | attrs->cap.max_recv_wr = rqsize - 1; | |
1605 | attrs->cap.max_send_wr = sqsize - 1; | |
1606 | attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; | |
1607 | ||
1608 | qhp->rhp = rhp; | |
1609 | qhp->attr.pd = php->pdid; | |
1610 | qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; | |
1611 | qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; | |
1612 | qhp->attr.sq_num_entries = attrs->cap.max_send_wr; | |
1613 | qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; | |
1614 | qhp->attr.sq_max_sges = attrs->cap.max_send_sge; | |
1615 | qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; | |
1616 | qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; | |
1617 | qhp->attr.state = C4IW_QP_STATE_IDLE; | |
1618 | qhp->attr.next_state = C4IW_QP_STATE_IDLE; | |
1619 | qhp->attr.enable_rdma_read = 1; | |
1620 | qhp->attr.enable_rdma_write = 1; | |
1621 | qhp->attr.enable_bind = 1; | |
1622 | qhp->attr.max_ord = 1; | |
1623 | qhp->attr.max_ird = 1; | |
ba32de9d | 1624 | qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR; |
cfdda9d7 | 1625 | spin_lock_init(&qhp->lock); |
2f5b48c3 | 1626 | mutex_init(&qhp->mutex); |
cfdda9d7 SW |
1627 | init_waitqueue_head(&qhp->wait); |
1628 | atomic_set(&qhp->refcnt, 1); | |
1629 | ||
05eb2389 | 1630 | ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); |
cfdda9d7 SW |
1631 | if (ret) |
1632 | goto err2; | |
1633 | ||
cfdda9d7 SW |
1634 | if (udata) { |
1635 | mm1 = kmalloc(sizeof *mm1, GFP_KERNEL); | |
1636 | if (!mm1) { | |
1637 | ret = -ENOMEM; | |
30a6a62f | 1638 | goto err3; |
cfdda9d7 SW |
1639 | } |
1640 | mm2 = kmalloc(sizeof *mm2, GFP_KERNEL); | |
1641 | if (!mm2) { | |
1642 | ret = -ENOMEM; | |
30a6a62f | 1643 | goto err4; |
cfdda9d7 SW |
1644 | } |
1645 | mm3 = kmalloc(sizeof *mm3, GFP_KERNEL); | |
1646 | if (!mm3) { | |
1647 | ret = -ENOMEM; | |
30a6a62f | 1648 | goto err5; |
cfdda9d7 SW |
1649 | } |
1650 | mm4 = kmalloc(sizeof *mm4, GFP_KERNEL); | |
1651 | if (!mm4) { | |
1652 | ret = -ENOMEM; | |
30a6a62f | 1653 | goto err6; |
cfdda9d7 | 1654 | } |
c6d7b267 SW |
1655 | if (t4_sq_onchip(&qhp->wq.sq)) { |
1656 | mm5 = kmalloc(sizeof *mm5, GFP_KERNEL); | |
1657 | if (!mm5) { | |
1658 | ret = -ENOMEM; | |
1659 | goto err7; | |
1660 | } | |
1661 | uresp.flags = C4IW_QPF_ONCHIP; | |
1662 | } else | |
1663 | uresp.flags = 0; | |
cfdda9d7 SW |
1664 | uresp.qid_mask = rhp->rdev.qpmask; |
1665 | uresp.sqid = qhp->wq.sq.qid; | |
1666 | uresp.sq_size = qhp->wq.sq.size; | |
1667 | uresp.sq_memsize = qhp->wq.sq.memsize; | |
1668 | uresp.rqid = qhp->wq.rq.qid; | |
1669 | uresp.rq_size = qhp->wq.rq.size; | |
1670 | uresp.rq_memsize = qhp->wq.rq.memsize; | |
1671 | spin_lock(&ucontext->mmap_lock); | |
c6d7b267 SW |
1672 | if (mm5) { |
1673 | uresp.ma_sync_key = ucontext->key; | |
1674 | ucontext->key += PAGE_SIZE; | |
ae1fe07f DC |
1675 | } else { |
1676 | uresp.ma_sync_key = 0; | |
c6d7b267 | 1677 | } |
cfdda9d7 SW |
1678 | uresp.sq_key = ucontext->key; |
1679 | ucontext->key += PAGE_SIZE; | |
1680 | uresp.rq_key = ucontext->key; | |
1681 | ucontext->key += PAGE_SIZE; | |
1682 | uresp.sq_db_gts_key = ucontext->key; | |
1683 | ucontext->key += PAGE_SIZE; | |
1684 | uresp.rq_db_gts_key = ucontext->key; | |
1685 | ucontext->key += PAGE_SIZE; | |
1686 | spin_unlock(&ucontext->mmap_lock); | |
1687 | ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); | |
1688 | if (ret) | |
c6d7b267 | 1689 | goto err8; |
cfdda9d7 | 1690 | mm1->key = uresp.sq_key; |
c6d7b267 | 1691 | mm1->addr = qhp->wq.sq.phys_addr; |
cfdda9d7 SW |
1692 | mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize); |
1693 | insert_mmap(ucontext, mm1); | |
1694 | mm2->key = uresp.rq_key; | |
1695 | mm2->addr = virt_to_phys(qhp->wq.rq.queue); | |
1696 | mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize); | |
1697 | insert_mmap(ucontext, mm2); | |
1698 | mm3->key = uresp.sq_db_gts_key; | |
fa658a98 | 1699 | mm3->addr = (__force unsigned long) qhp->wq.sq.udb; |
cfdda9d7 SW |
1700 | mm3->len = PAGE_SIZE; |
1701 | insert_mmap(ucontext, mm3); | |
1702 | mm4->key = uresp.rq_db_gts_key; | |
fa658a98 | 1703 | mm4->addr = (__force unsigned long) qhp->wq.rq.udb; |
cfdda9d7 SW |
1704 | mm4->len = PAGE_SIZE; |
1705 | insert_mmap(ucontext, mm4); | |
c6d7b267 SW |
1706 | if (mm5) { |
1707 | mm5->key = uresp.ma_sync_key; | |
1708 | mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0) | |
1709 | + A_PCIE_MA_SYNC) & PAGE_MASK; | |
1710 | mm5->len = PAGE_SIZE; | |
1711 | insert_mmap(ucontext, mm5); | |
1712 | } | |
cfdda9d7 SW |
1713 | } |
1714 | qhp->ibqp.qp_num = qhp->wq.sq.qid; | |
1715 | init_timer(&(qhp->timer)); | |
05eb2389 | 1716 | INIT_LIST_HEAD(&qhp->db_fc_entry); |
cfdda9d7 SW |
1717 | PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n", |
1718 | __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries, | |
1719 | qhp->wq.sq.qid); | |
1720 | return &qhp->ibqp; | |
c6d7b267 SW |
1721 | err8: |
1722 | kfree(mm5); | |
cfdda9d7 | 1723 | err7: |
30a6a62f | 1724 | kfree(mm4); |
cfdda9d7 | 1725 | err6: |
30a6a62f | 1726 | kfree(mm3); |
cfdda9d7 | 1727 | err5: |
30a6a62f | 1728 | kfree(mm2); |
cfdda9d7 | 1729 | err4: |
30a6a62f | 1730 | kfree(mm1); |
cfdda9d7 SW |
1731 | err3: |
1732 | remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); | |
1733 | err2: | |
1734 | destroy_qp(&rhp->rdev, &qhp->wq, | |
1735 | ucontext ? &ucontext->uctx : &rhp->rdev.uctx); | |
1736 | err1: | |
1737 | kfree(qhp); | |
1738 | return ERR_PTR(ret); | |
1739 | } | |
1740 | ||
1741 | int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
1742 | int attr_mask, struct ib_udata *udata) | |
1743 | { | |
1744 | struct c4iw_dev *rhp; | |
1745 | struct c4iw_qp *qhp; | |
1746 | enum c4iw_qp_attr_mask mask = 0; | |
1747 | struct c4iw_qp_attributes attrs; | |
1748 | ||
1749 | PDBG("%s ib_qp %p\n", __func__, ibqp); | |
1750 | ||
1751 | /* iwarp does not support the RTR state */ | |
1752 | if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) | |
1753 | attr_mask &= ~IB_QP_STATE; | |
1754 | ||
1755 | /* Make sure we still have something left to do */ | |
1756 | if (!attr_mask) | |
1757 | return 0; | |
1758 | ||
1759 | memset(&attrs, 0, sizeof attrs); | |
1760 | qhp = to_c4iw_qp(ibqp); | |
1761 | rhp = qhp->rhp; | |
1762 | ||
1763 | attrs.next_state = c4iw_convert_state(attr->qp_state); | |
1764 | attrs.enable_rdma_read = (attr->qp_access_flags & | |
1765 | IB_ACCESS_REMOTE_READ) ? 1 : 0; | |
1766 | attrs.enable_rdma_write = (attr->qp_access_flags & | |
1767 | IB_ACCESS_REMOTE_WRITE) ? 1 : 0; | |
1768 | attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; | |
1769 | ||
1770 | ||
1771 | mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; | |
1772 | mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? | |
1773 | (C4IW_QP_ATTR_ENABLE_RDMA_READ | | |
1774 | C4IW_QP_ATTR_ENABLE_RDMA_WRITE | | |
1775 | C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; | |
1776 | ||
2c974781 VP |
1777 | /* |
1778 | * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for | |
1779 | * ringing the queue db when we're in DB_FULL mode. | |
c2f9da92 | 1780 | * Only allow this on T4 devices. |
2c974781 VP |
1781 | */ |
1782 | attrs.sq_db_inc = attr->sq_psn; | |
1783 | attrs.rq_db_inc = attr->rq_psn; | |
1784 | mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0; | |
1785 | mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0; | |
c2f9da92 SW |
1786 | if (is_t5(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) && |
1787 | (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB))) | |
1788 | return -EINVAL; | |
2c974781 | 1789 | |
cfdda9d7 SW |
1790 | return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); |
1791 | } | |
1792 | ||
1793 | struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) | |
1794 | { | |
1795 | PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn); | |
1796 | return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); | |
1797 | } | |
67bbc055 VP |
1798 | |
1799 | int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
1800 | int attr_mask, struct ib_qp_init_attr *init_attr) | |
1801 | { | |
1802 | struct c4iw_qp *qhp = to_c4iw_qp(ibqp); | |
1803 | ||
1804 | memset(attr, 0, sizeof *attr); | |
1805 | memset(init_attr, 0, sizeof *init_attr); | |
1806 | attr->qp_state = to_ib_qp_state(qhp->attr.state); | |
1807 | return 0; | |
1808 | } |