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RDMA/cxgb4: Use the BAR2/WC path for kernel QPs and T5 devices
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / iw_cxgb4.h
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31#ifndef __IW_CXGB4_H__
32#define __IW_CXGB4_H__
33
34#include <linux/mutex.h>
35#include <linux/list.h>
36#include <linux/spinlock.h>
37#include <linux/idr.h>
c337374b 38#include <linux/completion.h>
cfdda9d7
SW		 39#include <linux/netdevice.h>
40#include <linux/sched.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/inet.h>
44#include <linux/wait.h>
45#include <linux/kref.h>
46#include <linux/timer.h>
47#include <linux/io.h>
cfdda9d7
SW		 48
49#include <asm/byteorder.h>
50
51#include <net/net_namespace.h>
52
53#include <rdma/ib_verbs.h>
54#include <rdma/iw_cm.h>
55
56#include "cxgb4.h"
57#include "cxgb4_uld.h"
58#include "l2t.h"
59#include "user.h"
60
61#define DRV_NAME "iw_cxgb4"
62#define MOD DRV_NAME ":"
63
64extern int c4iw_debug;
65#define PDBG(fmt, args...) \
66do { \
67 if (c4iw_debug) \
68 printk(MOD fmt, ## args); \
69} while (0)
70
71#include "t4.h"
72
73#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
74#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
75
76static inline void *cplhdr(struct sk_buff *skb)
77{
78 return skb->data;
79}
80
ec3eead2
VP		 81#define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
82#define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
83
84struct c4iw_id_table {
85 u32 flags;
86 u32 start; /* logical minimal id */
87 u32 last; /* hint for find */
88 u32 max;
89 spinlock_t lock;
90 unsigned long *table;
91};
92
cfdda9d7 93struct c4iw_resource {
ec3eead2
VP		 94 struct c4iw_id_table tpt_table;
95 struct c4iw_id_table qid_table;
96 struct c4iw_id_table pdid_table;
cfdda9d7
SW		 97};
98
99struct c4iw_qid_list {
100 struct list_head entry;
101 u32 qid;
102};
103
104struct c4iw_dev_ucontext {
105 struct list_head qpids;
106 struct list_head cqids;
107 struct mutex lock;
108};
109
110enum c4iw_rdev_flags {
111 T4_FATAL_ERROR = (1<<0),
05eb2389 112 T4_STATUS_PAGE_DISABLED = (1<<1),
cfdda9d7
SW		 113};
114
8d81ef34
VP		 115struct c4iw_stat {
116 u64 total;
117 u64 cur;
118 u64 max;
ec3eead2 119 u64 fail;
8d81ef34
VP		 120};
121
122struct c4iw_stats {
123 struct mutex lock;
124 struct c4iw_stat qid;
125 struct c4iw_stat pd;
126 struct c4iw_stat stag;
127 struct c4iw_stat pbl;
128 struct c4iw_stat rqt;
129 struct c4iw_stat ocqp;
2c974781
VP		 130 u64 db_full;
131 u64 db_empty;
132 u64 db_drop;
422eea0a 133 u64 db_state_transitions;
05eb2389 134 u64 db_fc_interruptions;
5be78ee9 135 u64 tcam_full;
793dad94
VP		 136 u64 act_ofld_conn_fails;
137 u64 pas_ofld_conn_fails;
8d81ef34
VP		 138};
139
cfdda9d7
SW		 140struct c4iw_rdev {
141 struct c4iw_resource resource;
142 unsigned long qpshift;
143 u32 qpmask;
144 unsigned long cqshift;
145 u32 cqmask;
146 struct c4iw_dev_ucontext uctx;
147 struct gen_pool *pbl_pool;
148 struct gen_pool *rqt_pool;
c6d7b267 149 struct gen_pool *ocqp_pool;
cfdda9d7
SW		 150 u32 flags;
151 struct cxgb4_lld_info lldi;
fa658a98
SW		 152 unsigned long bar2_pa;
153 void __iomem *bar2_kva;
c6d7b267
SW		 154 unsigned long oc_mw_pa;
155 void __iomem *oc_mw_kva;
8d81ef34 156 struct c4iw_stats stats;
05eb2389 157 struct t4_dev_status_page *status_page;
cfdda9d7
SW		 158};
159
160static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
161{
162 return rdev->flags & T4_FATAL_ERROR;
163}
164
165static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
166{
167 return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
168}
169
3b174d94 170#define C4IW_WR_TO (30*HZ)
aadc4df3
SW		 171
172struct c4iw_wr_wait {
c337374b 173 struct completion completion;
aadc4df3
SW		 174 int ret;
175};
176
177static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
178{
179 wr_waitp->ret = 0;
c337374b 180 init_completion(&wr_waitp->completion);
aadc4df3
SW		 181}
182
d9594d99
SW		 183static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
184{
185 wr_waitp->ret = ret;
c337374b 186 complete(&wr_waitp->completion);
d9594d99
SW		 187}
188
aadc4df3
SW		 189static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
190 struct c4iw_wr_wait *wr_waitp,
191 u32 hwtid, u32 qpid,
192 const char *func)
193{
194 unsigned to = C4IW_WR_TO;
d9594d99 195 int ret;
aadc4df3 196
d9594d99 197 do {
c337374b 198 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
d9594d99 199 if (!ret) {
aadc4df3
SW		 200 printk(KERN_ERR MOD "%s - Device %s not responding - "
201 "tid %u qpid %u\n", func,
202 pci_name(rdev->lldi.pdev), hwtid, qpid);
2f25e9a5
SW		 203 if (c4iw_fatal_error(rdev)) {
204 wr_waitp->ret = -EIO;
205 break;
206 }
aadc4df3
SW		 207 to = to << 2;
208 }
d9594d99 209 } while (!ret);
aadc4df3 210 if (wr_waitp->ret)
30c95c2d
SW		 211 PDBG("%s: FW reply %d tid %u qpid %u\n",
212 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
aadc4df3
SW		 213 return wr_waitp->ret;
214}
215
2c974781
VP		 216enum db_state {
217 NORMAL = 0,
218 FLOW_CONTROL = 1,
05eb2389
SW		 219 RECOVERY = 2,
220 STOPPED = 3
2c974781
VP		 221};
222
cfdda9d7
SW		 223struct c4iw_dev {
224 struct ib_device ibdev;
225 struct c4iw_rdev rdev;
226 u32 device_cap_flags;
227 struct idr cqidr;
228 struct idr qpidr;
229 struct idr mmidr;
230 spinlock_t lock;
2c974781 231 struct mutex db_mutex;
cfdda9d7 232 struct dentry *debugfs_root;
2c974781 233 enum db_state db_state;
793dad94
VP		 234 struct idr hwtid_idr;
235 struct idr atid_idr;
236 struct idr stid_idr;
05eb2389 237 struct list_head db_fc_list;
cfdda9d7
SW		 238};
239
240static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
241{
242 return container_of(ibdev, struct c4iw_dev, ibdev);
243}
244
245static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
246{
247 return container_of(rdev, struct c4iw_dev, rdev);
248}
249
250static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
251{
252 return idr_find(&rhp->cqidr, cqid);
253}
254
255static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
256{
257 return idr_find(&rhp->qpidr, qpid);
258}
259
260static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
261{
262 return idr_find(&rhp->mmidr, mmid);
263}
264
2c974781
VP		 265static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
266 void *handle, u32 id, int lock)
cfdda9d7
SW		 267{
268 int ret;
cfdda9d7 269
e8d4dd60
TH		 270 if (lock) {
271 idr_preload(GFP_KERNEL);
272 spin_lock_irq(&rhp->lock);
273 }
274
275 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
276
277 if (lock) {
278 spin_unlock_irq(&rhp->lock);
279 idr_preload_end();
280 }
281
282 BUG_ON(ret == -ENOSPC);
283 return ret < 0 ? ret : 0;
cfdda9d7
SW		 284}
285
2c974781
VP		 286static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
287 void *handle, u32 id)
288{
289 return _insert_handle(rhp, idr, handle, id, 1);
290}
291
292static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
293 void *handle, u32 id)
294{
295 return _insert_handle(rhp, idr, handle, id, 0);
296}
297
422eea0a
VP		 298static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
299 u32 id, int lock)
cfdda9d7 300{
422eea0a
VP		 301 if (lock)
302 spin_lock_irq(&rhp->lock);
cfdda9d7 303 idr_remove(idr, id);
422eea0a
VP		 304 if (lock)
305 spin_unlock_irq(&rhp->lock);
306}
307
308static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
309{
310 _remove_handle(rhp, idr, id, 1);
311}
312
313static inline void remove_handle_nolock(struct c4iw_dev *rhp,
314 struct idr *idr, u32 id)
315{
316 _remove_handle(rhp, idr, id, 0);
cfdda9d7
SW		 317}
318
319struct c4iw_pd {
320 struct ib_pd ibpd;
321 u32 pdid;
322 struct c4iw_dev *rhp;
323};
324
325static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
326{
327 return container_of(ibpd, struct c4iw_pd, ibpd);
328}
329
330struct tpt_attributes {
331 u64 len;
332 u64 va_fbo;
333 enum fw_ri_mem_perms perms;
334 u32 stag;
335 u32 pdid;
336 u32 qpid;
337 u32 pbl_addr;
338 u32 pbl_size;
339 u32 state:1;
340 u32 type:2;
341 u32 rsvd:1;
342 u32 remote_invaliate_disable:1;
343 u32 zbva:1;
344 u32 mw_bind_enable:1;
345 u32 page_size:5;
346};
347
348struct c4iw_mr {
349 struct ib_mr ibmr;
350 struct ib_umem *umem;
351 struct c4iw_dev *rhp;
352 u64 kva;
353 struct tpt_attributes attr;
354};
355
356static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
357{
358 return container_of(ibmr, struct c4iw_mr, ibmr);
359}
360
361struct c4iw_mw {
362 struct ib_mw ibmw;
363 struct c4iw_dev *rhp;
364 u64 kva;
365 struct tpt_attributes attr;
366};
367
368static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
369{
370 return container_of(ibmw, struct c4iw_mw, ibmw);
371}
372
373struct c4iw_fr_page_list {
374 struct ib_fast_reg_page_list ibpl;
f38926aa 375 DEFINE_DMA_UNMAP_ADDR(mapping);
cfdda9d7
SW		 376 dma_addr_t dma_addr;
377 struct c4iw_dev *dev;
eda6d1d1 378 int pll_len;
cfdda9d7
SW		 379};
380
381static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
382 struct ib_fast_reg_page_list *ibpl)
383{
384 return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
385}
386
387struct c4iw_cq {
388 struct ib_cq ibcq;
389 struct c4iw_dev *rhp;
390 struct t4_cq cq;
391 spinlock_t lock;
581bbe2c 392 spinlock_t comp_handler_lock;
cfdda9d7
SW		 393 atomic_t refcnt;
394 wait_queue_head_t wait;
395};
396
397static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
398{
399 return container_of(ibcq, struct c4iw_cq, ibcq);
400}
401
402struct c4iw_mpa_attributes {
403 u8 initiator;
404 u8 recv_marker_enabled;
405 u8 xmit_marker_enabled;
406 u8 crc_enabled;
d2fe99e8 407 u8 enhanced_rdma_conn;
cfdda9d7
SW		 408 u8 version;
409 u8 p2p_type;
410};
411
412struct c4iw_qp_attributes {
413 u32 scq;
414 u32 rcq;
415 u32 sq_num_entries;
416 u32 rq_num_entries;
417 u32 sq_max_sges;
418 u32 sq_max_sges_rdma_write;
419 u32 rq_max_sges;
420 u32 state;
421 u8 enable_rdma_read;
422 u8 enable_rdma_write;
423 u8 enable_bind;
424 u8 enable_mmid0_fastreg;
425 u32 max_ord;
426 u32 max_ird;
427 u32 pd;
428 u32 next_state;
429 char terminate_buffer[52];
430 u32 terminate_msg_len;
431 u8 is_terminate_local;
432 struct c4iw_mpa_attributes mpa_attr;
433 struct c4iw_ep *llp_stream_handle;
d2fe99e8
KS		 434 u8 layer_etype;
435 u8 ecode;
2c974781
VP		 436 u16 sq_db_inc;
437 u16 rq_db_inc;
cfdda9d7
SW		 438};
439
440struct c4iw_qp {
441 struct ib_qp ibqp;
05eb2389 442 struct list_head db_fc_entry;
cfdda9d7
SW		 443 struct c4iw_dev *rhp;
444 struct c4iw_ep *ep;
445 struct c4iw_qp_attributes attr;
446 struct t4_wq wq;
447 spinlock_t lock;
2f5b48c3 448 struct mutex mutex;
cfdda9d7
SW		 449 atomic_t refcnt;
450 wait_queue_head_t wait;
451 struct timer_list timer;
ba32de9d 452 int sq_sig_all;
cfdda9d7
SW		 453};
454
455static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
456{
457 return container_of(ibqp, struct c4iw_qp, ibqp);
458}
459
460struct c4iw_ucontext {
461 struct ib_ucontext ibucontext;
462 struct c4iw_dev_ucontext uctx;
463 u32 key;
464 spinlock_t mmap_lock;
465 struct list_head mmaps;
466};
467
468static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
469{
470 return container_of(c, struct c4iw_ucontext, ibucontext);
471}
472
473struct c4iw_mm_entry {
474 struct list_head entry;
475 u64 addr;
476 u32 key;
477 unsigned len;
478};
479
480static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
481 u32 key, unsigned len)
482{
483 struct list_head *pos, *nxt;
484 struct c4iw_mm_entry *mm;
485
486 spin_lock(&ucontext->mmap_lock);
487 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
488
489 mm = list_entry(pos, struct c4iw_mm_entry, entry);
490 if (mm->key == key && mm->len == len) {
491 list_del_init(&mm->entry);
492 spin_unlock(&ucontext->mmap_lock);
493 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
494 key, (unsigned long long) mm->addr, mm->len);
495 return mm;
496 }
497 }
498 spin_unlock(&ucontext->mmap_lock);
499 return NULL;
500}
501
502static inline void insert_mmap(struct c4iw_ucontext *ucontext,
503 struct c4iw_mm_entry *mm)
504{
505 spin_lock(&ucontext->mmap_lock);
506 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
507 mm->key, (unsigned long long) mm->addr, mm->len);
508 list_add_tail(&mm->entry, &ucontext->mmaps);
509 spin_unlock(&ucontext->mmap_lock);
510}
511
512enum c4iw_qp_attr_mask {
513 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
2c974781
VP		 514 C4IW_QP_ATTR_SQ_DB = 1<<1,
515 C4IW_QP_ATTR_RQ_DB = 1<<2,
cfdda9d7
SW		 516 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
517 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
518 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
519 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
520 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
521 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
522 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
523 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
524 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
525 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
526 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
527 C4IW_QP_ATTR_MAX_ORD |
528 C4IW_QP_ATTR_MAX_IRD |
529 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
530 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
531 C4IW_QP_ATTR_MPA_ATTR |
532 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
533};
534
535int c4iw_modify_qp(struct c4iw_dev *rhp,
536 struct c4iw_qp *qhp,
537 enum c4iw_qp_attr_mask mask,
538 struct c4iw_qp_attributes *attrs,
539 int internal);
540
541enum c4iw_qp_state {
542 C4IW_QP_STATE_IDLE,
543 C4IW_QP_STATE_RTS,
544 C4IW_QP_STATE_ERROR,
545 C4IW_QP_STATE_TERMINATE,
546 C4IW_QP_STATE_CLOSING,
547 C4IW_QP_STATE_TOT
548};
549
550static inline int c4iw_convert_state(enum ib_qp_state ib_state)
551{
552 switch (ib_state) {
553 case IB_QPS_RESET:
554 case IB_QPS_INIT:
555 return C4IW_QP_STATE_IDLE;
556 case IB_QPS_RTS:
557 return C4IW_QP_STATE_RTS;
558 case IB_QPS_SQD:
559 return C4IW_QP_STATE_CLOSING;
560 case IB_QPS_SQE:
561 return C4IW_QP_STATE_TERMINATE;
562 case IB_QPS_ERR:
563 return C4IW_QP_STATE_ERROR;
564 default:
565 return -1;
566 }
567}
568
67bbc055
VP		 569static inline int to_ib_qp_state(int c4iw_qp_state)
570{
571 switch (c4iw_qp_state) {
572 case C4IW_QP_STATE_IDLE:
573 return IB_QPS_INIT;
574 case C4IW_QP_STATE_RTS:
575 return IB_QPS_RTS;
576 case C4IW_QP_STATE_CLOSING:
577 return IB_QPS_SQD;
578 case C4IW_QP_STATE_TERMINATE:
579 return IB_QPS_SQE;
580 case C4IW_QP_STATE_ERROR:
581 return IB_QPS_ERR;
582 }
583 return IB_QPS_ERR;
584}
585
cfdda9d7
SW		 586static inline u32 c4iw_ib_to_tpt_access(int a)
587{
588 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
589 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
590 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
591 FW_RI_MEM_ACCESS_LOCAL_READ;
592}
593
594static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
595{
596 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
597 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
598}
599
600enum c4iw_mmid_state {
601 C4IW_STAG_STATE_VALID,
602 C4IW_STAG_STATE_INVALID
603};
604
605#define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
606
607#define MPA_KEY_REQ "MPA ID Req Frame"
608#define MPA_KEY_REP "MPA ID Rep Frame"
609
610#define MPA_MAX_PRIVATE_DATA 256
d2fe99e8 611#define MPA_ENHANCED_RDMA_CONN 0x10
cfdda9d7
SW		 612#define MPA_REJECT 0x20
613#define MPA_CRC 0x40
614#define MPA_MARKERS 0x80
615#define MPA_FLAGS_MASK 0xE0
616
d2fe99e8
KS		 617#define MPA_V2_PEER2PEER_MODEL 0x8000
618#define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
619#define MPA_V2_RDMA_WRITE_RTR 0x8000
620#define MPA_V2_RDMA_READ_RTR 0x4000
621#define MPA_V2_IRD_ORD_MASK 0x3FFF
622
cfdda9d7
SW		 623#define c4iw_put_ep(ep) { \
624 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
625 ep, atomic_read(&((ep)->kref.refcount))); \
626 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
627 kref_put(&((ep)->kref), _c4iw_free_ep); \
628}
629
630#define c4iw_get_ep(ep) { \
631 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
632 ep, atomic_read(&((ep)->kref.refcount))); \
633 kref_get(&((ep)->kref)); \
634}
635void _c4iw_free_ep(struct kref *kref);
636
637struct mpa_message {
638 u8 key[16];
639 u8 flags;
640 u8 revision;
641 __be16 private_data_size;
642 u8 private_data[0];
643};
644
d2fe99e8
KS		 645struct mpa_v2_conn_params {
646 __be16 ird;
647 __be16 ord;
648};
649
cfdda9d7
SW		 650struct terminate_message {
651 u8 layer_etype;
652 u8 ecode;
653 __be16 hdrct_rsvd;
654 u8 len_hdrs[0];
655};
656
657#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
658
659enum c4iw_layers_types {
660 LAYER_RDMAP = 0x00,
661 LAYER_DDP = 0x10,
662 LAYER_MPA = 0x20,
663 RDMAP_LOCAL_CATA = 0x00,
664 RDMAP_REMOTE_PROT = 0x01,
665 RDMAP_REMOTE_OP = 0x02,
666 DDP_LOCAL_CATA = 0x00,
667 DDP_TAGGED_ERR = 0x01,
668 DDP_UNTAGGED_ERR = 0x02,
669 DDP_LLP = 0x03
670};
671
672enum c4iw_rdma_ecodes {
673 RDMAP_INV_STAG = 0x00,
674 RDMAP_BASE_BOUNDS = 0x01,
675 RDMAP_ACC_VIOL = 0x02,
676 RDMAP_STAG_NOT_ASSOC = 0x03,
677 RDMAP_TO_WRAP = 0x04,
678 RDMAP_INV_VERS = 0x05,
679 RDMAP_INV_OPCODE = 0x06,
680 RDMAP_STREAM_CATA = 0x07,
681 RDMAP_GLOBAL_CATA = 0x08,
682 RDMAP_CANT_INV_STAG = 0x09,
683 RDMAP_UNSPECIFIED = 0xff
684};
685
686enum c4iw_ddp_ecodes {
687 DDPT_INV_STAG = 0x00,
688 DDPT_BASE_BOUNDS = 0x01,
689 DDPT_STAG_NOT_ASSOC = 0x02,
690 DDPT_TO_WRAP = 0x03,
691 DDPT_INV_VERS = 0x04,
692 DDPU_INV_QN = 0x01,
693 DDPU_INV_MSN_NOBUF = 0x02,
694 DDPU_INV_MSN_RANGE = 0x03,
695 DDPU_INV_MO = 0x04,
696 DDPU_MSG_TOOBIG = 0x05,
697 DDPU_INV_VERS = 0x06
698};
699
700enum c4iw_mpa_ecodes {
701 MPA_CRC_ERR = 0x02,
d2fe99e8
KS		 702 MPA_MARKER_ERR = 0x03,
703 MPA_LOCAL_CATA = 0x05,
704 MPA_INSUFF_IRD = 0x06,
705 MPA_NOMATCH_RTR = 0x07,
cfdda9d7
SW		 706};
707
708enum c4iw_ep_state {
709 IDLE = 0,
710 LISTEN,
711 CONNECTING,
712 MPA_REQ_WAIT,
713 MPA_REQ_SENT,
714 MPA_REQ_RCVD,
715 MPA_REP_SENT,
716 FPDU_MODE,
717 ABORTING,
718 CLOSING,
719 MORIBUND,
720 DEAD,
721};
722
723enum c4iw_ep_flags {
724 PEER_ABORT_IN_PROGRESS = 0,
725 ABORT_REQ_IN_PROGRESS = 1,
726 RELEASE_RESOURCES = 2,
727 CLOSE_SENT = 3,
1ec779cc 728 TIMEOUT = 4,
325abead 729 QP_REFERENCED = 5,
cfdda9d7
SW		 730};
731
793dad94
VP		 732enum c4iw_ep_history {
733 ACT_OPEN_REQ = 0,
734 ACT_OFLD_CONN = 1,
735 ACT_OPEN_RPL = 2,
736 ACT_ESTAB = 3,
737 PASS_ACCEPT_REQ = 4,
738 PASS_ESTAB = 5,
739 ABORT_UPCALL = 6,
740 ESTAB_UPCALL = 7,
741 CLOSE_UPCALL = 8,
742 ULP_ACCEPT = 9,
743 ULP_REJECT = 10,
744 TIMEDOUT = 11,
745 PEER_ABORT = 12,
746 PEER_CLOSE = 13,
747 CONNREQ_UPCALL = 14,
748 ABORT_CONN = 15,
749 DISCONN_UPCALL = 16,
750 EP_DISC_CLOSE = 17,
751 EP_DISC_ABORT = 18,
752 CONN_RPL_UPCALL = 19,
753 ACT_RETRY_NOMEM = 20,
754 ACT_RETRY_INUSE = 21
755};
756
cfdda9d7
SW		 757struct c4iw_ep_common {
758 struct iw_cm_id *cm_id;
759 struct c4iw_qp *qp;
760 struct c4iw_dev *dev;
761 enum c4iw_ep_state state;
762 struct kref kref;
2f5b48c3 763 struct mutex mutex;
830662f6
VP		 764 struct sockaddr_storage local_addr;
765 struct sockaddr_storage remote_addr;
aadc4df3 766 struct c4iw_wr_wait wr_wait;
cfdda9d7 767 unsigned long flags;
793dad94 768 unsigned long history;
cfdda9d7
SW		 769};
770
771struct c4iw_listen_ep {
772 struct c4iw_ep_common com;
773 unsigned int stid;
774 int backlog;
775};
776
777struct c4iw_ep {
778 struct c4iw_ep_common com;
779 struct c4iw_ep *parent_ep;
780 struct timer_list timer;
be4c9bad 781 struct list_head entry;
cfdda9d7
SW		 782 unsigned int atid;
783 u32 hwtid;
784 u32 snd_seq;
785 u32 rcv_seq;
786 struct l2t_entry *l2t;
787 struct dst_entry *dst;
788 struct sk_buff *mpa_skb;
789 struct c4iw_mpa_attributes mpa_attr;
790 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
791 unsigned int mpa_pkt_len;
792 u32 ird;
793 u32 ord;
794 u32 smac_idx;
795 u32 tx_chan;
796 u32 mtu;
797 u16 mss;
798 u16 emss;
799 u16 plen;
800 u16 rss_qid;
801 u16 txq_idx;
d4f1a5c6 802 u16 ctrlq_idx;
cfdda9d7 803 u8 tos;
d2fe99e8
KS		 804 u8 retry_with_mpa_v1;
805 u8 tried_with_mpa_v1;
793dad94 806 unsigned int retry_count;
cfdda9d7
SW		 807};
808
809static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
810{
811 return cm_id->provider_data;
812}
813
814static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
815{
816 return cm_id->provider_data;
817}
818
819static inline int compute_wscale(int win)
820{
821 int wscale = 0;
822
823 while (wscale < 14 && (65535<<wscale) < win)
824 wscale++;
825 return wscale;
826}
827
f079af7a
VP		 828static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
829{
830#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
831 return infop->vr->ocq.size > 0;
832#else
833 return 0;
834#endif
835}
836
ec3eead2
VP		 837u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
838void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
839int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
840 u32 reserved, u32 flags);
841void c4iw_id_table_free(struct c4iw_id_table *alloc);
842
cfdda9d7
SW		 843typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
844
845int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
846 struct l2t_entry *l2t);
847void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
848 struct c4iw_dev_ucontext *uctx);
ec3eead2
VP		 849u32 c4iw_get_resource(struct c4iw_id_table *id_table);
850void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
cfdda9d7
SW		 851int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
852int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
853int c4iw_pblpool_create(struct c4iw_rdev *rdev);
854int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
c6d7b267 855int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
cfdda9d7
SW		 856void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
857void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
c6d7b267 858void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
cfdda9d7
SW		 859void c4iw_destroy_resource(struct c4iw_resource *rscp);
860int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
861int c4iw_register_device(struct c4iw_dev *dev);
862void c4iw_unregister_device(struct c4iw_dev *dev);
863int __init c4iw_cm_init(void);
864void __exit c4iw_cm_term(void);
865void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
866 struct c4iw_dev_ucontext *uctx);
867void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
868 struct c4iw_dev_ucontext *uctx);
869int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
870int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
871 struct ib_send_wr **bad_wr);
872int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
873 struct ib_recv_wr **bad_wr);
874int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
875 struct ib_mw_bind *mw_bind);
876int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
877int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
878int c4iw_destroy_listen(struct iw_cm_id *cm_id);
879int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
880int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
881void c4iw_qp_add_ref(struct ib_qp *qp);
882void c4iw_qp_rem_ref(struct ib_qp *qp);
883void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
884struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
885 struct ib_device *device,
886 int page_list_len);
887struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
888int c4iw_dealloc_mw(struct ib_mw *mw);
7083e42e 889struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
cfdda9d7
SW		 890struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
891 u64 length, u64 virt, int acc,
892 struct ib_udata *udata);
893struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
894struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
895 struct ib_phys_buf *buffer_list,
896 int num_phys_buf,
897 int acc,
898 u64 *iova_start);
899int c4iw_reregister_phys_mem(struct ib_mr *mr,
900 int mr_rereg_mask,
901 struct ib_pd *pd,
902 struct ib_phys_buf *buffer_list,
903 int num_phys_buf,
904 int acc, u64 *iova_start);
905int c4iw_dereg_mr(struct ib_mr *ib_mr);
906int c4iw_destroy_cq(struct ib_cq *ib_cq);
907struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
908 int vector,
909 struct ib_ucontext *ib_context,
910 struct ib_udata *udata);
911int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
912int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
913int c4iw_destroy_qp(struct ib_qp *ib_qp);
914struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
915 struct ib_qp_init_attr *attrs,
916 struct ib_udata *udata);
917int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
918 int attr_mask, struct ib_udata *udata);
67bbc055
VP		 919int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
920 int attr_mask, struct ib_qp_init_attr *init_attr);
cfdda9d7
SW		 921struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
922u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
923void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
924u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
925void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
c6d7b267
SW		 926u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
927void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
cfdda9d7 928int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
1cf24dce 929void c4iw_flush_hw_cq(struct c4iw_cq *chp);
cfdda9d7 930void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
cfdda9d7
SW		 931int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
932int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
1cf24dce 933int c4iw_flush_sq(struct c4iw_qp *qhp);
cfdda9d7
SW		 934int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
935u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
cfdda9d7
SW		 936int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
937u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
938void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
939 struct c4iw_dev_ucontext *uctx);
940u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
941void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
942 struct c4iw_dev_ucontext *uctx);
943void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
944
945extern struct cxgb4_client t4c_client;
946extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
be4c9bad 947extern int c4iw_max_read_depth;
422eea0a 948extern int db_fc_threshold;
80ccdd60 949extern int db_coalescing_threshold;
42b6a949 950extern int use_dsgl;
422eea0a 951
cfdda9d7
SW		 952
953#endif
Linux 6.x block layer and io_uring tree(s)