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cxgb4: Use more common logging style
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / iw_cxgb4.h
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31#ifndef __IW_CXGB4_H__
32#define __IW_CXGB4_H__
33
34#include <linux/mutex.h>
35#include <linux/list.h>
36#include <linux/spinlock.h>
37#include <linux/idr.h>
c337374b 38#include <linux/completion.h>
cfdda9d7 39#include <linux/netdevice.h>
589ee628 40#include <linux/sched/mm.h>
cfdda9d7
SW		 41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/inet.h>
44#include <linux/wait.h>
45#include <linux/kref.h>
46#include <linux/timer.h>
47#include <linux/io.h>
c12a67fe 48#include <linux/workqueue.h>
cfdda9d7
SW		 49
50#include <asm/byteorder.h>
51
52#include <net/net_namespace.h>
53
54#include <rdma/ib_verbs.h>
55#include <rdma/iw_cm.h>
9eccfe10
SW		 56#include <rdma/rdma_netlink.h>
57#include <rdma/iw_portmap.h>
cfdda9d7
SW		 58
59#include "cxgb4.h"
60#include "cxgb4_uld.h"
61#include "l2t.h"
e44ee2fd 62#include <rdma/cxgb4-abi.h>
cfdda9d7
SW		 63
64#define DRV_NAME "iw_cxgb4"
65#define MOD DRV_NAME ":"
66
700456bd
JP		 67#ifdef pr_fmt
68#undef pr_fmt
69#endif
70
71#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
72
cfdda9d7
SW		 73extern int c4iw_debug;
74#define PDBG(fmt, args...) \
75do { \
76 if (c4iw_debug) \
77 printk(MOD fmt, ## args); \
78} while (0)
79
80#include "t4.h"
81
82#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
83#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
84
85static inline void *cplhdr(struct sk_buff *skb)
86{
87 return skb->data;
88}
89
ec3eead2
VP		 90#define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
91#define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
92
93struct c4iw_id_table {
94 u32 flags;
95 u32 start; /* logical minimal id */
96 u32 last; /* hint for find */
97 u32 max;
98 spinlock_t lock;
99 unsigned long *table;
100};
101
cfdda9d7 102struct c4iw_resource {
ec3eead2
VP		 103 struct c4iw_id_table tpt_table;
104 struct c4iw_id_table qid_table;
105 struct c4iw_id_table pdid_table;
cfdda9d7
SW		 106};
107
108struct c4iw_qid_list {
109 struct list_head entry;
110 u32 qid;
111};
112
113struct c4iw_dev_ucontext {
114 struct list_head qpids;
115 struct list_head cqids;
116 struct mutex lock;
c12a67fe 117 struct kref kref;
cfdda9d7
SW		 118};
119
120enum c4iw_rdev_flags {
121 T4_FATAL_ERROR = (1<<0),
05eb2389 122 T4_STATUS_PAGE_DISABLED = (1<<1),
cfdda9d7
SW		 123};
124
8d81ef34
VP		 125struct c4iw_stat {
126 u64 total;
127 u64 cur;
128 u64 max;
ec3eead2 129 u64 fail;
8d81ef34
VP		 130};
131
132struct c4iw_stats {
133 struct mutex lock;
134 struct c4iw_stat qid;
135 struct c4iw_stat pd;
136 struct c4iw_stat stag;
137 struct c4iw_stat pbl;
138 struct c4iw_stat rqt;
139 struct c4iw_stat ocqp;
2c974781
VP		 140 u64 db_full;
141 u64 db_empty;
142 u64 db_drop;
422eea0a 143 u64 db_state_transitions;
05eb2389 144 u64 db_fc_interruptions;
5be78ee9 145 u64 tcam_full;
793dad94
VP		 146 u64 act_ofld_conn_fails;
147 u64 pas_ofld_conn_fails;
179d03bb 148 u64 neg_adv;
8d81ef34
VP		 149};
150
04e10e21
HS		 151struct c4iw_hw_queue {
152 int t4_eq_status_entries;
153 int t4_max_eq_size;
154 int t4_max_iq_size;
155 int t4_max_rq_size;
156 int t4_max_sq_size;
157 int t4_max_qp_depth;
158 int t4_max_cq_depth;
159 int t4_stat_len;
160};
161
7730b4c7
HS		 162struct wr_log_entry {
163 struct timespec post_host_ts;
164 struct timespec poll_host_ts;
165 u64 post_sge_ts;
166 u64 cqe_sge_ts;
167 u64 poll_sge_ts;
168 u16 qid;
169 u16 wr_id;
170 u8 opcode;
171 u8 valid;
172};
173
cfdda9d7
SW		 174struct c4iw_rdev {
175 struct c4iw_resource resource;
cfdda9d7 176 u32 qpmask;
cfdda9d7
SW		 177 u32 cqmask;
178 struct c4iw_dev_ucontext uctx;
179 struct gen_pool *pbl_pool;
180 struct gen_pool *rqt_pool;
c6d7b267 181 struct gen_pool *ocqp_pool;
cfdda9d7
SW		 182 u32 flags;
183 struct cxgb4_lld_info lldi;
fa658a98
SW		 184 unsigned long bar2_pa;
185 void __iomem *bar2_kva;
c6d7b267
SW		 186 unsigned long oc_mw_pa;
187 void __iomem *oc_mw_kva;
8d81ef34 188 struct c4iw_stats stats;
04e10e21 189 struct c4iw_hw_queue hw_queue;
05eb2389 190 struct t4_dev_status_page *status_page;
7730b4c7
HS		 191 atomic_t wr_log_idx;
192 struct wr_log_entry *wr_log;
193 int wr_log_size;
c12a67fe 194 struct workqueue_struct *free_workq;
cfdda9d7
SW		 195};
196
197static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
198{
199 return rdev->flags & T4_FATAL_ERROR;
200}
201
202static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
203{
91244bbd 204 return (int)(rdev->lldi.vr->stag.size >> 5);
cfdda9d7
SW		 205}
206
1fc8190d 207#define C4IW_WR_TO (60*HZ)
aadc4df3
SW		 208
209struct c4iw_wr_wait {
c337374b 210 struct completion completion;
aadc4df3
SW		 211 int ret;
212};
213
214static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
215{
216 wr_waitp->ret = 0;
c337374b 217 init_completion(&wr_waitp->completion);
aadc4df3
SW		 218}
219
d9594d99
SW		 220static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
221{
222 wr_waitp->ret = ret;
c337374b 223 complete(&wr_waitp->completion);
d9594d99
SW		 224}
225
aadc4df3
SW		 226static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
227 struct c4iw_wr_wait *wr_waitp,
228 u32 hwtid, u32 qpid,
229 const char *func)
230{
d9594d99 231 int ret;
aadc4df3 232
1fc8190d
H		 233 if (c4iw_fatal_error(rdev)) {
234 wr_waitp->ret = -EIO;
235 goto out;
236 }
237
238 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO);
239 if (!ret) {
240 PDBG("%s - Device %s not responding (disabling device) - tid %u qpid %u\n",
241 func, pci_name(rdev->lldi.pdev), hwtid, qpid);
242 rdev->flags |= T4_FATAL_ERROR;
243 wr_waitp->ret = -EIO;
244 }
245out:
aadc4df3 246 if (wr_waitp->ret)
30c95c2d
SW		 247 PDBG("%s: FW reply %d tid %u qpid %u\n",
248 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
aadc4df3
SW		 249 return wr_waitp->ret;
250}
251
2c974781
VP		 252enum db_state {
253 NORMAL = 0,
254 FLOW_CONTROL = 1,
05eb2389
SW		 255 RECOVERY = 2,
256 STOPPED = 3
2c974781
VP		 257};
258
cfdda9d7
SW		 259struct c4iw_dev {
260 struct ib_device ibdev;
261 struct c4iw_rdev rdev;
262 u32 device_cap_flags;
263 struct idr cqidr;
264 struct idr qpidr;
265 struct idr mmidr;
266 spinlock_t lock;
2c974781 267 struct mutex db_mutex;
cfdda9d7 268 struct dentry *debugfs_root;
2c974781 269 enum db_state db_state;
793dad94
VP		 270 struct idr hwtid_idr;
271 struct idr atid_idr;
272 struct idr stid_idr;
05eb2389 273 struct list_head db_fc_list;
4c2c5763 274 u32 avail_ird;
37eb816c 275 wait_queue_head_t wait;
cfdda9d7
SW		 276};
277
278static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
279{
280 return container_of(ibdev, struct c4iw_dev, ibdev);
281}
282
283static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
284{
285 return container_of(rdev, struct c4iw_dev, rdev);
286}
287
288static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
289{
290 return idr_find(&rhp->cqidr, cqid);
291}
292
293static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
294{
295 return idr_find(&rhp->qpidr, qpid);
296}
297
298static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
299{
300 return idr_find(&rhp->mmidr, mmid);
301}
302
2c974781
VP		 303static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
304 void *handle, u32 id, int lock)
cfdda9d7
SW		 305{
306 int ret;
cfdda9d7 307
e8d4dd60
TH		 308 if (lock) {
309 idr_preload(GFP_KERNEL);
310 spin_lock_irq(&rhp->lock);
311 }
312
313 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
314
315 if (lock) {
316 spin_unlock_irq(&rhp->lock);
317 idr_preload_end();
318 }
319
320 BUG_ON(ret == -ENOSPC);
321 return ret < 0 ? ret : 0;
cfdda9d7
SW		 322}
323
2c974781
VP		 324static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
325 void *handle, u32 id)
326{
327 return _insert_handle(rhp, idr, handle, id, 1);
328}
329
330static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
331 void *handle, u32 id)
332{
333 return _insert_handle(rhp, idr, handle, id, 0);
334}
335
422eea0a
VP		 336static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
337 u32 id, int lock)
cfdda9d7 338{
422eea0a
VP		 339 if (lock)
340 spin_lock_irq(&rhp->lock);
cfdda9d7 341 idr_remove(idr, id);
422eea0a
VP		 342 if (lock)
343 spin_unlock_irq(&rhp->lock);
344}
345
346static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
347{
348 _remove_handle(rhp, idr, id, 1);
349}
350
351static inline void remove_handle_nolock(struct c4iw_dev *rhp,
352 struct idr *idr, u32 id)
353{
354 _remove_handle(rhp, idr, id, 0);
cfdda9d7
SW		 355}
356
4c2c5763
HS		 357extern uint c4iw_max_read_depth;
358
359static inline int cur_max_read_depth(struct c4iw_dev *dev)
360{
361 return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth);
362}
363
cfdda9d7
SW		 364struct c4iw_pd {
365 struct ib_pd ibpd;
366 u32 pdid;
367 struct c4iw_dev *rhp;
368};
369
370static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
371{
372 return container_of(ibpd, struct c4iw_pd, ibpd);
373}
374
375struct tpt_attributes {
376 u64 len;
377 u64 va_fbo;
378 enum fw_ri_mem_perms perms;
379 u32 stag;
380 u32 pdid;
381 u32 qpid;
382 u32 pbl_addr;
383 u32 pbl_size;
384 u32 state:1;
385 u32 type:2;
386 u32 rsvd:1;
387 u32 remote_invaliate_disable:1;
388 u32 zbva:1;
389 u32 mw_bind_enable:1;
390 u32 page_size:5;
391};
392
393struct c4iw_mr {
394 struct ib_mr ibmr;
395 struct ib_umem *umem;
396 struct c4iw_dev *rhp;
0f8ab0b6 397 struct sk_buff *dereg_skb;
cfdda9d7
SW		 398 u64 kva;
399 struct tpt_attributes attr;
8376b86d
SG		 400 u64 *mpl;
401 dma_addr_t mpl_addr;
402 u32 max_mpl_len;
403 u32 mpl_len;
cfdda9d7
SW		 404};
405
406static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
407{
408 return container_of(ibmr, struct c4iw_mr, ibmr);
409}
410
411struct c4iw_mw {
412 struct ib_mw ibmw;
413 struct c4iw_dev *rhp;
0f8ab0b6 414 struct sk_buff *dereg_skb;
cfdda9d7
SW		 415 u64 kva;
416 struct tpt_attributes attr;
417};
418
419static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
420{
421 return container_of(ibmw, struct c4iw_mw, ibmw);
422}
423
cfdda9d7
SW		 424struct c4iw_cq {
425 struct ib_cq ibcq;
426 struct c4iw_dev *rhp;
dd6b0241 427 struct sk_buff *destroy_skb;
cfdda9d7
SW		 428 struct t4_cq cq;
429 spinlock_t lock;
581bbe2c 430 spinlock_t comp_handler_lock;
cfdda9d7
SW		 431 atomic_t refcnt;
432 wait_queue_head_t wait;
433};
434
435static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
436{
437 return container_of(ibcq, struct c4iw_cq, ibcq);
438}
439
440struct c4iw_mpa_attributes {
441 u8 initiator;
442 u8 recv_marker_enabled;
443 u8 xmit_marker_enabled;
444 u8 crc_enabled;
d2fe99e8 445 u8 enhanced_rdma_conn;
cfdda9d7
SW		 446 u8 version;
447 u8 p2p_type;
448};
449
450struct c4iw_qp_attributes {
451 u32 scq;
452 u32 rcq;
453 u32 sq_num_entries;
454 u32 rq_num_entries;
455 u32 sq_max_sges;
456 u32 sq_max_sges_rdma_write;
457 u32 rq_max_sges;
458 u32 state;
459 u8 enable_rdma_read;
460 u8 enable_rdma_write;
461 u8 enable_bind;
462 u8 enable_mmid0_fastreg;
463 u32 max_ord;
464 u32 max_ird;
465 u32 pd;
466 u32 next_state;
467 char terminate_buffer[52];
468 u32 terminate_msg_len;
469 u8 is_terminate_local;
470 struct c4iw_mpa_attributes mpa_attr;
471 struct c4iw_ep *llp_stream_handle;
d2fe99e8
KS		 472 u8 layer_etype;
473 u8 ecode;
2c974781
VP		 474 u16 sq_db_inc;
475 u16 rq_db_inc;
cc18b939 476 u8 send_term;
cfdda9d7
SW		 477};
478
479struct c4iw_qp {
480 struct ib_qp ibqp;
05eb2389 481 struct list_head db_fc_entry;
cfdda9d7
SW		 482 struct c4iw_dev *rhp;
483 struct c4iw_ep *ep;
484 struct c4iw_qp_attributes attr;
485 struct t4_wq wq;
486 spinlock_t lock;
2f5b48c3 487 struct mutex mutex;
ad61a4c7 488 struct kref kref;
cfdda9d7
SW		 489 wait_queue_head_t wait;
490 struct timer_list timer;
ba32de9d 491 int sq_sig_all;
c12a67fe
SW		 492 struct work_struct free_work;
493 struct c4iw_ucontext *ucontext;
cfdda9d7
SW		 494};
495
496static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
497{
498 return container_of(ibqp, struct c4iw_qp, ibqp);
499}
500
501struct c4iw_ucontext {
502 struct ib_ucontext ibucontext;
503 struct c4iw_dev_ucontext uctx;
504 u32 key;
505 spinlock_t mmap_lock;
506 struct list_head mmaps;
c12a67fe 507 struct kref kref;
cfdda9d7
SW		 508};
509
510static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
511{
512 return container_of(c, struct c4iw_ucontext, ibucontext);
513}
514
c12a67fe
SW		 515void _c4iw_free_ucontext(struct kref *kref);
516
517static inline void c4iw_put_ucontext(struct c4iw_ucontext *ucontext)
518{
519 kref_put(&ucontext->kref, _c4iw_free_ucontext);
520}
521
522static inline void c4iw_get_ucontext(struct c4iw_ucontext *ucontext)
523{
524 kref_get(&ucontext->kref);
525}
526
cfdda9d7
SW		 527struct c4iw_mm_entry {
528 struct list_head entry;
529 u64 addr;
530 u32 key;
531 unsigned len;
532};
533
534static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
535 u32 key, unsigned len)
536{
537 struct list_head *pos, *nxt;
538 struct c4iw_mm_entry *mm;
539
540 spin_lock(&ucontext->mmap_lock);
541 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
542
543 mm = list_entry(pos, struct c4iw_mm_entry, entry);
544 if (mm->key == key && mm->len == len) {
545 list_del_init(&mm->entry);
546 spin_unlock(&ucontext->mmap_lock);
547 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
548 key, (unsigned long long) mm->addr, mm->len);
549 return mm;
550 }
551 }
552 spin_unlock(&ucontext->mmap_lock);
553 return NULL;
554}
555
556static inline void insert_mmap(struct c4iw_ucontext *ucontext,
557 struct c4iw_mm_entry *mm)
558{
559 spin_lock(&ucontext->mmap_lock);
560 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
561 mm->key, (unsigned long long) mm->addr, mm->len);
562 list_add_tail(&mm->entry, &ucontext->mmaps);
563 spin_unlock(&ucontext->mmap_lock);
564}
565
566enum c4iw_qp_attr_mask {
567 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
2c974781
VP		 568 C4IW_QP_ATTR_SQ_DB = 1<<1,
569 C4IW_QP_ATTR_RQ_DB = 1<<2,
cfdda9d7
SW		 570 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
571 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
572 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
573 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
574 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
575 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
576 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
577 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
578 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
579 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
580 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
581 C4IW_QP_ATTR_MAX_ORD |
582 C4IW_QP_ATTR_MAX_IRD |
583 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
584 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
585 C4IW_QP_ATTR_MPA_ATTR |
586 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
587};
588
589int c4iw_modify_qp(struct c4iw_dev *rhp,
590 struct c4iw_qp *qhp,
591 enum c4iw_qp_attr_mask mask,
592 struct c4iw_qp_attributes *attrs,
593 int internal);
594
595enum c4iw_qp_state {
596 C4IW_QP_STATE_IDLE,
597 C4IW_QP_STATE_RTS,
598 C4IW_QP_STATE_ERROR,
599 C4IW_QP_STATE_TERMINATE,
600 C4IW_QP_STATE_CLOSING,
601 C4IW_QP_STATE_TOT
602};
603
604static inline int c4iw_convert_state(enum ib_qp_state ib_state)
605{
606 switch (ib_state) {
607 case IB_QPS_RESET:
608 case IB_QPS_INIT:
609 return C4IW_QP_STATE_IDLE;
610 case IB_QPS_RTS:
611 return C4IW_QP_STATE_RTS;
612 case IB_QPS_SQD:
613 return C4IW_QP_STATE_CLOSING;
614 case IB_QPS_SQE:
615 return C4IW_QP_STATE_TERMINATE;
616 case IB_QPS_ERR:
617 return C4IW_QP_STATE_ERROR;
618 default:
619 return -1;
620 }
621}
622
67bbc055
VP		 623static inline int to_ib_qp_state(int c4iw_qp_state)
624{
625 switch (c4iw_qp_state) {
626 case C4IW_QP_STATE_IDLE:
627 return IB_QPS_INIT;
628 case C4IW_QP_STATE_RTS:
629 return IB_QPS_RTS;
630 case C4IW_QP_STATE_CLOSING:
631 return IB_QPS_SQD;
632 case C4IW_QP_STATE_TERMINATE:
633 return IB_QPS_SQE;
634 case C4IW_QP_STATE_ERROR:
635 return IB_QPS_ERR;
636 }
637 return IB_QPS_ERR;
638}
639
4fe7c296
SW		 640#define C4IW_DRAIN_OPCODE FW_RI_SGE_EC_CR_RETURN
641
cfdda9d7
SW		 642static inline u32 c4iw_ib_to_tpt_access(int a)
643{
644 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
645 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
646 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
647 FW_RI_MEM_ACCESS_LOCAL_READ;
648}
649
650static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
651{
652 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
653 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
654}
655
656enum c4iw_mmid_state {
657 C4IW_STAG_STATE_VALID,
658 C4IW_STAG_STATE_INVALID
659};
660
661#define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
662
663#define MPA_KEY_REQ "MPA ID Req Frame"
664#define MPA_KEY_REP "MPA ID Rep Frame"
665
666#define MPA_MAX_PRIVATE_DATA 256
d2fe99e8 667#define MPA_ENHANCED_RDMA_CONN 0x10
cfdda9d7
SW		 668#define MPA_REJECT 0x20
669#define MPA_CRC 0x40
670#define MPA_MARKERS 0x80
671#define MPA_FLAGS_MASK 0xE0
672
d2fe99e8
KS		 673#define MPA_V2_PEER2PEER_MODEL 0x8000
674#define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
675#define MPA_V2_RDMA_WRITE_RTR 0x8000
676#define MPA_V2_RDMA_READ_RTR 0x4000
677#define MPA_V2_IRD_ORD_MASK 0x3FFF
678
cfdda9d7
SW		 679#define c4iw_put_ep(ep) { \
680 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
2c935bc5
PZ		 681 ep, kref_read(&((ep)->kref))); \
682 WARN_ON(kref_read(&((ep)->kref)) < 1); \
cfdda9d7
SW		 683 kref_put(&((ep)->kref), _c4iw_free_ep); \
684}
685
686#define c4iw_get_ep(ep) { \
687 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
2c935bc5 688 ep, kref_read(&((ep)->kref))); \
cfdda9d7
SW		 689 kref_get(&((ep)->kref)); \
690}
691void _c4iw_free_ep(struct kref *kref);
692
693struct mpa_message {
694 u8 key[16];
695 u8 flags;
696 u8 revision;
697 __be16 private_data_size;
698 u8 private_data[0];
699};
700
d2fe99e8
KS		 701struct mpa_v2_conn_params {
702 __be16 ird;
703 __be16 ord;
704};
705
cfdda9d7
SW		 706struct terminate_message {
707 u8 layer_etype;
708 u8 ecode;
709 __be16 hdrct_rsvd;
710 u8 len_hdrs[0];
711};
712
713#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
714
715enum c4iw_layers_types {
716 LAYER_RDMAP = 0x00,
717 LAYER_DDP = 0x10,
718 LAYER_MPA = 0x20,
719 RDMAP_LOCAL_CATA = 0x00,
720 RDMAP_REMOTE_PROT = 0x01,
721 RDMAP_REMOTE_OP = 0x02,
722 DDP_LOCAL_CATA = 0x00,
723 DDP_TAGGED_ERR = 0x01,
724 DDP_UNTAGGED_ERR = 0x02,
725 DDP_LLP = 0x03
726};
727
728enum c4iw_rdma_ecodes {
729 RDMAP_INV_STAG = 0x00,
730 RDMAP_BASE_BOUNDS = 0x01,
731 RDMAP_ACC_VIOL = 0x02,
732 RDMAP_STAG_NOT_ASSOC = 0x03,
733 RDMAP_TO_WRAP = 0x04,
734 RDMAP_INV_VERS = 0x05,
735 RDMAP_INV_OPCODE = 0x06,
736 RDMAP_STREAM_CATA = 0x07,
737 RDMAP_GLOBAL_CATA = 0x08,
738 RDMAP_CANT_INV_STAG = 0x09,
739 RDMAP_UNSPECIFIED = 0xff
740};
741
742enum c4iw_ddp_ecodes {
743 DDPT_INV_STAG = 0x00,
744 DDPT_BASE_BOUNDS = 0x01,
745 DDPT_STAG_NOT_ASSOC = 0x02,
746 DDPT_TO_WRAP = 0x03,
747 DDPT_INV_VERS = 0x04,
748 DDPU_INV_QN = 0x01,
749 DDPU_INV_MSN_NOBUF = 0x02,
750 DDPU_INV_MSN_RANGE = 0x03,
751 DDPU_INV_MO = 0x04,
752 DDPU_MSG_TOOBIG = 0x05,
753 DDPU_INV_VERS = 0x06
754};
755
756enum c4iw_mpa_ecodes {
757 MPA_CRC_ERR = 0x02,
d2fe99e8
KS		 758 MPA_MARKER_ERR = 0x03,
759 MPA_LOCAL_CATA = 0x05,
760 MPA_INSUFF_IRD = 0x06,
761 MPA_NOMATCH_RTR = 0x07,
cfdda9d7
SW		 762};
763
764enum c4iw_ep_state {
765 IDLE = 0,
766 LISTEN,
767 CONNECTING,
768 MPA_REQ_WAIT,
769 MPA_REQ_SENT,
770 MPA_REQ_RCVD,
771 MPA_REP_SENT,
772 FPDU_MODE,
773 ABORTING,
774 CLOSING,
775 MORIBUND,
776 DEAD,
777};
778
779enum c4iw_ep_flags {
780 PEER_ABORT_IN_PROGRESS = 0,
781 ABORT_REQ_IN_PROGRESS = 1,
782 RELEASE_RESOURCES = 2,
783 CLOSE_SENT = 3,
1ec779cc 784 TIMEOUT = 4,
325abead 785 QP_REFERENCED = 5,
e4b76a2a 786 STOP_MPA_TIMER = 7,
cfdda9d7
SW		 787};
788
793dad94
VP		 789enum c4iw_ep_history {
790 ACT_OPEN_REQ = 0,
791 ACT_OFLD_CONN = 1,
792 ACT_OPEN_RPL = 2,
793 ACT_ESTAB = 3,
794 PASS_ACCEPT_REQ = 4,
795 PASS_ESTAB = 5,
796 ABORT_UPCALL = 6,
797 ESTAB_UPCALL = 7,
798 CLOSE_UPCALL = 8,
799 ULP_ACCEPT = 9,
800 ULP_REJECT = 10,
801 TIMEDOUT = 11,
802 PEER_ABORT = 12,
803 PEER_CLOSE = 13,
804 CONNREQ_UPCALL = 14,
805 ABORT_CONN = 15,
806 DISCONN_UPCALL = 16,
807 EP_DISC_CLOSE = 17,
808 EP_DISC_ABORT = 18,
809 CONN_RPL_UPCALL = 19,
810 ACT_RETRY_NOMEM = 20,
9ca6f7cf
H		 811 ACT_RETRY_INUSE = 21,
812 CLOSE_CON_RPL = 22,
813 EP_DISC_FAIL = 24,
814 QP_REFED = 25,
815 QP_DEREFED = 26,
816 CM_ID_REFED = 27,
817 CM_ID_DEREFED = 28,
793dad94
VP		 818};
819
4a740838
H		 820enum conn_pre_alloc_buffers {
821 CN_ABORT_REQ_BUF,
822 CN_ABORT_RPL_BUF,
823 CN_CLOSE_CON_REQ_BUF,
824 CN_DESTROY_BUF,
825 CN_FLOWC_BUF,
826 CN_MAX_CON_BUF
827};
828
829#define FLOWC_LEN 80
830union cpl_wr_size {
831 struct cpl_abort_req abrt_req;
832 struct cpl_abort_rpl abrt_rpl;
833 struct fw_ri_wr ri_req;
834 struct cpl_close_con_req close_req;
835 char flowc_buf[FLOWC_LEN];
836};
837
cfdda9d7
SW		 838struct c4iw_ep_common {
839 struct iw_cm_id *cm_id;
840 struct c4iw_qp *qp;
841 struct c4iw_dev *dev;
4a740838 842 struct sk_buff_head ep_skb_list;
cfdda9d7
SW		 843 enum c4iw_ep_state state;
844 struct kref kref;
2f5b48c3 845 struct mutex mutex;
830662f6
VP		 846 struct sockaddr_storage local_addr;
847 struct sockaddr_storage remote_addr;
aadc4df3 848 struct c4iw_wr_wait wr_wait;
cfdda9d7 849 unsigned long flags;
793dad94 850 unsigned long history;
cfdda9d7
SW		 851};
852
853struct c4iw_listen_ep {
854 struct c4iw_ep_common com;
855 unsigned int stid;
856 int backlog;
857};
858
179d03bb
H		 859struct c4iw_ep_stats {
860 unsigned connect_neg_adv;
861 unsigned abort_neg_adv;
862};
863
cfdda9d7
SW		 864struct c4iw_ep {
865 struct c4iw_ep_common com;
866 struct c4iw_ep *parent_ep;
867 struct timer_list timer;
be4c9bad 868 struct list_head entry;
cfdda9d7
SW		 869 unsigned int atid;
870 u32 hwtid;
871 u32 snd_seq;
872 u32 rcv_seq;
873 struct l2t_entry *l2t;
874 struct dst_entry *dst;
875 struct sk_buff *mpa_skb;
876 struct c4iw_mpa_attributes mpa_attr;
877 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
878 unsigned int mpa_pkt_len;
879 u32 ird;
880 u32 ord;
881 u32 smac_idx;
882 u32 tx_chan;
883 u32 mtu;
884 u16 mss;
885 u16 emss;
886 u16 plen;
887 u16 rss_qid;
888 u16 txq_idx;
d4f1a5c6 889 u16 ctrlq_idx;
cfdda9d7 890 u8 tos;
d2fe99e8
KS		 891 u8 retry_with_mpa_v1;
892 u8 tried_with_mpa_v1;
793dad94 893 unsigned int retry_count;
b408ff28
HS		 894 int snd_win;
895 int rcv_win;
179d03bb 896 struct c4iw_ep_stats stats;
cfdda9d7
SW		 897};
898
899static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
900{
901 return cm_id->provider_data;
902}
903
904static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
905{
906 return cm_id->provider_data;
907}
908
f079af7a
VP		 909static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
910{
911#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
912 return infop->vr->ocq.size > 0;
913#else
914 return 0;
915#endif
916}
917
ec3eead2
VP		 918u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
919void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
920int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
921 u32 reserved, u32 flags);
922void c4iw_id_table_free(struct c4iw_id_table *alloc);
923
cfdda9d7
SW		 924typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
925
926int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
927 struct l2t_entry *l2t);
928void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
929 struct c4iw_dev_ucontext *uctx);
ec3eead2
VP		 930u32 c4iw_get_resource(struct c4iw_id_table *id_table);
931void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
cfdda9d7
SW		 932int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
933int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
934int c4iw_pblpool_create(struct c4iw_rdev *rdev);
935int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
c6d7b267 936int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
cfdda9d7
SW		 937void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
938void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
c6d7b267 939void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
cfdda9d7
SW		 940void c4iw_destroy_resource(struct c4iw_resource *rscp);
941int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
942int c4iw_register_device(struct c4iw_dev *dev);
943void c4iw_unregister_device(struct c4iw_dev *dev);
944int __init c4iw_cm_init(void);
46c1376d 945void c4iw_cm_term(void);
cfdda9d7
SW		 946void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
947 struct c4iw_dev_ucontext *uctx);
948void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
949 struct c4iw_dev_ucontext *uctx);
950int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
951int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
952 struct ib_send_wr **bad_wr);
953int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
954 struct ib_recv_wr **bad_wr);
cfdda9d7
SW		 955int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
956int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
957int c4iw_destroy_listen(struct iw_cm_id *cm_id);
958int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
959int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
960void c4iw_qp_add_ref(struct ib_qp *qp);
961void c4iw_qp_rem_ref(struct ib_qp *qp);
a2164034
SG		 962struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
963 enum ib_mr_type mr_type,
964 u32 max_num_sg);
ff2ba993 965int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
9aa8b321 966 unsigned int *sg_offset);
cfdda9d7 967int c4iw_dealloc_mw(struct ib_mw *mw);
b2a239df
MB		 968struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
969 struct ib_udata *udata);
cfdda9d7
SW		 970struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
971 u64 length, u64 virt, int acc,
972 struct ib_udata *udata);
973struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
cfdda9d7
SW		 974int c4iw_dereg_mr(struct ib_mr *ib_mr);
975int c4iw_destroy_cq(struct ib_cq *ib_cq);
bcf4c1ea
MB		 976struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
977 const struct ib_cq_init_attr *attr,
978 struct ib_ucontext *ib_context,
979 struct ib_udata *udata);
cfdda9d7
SW		 980int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
981int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
982int c4iw_destroy_qp(struct ib_qp *ib_qp);
983struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
984 struct ib_qp_init_attr *attrs,
985 struct ib_udata *udata);
986int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
987 int attr_mask, struct ib_udata *udata);
67bbc055
VP		 988int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
989 int attr_mask, struct ib_qp_init_attr *init_attr);
cfdda9d7
SW		 990struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
991u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
992void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
993u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
994void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
c6d7b267
SW		 995u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
996void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
cfdda9d7 997int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
1cf24dce 998void c4iw_flush_hw_cq(struct c4iw_cq *chp);
cfdda9d7 999void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
cfdda9d7
SW		 1000int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
1001int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
1cf24dce 1002int c4iw_flush_sq(struct c4iw_qp *qhp);
cfdda9d7
SW		 1003int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
1004u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
cfdda9d7
SW		 1005int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
1006u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1007void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
1008 struct c4iw_dev_ucontext *uctx);
1009u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1010void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
1011 struct c4iw_dev_ucontext *uctx);
1012void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
1013
1014extern struct cxgb4_client t4c_client;
1015extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
74217d4c
H		 1016void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
1017 enum cxgb4_bar2_qtype qtype,
1018 unsigned int *pbar2_qid, u64 *pbar2_pa);
7730b4c7
HS		 1019extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe);
1020extern int c4iw_wr_log;
422eea0a 1021extern int db_fc_threshold;
80ccdd60 1022extern int db_coalescing_threshold;
42b6a949 1023extern int use_dsgl;
5c6b2aaf 1024void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey);
cfdda9d7
SW		 1025
1026#endif
Linux 6.x block layer and io_uring tree(s)