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iw_cxgb4: block module unload until all ep resources are released
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / iw_cxgb4.h
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31#ifndef __IW_CXGB4_H__
32#define __IW_CXGB4_H__
33
34#include <linux/mutex.h>
35#include <linux/list.h>
36#include <linux/spinlock.h>
37#include <linux/idr.h>
c337374b 38#include <linux/completion.h>
cfdda9d7
SW		 39#include <linux/netdevice.h>
40#include <linux/sched.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/inet.h>
44#include <linux/wait.h>
45#include <linux/kref.h>
46#include <linux/timer.h>
47#include <linux/io.h>
cfdda9d7
SW		 48
49#include <asm/byteorder.h>
50
51#include <net/net_namespace.h>
52
53#include <rdma/ib_verbs.h>
54#include <rdma/iw_cm.h>
9eccfe10
SW		 55#include <rdma/rdma_netlink.h>
56#include <rdma/iw_portmap.h>
cfdda9d7
SW		 57
58#include "cxgb4.h"
59#include "cxgb4_uld.h"
60#include "l2t.h"
61#include "user.h"
62
63#define DRV_NAME "iw_cxgb4"
64#define MOD DRV_NAME ":"
65
66extern int c4iw_debug;
67#define PDBG(fmt, args...) \
68do { \
69 if (c4iw_debug) \
70 printk(MOD fmt, ## args); \
71} while (0)
72
73#include "t4.h"
74
75#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
76#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
77
78static inline void *cplhdr(struct sk_buff *skb)
79{
80 return skb->data;
81}
82
ec3eead2
VP		 83#define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
84#define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
85
86struct c4iw_id_table {
87 u32 flags;
88 u32 start; /* logical minimal id */
89 u32 last; /* hint for find */
90 u32 max;
91 spinlock_t lock;
92 unsigned long *table;
93};
94
cfdda9d7 95struct c4iw_resource {
ec3eead2
VP		 96 struct c4iw_id_table tpt_table;
97 struct c4iw_id_table qid_table;
98 struct c4iw_id_table pdid_table;
cfdda9d7
SW		 99};
100
101struct c4iw_qid_list {
102 struct list_head entry;
103 u32 qid;
104};
105
106struct c4iw_dev_ucontext {
107 struct list_head qpids;
108 struct list_head cqids;
109 struct mutex lock;
110};
111
112enum c4iw_rdev_flags {
113 T4_FATAL_ERROR = (1<<0),
05eb2389 114 T4_STATUS_PAGE_DISABLED = (1<<1),
cfdda9d7
SW		 115};
116
8d81ef34
VP		 117struct c4iw_stat {
118 u64 total;
119 u64 cur;
120 u64 max;
ec3eead2 121 u64 fail;
8d81ef34
VP		 122};
123
124struct c4iw_stats {
125 struct mutex lock;
126 struct c4iw_stat qid;
127 struct c4iw_stat pd;
128 struct c4iw_stat stag;
129 struct c4iw_stat pbl;
130 struct c4iw_stat rqt;
131 struct c4iw_stat ocqp;
2c974781
VP		 132 u64 db_full;
133 u64 db_empty;
134 u64 db_drop;
422eea0a 135 u64 db_state_transitions;
05eb2389 136 u64 db_fc_interruptions;
5be78ee9 137 u64 tcam_full;
793dad94
VP		 138 u64 act_ofld_conn_fails;
139 u64 pas_ofld_conn_fails;
179d03bb 140 u64 neg_adv;
8d81ef34
VP		 141};
142
04e10e21
HS		 143struct c4iw_hw_queue {
144 int t4_eq_status_entries;
145 int t4_max_eq_size;
146 int t4_max_iq_size;
147 int t4_max_rq_size;
148 int t4_max_sq_size;
149 int t4_max_qp_depth;
150 int t4_max_cq_depth;
151 int t4_stat_len;
152};
153
7730b4c7
HS		 154struct wr_log_entry {
155 struct timespec post_host_ts;
156 struct timespec poll_host_ts;
157 u64 post_sge_ts;
158 u64 cqe_sge_ts;
159 u64 poll_sge_ts;
160 u16 qid;
161 u16 wr_id;
162 u8 opcode;
163 u8 valid;
164};
165
cfdda9d7
SW		 166struct c4iw_rdev {
167 struct c4iw_resource resource;
cfdda9d7 168 u32 qpmask;
cfdda9d7
SW		 169 u32 cqmask;
170 struct c4iw_dev_ucontext uctx;
171 struct gen_pool *pbl_pool;
172 struct gen_pool *rqt_pool;
c6d7b267 173 struct gen_pool *ocqp_pool;
cfdda9d7
SW		 174 u32 flags;
175 struct cxgb4_lld_info lldi;
fa658a98
SW		 176 unsigned long bar2_pa;
177 void __iomem *bar2_kva;
c6d7b267
SW		 178 unsigned long oc_mw_pa;
179 void __iomem *oc_mw_kva;
8d81ef34 180 struct c4iw_stats stats;
04e10e21 181 struct c4iw_hw_queue hw_queue;
05eb2389 182 struct t4_dev_status_page *status_page;
7730b4c7
HS		 183 atomic_t wr_log_idx;
184 struct wr_log_entry *wr_log;
185 int wr_log_size;
cfdda9d7
SW		 186};
187
188static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
189{
190 return rdev->flags & T4_FATAL_ERROR;
191}
192
193static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
194{
91244bbd 195 return (int)(rdev->lldi.vr->stag.size >> 5);
cfdda9d7
SW		 196}
197
1fc8190d 198#define C4IW_WR_TO (60*HZ)
aadc4df3
SW		 199
200struct c4iw_wr_wait {
c337374b 201 struct completion completion;
aadc4df3
SW		 202 int ret;
203};
204
205static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
206{
207 wr_waitp->ret = 0;
c337374b 208 init_completion(&wr_waitp->completion);
aadc4df3
SW		 209}
210
d9594d99
SW		 211static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
212{
213 wr_waitp->ret = ret;
c337374b 214 complete(&wr_waitp->completion);
d9594d99
SW		 215}
216
aadc4df3
SW		 217static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
218 struct c4iw_wr_wait *wr_waitp,
219 u32 hwtid, u32 qpid,
220 const char *func)
221{
d9594d99 222 int ret;
aadc4df3 223
1fc8190d
H		 224 if (c4iw_fatal_error(rdev)) {
225 wr_waitp->ret = -EIO;
226 goto out;
227 }
228
229 ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO);
230 if (!ret) {
231 PDBG("%s - Device %s not responding (disabling device) - tid %u qpid %u\n",
232 func, pci_name(rdev->lldi.pdev), hwtid, qpid);
233 rdev->flags |= T4_FATAL_ERROR;
234 wr_waitp->ret = -EIO;
235 }
236out:
aadc4df3 237 if (wr_waitp->ret)
30c95c2d
SW		 238 PDBG("%s: FW reply %d tid %u qpid %u\n",
239 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
aadc4df3
SW		 240 return wr_waitp->ret;
241}
242
2c974781
VP		 243enum db_state {
244 NORMAL = 0,
245 FLOW_CONTROL = 1,
05eb2389
SW		 246 RECOVERY = 2,
247 STOPPED = 3
2c974781
VP		 248};
249
cfdda9d7
SW		 250struct c4iw_dev {
251 struct ib_device ibdev;
252 struct c4iw_rdev rdev;
253 u32 device_cap_flags;
254 struct idr cqidr;
255 struct idr qpidr;
256 struct idr mmidr;
257 spinlock_t lock;
2c974781 258 struct mutex db_mutex;
cfdda9d7 259 struct dentry *debugfs_root;
2c974781 260 enum db_state db_state;
793dad94
VP		 261 struct idr hwtid_idr;
262 struct idr atid_idr;
263 struct idr stid_idr;
05eb2389 264 struct list_head db_fc_list;
4c2c5763 265 u32 avail_ird;
37eb816c 266 wait_queue_head_t wait;
cfdda9d7
SW		 267};
268
269static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
270{
271 return container_of(ibdev, struct c4iw_dev, ibdev);
272}
273
274static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
275{
276 return container_of(rdev, struct c4iw_dev, rdev);
277}
278
279static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
280{
281 return idr_find(&rhp->cqidr, cqid);
282}
283
284static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
285{
286 return idr_find(&rhp->qpidr, qpid);
287}
288
289static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
290{
291 return idr_find(&rhp->mmidr, mmid);
292}
293
2c974781
VP		 294static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
295 void *handle, u32 id, int lock)
cfdda9d7
SW		 296{
297 int ret;
cfdda9d7 298
e8d4dd60
TH		 299 if (lock) {
300 idr_preload(GFP_KERNEL);
301 spin_lock_irq(&rhp->lock);
302 }
303
304 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
305
306 if (lock) {
307 spin_unlock_irq(&rhp->lock);
308 idr_preload_end();
309 }
310
311 BUG_ON(ret == -ENOSPC);
312 return ret < 0 ? ret : 0;
cfdda9d7
SW		 313}
314
2c974781
VP		 315static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
316 void *handle, u32 id)
317{
318 return _insert_handle(rhp, idr, handle, id, 1);
319}
320
321static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
322 void *handle, u32 id)
323{
324 return _insert_handle(rhp, idr, handle, id, 0);
325}
326
422eea0a
VP		 327static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
328 u32 id, int lock)
cfdda9d7 329{
422eea0a
VP		 330 if (lock)
331 spin_lock_irq(&rhp->lock);
cfdda9d7 332 idr_remove(idr, id);
422eea0a
VP		 333 if (lock)
334 spin_unlock_irq(&rhp->lock);
335}
336
337static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
338{
339 _remove_handle(rhp, idr, id, 1);
340}
341
342static inline void remove_handle_nolock(struct c4iw_dev *rhp,
343 struct idr *idr, u32 id)
344{
345 _remove_handle(rhp, idr, id, 0);
cfdda9d7
SW		 346}
347
4c2c5763
HS		 348extern uint c4iw_max_read_depth;
349
350static inline int cur_max_read_depth(struct c4iw_dev *dev)
351{
352 return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth);
353}
354
cfdda9d7
SW		 355struct c4iw_pd {
356 struct ib_pd ibpd;
357 u32 pdid;
358 struct c4iw_dev *rhp;
359};
360
361static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
362{
363 return container_of(ibpd, struct c4iw_pd, ibpd);
364}
365
366struct tpt_attributes {
367 u64 len;
368 u64 va_fbo;
369 enum fw_ri_mem_perms perms;
370 u32 stag;
371 u32 pdid;
372 u32 qpid;
373 u32 pbl_addr;
374 u32 pbl_size;
375 u32 state:1;
376 u32 type:2;
377 u32 rsvd:1;
378 u32 remote_invaliate_disable:1;
379 u32 zbva:1;
380 u32 mw_bind_enable:1;
381 u32 page_size:5;
382};
383
384struct c4iw_mr {
385 struct ib_mr ibmr;
386 struct ib_umem *umem;
387 struct c4iw_dev *rhp;
388 u64 kva;
389 struct tpt_attributes attr;
8376b86d
SG		 390 u64 *mpl;
391 dma_addr_t mpl_addr;
392 u32 max_mpl_len;
393 u32 mpl_len;
cfdda9d7
SW		 394};
395
396static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
397{
398 return container_of(ibmr, struct c4iw_mr, ibmr);
399}
400
401struct c4iw_mw {
402 struct ib_mw ibmw;
403 struct c4iw_dev *rhp;
404 u64 kva;
405 struct tpt_attributes attr;
406};
407
408static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
409{
410 return container_of(ibmw, struct c4iw_mw, ibmw);
411}
412
cfdda9d7
SW		 413struct c4iw_cq {
414 struct ib_cq ibcq;
415 struct c4iw_dev *rhp;
416 struct t4_cq cq;
417 spinlock_t lock;
581bbe2c 418 spinlock_t comp_handler_lock;
cfdda9d7
SW		 419 atomic_t refcnt;
420 wait_queue_head_t wait;
421};
422
423static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
424{
425 return container_of(ibcq, struct c4iw_cq, ibcq);
426}
427
428struct c4iw_mpa_attributes {
429 u8 initiator;
430 u8 recv_marker_enabled;
431 u8 xmit_marker_enabled;
432 u8 crc_enabled;
d2fe99e8 433 u8 enhanced_rdma_conn;
cfdda9d7
SW		 434 u8 version;
435 u8 p2p_type;
436};
437
438struct c4iw_qp_attributes {
439 u32 scq;
440 u32 rcq;
441 u32 sq_num_entries;
442 u32 rq_num_entries;
443 u32 sq_max_sges;
444 u32 sq_max_sges_rdma_write;
445 u32 rq_max_sges;
446 u32 state;
447 u8 enable_rdma_read;
448 u8 enable_rdma_write;
449 u8 enable_bind;
450 u8 enable_mmid0_fastreg;
451 u32 max_ord;
452 u32 max_ird;
453 u32 pd;
454 u32 next_state;
455 char terminate_buffer[52];
456 u32 terminate_msg_len;
457 u8 is_terminate_local;
458 struct c4iw_mpa_attributes mpa_attr;
459 struct c4iw_ep *llp_stream_handle;
d2fe99e8
KS		 460 u8 layer_etype;
461 u8 ecode;
2c974781
VP		 462 u16 sq_db_inc;
463 u16 rq_db_inc;
cc18b939 464 u8 send_term;
cfdda9d7
SW		 465};
466
467struct c4iw_qp {
468 struct ib_qp ibqp;
05eb2389 469 struct list_head db_fc_entry;
cfdda9d7
SW		 470 struct c4iw_dev *rhp;
471 struct c4iw_ep *ep;
472 struct c4iw_qp_attributes attr;
473 struct t4_wq wq;
474 spinlock_t lock;
2f5b48c3 475 struct mutex mutex;
cfdda9d7
SW		 476 atomic_t refcnt;
477 wait_queue_head_t wait;
478 struct timer_list timer;
ba32de9d 479 int sq_sig_all;
086dc6e3
SW		 480 struct completion rq_drained;
481 struct completion sq_drained;
cfdda9d7
SW		 482};
483
484static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
485{
486 return container_of(ibqp, struct c4iw_qp, ibqp);
487}
488
489struct c4iw_ucontext {
490 struct ib_ucontext ibucontext;
491 struct c4iw_dev_ucontext uctx;
492 u32 key;
493 spinlock_t mmap_lock;
494 struct list_head mmaps;
495};
496
497static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
498{
499 return container_of(c, struct c4iw_ucontext, ibucontext);
500}
501
502struct c4iw_mm_entry {
503 struct list_head entry;
504 u64 addr;
505 u32 key;
506 unsigned len;
507};
508
509static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
510 u32 key, unsigned len)
511{
512 struct list_head *pos, *nxt;
513 struct c4iw_mm_entry *mm;
514
515 spin_lock(&ucontext->mmap_lock);
516 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
517
518 mm = list_entry(pos, struct c4iw_mm_entry, entry);
519 if (mm->key == key && mm->len == len) {
520 list_del_init(&mm->entry);
521 spin_unlock(&ucontext->mmap_lock);
522 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
523 key, (unsigned long long) mm->addr, mm->len);
524 return mm;
525 }
526 }
527 spin_unlock(&ucontext->mmap_lock);
528 return NULL;
529}
530
531static inline void insert_mmap(struct c4iw_ucontext *ucontext,
532 struct c4iw_mm_entry *mm)
533{
534 spin_lock(&ucontext->mmap_lock);
535 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
536 mm->key, (unsigned long long) mm->addr, mm->len);
537 list_add_tail(&mm->entry, &ucontext->mmaps);
538 spin_unlock(&ucontext->mmap_lock);
539}
540
541enum c4iw_qp_attr_mask {
542 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
2c974781
VP		 543 C4IW_QP_ATTR_SQ_DB = 1<<1,
544 C4IW_QP_ATTR_RQ_DB = 1<<2,
cfdda9d7
SW		 545 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
546 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
547 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
548 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
549 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
550 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
551 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
552 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
553 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
554 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
555 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
556 C4IW_QP_ATTR_MAX_ORD |
557 C4IW_QP_ATTR_MAX_IRD |
558 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
559 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
560 C4IW_QP_ATTR_MPA_ATTR |
561 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
562};
563
564int c4iw_modify_qp(struct c4iw_dev *rhp,
565 struct c4iw_qp *qhp,
566 enum c4iw_qp_attr_mask mask,
567 struct c4iw_qp_attributes *attrs,
568 int internal);
569
570enum c4iw_qp_state {
571 C4IW_QP_STATE_IDLE,
572 C4IW_QP_STATE_RTS,
573 C4IW_QP_STATE_ERROR,
574 C4IW_QP_STATE_TERMINATE,
575 C4IW_QP_STATE_CLOSING,
576 C4IW_QP_STATE_TOT
577};
578
579static inline int c4iw_convert_state(enum ib_qp_state ib_state)
580{
581 switch (ib_state) {
582 case IB_QPS_RESET:
583 case IB_QPS_INIT:
584 return C4IW_QP_STATE_IDLE;
585 case IB_QPS_RTS:
586 return C4IW_QP_STATE_RTS;
587 case IB_QPS_SQD:
588 return C4IW_QP_STATE_CLOSING;
589 case IB_QPS_SQE:
590 return C4IW_QP_STATE_TERMINATE;
591 case IB_QPS_ERR:
592 return C4IW_QP_STATE_ERROR;
593 default:
594 return -1;
595 }
596}
597
67bbc055
VP		 598static inline int to_ib_qp_state(int c4iw_qp_state)
599{
600 switch (c4iw_qp_state) {
601 case C4IW_QP_STATE_IDLE:
602 return IB_QPS_INIT;
603 case C4IW_QP_STATE_RTS:
604 return IB_QPS_RTS;
605 case C4IW_QP_STATE_CLOSING:
606 return IB_QPS_SQD;
607 case C4IW_QP_STATE_TERMINATE:
608 return IB_QPS_SQE;
609 case C4IW_QP_STATE_ERROR:
610 return IB_QPS_ERR;
611 }
612 return IB_QPS_ERR;
613}
614
cfdda9d7
SW		 615static inline u32 c4iw_ib_to_tpt_access(int a)
616{
617 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
618 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
619 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
620 FW_RI_MEM_ACCESS_LOCAL_READ;
621}
622
623static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
624{
625 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
626 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
627}
628
629enum c4iw_mmid_state {
630 C4IW_STAG_STATE_VALID,
631 C4IW_STAG_STATE_INVALID
632};
633
634#define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
635
636#define MPA_KEY_REQ "MPA ID Req Frame"
637#define MPA_KEY_REP "MPA ID Rep Frame"
638
639#define MPA_MAX_PRIVATE_DATA 256
d2fe99e8 640#define MPA_ENHANCED_RDMA_CONN 0x10
cfdda9d7
SW		 641#define MPA_REJECT 0x20
642#define MPA_CRC 0x40
643#define MPA_MARKERS 0x80
644#define MPA_FLAGS_MASK 0xE0
645
d2fe99e8
KS		 646#define MPA_V2_PEER2PEER_MODEL 0x8000
647#define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
648#define MPA_V2_RDMA_WRITE_RTR 0x8000
649#define MPA_V2_RDMA_READ_RTR 0x4000
650#define MPA_V2_IRD_ORD_MASK 0x3FFF
651
cfdda9d7
SW		 652#define c4iw_put_ep(ep) { \
653 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
654 ep, atomic_read(&((ep)->kref.refcount))); \
655 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
656 kref_put(&((ep)->kref), _c4iw_free_ep); \
657}
658
659#define c4iw_get_ep(ep) { \
660 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
661 ep, atomic_read(&((ep)->kref.refcount))); \
662 kref_get(&((ep)->kref)); \
663}
664void _c4iw_free_ep(struct kref *kref);
665
666struct mpa_message {
667 u8 key[16];
668 u8 flags;
669 u8 revision;
670 __be16 private_data_size;
671 u8 private_data[0];
672};
673
d2fe99e8
KS		 674struct mpa_v2_conn_params {
675 __be16 ird;
676 __be16 ord;
677};
678
cfdda9d7
SW		 679struct terminate_message {
680 u8 layer_etype;
681 u8 ecode;
682 __be16 hdrct_rsvd;
683 u8 len_hdrs[0];
684};
685
686#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
687
688enum c4iw_layers_types {
689 LAYER_RDMAP = 0x00,
690 LAYER_DDP = 0x10,
691 LAYER_MPA = 0x20,
692 RDMAP_LOCAL_CATA = 0x00,
693 RDMAP_REMOTE_PROT = 0x01,
694 RDMAP_REMOTE_OP = 0x02,
695 DDP_LOCAL_CATA = 0x00,
696 DDP_TAGGED_ERR = 0x01,
697 DDP_UNTAGGED_ERR = 0x02,
698 DDP_LLP = 0x03
699};
700
701enum c4iw_rdma_ecodes {
702 RDMAP_INV_STAG = 0x00,
703 RDMAP_BASE_BOUNDS = 0x01,
704 RDMAP_ACC_VIOL = 0x02,
705 RDMAP_STAG_NOT_ASSOC = 0x03,
706 RDMAP_TO_WRAP = 0x04,
707 RDMAP_INV_VERS = 0x05,
708 RDMAP_INV_OPCODE = 0x06,
709 RDMAP_STREAM_CATA = 0x07,
710 RDMAP_GLOBAL_CATA = 0x08,
711 RDMAP_CANT_INV_STAG = 0x09,
712 RDMAP_UNSPECIFIED = 0xff
713};
714
715enum c4iw_ddp_ecodes {
716 DDPT_INV_STAG = 0x00,
717 DDPT_BASE_BOUNDS = 0x01,
718 DDPT_STAG_NOT_ASSOC = 0x02,
719 DDPT_TO_WRAP = 0x03,
720 DDPT_INV_VERS = 0x04,
721 DDPU_INV_QN = 0x01,
722 DDPU_INV_MSN_NOBUF = 0x02,
723 DDPU_INV_MSN_RANGE = 0x03,
724 DDPU_INV_MO = 0x04,
725 DDPU_MSG_TOOBIG = 0x05,
726 DDPU_INV_VERS = 0x06
727};
728
729enum c4iw_mpa_ecodes {
730 MPA_CRC_ERR = 0x02,
d2fe99e8
KS		 731 MPA_MARKER_ERR = 0x03,
732 MPA_LOCAL_CATA = 0x05,
733 MPA_INSUFF_IRD = 0x06,
734 MPA_NOMATCH_RTR = 0x07,
cfdda9d7
SW		 735};
736
737enum c4iw_ep_state {
738 IDLE = 0,
739 LISTEN,
740 CONNECTING,
741 MPA_REQ_WAIT,
742 MPA_REQ_SENT,
743 MPA_REQ_RCVD,
744 MPA_REP_SENT,
745 FPDU_MODE,
746 ABORTING,
747 CLOSING,
748 MORIBUND,
749 DEAD,
750};
751
752enum c4iw_ep_flags {
753 PEER_ABORT_IN_PROGRESS = 0,
754 ABORT_REQ_IN_PROGRESS = 1,
755 RELEASE_RESOURCES = 2,
756 CLOSE_SENT = 3,
1ec779cc 757 TIMEOUT = 4,
325abead 758 QP_REFERENCED = 5,
e4b76a2a 759 STOP_MPA_TIMER = 7,
cfdda9d7
SW		 760};
761
793dad94
VP		 762enum c4iw_ep_history {
763 ACT_OPEN_REQ = 0,
764 ACT_OFLD_CONN = 1,
765 ACT_OPEN_RPL = 2,
766 ACT_ESTAB = 3,
767 PASS_ACCEPT_REQ = 4,
768 PASS_ESTAB = 5,
769 ABORT_UPCALL = 6,
770 ESTAB_UPCALL = 7,
771 CLOSE_UPCALL = 8,
772 ULP_ACCEPT = 9,
773 ULP_REJECT = 10,
774 TIMEDOUT = 11,
775 PEER_ABORT = 12,
776 PEER_CLOSE = 13,
777 CONNREQ_UPCALL = 14,
778 ABORT_CONN = 15,
779 DISCONN_UPCALL = 16,
780 EP_DISC_CLOSE = 17,
781 EP_DISC_ABORT = 18,
782 CONN_RPL_UPCALL = 19,
783 ACT_RETRY_NOMEM = 20,
9ca6f7cf
H		 784 ACT_RETRY_INUSE = 21,
785 CLOSE_CON_RPL = 22,
786 EP_DISC_FAIL = 24,
787 QP_REFED = 25,
788 QP_DEREFED = 26,
789 CM_ID_REFED = 27,
790 CM_ID_DEREFED = 28,
793dad94
VP		 791};
792
cfdda9d7
SW		 793struct c4iw_ep_common {
794 struct iw_cm_id *cm_id;
795 struct c4iw_qp *qp;
796 struct c4iw_dev *dev;
797 enum c4iw_ep_state state;
798 struct kref kref;
2f5b48c3 799 struct mutex mutex;
830662f6
VP		 800 struct sockaddr_storage local_addr;
801 struct sockaddr_storage remote_addr;
aadc4df3 802 struct c4iw_wr_wait wr_wait;
cfdda9d7 803 unsigned long flags;
793dad94 804 unsigned long history;
cfdda9d7
SW		 805};
806
807struct c4iw_listen_ep {
808 struct c4iw_ep_common com;
809 unsigned int stid;
810 int backlog;
811};
812
179d03bb
H		 813struct c4iw_ep_stats {
814 unsigned connect_neg_adv;
815 unsigned abort_neg_adv;
816};
817
cfdda9d7
SW		 818struct c4iw_ep {
819 struct c4iw_ep_common com;
820 struct c4iw_ep *parent_ep;
821 struct timer_list timer;
be4c9bad 822 struct list_head entry;
cfdda9d7
SW		 823 unsigned int atid;
824 u32 hwtid;
825 u32 snd_seq;
826 u32 rcv_seq;
827 struct l2t_entry *l2t;
828 struct dst_entry *dst;
829 struct sk_buff *mpa_skb;
830 struct c4iw_mpa_attributes mpa_attr;
831 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
832 unsigned int mpa_pkt_len;
833 u32 ird;
834 u32 ord;
835 u32 smac_idx;
836 u32 tx_chan;
837 u32 mtu;
838 u16 mss;
839 u16 emss;
840 u16 plen;
841 u16 rss_qid;
842 u16 txq_idx;
d4f1a5c6 843 u16 ctrlq_idx;
cfdda9d7 844 u8 tos;
d2fe99e8
KS		 845 u8 retry_with_mpa_v1;
846 u8 tried_with_mpa_v1;
793dad94 847 unsigned int retry_count;
b408ff28
HS		 848 int snd_win;
849 int rcv_win;
179d03bb 850 struct c4iw_ep_stats stats;
cfdda9d7
SW		 851};
852
853static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
854{
855 return cm_id->provider_data;
856}
857
858static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
859{
860 return cm_id->provider_data;
861}
862
863static inline int compute_wscale(int win)
864{
865 int wscale = 0;
866
867 while (wscale < 14 && (65535<<wscale) < win)
868 wscale++;
869 return wscale;
870}
871
f079af7a
VP		 872static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
873{
874#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
875 return infop->vr->ocq.size > 0;
876#else
877 return 0;
878#endif
879}
880
ec3eead2
VP		 881u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
882void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
883int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
884 u32 reserved, u32 flags);
885void c4iw_id_table_free(struct c4iw_id_table *alloc);
886
cfdda9d7
SW		 887typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
888
889int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
890 struct l2t_entry *l2t);
891void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
892 struct c4iw_dev_ucontext *uctx);
ec3eead2
VP		 893u32 c4iw_get_resource(struct c4iw_id_table *id_table);
894void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
cfdda9d7
SW		 895int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
896int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
897int c4iw_pblpool_create(struct c4iw_rdev *rdev);
898int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
c6d7b267 899int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
cfdda9d7
SW		 900void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
901void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
c6d7b267 902void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
cfdda9d7
SW		 903void c4iw_destroy_resource(struct c4iw_resource *rscp);
904int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
905int c4iw_register_device(struct c4iw_dev *dev);
906void c4iw_unregister_device(struct c4iw_dev *dev);
907int __init c4iw_cm_init(void);
46c1376d 908void c4iw_cm_term(void);
cfdda9d7
SW		 909void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
910 struct c4iw_dev_ucontext *uctx);
911void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
912 struct c4iw_dev_ucontext *uctx);
913int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
914int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
915 struct ib_send_wr **bad_wr);
916int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
917 struct ib_recv_wr **bad_wr);
cfdda9d7
SW		 918int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
919int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
920int c4iw_destroy_listen(struct iw_cm_id *cm_id);
921int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
922int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
923void c4iw_qp_add_ref(struct ib_qp *qp);
924void c4iw_qp_rem_ref(struct ib_qp *qp);
a2164034
SG		 925struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
926 enum ib_mr_type mr_type,
927 u32 max_num_sg);
ff2ba993 928int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
9aa8b321 929 unsigned int *sg_offset);
cfdda9d7 930int c4iw_dealloc_mw(struct ib_mw *mw);
b2a239df
MB		 931struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
932 struct ib_udata *udata);
cfdda9d7
SW		 933struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
934 u64 length, u64 virt, int acc,
935 struct ib_udata *udata);
936struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
cfdda9d7
SW		 937int c4iw_dereg_mr(struct ib_mr *ib_mr);
938int c4iw_destroy_cq(struct ib_cq *ib_cq);
bcf4c1ea
MB		 939struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
940 const struct ib_cq_init_attr *attr,
941 struct ib_ucontext *ib_context,
942 struct ib_udata *udata);
cfdda9d7
SW		 943int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
944int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
945int c4iw_destroy_qp(struct ib_qp *ib_qp);
946struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
947 struct ib_qp_init_attr *attrs,
948 struct ib_udata *udata);
949int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
950 int attr_mask, struct ib_udata *udata);
67bbc055
VP		 951int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
952 int attr_mask, struct ib_qp_init_attr *init_attr);
cfdda9d7
SW		 953struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
954u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
955void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
956u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
957void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
c6d7b267
SW		 958u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
959void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
cfdda9d7 960int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
1cf24dce 961void c4iw_flush_hw_cq(struct c4iw_cq *chp);
cfdda9d7 962void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
cfdda9d7
SW		 963int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
964int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
1cf24dce 965int c4iw_flush_sq(struct c4iw_qp *qhp);
cfdda9d7
SW		 966int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
967u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
cfdda9d7
SW		 968int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
969u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
970void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
971 struct c4iw_dev_ucontext *uctx);
972u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
973void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
974 struct c4iw_dev_ucontext *uctx);
975void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
976
977extern struct cxgb4_client t4c_client;
978extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
74217d4c
H		 979void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
980 enum cxgb4_bar2_qtype qtype,
981 unsigned int *pbar2_qid, u64 *pbar2_pa);
7730b4c7
HS		 982extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe);
983extern int c4iw_wr_log;
422eea0a 984extern int db_fc_threshold;
80ccdd60 985extern int db_coalescing_threshold;
42b6a949 986extern int use_dsgl;
086dc6e3
SW		 987void c4iw_drain_rq(struct ib_qp *qp);
988void c4iw_drain_sq(struct ib_qp *qp);
422eea0a 989
cfdda9d7
SW		 990
991#endif
Linux 6.x block layer and io_uring tree(s)