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cxgb4/iw_cxgb4: Doorbell Drop Avoidance Bug Fixes
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / iw_cxgb4.h
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31#ifndef __IW_CXGB4_H__
32#define __IW_CXGB4_H__
33
34#include <linux/mutex.h>
35#include <linux/list.h>
36#include <linux/spinlock.h>
37#include <linux/idr.h>
c337374b 38#include <linux/completion.h>
cfdda9d7
SW		 39#include <linux/netdevice.h>
40#include <linux/sched.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/inet.h>
44#include <linux/wait.h>
45#include <linux/kref.h>
46#include <linux/timer.h>
47#include <linux/io.h>
cfdda9d7
SW		 48
49#include <asm/byteorder.h>
50
51#include <net/net_namespace.h>
52
53#include <rdma/ib_verbs.h>
54#include <rdma/iw_cm.h>
55
56#include "cxgb4.h"
57#include "cxgb4_uld.h"
58#include "l2t.h"
59#include "user.h"
60
61#define DRV_NAME "iw_cxgb4"
62#define MOD DRV_NAME ":"
63
64extern int c4iw_debug;
65#define PDBG(fmt, args...) \
66do { \
67 if (c4iw_debug) \
68 printk(MOD fmt, ## args); \
69} while (0)
70
71#include "t4.h"
72
73#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
74#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
75
76static inline void *cplhdr(struct sk_buff *skb)
77{
78 return skb->data;
79}
80
ec3eead2
VP		 81#define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
82#define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
83
84struct c4iw_id_table {
85 u32 flags;
86 u32 start; /* logical minimal id */
87 u32 last; /* hint for find */
88 u32 max;
89 spinlock_t lock;
90 unsigned long *table;
91};
92
cfdda9d7 93struct c4iw_resource {
ec3eead2
VP		 94 struct c4iw_id_table tpt_table;
95 struct c4iw_id_table qid_table;
96 struct c4iw_id_table pdid_table;
cfdda9d7
SW		 97};
98
99struct c4iw_qid_list {
100 struct list_head entry;
101 u32 qid;
102};
103
104struct c4iw_dev_ucontext {
105 struct list_head qpids;
106 struct list_head cqids;
107 struct mutex lock;
108};
109
110enum c4iw_rdev_flags {
111 T4_FATAL_ERROR = (1<<0),
05eb2389 112 T4_STATUS_PAGE_DISABLED = (1<<1),
cfdda9d7
SW		 113};
114
8d81ef34
VP		 115struct c4iw_stat {
116 u64 total;
117 u64 cur;
118 u64 max;
ec3eead2 119 u64 fail;
8d81ef34
VP		 120};
121
122struct c4iw_stats {
123 struct mutex lock;
124 struct c4iw_stat qid;
125 struct c4iw_stat pd;
126 struct c4iw_stat stag;
127 struct c4iw_stat pbl;
128 struct c4iw_stat rqt;
129 struct c4iw_stat ocqp;
2c974781
VP		 130 u64 db_full;
131 u64 db_empty;
132 u64 db_drop;
422eea0a 133 u64 db_state_transitions;
05eb2389 134 u64 db_fc_interruptions;
5be78ee9 135 u64 tcam_full;
793dad94
VP		 136 u64 act_ofld_conn_fails;
137 u64 pas_ofld_conn_fails;
8d81ef34
VP		 138};
139
cfdda9d7
SW		 140struct c4iw_rdev {
141 struct c4iw_resource resource;
142 unsigned long qpshift;
143 u32 qpmask;
144 unsigned long cqshift;
145 u32 cqmask;
146 struct c4iw_dev_ucontext uctx;
147 struct gen_pool *pbl_pool;
148 struct gen_pool *rqt_pool;
c6d7b267 149 struct gen_pool *ocqp_pool;
cfdda9d7
SW		 150 u32 flags;
151 struct cxgb4_lld_info lldi;
c6d7b267
SW		 152 unsigned long oc_mw_pa;
153 void __iomem *oc_mw_kva;
8d81ef34 154 struct c4iw_stats stats;
05eb2389 155 struct t4_dev_status_page *status_page;
cfdda9d7
SW		 156};
157
158static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
159{
160 return rdev->flags & T4_FATAL_ERROR;
161}
162
163static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
164{
165 return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
166}
167
3b174d94 168#define C4IW_WR_TO (30*HZ)
aadc4df3
SW		 169
170struct c4iw_wr_wait {
c337374b 171 struct completion completion;
aadc4df3
SW		 172 int ret;
173};
174
175static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
176{
177 wr_waitp->ret = 0;
c337374b 178 init_completion(&wr_waitp->completion);
aadc4df3
SW		 179}
180
d9594d99
SW		 181static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
182{
183 wr_waitp->ret = ret;
c337374b 184 complete(&wr_waitp->completion);
d9594d99
SW		 185}
186
aadc4df3
SW		 187static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
188 struct c4iw_wr_wait *wr_waitp,
189 u32 hwtid, u32 qpid,
190 const char *func)
191{
192 unsigned to = C4IW_WR_TO;
d9594d99 193 int ret;
aadc4df3 194
d9594d99 195 do {
c337374b 196 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
d9594d99 197 if (!ret) {
aadc4df3
SW		 198 printk(KERN_ERR MOD "%s - Device %s not responding - "
199 "tid %u qpid %u\n", func,
200 pci_name(rdev->lldi.pdev), hwtid, qpid);
2f25e9a5
SW		 201 if (c4iw_fatal_error(rdev)) {
202 wr_waitp->ret = -EIO;
203 break;
204 }
aadc4df3
SW		 205 to = to << 2;
206 }
d9594d99 207 } while (!ret);
aadc4df3 208 if (wr_waitp->ret)
30c95c2d
SW		 209 PDBG("%s: FW reply %d tid %u qpid %u\n",
210 pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
aadc4df3
SW		 211 return wr_waitp->ret;
212}
213
2c974781
VP		 214enum db_state {
215 NORMAL = 0,
216 FLOW_CONTROL = 1,
05eb2389
SW		 217 RECOVERY = 2,
218 STOPPED = 3
2c974781
VP		 219};
220
cfdda9d7
SW		 221struct c4iw_dev {
222 struct ib_device ibdev;
223 struct c4iw_rdev rdev;
224 u32 device_cap_flags;
225 struct idr cqidr;
226 struct idr qpidr;
227 struct idr mmidr;
228 spinlock_t lock;
2c974781 229 struct mutex db_mutex;
cfdda9d7 230 struct dentry *debugfs_root;
2c974781 231 enum db_state db_state;
793dad94
VP		 232 struct idr hwtid_idr;
233 struct idr atid_idr;
234 struct idr stid_idr;
05eb2389 235 struct list_head db_fc_list;
cfdda9d7
SW		 236};
237
238static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
239{
240 return container_of(ibdev, struct c4iw_dev, ibdev);
241}
242
243static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
244{
245 return container_of(rdev, struct c4iw_dev, rdev);
246}
247
248static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
249{
250 return idr_find(&rhp->cqidr, cqid);
251}
252
253static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
254{
255 return idr_find(&rhp->qpidr, qpid);
256}
257
258static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
259{
260 return idr_find(&rhp->mmidr, mmid);
261}
262
2c974781
VP		 263static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
264 void *handle, u32 id, int lock)
cfdda9d7
SW		 265{
266 int ret;
cfdda9d7 267
e8d4dd60
TH		 268 if (lock) {
269 idr_preload(GFP_KERNEL);
270 spin_lock_irq(&rhp->lock);
271 }
272
273 ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
274
275 if (lock) {
276 spin_unlock_irq(&rhp->lock);
277 idr_preload_end();
278 }
279
280 BUG_ON(ret == -ENOSPC);
281 return ret < 0 ? ret : 0;
cfdda9d7
SW		 282}
283
2c974781
VP		 284static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
285 void *handle, u32 id)
286{
287 return _insert_handle(rhp, idr, handle, id, 1);
288}
289
290static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
291 void *handle, u32 id)
292{
293 return _insert_handle(rhp, idr, handle, id, 0);
294}
295
422eea0a
VP		 296static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
297 u32 id, int lock)
cfdda9d7 298{
422eea0a
VP		 299 if (lock)
300 spin_lock_irq(&rhp->lock);
cfdda9d7 301 idr_remove(idr, id);
422eea0a
VP		 302 if (lock)
303 spin_unlock_irq(&rhp->lock);
304}
305
306static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
307{
308 _remove_handle(rhp, idr, id, 1);
309}
310
311static inline void remove_handle_nolock(struct c4iw_dev *rhp,
312 struct idr *idr, u32 id)
313{
314 _remove_handle(rhp, idr, id, 0);
cfdda9d7
SW		 315}
316
317struct c4iw_pd {
318 struct ib_pd ibpd;
319 u32 pdid;
320 struct c4iw_dev *rhp;
321};
322
323static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
324{
325 return container_of(ibpd, struct c4iw_pd, ibpd);
326}
327
328struct tpt_attributes {
329 u64 len;
330 u64 va_fbo;
331 enum fw_ri_mem_perms perms;
332 u32 stag;
333 u32 pdid;
334 u32 qpid;
335 u32 pbl_addr;
336 u32 pbl_size;
337 u32 state:1;
338 u32 type:2;
339 u32 rsvd:1;
340 u32 remote_invaliate_disable:1;
341 u32 zbva:1;
342 u32 mw_bind_enable:1;
343 u32 page_size:5;
344};
345
346struct c4iw_mr {
347 struct ib_mr ibmr;
348 struct ib_umem *umem;
349 struct c4iw_dev *rhp;
350 u64 kva;
351 struct tpt_attributes attr;
352};
353
354static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
355{
356 return container_of(ibmr, struct c4iw_mr, ibmr);
357}
358
359struct c4iw_mw {
360 struct ib_mw ibmw;
361 struct c4iw_dev *rhp;
362 u64 kva;
363 struct tpt_attributes attr;
364};
365
366static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
367{
368 return container_of(ibmw, struct c4iw_mw, ibmw);
369}
370
371struct c4iw_fr_page_list {
372 struct ib_fast_reg_page_list ibpl;
f38926aa 373 DEFINE_DMA_UNMAP_ADDR(mapping);
cfdda9d7
SW		 374 dma_addr_t dma_addr;
375 struct c4iw_dev *dev;
cfdda9d7
SW		 376};
377
378static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
379 struct ib_fast_reg_page_list *ibpl)
380{
381 return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
382}
383
384struct c4iw_cq {
385 struct ib_cq ibcq;
386 struct c4iw_dev *rhp;
387 struct t4_cq cq;
388 spinlock_t lock;
581bbe2c 389 spinlock_t comp_handler_lock;
cfdda9d7
SW		 390 atomic_t refcnt;
391 wait_queue_head_t wait;
392};
393
394static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
395{
396 return container_of(ibcq, struct c4iw_cq, ibcq);
397}
398
399struct c4iw_mpa_attributes {
400 u8 initiator;
401 u8 recv_marker_enabled;
402 u8 xmit_marker_enabled;
403 u8 crc_enabled;
d2fe99e8 404 u8 enhanced_rdma_conn;
cfdda9d7
SW		 405 u8 version;
406 u8 p2p_type;
407};
408
409struct c4iw_qp_attributes {
410 u32 scq;
411 u32 rcq;
412 u32 sq_num_entries;
413 u32 rq_num_entries;
414 u32 sq_max_sges;
415 u32 sq_max_sges_rdma_write;
416 u32 rq_max_sges;
417 u32 state;
418 u8 enable_rdma_read;
419 u8 enable_rdma_write;
420 u8 enable_bind;
421 u8 enable_mmid0_fastreg;
422 u32 max_ord;
423 u32 max_ird;
424 u32 pd;
425 u32 next_state;
426 char terminate_buffer[52];
427 u32 terminate_msg_len;
428 u8 is_terminate_local;
429 struct c4iw_mpa_attributes mpa_attr;
430 struct c4iw_ep *llp_stream_handle;
d2fe99e8
KS		 431 u8 layer_etype;
432 u8 ecode;
2c974781
VP		 433 u16 sq_db_inc;
434 u16 rq_db_inc;
cfdda9d7
SW		 435};
436
437struct c4iw_qp {
438 struct ib_qp ibqp;
05eb2389 439 struct list_head db_fc_entry;
cfdda9d7
SW		 440 struct c4iw_dev *rhp;
441 struct c4iw_ep *ep;
442 struct c4iw_qp_attributes attr;
443 struct t4_wq wq;
444 spinlock_t lock;
2f5b48c3 445 struct mutex mutex;
cfdda9d7
SW		 446 atomic_t refcnt;
447 wait_queue_head_t wait;
448 struct timer_list timer;
449};
450
451static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
452{
453 return container_of(ibqp, struct c4iw_qp, ibqp);
454}
455
456struct c4iw_ucontext {
457 struct ib_ucontext ibucontext;
458 struct c4iw_dev_ucontext uctx;
459 u32 key;
460 spinlock_t mmap_lock;
461 struct list_head mmaps;
462};
463
464static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
465{
466 return container_of(c, struct c4iw_ucontext, ibucontext);
467}
468
469struct c4iw_mm_entry {
470 struct list_head entry;
471 u64 addr;
472 u32 key;
473 unsigned len;
474};
475
476static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
477 u32 key, unsigned len)
478{
479 struct list_head *pos, *nxt;
480 struct c4iw_mm_entry *mm;
481
482 spin_lock(&ucontext->mmap_lock);
483 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
484
485 mm = list_entry(pos, struct c4iw_mm_entry, entry);
486 if (mm->key == key && mm->len == len) {
487 list_del_init(&mm->entry);
488 spin_unlock(&ucontext->mmap_lock);
489 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
490 key, (unsigned long long) mm->addr, mm->len);
491 return mm;
492 }
493 }
494 spin_unlock(&ucontext->mmap_lock);
495 return NULL;
496}
497
498static inline void insert_mmap(struct c4iw_ucontext *ucontext,
499 struct c4iw_mm_entry *mm)
500{
501 spin_lock(&ucontext->mmap_lock);
502 PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
503 mm->key, (unsigned long long) mm->addr, mm->len);
504 list_add_tail(&mm->entry, &ucontext->mmaps);
505 spin_unlock(&ucontext->mmap_lock);
506}
507
508enum c4iw_qp_attr_mask {
509 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
2c974781
VP		 510 C4IW_QP_ATTR_SQ_DB = 1<<1,
511 C4IW_QP_ATTR_RQ_DB = 1<<2,
cfdda9d7
SW		 512 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
513 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
514 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
515 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
516 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
517 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
518 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
519 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
520 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
521 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
522 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
523 C4IW_QP_ATTR_MAX_ORD |
524 C4IW_QP_ATTR_MAX_IRD |
525 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
526 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
527 C4IW_QP_ATTR_MPA_ATTR |
528 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
529};
530
531int c4iw_modify_qp(struct c4iw_dev *rhp,
532 struct c4iw_qp *qhp,
533 enum c4iw_qp_attr_mask mask,
534 struct c4iw_qp_attributes *attrs,
535 int internal);
536
537enum c4iw_qp_state {
538 C4IW_QP_STATE_IDLE,
539 C4IW_QP_STATE_RTS,
540 C4IW_QP_STATE_ERROR,
541 C4IW_QP_STATE_TERMINATE,
542 C4IW_QP_STATE_CLOSING,
543 C4IW_QP_STATE_TOT
544};
545
546static inline int c4iw_convert_state(enum ib_qp_state ib_state)
547{
548 switch (ib_state) {
549 case IB_QPS_RESET:
550 case IB_QPS_INIT:
551 return C4IW_QP_STATE_IDLE;
552 case IB_QPS_RTS:
553 return C4IW_QP_STATE_RTS;
554 case IB_QPS_SQD:
555 return C4IW_QP_STATE_CLOSING;
556 case IB_QPS_SQE:
557 return C4IW_QP_STATE_TERMINATE;
558 case IB_QPS_ERR:
559 return C4IW_QP_STATE_ERROR;
560 default:
561 return -1;
562 }
563}
564
67bbc055
VP		 565static inline int to_ib_qp_state(int c4iw_qp_state)
566{
567 switch (c4iw_qp_state) {
568 case C4IW_QP_STATE_IDLE:
569 return IB_QPS_INIT;
570 case C4IW_QP_STATE_RTS:
571 return IB_QPS_RTS;
572 case C4IW_QP_STATE_CLOSING:
573 return IB_QPS_SQD;
574 case C4IW_QP_STATE_TERMINATE:
575 return IB_QPS_SQE;
576 case C4IW_QP_STATE_ERROR:
577 return IB_QPS_ERR;
578 }
579 return IB_QPS_ERR;
580}
581
cfdda9d7
SW		 582static inline u32 c4iw_ib_to_tpt_access(int a)
583{
584 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
585 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
586 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
587 FW_RI_MEM_ACCESS_LOCAL_READ;
588}
589
590static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
591{
592 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
593 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
594}
595
596enum c4iw_mmid_state {
597 C4IW_STAG_STATE_VALID,
598 C4IW_STAG_STATE_INVALID
599};
600
601#define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
602
603#define MPA_KEY_REQ "MPA ID Req Frame"
604#define MPA_KEY_REP "MPA ID Rep Frame"
605
606#define MPA_MAX_PRIVATE_DATA 256
d2fe99e8 607#define MPA_ENHANCED_RDMA_CONN 0x10
cfdda9d7
SW		 608#define MPA_REJECT 0x20
609#define MPA_CRC 0x40
610#define MPA_MARKERS 0x80
611#define MPA_FLAGS_MASK 0xE0
612
d2fe99e8
KS		 613#define MPA_V2_PEER2PEER_MODEL 0x8000
614#define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
615#define MPA_V2_RDMA_WRITE_RTR 0x8000
616#define MPA_V2_RDMA_READ_RTR 0x4000
617#define MPA_V2_IRD_ORD_MASK 0x3FFF
618
cfdda9d7
SW		 619#define c4iw_put_ep(ep) { \
620 PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
621 ep, atomic_read(&((ep)->kref.refcount))); \
622 WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
623 kref_put(&((ep)->kref), _c4iw_free_ep); \
624}
625
626#define c4iw_get_ep(ep) { \
627 PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
628 ep, atomic_read(&((ep)->kref.refcount))); \
629 kref_get(&((ep)->kref)); \
630}
631void _c4iw_free_ep(struct kref *kref);
632
633struct mpa_message {
634 u8 key[16];
635 u8 flags;
636 u8 revision;
637 __be16 private_data_size;
638 u8 private_data[0];
639};
640
d2fe99e8
KS		 641struct mpa_v2_conn_params {
642 __be16 ird;
643 __be16 ord;
644};
645
cfdda9d7
SW		 646struct terminate_message {
647 u8 layer_etype;
648 u8 ecode;
649 __be16 hdrct_rsvd;
650 u8 len_hdrs[0];
651};
652
653#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
654
655enum c4iw_layers_types {
656 LAYER_RDMAP = 0x00,
657 LAYER_DDP = 0x10,
658 LAYER_MPA = 0x20,
659 RDMAP_LOCAL_CATA = 0x00,
660 RDMAP_REMOTE_PROT = 0x01,
661 RDMAP_REMOTE_OP = 0x02,
662 DDP_LOCAL_CATA = 0x00,
663 DDP_TAGGED_ERR = 0x01,
664 DDP_UNTAGGED_ERR = 0x02,
665 DDP_LLP = 0x03
666};
667
668enum c4iw_rdma_ecodes {
669 RDMAP_INV_STAG = 0x00,
670 RDMAP_BASE_BOUNDS = 0x01,
671 RDMAP_ACC_VIOL = 0x02,
672 RDMAP_STAG_NOT_ASSOC = 0x03,
673 RDMAP_TO_WRAP = 0x04,
674 RDMAP_INV_VERS = 0x05,
675 RDMAP_INV_OPCODE = 0x06,
676 RDMAP_STREAM_CATA = 0x07,
677 RDMAP_GLOBAL_CATA = 0x08,
678 RDMAP_CANT_INV_STAG = 0x09,
679 RDMAP_UNSPECIFIED = 0xff
680};
681
682enum c4iw_ddp_ecodes {
683 DDPT_INV_STAG = 0x00,
684 DDPT_BASE_BOUNDS = 0x01,
685 DDPT_STAG_NOT_ASSOC = 0x02,
686 DDPT_TO_WRAP = 0x03,
687 DDPT_INV_VERS = 0x04,
688 DDPU_INV_QN = 0x01,
689 DDPU_INV_MSN_NOBUF = 0x02,
690 DDPU_INV_MSN_RANGE = 0x03,
691 DDPU_INV_MO = 0x04,
692 DDPU_MSG_TOOBIG = 0x05,
693 DDPU_INV_VERS = 0x06
694};
695
696enum c4iw_mpa_ecodes {
697 MPA_CRC_ERR = 0x02,
d2fe99e8
KS		 698 MPA_MARKER_ERR = 0x03,
699 MPA_LOCAL_CATA = 0x05,
700 MPA_INSUFF_IRD = 0x06,
701 MPA_NOMATCH_RTR = 0x07,
cfdda9d7
SW		 702};
703
704enum c4iw_ep_state {
705 IDLE = 0,
706 LISTEN,
707 CONNECTING,
708 MPA_REQ_WAIT,
709 MPA_REQ_SENT,
710 MPA_REQ_RCVD,
711 MPA_REP_SENT,
712 FPDU_MODE,
713 ABORTING,
714 CLOSING,
715 MORIBUND,
716 DEAD,
717};
718
719enum c4iw_ep_flags {
720 PEER_ABORT_IN_PROGRESS = 0,
721 ABORT_REQ_IN_PROGRESS = 1,
722 RELEASE_RESOURCES = 2,
723 CLOSE_SENT = 3,
1ec779cc 724 TIMEOUT = 4,
325abead 725 QP_REFERENCED = 5,
cfdda9d7
SW		 726};
727
793dad94
VP		 728enum c4iw_ep_history {
729 ACT_OPEN_REQ = 0,
730 ACT_OFLD_CONN = 1,
731 ACT_OPEN_RPL = 2,
732 ACT_ESTAB = 3,
733 PASS_ACCEPT_REQ = 4,
734 PASS_ESTAB = 5,
735 ABORT_UPCALL = 6,
736 ESTAB_UPCALL = 7,
737 CLOSE_UPCALL = 8,
738 ULP_ACCEPT = 9,
739 ULP_REJECT = 10,
740 TIMEDOUT = 11,
741 PEER_ABORT = 12,
742 PEER_CLOSE = 13,
743 CONNREQ_UPCALL = 14,
744 ABORT_CONN = 15,
745 DISCONN_UPCALL = 16,
746 EP_DISC_CLOSE = 17,
747 EP_DISC_ABORT = 18,
748 CONN_RPL_UPCALL = 19,
749 ACT_RETRY_NOMEM = 20,
750 ACT_RETRY_INUSE = 21
751};
752
cfdda9d7
SW		 753struct c4iw_ep_common {
754 struct iw_cm_id *cm_id;
755 struct c4iw_qp *qp;
756 struct c4iw_dev *dev;
757 enum c4iw_ep_state state;
758 struct kref kref;
2f5b48c3 759 struct mutex mutex;
830662f6
VP		 760 struct sockaddr_storage local_addr;
761 struct sockaddr_storage remote_addr;
aadc4df3 762 struct c4iw_wr_wait wr_wait;
cfdda9d7 763 unsigned long flags;
793dad94 764 unsigned long history;
cfdda9d7
SW		 765};
766
767struct c4iw_listen_ep {
768 struct c4iw_ep_common com;
769 unsigned int stid;
770 int backlog;
771};
772
773struct c4iw_ep {
774 struct c4iw_ep_common com;
775 struct c4iw_ep *parent_ep;
776 struct timer_list timer;
be4c9bad 777 struct list_head entry;
cfdda9d7
SW		 778 unsigned int atid;
779 u32 hwtid;
780 u32 snd_seq;
781 u32 rcv_seq;
782 struct l2t_entry *l2t;
783 struct dst_entry *dst;
784 struct sk_buff *mpa_skb;
785 struct c4iw_mpa_attributes mpa_attr;
786 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
787 unsigned int mpa_pkt_len;
788 u32 ird;
789 u32 ord;
790 u32 smac_idx;
791 u32 tx_chan;
792 u32 mtu;
793 u16 mss;
794 u16 emss;
795 u16 plen;
796 u16 rss_qid;
797 u16 txq_idx;
d4f1a5c6 798 u16 ctrlq_idx;
cfdda9d7 799 u8 tos;
d2fe99e8
KS		 800 u8 retry_with_mpa_v1;
801 u8 tried_with_mpa_v1;
793dad94 802 unsigned int retry_count;
cfdda9d7
SW		 803};
804
805static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
806{
807 return cm_id->provider_data;
808}
809
810static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
811{
812 return cm_id->provider_data;
813}
814
815static inline int compute_wscale(int win)
816{
817 int wscale = 0;
818
819 while (wscale < 14 && (65535<<wscale) < win)
820 wscale++;
821 return wscale;
822}
823
f079af7a
VP		 824static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
825{
826#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
827 return infop->vr->ocq.size > 0;
828#else
829 return 0;
830#endif
831}
832
ec3eead2
VP		 833u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
834void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
835int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
836 u32 reserved, u32 flags);
837void c4iw_id_table_free(struct c4iw_id_table *alloc);
838
cfdda9d7
SW		 839typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
840
841int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
842 struct l2t_entry *l2t);
843void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
844 struct c4iw_dev_ucontext *uctx);
ec3eead2
VP		 845u32 c4iw_get_resource(struct c4iw_id_table *id_table);
846void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
cfdda9d7
SW		 847int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
848int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
849int c4iw_pblpool_create(struct c4iw_rdev *rdev);
850int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
c6d7b267 851int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
cfdda9d7
SW		 852void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
853void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
c6d7b267 854void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
cfdda9d7
SW		 855void c4iw_destroy_resource(struct c4iw_resource *rscp);
856int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
857int c4iw_register_device(struct c4iw_dev *dev);
858void c4iw_unregister_device(struct c4iw_dev *dev);
859int __init c4iw_cm_init(void);
860void __exit c4iw_cm_term(void);
861void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
862 struct c4iw_dev_ucontext *uctx);
863void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
864 struct c4iw_dev_ucontext *uctx);
865int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
866int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
867 struct ib_send_wr **bad_wr);
868int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
869 struct ib_recv_wr **bad_wr);
870int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
871 struct ib_mw_bind *mw_bind);
872int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
873int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
874int c4iw_destroy_listen(struct iw_cm_id *cm_id);
875int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
876int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
877void c4iw_qp_add_ref(struct ib_qp *qp);
878void c4iw_qp_rem_ref(struct ib_qp *qp);
879void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
880struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
881 struct ib_device *device,
882 int page_list_len);
883struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
884int c4iw_dealloc_mw(struct ib_mw *mw);
7083e42e 885struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
cfdda9d7
SW		 886struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
887 u64 length, u64 virt, int acc,
888 struct ib_udata *udata);
889struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
890struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
891 struct ib_phys_buf *buffer_list,
892 int num_phys_buf,
893 int acc,
894 u64 *iova_start);
895int c4iw_reregister_phys_mem(struct ib_mr *mr,
896 int mr_rereg_mask,
897 struct ib_pd *pd,
898 struct ib_phys_buf *buffer_list,
899 int num_phys_buf,
900 int acc, u64 *iova_start);
901int c4iw_dereg_mr(struct ib_mr *ib_mr);
902int c4iw_destroy_cq(struct ib_cq *ib_cq);
903struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
904 int vector,
905 struct ib_ucontext *ib_context,
906 struct ib_udata *udata);
907int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
908int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
909int c4iw_destroy_qp(struct ib_qp *ib_qp);
910struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
911 struct ib_qp_init_attr *attrs,
912 struct ib_udata *udata);
913int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
914 int attr_mask, struct ib_udata *udata);
67bbc055
VP		 915int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
916 int attr_mask, struct ib_qp_init_attr *init_attr);
cfdda9d7
SW		 917struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
918u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
919void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
920u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
921void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
c6d7b267
SW		 922u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
923void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
cfdda9d7 924int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
1cf24dce 925void c4iw_flush_hw_cq(struct c4iw_cq *chp);
cfdda9d7 926void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
cfdda9d7
SW		 927int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
928int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
1cf24dce 929int c4iw_flush_sq(struct c4iw_qp *qhp);
cfdda9d7
SW		 930int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
931u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
cfdda9d7
SW		 932int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
933u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
934void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
935 struct c4iw_dev_ucontext *uctx);
936u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
937void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
938 struct c4iw_dev_ucontext *uctx);
939void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
940
941extern struct cxgb4_client t4c_client;
942extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
be4c9bad 943extern int c4iw_max_read_depth;
422eea0a 944extern int db_fc_threshold;
80ccdd60 945extern int db_coalescing_threshold;
42b6a949 946extern int use_dsgl;
422eea0a 947
cfdda9d7
SW		 948
949#endif
Linux 6.x block layer and io_uring tree(s)