Merge tag 'amlogic-dt-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman...
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / device.c
CommitLineData
cfdda9d7
SW
1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/debugfs.h>
e572568f 35#include <linux/vmalloc.h>
da388973 36#include <linux/math64.h>
cfdda9d7
SW
37
38#include <rdma/ib_verbs.h>
39
40#include "iw_cxgb4.h"
41
42#define DRV_VERSION "0.1"
43
44MODULE_AUTHOR("Steve Wise");
f079af7a 45MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
cfdda9d7 46MODULE_LICENSE("Dual BSD/GPL");
cfdda9d7 47
80ccdd60
VP
48static int allow_db_fc_on_t5;
49module_param(allow_db_fc_on_t5, int, 0644);
50MODULE_PARM_DESC(allow_db_fc_on_t5,
51 "Allow DB Flow Control on T5 (default = 0)");
52
53static int allow_db_coalescing_on_t5;
54module_param(allow_db_coalescing_on_t5, int, 0644);
55MODULE_PARM_DESC(allow_db_coalescing_on_t5,
56 "Allow DB Coalescing on T5 (default = 0)");
57
7730b4c7
HS
58int c4iw_wr_log = 0;
59module_param(c4iw_wr_log, int, 0444);
60MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
61
65d4c01a 62static int c4iw_wr_log_size_order = 12;
7730b4c7
HS
63module_param(c4iw_wr_log_size_order, int, 0444);
64MODULE_PARM_DESC(c4iw_wr_log_size_order,
65 "Number of entries (log2) in the work request timing log.");
66
2f25e9a5 67static LIST_HEAD(uld_ctx_list);
cfdda9d7 68static DEFINE_MUTEX(dev_mutex);
0cb65d42 69static struct workqueue_struct *reg_workq;
cfdda9d7 70
05eb2389
SW
71#define DB_FC_RESUME_SIZE 64
72#define DB_FC_RESUME_DELAY 1
73#define DB_FC_DRAIN_THRESH 0
74
cfdda9d7
SW
75static struct dentry *c4iw_debugfs_root;
76
9e8d1fa3 77struct c4iw_debugfs_data {
cfdda9d7
SW
78 struct c4iw_dev *devp;
79 char *buf;
80 int bufsize;
81 int pos;
82};
83
9e8d1fa3 84static int count_idrs(int id, void *p, void *data)
cfdda9d7 85{
cfdda9d7
SW
86 int *countp = data;
87
cfdda9d7
SW
88 *countp = *countp + 1;
89 return 0;
90}
91
9e8d1fa3
SW
92static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
93 loff_t *ppos)
94{
95 struct c4iw_debugfs_data *d = file->private_data;
9e8d1fa3 96
3160977a 97 return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
9e8d1fa3
SW
98}
99
7730b4c7
HS
100void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
101{
102 struct wr_log_entry le;
103 int idx;
104
105 if (!wq->rdev->wr_log)
106 return;
107
108 idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
109 (wq->rdev->wr_log_size - 1);
110 le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
f8109d9e 111 le.poll_host_time = ktime_get();
7730b4c7
HS
112 le.valid = 1;
113 le.cqe_sge_ts = CQE_TS(cqe);
114 if (SQ_TYPE(cqe)) {
115 le.qid = wq->sq.qid;
116 le.opcode = CQE_OPCODE(cqe);
f8109d9e 117 le.post_host_time = wq->sq.sw_sq[wq->sq.cidx].host_time;
7730b4c7
HS
118 le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
119 le.wr_id = CQE_WRID_SQ_IDX(cqe);
120 } else {
121 le.qid = wq->rq.qid;
122 le.opcode = FW_RI_RECEIVE;
f8109d9e 123 le.post_host_time = wq->rq.sw_rq[wq->rq.cidx].host_time;
7730b4c7
HS
124 le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
125 le.wr_id = CQE_WRID_MSN(cqe);
126 }
127 wq->rdev->wr_log[idx] = le;
128}
129
130static int wr_log_show(struct seq_file *seq, void *v)
131{
132 struct c4iw_dev *dev = seq->private;
f8109d9e 133 ktime_t prev_time;
7730b4c7 134 struct wr_log_entry *lep;
f8109d9e 135 int prev_time_set = 0;
7730b4c7
HS
136 int idx, end;
137
6198dd8d 138#define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)
7730b4c7
HS
139
140 idx = atomic_read(&dev->rdev.wr_log_idx) &
141 (dev->rdev.wr_log_size - 1);
142 end = idx - 1;
143 if (end < 0)
144 end = dev->rdev.wr_log_size - 1;
145 lep = &dev->rdev.wr_log[idx];
146 while (idx != end) {
147 if (lep->valid) {
f8109d9e
AB
148 if (!prev_time_set) {
149 prev_time_set = 1;
150 prev_time = lep->poll_host_time;
7730b4c7 151 }
f8109d9e
AB
152 seq_printf(seq, "%04u: nsec %llu qid %u opcode "
153 "%u %s 0x%x host_wr_delta nsec %llu "
7730b4c7
HS
154 "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
155 "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
156 "cqe_poll_delta_ns %llu\n",
157 idx,
f8109d9e
AB
158 ktime_to_ns(ktime_sub(lep->poll_host_time,
159 prev_time)),
7730b4c7
HS
160 lep->qid, lep->opcode,
161 lep->opcode == FW_RI_RECEIVE ?
162 "msn" : "wrid",
163 lep->wr_id,
f8109d9e
AB
164 ktime_to_ns(ktime_sub(lep->poll_host_time,
165 lep->post_host_time)),
7730b4c7
HS
166 lep->post_sge_ts, lep->cqe_sge_ts,
167 lep->poll_sge_ts,
168 ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
169 ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
f8109d9e 170 prev_time = lep->poll_host_time;
7730b4c7
HS
171 }
172 idx++;
173 if (idx > (dev->rdev.wr_log_size - 1))
174 idx = 0;
175 lep = &dev->rdev.wr_log[idx];
176 }
177#undef ts2ns
178 return 0;
179}
180
181static int wr_log_open(struct inode *inode, struct file *file)
182{
183 return single_open(file, wr_log_show, inode->i_private);
184}
185
186static ssize_t wr_log_clear(struct file *file, const char __user *buf,
187 size_t count, loff_t *pos)
188{
189 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
190 int i;
191
192 if (dev->rdev.wr_log)
193 for (i = 0; i < dev->rdev.wr_log_size; i++)
194 dev->rdev.wr_log[i].valid = 0;
195 return count;
196}
197
198static const struct file_operations wr_log_debugfs_fops = {
199 .owner = THIS_MODULE,
200 .open = wr_log_open,
201 .release = single_release,
202 .read = seq_read,
203 .llseek = seq_lseek,
204 .write = wr_log_clear,
205};
206
bab572f1
GG
207static struct sockaddr_in zero_sin = {
208 .sin_family = AF_INET,
209};
210
211static struct sockaddr_in6 zero_sin6 = {
212 .sin6_family = AF_INET6,
213};
214
215static void set_ep_sin_addrs(struct c4iw_ep *ep,
216 struct sockaddr_in **lsin,
217 struct sockaddr_in **rsin,
218 struct sockaddr_in **m_lsin,
219 struct sockaddr_in **m_rsin)
220{
221 struct iw_cm_id *id = ep->com.cm_id;
222
44016b34
BP
223 *m_lsin = (struct sockaddr_in *)&ep->com.local_addr;
224 *m_rsin = (struct sockaddr_in *)&ep->com.remote_addr;
bab572f1 225 if (id) {
44016b34
BP
226 *lsin = (struct sockaddr_in *)&id->local_addr;
227 *rsin = (struct sockaddr_in *)&id->remote_addr;
bab572f1 228 } else {
44016b34
BP
229 *lsin = &zero_sin;
230 *rsin = &zero_sin;
bab572f1
GG
231 }
232}
233
234static void set_ep_sin6_addrs(struct c4iw_ep *ep,
235 struct sockaddr_in6 **lsin6,
236 struct sockaddr_in6 **rsin6,
237 struct sockaddr_in6 **m_lsin6,
238 struct sockaddr_in6 **m_rsin6)
239{
240 struct iw_cm_id *id = ep->com.cm_id;
241
44016b34
BP
242 *m_lsin6 = (struct sockaddr_in6 *)&ep->com.local_addr;
243 *m_rsin6 = (struct sockaddr_in6 *)&ep->com.remote_addr;
bab572f1 244 if (id) {
44016b34
BP
245 *lsin6 = (struct sockaddr_in6 *)&id->local_addr;
246 *rsin6 = (struct sockaddr_in6 *)&id->remote_addr;
bab572f1 247 } else {
44016b34
BP
248 *lsin6 = &zero_sin6;
249 *rsin6 = &zero_sin6;
bab572f1
GG
250 }
251}
252
9e8d1fa3 253static int dump_qp(int id, void *p, void *data)
cfdda9d7
SW
254{
255 struct c4iw_qp *qp = p;
9e8d1fa3 256 struct c4iw_debugfs_data *qpd = data;
cfdda9d7
SW
257 int space;
258 int cc;
259
260 if (id != qp->wq.sq.qid)
261 return 0;
262
263 space = qpd->bufsize - qpd->pos - 1;
264 if (space == 0)
265 return 1;
266
830662f6 267 if (qp->ep) {
bab572f1
GG
268 struct c4iw_ep *ep = qp->ep;
269
270 if (ep->com.local_addr.ss_family == AF_INET) {
271 struct sockaddr_in *lsin;
272 struct sockaddr_in *rsin;
273 struct sockaddr_in *m_lsin;
274 struct sockaddr_in *m_rsin;
830662f6 275
bab572f1 276 set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
830662f6
VP
277 cc = snprintf(qpd->buf + qpd->pos, space,
278 "rc qp sq id %u rq id %u state %u "
279 "onchip %u ep tid %u state %u "
9eccfe10 280 "%pI4:%u/%u->%pI4:%u/%u\n",
830662f6
VP
281 qp->wq.sq.qid, qp->wq.rq.qid,
282 (int)qp->attr.state,
283 qp->wq.sq.flags & T4_SQ_ONCHIP,
bab572f1 284 ep->hwtid, (int)ep->com.state,
830662f6 285 &lsin->sin_addr, ntohs(lsin->sin_port),
bab572f1 286 ntohs(m_lsin->sin_port),
9eccfe10 287 &rsin->sin_addr, ntohs(rsin->sin_port),
bab572f1 288 ntohs(m_rsin->sin_port));
830662f6 289 } else {
bab572f1
GG
290 struct sockaddr_in6 *lsin6;
291 struct sockaddr_in6 *rsin6;
292 struct sockaddr_in6 *m_lsin6;
293 struct sockaddr_in6 *m_rsin6;
830662f6 294
bab572f1
GG
295 set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6,
296 &m_rsin6);
830662f6
VP
297 cc = snprintf(qpd->buf + qpd->pos, space,
298 "rc qp sq id %u rq id %u state %u "
299 "onchip %u ep tid %u state %u "
9eccfe10 300 "%pI6:%u/%u->%pI6:%u/%u\n",
830662f6
VP
301 qp->wq.sq.qid, qp->wq.rq.qid,
302 (int)qp->attr.state,
303 qp->wq.sq.flags & T4_SQ_ONCHIP,
bab572f1 304 ep->hwtid, (int)ep->com.state,
830662f6
VP
305 &lsin6->sin6_addr,
306 ntohs(lsin6->sin6_port),
bab572f1 307 ntohs(m_lsin6->sin6_port),
830662f6 308 &rsin6->sin6_addr,
9eccfe10 309 ntohs(rsin6->sin6_port),
bab572f1 310 ntohs(m_rsin6->sin6_port));
830662f6
VP
311 }
312 } else
db5d040d
SW
313 cc = snprintf(qpd->buf + qpd->pos, space,
314 "qp sq id %u rq id %u state %u onchip %u\n",
315 qp->wq.sq.qid, qp->wq.rq.qid,
316 (int)qp->attr.state,
317 qp->wq.sq.flags & T4_SQ_ONCHIP);
cfdda9d7
SW
318 if (cc < space)
319 qpd->pos += cc;
320 return 0;
321}
322
323static int qp_release(struct inode *inode, struct file *file)
324{
9e8d1fa3 325 struct c4iw_debugfs_data *qpd = file->private_data;
cfdda9d7 326 if (!qpd) {
700456bd 327 pr_info("%s null qpd?\n", __func__);
cfdda9d7
SW
328 return 0;
329 }
d716a2a0 330 vfree(qpd->buf);
cfdda9d7
SW
331 kfree(qpd);
332 return 0;
333}
334
335static int qp_open(struct inode *inode, struct file *file)
336{
9e8d1fa3 337 struct c4iw_debugfs_data *qpd;
cfdda9d7
SW
338 int count = 1;
339
340 qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
4275a5b2
H
341 if (!qpd)
342 return -ENOMEM;
343
cfdda9d7
SW
344 qpd->devp = inode->i_private;
345 qpd->pos = 0;
346
347 spin_lock_irq(&qpd->devp->lock);
9e8d1fa3 348 idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
cfdda9d7
SW
349 spin_unlock_irq(&qpd->devp->lock);
350
68cebcab 351 qpd->bufsize = count * 180;
d716a2a0 352 qpd->buf = vmalloc(qpd->bufsize);
cfdda9d7 353 if (!qpd->buf) {
4275a5b2
H
354 kfree(qpd);
355 return -ENOMEM;
cfdda9d7
SW
356 }
357
358 spin_lock_irq(&qpd->devp->lock);
9e8d1fa3 359 idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
cfdda9d7
SW
360 spin_unlock_irq(&qpd->devp->lock);
361
362 qpd->buf[qpd->pos++] = 0;
363 file->private_data = qpd;
4275a5b2 364 return 0;
cfdda9d7
SW
365}
366
9e8d1fa3
SW
367static const struct file_operations qp_debugfs_fops = {
368 .owner = THIS_MODULE,
369 .open = qp_open,
370 .release = qp_release,
371 .read = debugfs_read,
8bbac892 372 .llseek = default_llseek,
9e8d1fa3
SW
373};
374
375static int dump_stag(int id, void *p, void *data)
cfdda9d7 376{
9e8d1fa3
SW
377 struct c4iw_debugfs_data *stagd = data;
378 int space;
379 int cc;
031cf476
HS
380 struct fw_ri_tpte tpte;
381 int ret;
cfdda9d7 382
9e8d1fa3
SW
383 space = stagd->bufsize - stagd->pos - 1;
384 if (space == 0)
385 return 1;
386
031cf476
HS
387 ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
388 (__be32 *)&tpte);
389 if (ret) {
390 dev_err(&stagd->devp->rdev.lldi.pdev->dev,
391 "%s cxgb4_read_tpte err %d\n", __func__, ret);
392 return ret;
393 }
394 cc = snprintf(stagd->buf + stagd->pos, space,
395 "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
396 "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
397 (u32)id<<8,
cf7fe64a
HS
398 FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
399 FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
400 FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
401 FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
402 FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
403 FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
031cf476
HS
404 ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
405 ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
9e8d1fa3
SW
406 if (cc < space)
407 stagd->pos += cc;
408 return 0;
409}
410
411static int stag_release(struct inode *inode, struct file *file)
412{
413 struct c4iw_debugfs_data *stagd = file->private_data;
414 if (!stagd) {
700456bd 415 pr_info("%s null stagd?\n", __func__);
cfdda9d7 416 return 0;
9e8d1fa3 417 }
031cf476 418 vfree(stagd->buf);
9e8d1fa3
SW
419 kfree(stagd);
420 return 0;
421}
cfdda9d7 422
9e8d1fa3
SW
423static int stag_open(struct inode *inode, struct file *file)
424{
425 struct c4iw_debugfs_data *stagd;
426 int ret = 0;
427 int count = 1;
cfdda9d7 428
9e8d1fa3
SW
429 stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
430 if (!stagd) {
431 ret = -ENOMEM;
432 goto out;
433 }
434 stagd->devp = inode->i_private;
435 stagd->pos = 0;
cfdda9d7 436
9e8d1fa3
SW
437 spin_lock_irq(&stagd->devp->lock);
438 idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
439 spin_unlock_irq(&stagd->devp->lock);
440
031cf476
HS
441 stagd->bufsize = count * 256;
442 stagd->buf = vmalloc(stagd->bufsize);
9e8d1fa3
SW
443 if (!stagd->buf) {
444 ret = -ENOMEM;
445 goto err1;
cfdda9d7 446 }
9e8d1fa3
SW
447
448 spin_lock_irq(&stagd->devp->lock);
449 idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
450 spin_unlock_irq(&stagd->devp->lock);
451
452 stagd->buf[stagd->pos++] = 0;
453 file->private_data = stagd;
454 goto out;
455err1:
456 kfree(stagd);
457out:
458 return ret;
cfdda9d7
SW
459}
460
9e8d1fa3 461static const struct file_operations stag_debugfs_fops = {
cfdda9d7 462 .owner = THIS_MODULE,
9e8d1fa3
SW
463 .open = stag_open,
464 .release = stag_release,
465 .read = debugfs_read,
8bbac892 466 .llseek = default_llseek,
cfdda9d7
SW
467};
468
05eb2389 469static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
422eea0a 470
8d81ef34
VP
471static int stats_show(struct seq_file *seq, void *v)
472{
473 struct c4iw_dev *dev = seq->private;
474
ec3eead2
VP
475 seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
476 "Max", "Fail");
477 seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
8d81ef34 478 dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
ec3eead2
VP
479 dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
480 seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
8d81ef34 481 dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
ec3eead2
VP
482 dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
483 seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
8d81ef34 484 dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
ec3eead2
VP
485 dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
486 seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
8d81ef34 487 dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
ec3eead2
VP
488 dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
489 seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
8d81ef34 490 dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
ec3eead2
VP
491 dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
492 seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
8d81ef34 493 dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
ec3eead2 494 dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
2c974781
VP
495 seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
496 seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
497 seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
05eb2389 498 seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
422eea0a 499 db_state_str[dev->db_state],
05eb2389
SW
500 dev->rdev.stats.db_state_transitions,
501 dev->rdev.stats.db_fc_interruptions);
1cab775c 502 seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
793dad94
VP
503 seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
504 dev->rdev.stats.act_ofld_conn_fails);
505 seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
506 dev->rdev.stats.pas_ofld_conn_fails);
179d03bb 507 seq_printf(seq, "NEG_ADV_RCVD: %10llu\n", dev->rdev.stats.neg_adv);
4c2c5763 508 seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
8d81ef34
VP
509 return 0;
510}
511
512static int stats_open(struct inode *inode, struct file *file)
513{
514 return single_open(file, stats_show, inode->i_private);
515}
516
517static ssize_t stats_clear(struct file *file, const char __user *buf,
518 size_t count, loff_t *pos)
519{
520 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
521
522 mutex_lock(&dev->rdev.stats.lock);
523 dev->rdev.stats.pd.max = 0;
ec3eead2 524 dev->rdev.stats.pd.fail = 0;
8d81ef34 525 dev->rdev.stats.qid.max = 0;
ec3eead2 526 dev->rdev.stats.qid.fail = 0;
8d81ef34 527 dev->rdev.stats.stag.max = 0;
ec3eead2 528 dev->rdev.stats.stag.fail = 0;
8d81ef34 529 dev->rdev.stats.pbl.max = 0;
ec3eead2 530 dev->rdev.stats.pbl.fail = 0;
8d81ef34 531 dev->rdev.stats.rqt.max = 0;
ec3eead2 532 dev->rdev.stats.rqt.fail = 0;
8d81ef34 533 dev->rdev.stats.ocqp.max = 0;
ec3eead2 534 dev->rdev.stats.ocqp.fail = 0;
2c974781
VP
535 dev->rdev.stats.db_full = 0;
536 dev->rdev.stats.db_empty = 0;
537 dev->rdev.stats.db_drop = 0;
422eea0a 538 dev->rdev.stats.db_state_transitions = 0;
793dad94
VP
539 dev->rdev.stats.tcam_full = 0;
540 dev->rdev.stats.act_ofld_conn_fails = 0;
541 dev->rdev.stats.pas_ofld_conn_fails = 0;
8d81ef34
VP
542 mutex_unlock(&dev->rdev.stats.lock);
543 return count;
544}
545
546static const struct file_operations stats_debugfs_fops = {
547 .owner = THIS_MODULE,
548 .open = stats_open,
549 .release = single_release,
550 .read = seq_read,
551 .llseek = seq_lseek,
552 .write = stats_clear,
553};
554
793dad94
VP
555static int dump_ep(int id, void *p, void *data)
556{
557 struct c4iw_ep *ep = p;
558 struct c4iw_debugfs_data *epd = data;
559 int space;
560 int cc;
561
562 space = epd->bufsize - epd->pos - 1;
563 if (space == 0)
564 return 1;
565
830662f6 566 if (ep->com.local_addr.ss_family == AF_INET) {
bab572f1
GG
567 struct sockaddr_in *lsin;
568 struct sockaddr_in *rsin;
569 struct sockaddr_in *m_lsin;
570 struct sockaddr_in *m_rsin;
830662f6 571
bab572f1 572 set_ep_sin_addrs(ep, &lsin, &rsin, &m_lsin, &m_rsin);
830662f6
VP
573 cc = snprintf(epd->buf + epd->pos, space,
574 "ep %p cm_id %p qp %p state %d flags 0x%lx "
575 "history 0x%lx hwtid %d atid %d "
179d03bb 576 "conn_na %u abort_na %u "
9eccfe10 577 "%pI4:%d/%d <-> %pI4:%d/%d\n",
830662f6
VP
578 ep, ep->com.cm_id, ep->com.qp,
579 (int)ep->com.state, ep->com.flags,
580 ep->com.history, ep->hwtid, ep->atid,
179d03bb
H
581 ep->stats.connect_neg_adv,
582 ep->stats.abort_neg_adv,
830662f6 583 &lsin->sin_addr, ntohs(lsin->sin_port),
bab572f1 584 ntohs(m_lsin->sin_port),
9eccfe10 585 &rsin->sin_addr, ntohs(rsin->sin_port),
bab572f1 586 ntohs(m_rsin->sin_port));
830662f6 587 } else {
bab572f1
GG
588 struct sockaddr_in6 *lsin6;
589 struct sockaddr_in6 *rsin6;
590 struct sockaddr_in6 *m_lsin6;
591 struct sockaddr_in6 *m_rsin6;
830662f6 592
bab572f1 593 set_ep_sin6_addrs(ep, &lsin6, &rsin6, &m_lsin6, &m_rsin6);
830662f6
VP
594 cc = snprintf(epd->buf + epd->pos, space,
595 "ep %p cm_id %p qp %p state %d flags 0x%lx "
596 "history 0x%lx hwtid %d atid %d "
179d03bb 597 "conn_na %u abort_na %u "
9eccfe10 598 "%pI6:%d/%d <-> %pI6:%d/%d\n",
830662f6
VP
599 ep, ep->com.cm_id, ep->com.qp,
600 (int)ep->com.state, ep->com.flags,
601 ep->com.history, ep->hwtid, ep->atid,
179d03bb
H
602 ep->stats.connect_neg_adv,
603 ep->stats.abort_neg_adv,
830662f6 604 &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
bab572f1 605 ntohs(m_lsin6->sin6_port),
9eccfe10 606 &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
bab572f1 607 ntohs(m_rsin6->sin6_port));
830662f6 608 }
793dad94
VP
609 if (cc < space)
610 epd->pos += cc;
611 return 0;
612}
613
614static int dump_listen_ep(int id, void *p, void *data)
615{
616 struct c4iw_listen_ep *ep = p;
617 struct c4iw_debugfs_data *epd = data;
618 int space;
619 int cc;
620
621 space = epd->bufsize - epd->pos - 1;
622 if (space == 0)
623 return 1;
624
830662f6
VP
625 if (ep->com.local_addr.ss_family == AF_INET) {
626 struct sockaddr_in *lsin = (struct sockaddr_in *)
170003c8 627 &ep->com.cm_id->local_addr;
bab572f1 628 struct sockaddr_in *m_lsin = (struct sockaddr_in *)
170003c8 629 &ep->com.cm_id->m_local_addr;
830662f6
VP
630
631 cc = snprintf(epd->buf + epd->pos, space,
632 "ep %p cm_id %p state %d flags 0x%lx stid %d "
9eccfe10 633 "backlog %d %pI4:%d/%d\n",
830662f6
VP
634 ep, ep->com.cm_id, (int)ep->com.state,
635 ep->com.flags, ep->stid, ep->backlog,
9eccfe10 636 &lsin->sin_addr, ntohs(lsin->sin_port),
bab572f1 637 ntohs(m_lsin->sin_port));
830662f6
VP
638 } else {
639 struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
170003c8 640 &ep->com.cm_id->local_addr;
bab572f1 641 struct sockaddr_in6 *m_lsin6 = (struct sockaddr_in6 *)
170003c8 642 &ep->com.cm_id->m_local_addr;
830662f6
VP
643
644 cc = snprintf(epd->buf + epd->pos, space,
645 "ep %p cm_id %p state %d flags 0x%lx stid %d "
9eccfe10 646 "backlog %d %pI6:%d/%d\n",
830662f6
VP
647 ep, ep->com.cm_id, (int)ep->com.state,
648 ep->com.flags, ep->stid, ep->backlog,
9eccfe10 649 &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
bab572f1 650 ntohs(m_lsin6->sin6_port));
830662f6 651 }
793dad94
VP
652 if (cc < space)
653 epd->pos += cc;
654 return 0;
655}
656
657static int ep_release(struct inode *inode, struct file *file)
658{
659 struct c4iw_debugfs_data *epd = file->private_data;
660 if (!epd) {
661 pr_info("%s null qpd?\n", __func__);
662 return 0;
663 }
664 vfree(epd->buf);
665 kfree(epd);
666 return 0;
667}
668
669static int ep_open(struct inode *inode, struct file *file)
670{
671 struct c4iw_debugfs_data *epd;
672 int ret = 0;
673 int count = 1;
674
675 epd = kmalloc(sizeof(*epd), GFP_KERNEL);
676 if (!epd) {
677 ret = -ENOMEM;
678 goto out;
679 }
680 epd->devp = inode->i_private;
681 epd->pos = 0;
682
683 spin_lock_irq(&epd->devp->lock);
684 idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
685 idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
686 idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
687 spin_unlock_irq(&epd->devp->lock);
688
63a71ba6 689 epd->bufsize = count * 240;
793dad94
VP
690 epd->buf = vmalloc(epd->bufsize);
691 if (!epd->buf) {
692 ret = -ENOMEM;
693 goto err1;
694 }
695
696 spin_lock_irq(&epd->devp->lock);
697 idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
698 idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
699 idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
700 spin_unlock_irq(&epd->devp->lock);
701
702 file->private_data = epd;
703 goto out;
704err1:
705 kfree(epd);
706out:
707 return ret;
708}
709
710static const struct file_operations ep_debugfs_fops = {
711 .owner = THIS_MODULE,
712 .open = ep_open,
713 .release = ep_release,
714 .read = debugfs_read,
715};
716
cfdda9d7
SW
717static int setup_debugfs(struct c4iw_dev *devp)
718{
cfdda9d7
SW
719 if (!devp->debugfs_root)
720 return -1;
721
e59b4e91
DH
722 debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root,
723 (void *)devp, &qp_debugfs_fops, 4096);
724
725 debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root,
726 (void *)devp, &stag_debugfs_fops, 4096);
727
728 debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root,
729 (void *)devp, &stats_debugfs_fops, 4096);
730
731 debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root,
732 (void *)devp, &ep_debugfs_fops, 4096);
733
734 if (c4iw_wr_log)
735 debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root,
736 (void *)devp, &wr_log_debugfs_fops, 4096);
cfdda9d7
SW
737 return 0;
738}
739
740void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
741 struct c4iw_dev_ucontext *uctx)
742{
743 struct list_head *pos, *nxt;
744 struct c4iw_qid_list *entry;
745
746 mutex_lock(&uctx->lock);
747 list_for_each_safe(pos, nxt, &uctx->qpids) {
748 entry = list_entry(pos, struct c4iw_qid_list, entry);
749 list_del_init(&entry->entry);
8d81ef34 750 if (!(entry->qid & rdev->qpmask)) {
ec3eead2
VP
751 c4iw_put_resource(&rdev->resource.qid_table,
752 entry->qid);
8d81ef34
VP
753 mutex_lock(&rdev->stats.lock);
754 rdev->stats.qid.cur -= rdev->qpmask + 1;
755 mutex_unlock(&rdev->stats.lock);
756 }
cfdda9d7
SW
757 kfree(entry);
758 }
759
d4702645 760 list_for_each_safe(pos, nxt, &uctx->cqids) {
cfdda9d7
SW
761 entry = list_entry(pos, struct c4iw_qid_list, entry);
762 list_del_init(&entry->entry);
763 kfree(entry);
764 }
765 mutex_unlock(&uctx->lock);
766}
767
768void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
769 struct c4iw_dev_ucontext *uctx)
770{
771 INIT_LIST_HEAD(&uctx->qpids);
772 INIT_LIST_HEAD(&uctx->cqids);
773 mutex_init(&uctx->lock);
774}
775
776/* Caller takes care of locking if needed */
777static int c4iw_rdev_open(struct c4iw_rdev *rdev)
778{
779 int err;
780
781 c4iw_init_dev_ucontext(rdev, &rdev->uctx);
782
4a75a86c
H
783 /*
784 * This implementation assumes udb_density == ucq_density! Eventually
785 * we might need to support this but for now fail the open. Also the
786 * cqid and qpid range must match for now.
787 */
788 if (rdev->lldi.udb_density != rdev->lldi.ucq_density) {
700456bd 789 pr_err("%s: unsupported udb/ucq densities %u/%u\n",
4a75a86c
H
790 pci_name(rdev->lldi.pdev), rdev->lldi.udb_density,
791 rdev->lldi.ucq_density);
4275a5b2 792 return -EINVAL;
4a75a86c
H
793 }
794 if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start ||
795 rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) {
700456bd 796 pr_err("%s: unsupported qp and cq id ranges qp start %u size %u cq start %u size %u\n",
4a75a86c
H
797 pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start,
798 rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size,
799 rdev->lldi.vr->cq.size);
4275a5b2 800 return -EINVAL;
4a75a86c
H
801 }
802
cfdda9d7 803 rdev->qpmask = rdev->lldi.udb_density - 1;
cfdda9d7 804 rdev->cqmask = rdev->lldi.ucq_density - 1;
548ddb19
BP
805 pr_debug("dev %s stag start 0x%0x size 0x%0x num stags %d pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x qp qid start %u size %u cq qid start %u size %u\n",
806 pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
a9a42886
JP
807 rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
808 rdev->lldi.vr->pbl.start,
809 rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
810 rdev->lldi.vr->rq.size,
811 rdev->lldi.vr->qp.start,
812 rdev->lldi.vr->qp.size,
813 rdev->lldi.vr->cq.start,
814 rdev->lldi.vr->cq.size);
815 pr_debug("udb %pR db_reg %p gts_reg %p qpmask 0x%x cqmask 0x%x\n",
816 &rdev->lldi.pdev->resource[2],
817 rdev->lldi.db_reg, rdev->lldi.gts_reg,
818 rdev->qpmask, rdev->cqmask);
cfdda9d7 819
4275a5b2
H
820 if (c4iw_num_stags(rdev) == 0)
821 return -EINVAL;
cfdda9d7 822
8d81ef34
VP
823 rdev->stats.pd.total = T4_MAX_NUM_PD;
824 rdev->stats.stag.total = rdev->lldi.vr->stag.size;
825 rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
826 rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
827 rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
828 rdev->stats.qid.total = rdev->lldi.vr->qp.size;
829
cfdda9d7
SW
830 err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
831 if (err) {
700456bd 832 pr_err("error %d initializing resources\n", err);
4275a5b2 833 return err;
cfdda9d7
SW
834 }
835 err = c4iw_pblpool_create(rdev);
836 if (err) {
700456bd 837 pr_err("error %d initializing pbl pool\n", err);
4275a5b2 838 goto destroy_resource;
cfdda9d7
SW
839 }
840 err = c4iw_rqtpool_create(rdev);
841 if (err) {
700456bd 842 pr_err("error %d initializing rqt pool\n", err);
4275a5b2 843 goto destroy_pblpool;
cfdda9d7 844 }
c6d7b267
SW
845 err = c4iw_ocqp_pool_create(rdev);
846 if (err) {
700456bd 847 pr_err("error %d initializing ocqp pool\n", err);
4275a5b2 848 goto destroy_rqtpool;
c6d7b267 849 }
05eb2389
SW
850 rdev->status_page = (struct t4_dev_status_page *)
851 __get_free_page(GFP_KERNEL);
15f7e3c2
WY
852 if (!rdev->status_page) {
853 err = -ENOMEM;
82b1df1b 854 goto destroy_ocqp_pool;
15f7e3c2 855 }
c5dfb000
H
856 rdev->status_page->qp_start = rdev->lldi.vr->qp.start;
857 rdev->status_page->qp_size = rdev->lldi.vr->qp.size;
858 rdev->status_page->cq_start = rdev->lldi.vr->cq.start;
859 rdev->status_page->cq_size = rdev->lldi.vr->cq.size;
8fd90bb8 860
7730b4c7
HS
861 if (c4iw_wr_log) {
862 rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) *
863 sizeof(*rdev->wr_log), GFP_KERNEL);
864 if (rdev->wr_log) {
865 rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
866 atomic_set(&rdev->wr_log_idx, 0);
7730b4c7
HS
867 }
868 }
8fd90bb8 869
c12a67fe
SW
870 rdev->free_workq = create_singlethread_workqueue("iw_cxgb4_free");
871 if (!rdev->free_workq) {
872 err = -ENOMEM;
d4702645 873 goto err_free_status_page_and_wr_log;
c12a67fe
SW
874 }
875
6b54d54d 876 rdev->status_page->db_off = 0;
8fd90bb8 877
26bff1bd
RR
878 init_completion(&rdev->rqt_compl);
879 init_completion(&rdev->pbl_compl);
880 kref_init(&rdev->rqt_kref);
881 kref_init(&rdev->pbl_kref);
882
cfdda9d7 883 return 0;
d4702645
RR
884err_free_status_page_and_wr_log:
885 if (c4iw_wr_log && rdev->wr_log)
886 kfree(rdev->wr_log);
c12a67fe 887 free_page((unsigned long)rdev->status_page);
82b1df1b
H
888destroy_ocqp_pool:
889 c4iw_ocqp_pool_destroy(rdev);
4275a5b2 890destroy_rqtpool:
c6d7b267 891 c4iw_rqtpool_destroy(rdev);
4275a5b2 892destroy_pblpool:
cfdda9d7 893 c4iw_pblpool_destroy(rdev);
4275a5b2 894destroy_resource:
cfdda9d7 895 c4iw_destroy_resource(&rdev->resource);
cfdda9d7
SW
896 return err;
897}
898
899static void c4iw_rdev_close(struct c4iw_rdev *rdev)
900{
7730b4c7 901 kfree(rdev->wr_log);
d4702645 902 c4iw_release_dev_ucontext(rdev, &rdev->uctx);
05eb2389 903 free_page((unsigned long)rdev->status_page);
cfdda9d7
SW
904 c4iw_pblpool_destroy(rdev);
905 c4iw_rqtpool_destroy(rdev);
26bff1bd
RR
906 wait_for_completion(&rdev->pbl_compl);
907 wait_for_completion(&rdev->rqt_compl);
d4702645 908 c4iw_ocqp_pool_destroy(rdev);
26bff1bd 909 destroy_workqueue(rdev->free_workq);
cfdda9d7
SW
910 c4iw_destroy_resource(&rdev->resource);
911}
912
1c8f1da5 913void c4iw_dealloc(struct uld_ctx *ctx)
cfdda9d7 914{
2f25e9a5 915 c4iw_rdev_close(&ctx->dev->rdev);
37eb816c 916 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->cqidr));
2f25e9a5 917 idr_destroy(&ctx->dev->cqidr);
37eb816c 918 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->qpidr));
2f25e9a5 919 idr_destroy(&ctx->dev->qpidr);
37eb816c 920 WARN_ON_ONCE(!idr_is_empty(&ctx->dev->mmidr));
2f25e9a5 921 idr_destroy(&ctx->dev->mmidr);
37eb816c 922 wait_event(ctx->dev->wait, idr_is_empty(&ctx->dev->hwtid_idr));
793dad94
VP
923 idr_destroy(&ctx->dev->hwtid_idr);
924 idr_destroy(&ctx->dev->stid_idr);
925 idr_destroy(&ctx->dev->atid_idr);
fa658a98
SW
926 if (ctx->dev->rdev.bar2_kva)
927 iounmap(ctx->dev->rdev.bar2_kva);
928 if (ctx->dev->rdev.oc_mw_kva)
929 iounmap(ctx->dev->rdev.oc_mw_kva);
2f25e9a5
SW
930 ib_dealloc_device(&ctx->dev->ibdev);
931 ctx->dev = NULL;
cfdda9d7
SW
932}
933
9efe10a1
SW
934static void c4iw_remove(struct uld_ctx *ctx)
935{
548ddb19 936 pr_debug("c4iw_dev %p\n", ctx->dev);
9efe10a1
SW
937 c4iw_unregister_device(ctx->dev);
938 c4iw_dealloc(ctx);
939}
940
941static int rdma_supported(const struct cxgb4_lld_info *infop)
942{
943 return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
944 infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
f079af7a 945 infop->vr->cq.size > 0;
9efe10a1
SW
946}
947
cfdda9d7
SW
948static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
949{
950 struct c4iw_dev *devp;
951 int ret;
952
9efe10a1 953 if (!rdma_supported(infop)) {
700456bd
JP
954 pr_info("%s: RDMA not supported on this device\n",
955 pci_name(infop->pdev));
9efe10a1
SW
956 return ERR_PTR(-ENOSYS);
957 }
f079af7a 958 if (!ocqp_supported(infop))
700456bd 959 pr_info("%s: On-Chip Queues not supported on this device\n",
f079af7a 960 pci_name(infop->pdev));
80ccdd60 961
cfdda9d7
SW
962 devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
963 if (!devp) {
700456bd 964 pr_err("Cannot allocate ib device\n");
bbe9a0a2 965 return ERR_PTR(-ENOMEM);
cfdda9d7
SW
966 }
967 devp->rdev.lldi = *infop;
968
04e10e21 969 /* init various hw-queue params based on lld info */
548ddb19
BP
970 pr_debug("Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
971 devp->rdev.lldi.sge_ingpadboundary,
a9a42886 972 devp->rdev.lldi.sge_egrstatuspagesize);
04e10e21
HS
973
974 devp->rdev.hw_queue.t4_eq_status_entries =
4bbfabed 975 devp->rdev.lldi.sge_egrstatuspagesize / 64;
66eb19af
HS
976 devp->rdev.hw_queue.t4_max_eq_size = 65520;
977 devp->rdev.hw_queue.t4_max_iq_size = 65520;
978 devp->rdev.hw_queue.t4_max_rq_size = 8192 -
979 devp->rdev.hw_queue.t4_eq_status_entries - 1;
04e10e21 980 devp->rdev.hw_queue.t4_max_sq_size =
66eb19af
HS
981 devp->rdev.hw_queue.t4_max_eq_size -
982 devp->rdev.hw_queue.t4_eq_status_entries - 1;
04e10e21 983 devp->rdev.hw_queue.t4_max_qp_depth =
66eb19af 984 devp->rdev.hw_queue.t4_max_rq_size;
04e10e21 985 devp->rdev.hw_queue.t4_max_cq_depth =
66eb19af 986 devp->rdev.hw_queue.t4_max_iq_size - 2;
04e10e21
HS
987 devp->rdev.hw_queue.t4_stat_len =
988 devp->rdev.lldi.sge_egrstatuspagesize;
989
fa658a98 990 /*
963cab50 991 * For T5/T6 devices, we map all of BAR2 with WC.
fa658a98
SW
992 * For T4 devices with onchip qp mem, we map only that part
993 * of BAR2 with WC.
994 */
995 devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
963cab50 996 if (!is_t4(devp->rdev.lldi.adapter_type)) {
fa658a98
SW
997 devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
998 pci_resource_len(devp->rdev.lldi.pdev, 2));
999 if (!devp->rdev.bar2_kva) {
700456bd 1000 pr_err("Unable to ioremap BAR2\n");
65b302ad 1001 ib_dealloc_device(&devp->ibdev);
fa658a98
SW
1002 return ERR_PTR(-EINVAL);
1003 }
1004 } else if (ocqp_supported(infop)) {
1005 devp->rdev.oc_mw_pa =
1006 pci_resource_start(devp->rdev.lldi.pdev, 2) +
1007 pci_resource_len(devp->rdev.lldi.pdev, 2) -
1008 roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
1009 devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
1010 devp->rdev.lldi.vr->ocq.size);
1011 if (!devp->rdev.oc_mw_kva) {
700456bd 1012 pr_err("Unable to ioremap onchip mem\n");
65b302ad 1013 ib_dealloc_device(&devp->ibdev);
fa658a98
SW
1014 return ERR_PTR(-EINVAL);
1015 }
1016 }
c6d7b267 1017
a9a42886
JP
1018 pr_debug("ocq memory: hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
1019 devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
1020 devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
c6d7b267 1021
cfdda9d7
SW
1022 ret = c4iw_rdev_open(&devp->rdev);
1023 if (ret) {
700456bd 1024 pr_err("Unable to open CXIO rdev err %d\n", ret);
cfdda9d7 1025 ib_dealloc_device(&devp->ibdev);
bbe9a0a2 1026 return ERR_PTR(ret);
cfdda9d7
SW
1027 }
1028
1029 idr_init(&devp->cqidr);
1030 idr_init(&devp->qpidr);
1031 idr_init(&devp->mmidr);
793dad94
VP
1032 idr_init(&devp->hwtid_idr);
1033 idr_init(&devp->stid_idr);
1034 idr_init(&devp->atid_idr);
cfdda9d7 1035 spin_lock_init(&devp->lock);
8d81ef34 1036 mutex_init(&devp->rdev.stats.lock);
2c974781 1037 mutex_init(&devp->db_mutex);
05eb2389 1038 INIT_LIST_HEAD(&devp->db_fc_list);
37eb816c 1039 init_waitqueue_head(&devp->wait);
4c2c5763 1040 devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
cfdda9d7 1041
cfdda9d7
SW
1042 if (c4iw_debugfs_root) {
1043 devp->debugfs_root = debugfs_create_dir(
1044 pci_name(devp->rdev.lldi.pdev),
1045 c4iw_debugfs_root);
1046 setup_debugfs(devp);
1047 }
9eccfe10 1048
9eccfe10 1049
cfdda9d7
SW
1050 return devp;
1051}
1052
1053static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
1054{
2f25e9a5 1055 struct uld_ctx *ctx;
cfdda9d7
SW
1056 static int vers_printed;
1057 int i;
1058
1059 if (!vers_printed++)
f079af7a
VP
1060 pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
1061 DRV_VERSION);
cfdda9d7 1062
2f25e9a5
SW
1063 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1064 if (!ctx) {
1065 ctx = ERR_PTR(-ENOMEM);
cfdda9d7 1066 goto out;
2f25e9a5
SW
1067 }
1068 ctx->lldi = *infop;
cfdda9d7 1069
548ddb19
BP
1070 pr_debug("found device %s nchan %u nrxq %u ntxq %u nports %u\n",
1071 pci_name(ctx->lldi.pdev),
a9a42886
JP
1072 ctx->lldi.nchan, ctx->lldi.nrxq,
1073 ctx->lldi.ntxq, ctx->lldi.nports);
2f25e9a5
SW
1074
1075 mutex_lock(&dev_mutex);
1076 list_add_tail(&ctx->entry, &uld_ctx_list);
1077 mutex_unlock(&dev_mutex);
cfdda9d7 1078
2f25e9a5 1079 for (i = 0; i < ctx->lldi.nrxq; i++)
a9a42886 1080 pr_debug("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
cfdda9d7 1081out:
2f25e9a5 1082 return ctx;
cfdda9d7
SW
1083}
1084
1cab775c
VP
1085static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
1086 const __be64 *rsp,
1087 u32 pktshift)
1088{
1089 struct sk_buff *skb;
1090
1091 /*
1092 * Allocate space for cpl_pass_accept_req which will be synthesized by
1093 * driver. Once the driver synthesizes the request the skb will go
1094 * through the regular cpl_pass_accept_req processing.
1095 * The math here assumes sizeof cpl_pass_accept_req >= sizeof
1096 * cpl_rx_pkt.
1097 */
1098 skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
1099 sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
1100 if (unlikely(!skb))
1101 return NULL;
1102
70d72568
BVA
1103 __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
1104 sizeof(struct rss_header) - pktshift);
1cab775c
VP
1105
1106 /*
1107 * This skb will contain:
1108 * rss_header from the rspq descriptor (1 flit)
1109 * cpl_rx_pkt struct from the rspq descriptor (2 flits)
1110 * space for the difference between the size of an
1111 * rx_pkt and pass_accept_req cpl (1 flit)
1112 * the packet data from the gl
1113 */
1114 skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
1115 sizeof(struct rss_header));
1116 skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
1117 sizeof(struct cpl_pass_accept_req),
1118 gl->va + pktshift,
1119 gl->tot_len - pktshift);
1120 return skb;
1121}
1122
1123static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
1124 const __be64 *rsp)
1125{
1126 unsigned int opcode = *(u8 *)rsp;
1127 struct sk_buff *skb;
1128
1129 if (opcode != CPL_RX_PKT)
1130 goto out;
1131
1132 skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
1133 if (skb == NULL)
1134 goto out;
1135
1136 if (c4iw_handlers[opcode] == NULL) {
700456bd 1137 pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
1cab775c
VP
1138 kfree_skb(skb);
1139 goto out;
1140 }
1141 c4iw_handlers[opcode](dev, skb);
1142 return 1;
1143out:
1144 return 0;
1145}
1146
cfdda9d7
SW
1147static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
1148 const struct pkt_gl *gl)
1149{
2f25e9a5
SW
1150 struct uld_ctx *ctx = handle;
1151 struct c4iw_dev *dev = ctx->dev;
cfdda9d7 1152 struct sk_buff *skb;
1cab775c 1153 u8 opcode;
cfdda9d7
SW
1154
1155 if (gl == NULL) {
1156 /* omit RSS and rsp_ctrl at end of descriptor */
1157 unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
1158
1159 skb = alloc_skb(256, GFP_ATOMIC);
1160 if (!skb)
1161 goto nomem;
1162 __skb_put(skb, len);
1163 skb_copy_to_linear_data(skb, &rsp[1], len);
1164 } else if (gl == CXGB4_MSG_AN) {
1165 const struct rsp_ctrl *rc = (void *)rsp;
1166
1167 u32 qid = be32_to_cpu(rc->pldbuflen_qid);
1168 c4iw_ev_handler(dev, qid);
1cab775c
VP
1169 return 0;
1170 } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
1171 if (recv_rx_pkt(dev, gl, rsp))
1172 return 0;
1173
700456bd
JP
1174 pr_info("%s: unexpected FL contents at %p, RSS %#llx, FL %#llx, len %u\n",
1175 pci_name(ctx->lldi.pdev), gl->va,
1176 be64_to_cpu(*rsp),
1177 be64_to_cpu(*(__force __be64 *)gl->va),
1178 gl->tot_len);
1cab775c 1179
cfdda9d7
SW
1180 return 0;
1181 } else {
da411ba1 1182 skb = cxgb4_pktgl_to_skb(gl, 128, 128);
cfdda9d7
SW
1183 if (unlikely(!skb))
1184 goto nomem;
1185 }
1186
1cab775c 1187 opcode = *(u8 *)rsp;
dbb084cc 1188 if (c4iw_handlers[opcode]) {
cfdda9d7 1189 c4iw_handlers[opcode](dev, skb);
dbb084cc 1190 } else {
700456bd 1191 pr_info("%s no handler opcode 0x%x...\n", __func__, opcode);
dbb084cc
SW
1192 kfree_skb(skb);
1193 }
cfdda9d7
SW
1194
1195 return 0;
1196nomem:
1197 return -1;
1198}
1199
1200static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
1201{
2f25e9a5 1202 struct uld_ctx *ctx = handle;
1c01c538 1203
548ddb19 1204 pr_debug("new_state %u\n", new_state);
1c01c538
SW
1205 switch (new_state) {
1206 case CXGB4_STATE_UP:
700456bd 1207 pr_info("%s: Up\n", pci_name(ctx->lldi.pdev));
2f25e9a5 1208 if (!ctx->dev) {
2f25e9a5 1209 ctx->dev = c4iw_alloc(&ctx->lldi);
9efe10a1 1210 if (IS_ERR(ctx->dev)) {
700456bd 1211 pr_err("%s: initialization failed: %ld\n",
9efe10a1
SW
1212 pci_name(ctx->lldi.pdev),
1213 PTR_ERR(ctx->dev));
1214 ctx->dev = NULL;
1215 break;
1216 }
1c8f1da5
BP
1217
1218 INIT_WORK(&ctx->reg_work, c4iw_register_device);
1219 queue_work(reg_workq, &ctx->reg_work);
1c01c538
SW
1220 }
1221 break;
1222 case CXGB4_STATE_DOWN:
700456bd 1223 pr_info("%s: Down\n", pci_name(ctx->lldi.pdev));
2f25e9a5
SW
1224 if (ctx->dev)
1225 c4iw_remove(ctx);
1c01c538 1226 break;
8b7372c1 1227 case CXGB4_STATE_FATAL_ERROR:
1c01c538 1228 case CXGB4_STATE_START_RECOVERY:
700456bd 1229 pr_info("%s: Fatal Error\n", pci_name(ctx->lldi.pdev));
2f25e9a5 1230 if (ctx->dev) {
767fbe81
SW
1231 struct ib_event event;
1232
2f25e9a5 1233 ctx->dev->rdev.flags |= T4_FATAL_ERROR;
767fbe81
SW
1234 memset(&event, 0, sizeof event);
1235 event.event = IB_EVENT_DEVICE_FATAL;
2f25e9a5 1236 event.device = &ctx->dev->ibdev;
767fbe81 1237 ib_dispatch_event(&event);
2f25e9a5 1238 c4iw_remove(ctx);
767fbe81 1239 }
1c01c538
SW
1240 break;
1241 case CXGB4_STATE_DETACH:
700456bd 1242 pr_info("%s: Detach\n", pci_name(ctx->lldi.pdev));
2f25e9a5
SW
1243 if (ctx->dev)
1244 c4iw_remove(ctx);
1c01c538
SW
1245 break;
1246 }
cfdda9d7
SW
1247 return 0;
1248}
1249
2c974781
VP
1250static int disable_qp_db(int id, void *p, void *data)
1251{
1252 struct c4iw_qp *qp = p;
1253
1254 t4_disable_wq_db(&qp->wq);
1255 return 0;
1256}
1257
1258static void stop_queues(struct uld_ctx *ctx)
1259{
05eb2389
SW
1260 unsigned long flags;
1261
1262 spin_lock_irqsave(&ctx->dev->lock, flags);
1263 ctx->dev->rdev.stats.db_state_transitions++;
1264 ctx->dev->db_state = STOPPED;
1265 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
422eea0a 1266 idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
05eb2389
SW
1267 else
1268 ctx->dev->rdev.status_page->db_off = 1;
1269 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2c974781
VP
1270}
1271
1272static int enable_qp_db(int id, void *p, void *data)
1273{
1274 struct c4iw_qp *qp = p;
1275
1276 t4_enable_wq_db(&qp->wq);
1277 return 0;
1278}
1279
05eb2389
SW
1280static void resume_rc_qp(struct c4iw_qp *qp)
1281{
1282 spin_lock(&qp->lock);
963cab50 1283 t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc, NULL);
05eb2389 1284 qp->wq.sq.wq_pidx_inc = 0;
963cab50 1285 t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc, NULL);
05eb2389
SW
1286 qp->wq.rq.wq_pidx_inc = 0;
1287 spin_unlock(&qp->lock);
1288}
1289
1290static void resume_a_chunk(struct uld_ctx *ctx)
1291{
1292 int i;
1293 struct c4iw_qp *qp;
1294
1295 for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
1296 qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
1297 db_fc_entry);
1298 list_del_init(&qp->db_fc_entry);
1299 resume_rc_qp(qp);
1300 if (list_empty(&ctx->dev->db_fc_list))
1301 break;
1302 }
1303}
1304
2c974781
VP
1305static void resume_queues(struct uld_ctx *ctx)
1306{
1307 spin_lock_irq(&ctx->dev->lock);
05eb2389
SW
1308 if (ctx->dev->db_state != STOPPED)
1309 goto out;
1310 ctx->dev->db_state = FLOW_CONTROL;
1311 while (1) {
1312 if (list_empty(&ctx->dev->db_fc_list)) {
1313 WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
1314 ctx->dev->db_state = NORMAL;
1315 ctx->dev->rdev.stats.db_state_transitions++;
1316 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
1317 idr_for_each(&ctx->dev->qpidr, enable_qp_db,
1318 NULL);
1319 } else {
1320 ctx->dev->rdev.status_page->db_off = 0;
1321 }
1322 break;
1323 } else {
1324 if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
1325 < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
1326 DB_FC_DRAIN_THRESH)) {
1327 resume_a_chunk(ctx);
1328 }
1329 if (!list_empty(&ctx->dev->db_fc_list)) {
1330 spin_unlock_irq(&ctx->dev->lock);
1331 if (DB_FC_RESUME_DELAY) {
1332 set_current_state(TASK_UNINTERRUPTIBLE);
1333 schedule_timeout(DB_FC_RESUME_DELAY);
1334 }
1335 spin_lock_irq(&ctx->dev->lock);
1336 if (ctx->dev->db_state != FLOW_CONTROL)
1337 break;
1338 }
1339 }
422eea0a 1340 }
05eb2389
SW
1341out:
1342 if (ctx->dev->db_state != NORMAL)
1343 ctx->dev->rdev.stats.db_fc_interruptions++;
422eea0a
VP
1344 spin_unlock_irq(&ctx->dev->lock);
1345}
1346
1347struct qp_list {
1348 unsigned idx;
1349 struct c4iw_qp **qps;
1350};
1351
1352static int add_and_ref_qp(int id, void *p, void *data)
1353{
1354 struct qp_list *qp_listp = data;
1355 struct c4iw_qp *qp = p;
1356
1357 c4iw_qp_add_ref(&qp->ibqp);
1358 qp_listp->qps[qp_listp->idx++] = qp;
1359 return 0;
1360}
1361
1362static int count_qps(int id, void *p, void *data)
1363{
1364 unsigned *countp = data;
1365 (*countp)++;
1366 return 0;
1367}
1368
05eb2389 1369static void deref_qps(struct qp_list *qp_list)
422eea0a
VP
1370{
1371 int idx;
1372
05eb2389
SW
1373 for (idx = 0; idx < qp_list->idx; idx++)
1374 c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
422eea0a
VP
1375}
1376
1377static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
1378{
1379 int idx;
1380 int ret;
1381
1382 for (idx = 0; idx < qp_list->idx; idx++) {
1383 struct c4iw_qp *qp = qp_list->qps[idx];
1384
05eb2389
SW
1385 spin_lock_irq(&qp->rhp->lock);
1386 spin_lock(&qp->lock);
422eea0a
VP
1387 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
1388 qp->wq.sq.qid,
1389 t4_sq_host_wq_pidx(&qp->wq),
1390 t4_sq_wq_size(&qp->wq));
1391 if (ret) {
700456bd 1392 pr_err("%s: Fatal error - DB overflow recovery failed - error syncing SQ qid %u\n",
422eea0a 1393 pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
05eb2389
SW
1394 spin_unlock(&qp->lock);
1395 spin_unlock_irq(&qp->rhp->lock);
422eea0a
VP
1396 return;
1397 }
05eb2389 1398 qp->wq.sq.wq_pidx_inc = 0;
422eea0a
VP
1399
1400 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
1401 qp->wq.rq.qid,
1402 t4_rq_host_wq_pidx(&qp->wq),
1403 t4_rq_wq_size(&qp->wq));
1404
1405 if (ret) {
700456bd 1406 pr_err("%s: Fatal error - DB overflow recovery failed - error syncing RQ qid %u\n",
422eea0a 1407 pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
05eb2389
SW
1408 spin_unlock(&qp->lock);
1409 spin_unlock_irq(&qp->rhp->lock);
422eea0a
VP
1410 return;
1411 }
05eb2389
SW
1412 qp->wq.rq.wq_pidx_inc = 0;
1413 spin_unlock(&qp->lock);
1414 spin_unlock_irq(&qp->rhp->lock);
422eea0a
VP
1415
1416 /* Wait for the dbfifo to drain */
1417 while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
1418 set_current_state(TASK_UNINTERRUPTIBLE);
1419 schedule_timeout(usecs_to_jiffies(10));
1420 }
1421 }
1422}
1423
1424static void recover_queues(struct uld_ctx *ctx)
1425{
1426 int count = 0;
1427 struct qp_list qp_list;
1428 int ret;
1429
422eea0a
VP
1430 /* slow everybody down */
1431 set_current_state(TASK_UNINTERRUPTIBLE);
1432 schedule_timeout(usecs_to_jiffies(1000));
1433
422eea0a
VP
1434 /* flush the SGE contexts */
1435 ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
1436 if (ret) {
700456bd 1437 pr_err("%s: Fatal error - DB overflow recovery failed\n",
422eea0a 1438 pci_name(ctx->lldi.pdev));
05eb2389 1439 return;
422eea0a
VP
1440 }
1441
1442 /* Count active queues so we can build a list of queues to recover */
1443 spin_lock_irq(&ctx->dev->lock);
05eb2389
SW
1444 WARN_ON(ctx->dev->db_state != STOPPED);
1445 ctx->dev->db_state = RECOVERY;
422eea0a
VP
1446 idr_for_each(&ctx->dev->qpidr, count_qps, &count);
1447
1448 qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
1449 if (!qp_list.qps) {
422eea0a 1450 spin_unlock_irq(&ctx->dev->lock);
05eb2389 1451 return;
422eea0a
VP
1452 }
1453 qp_list.idx = 0;
1454
1455 /* add and ref each qp so it doesn't get freed */
1456 idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
1457
2c974781 1458 spin_unlock_irq(&ctx->dev->lock);
422eea0a
VP
1459
1460 /* now traverse the list in a safe context to recover the db state*/
1461 recover_lost_dbs(ctx, &qp_list);
1462
1463 /* we're almost done! deref the qps and clean up */
05eb2389 1464 deref_qps(&qp_list);
422eea0a
VP
1465 kfree(qp_list.qps);
1466
422eea0a 1467 spin_lock_irq(&ctx->dev->lock);
05eb2389
SW
1468 WARN_ON(ctx->dev->db_state != RECOVERY);
1469 ctx->dev->db_state = STOPPED;
422eea0a 1470 spin_unlock_irq(&ctx->dev->lock);
2c974781
VP
1471}
1472
1473static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
1474{
1475 struct uld_ctx *ctx = handle;
1476
1477 switch (control) {
1478 case CXGB4_CONTROL_DB_FULL:
1479 stop_queues(ctx);
2c974781 1480 ctx->dev->rdev.stats.db_full++;
2c974781
VP
1481 break;
1482 case CXGB4_CONTROL_DB_EMPTY:
1483 resume_queues(ctx);
1484 mutex_lock(&ctx->dev->rdev.stats.lock);
1485 ctx->dev->rdev.stats.db_empty++;
1486 mutex_unlock(&ctx->dev->rdev.stats.lock);
1487 break;
1488 case CXGB4_CONTROL_DB_DROP:
422eea0a 1489 recover_queues(ctx);
2c974781
VP
1490 mutex_lock(&ctx->dev->rdev.stats.lock);
1491 ctx->dev->rdev.stats.db_drop++;
1492 mutex_unlock(&ctx->dev->rdev.stats.lock);
1493 break;
1494 default:
700456bd
JP
1495 pr_warn("%s: unknown control cmd %u\n",
1496 pci_name(ctx->lldi.pdev), control);
2c974781
VP
1497 break;
1498 }
1499 return 0;
1500}
1501
cfdda9d7
SW
1502static struct cxgb4_uld_info c4iw_uld_info = {
1503 .name = DRV_NAME,
0fbc81b3 1504 .nrxq = MAX_ULD_QSETS,
ab677ff4 1505 .ntxq = MAX_ULD_QSETS,
0fbc81b3
HS
1506 .rxq_size = 511,
1507 .ciq = true,
1508 .lro = false,
cfdda9d7
SW
1509 .add = c4iw_uld_add,
1510 .rx_handler = c4iw_uld_rx_handler,
1511 .state_change = c4iw_uld_state_change,
2c974781 1512 .control = c4iw_uld_control,
cfdda9d7
SW
1513};
1514
2015f26c
SW
1515void _c4iw_free_wr_wait(struct kref *kref)
1516{
1517 struct c4iw_wr_wait *wr_waitp;
1518
1519 wr_waitp = container_of(kref, struct c4iw_wr_wait, kref);
1520 pr_debug("Free wr_wait %p\n", wr_waitp);
1521 kfree(wr_waitp);
1522}
1523
1524struct c4iw_wr_wait *c4iw_alloc_wr_wait(gfp_t gfp)
1525{
1526 struct c4iw_wr_wait *wr_waitp;
1527
1528 wr_waitp = kzalloc(sizeof(*wr_waitp), gfp);
1529 if (wr_waitp) {
1530 kref_init(&wr_waitp->kref);
1531 pr_debug("wr_wait %p\n", wr_waitp);
1532 }
1533 return wr_waitp;
1534}
1535
cfdda9d7
SW
1536static int __init c4iw_init_module(void)
1537{
1538 int err;
1539
1540 err = c4iw_cm_init();
1541 if (err)
1542 return err;
1543
1544 c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
1545 if (!c4iw_debugfs_root)
700456bd 1546 pr_warn("could not create debugfs entry, continuing\n");
cfdda9d7 1547
1c8f1da5
BP
1548 reg_workq = create_singlethread_workqueue("Register_iWARP_device");
1549 if (!reg_workq) {
1550 pr_err("Failed creating workqueue to register iwarp device\n");
1551 return -ENOMEM;
1552 }
1553
cfdda9d7
SW
1554 cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
1555
1556 return 0;
1557}
1558
1559static void __exit c4iw_exit_module(void)
1560{
2f25e9a5 1561 struct uld_ctx *ctx, *tmp;
cfdda9d7 1562
cfdda9d7 1563 mutex_lock(&dev_mutex);
2f25e9a5
SW
1564 list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
1565 if (ctx->dev)
1566 c4iw_remove(ctx);
1567 kfree(ctx);
cfdda9d7
SW
1568 }
1569 mutex_unlock(&dev_mutex);
1c8f1da5
BP
1570 flush_workqueue(reg_workq);
1571 destroy_workqueue(reg_workq);
fd388ce6 1572 cxgb4_unregister_uld(CXGB4_ULD_RDMA);
cfdda9d7
SW
1573 c4iw_cm_term();
1574 debugfs_remove_recursive(c4iw_debugfs_root);
1575}
1576
1577module_init(c4iw_init_module);
1578module_exit(c4iw_exit_module);