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iw_cxgb4: Cleanup register defines/MACROS
[linux-2.6-block.git] / drivers / infiniband / hw / cxgb4 / device.c
CommitLineData
cfdda9d7
SW		 1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/debugfs.h>
e572568f 35#include <linux/vmalloc.h>
da388973 36#include <linux/math64.h>
cfdda9d7
SW		 37
38#include <rdma/ib_verbs.h>
39
40#include "iw_cxgb4.h"
41
42#define DRV_VERSION "0.1"
43
44MODULE_AUTHOR("Steve Wise");
f079af7a 45MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
cfdda9d7
SW		 46MODULE_LICENSE("Dual BSD/GPL");
47MODULE_VERSION(DRV_VERSION);
48
80ccdd60
VP		 49static int allow_db_fc_on_t5;
50module_param(allow_db_fc_on_t5, int, 0644);
51MODULE_PARM_DESC(allow_db_fc_on_t5,
52 "Allow DB Flow Control on T5 (default = 0)");
53
54static int allow_db_coalescing_on_t5;
55module_param(allow_db_coalescing_on_t5, int, 0644);
56MODULE_PARM_DESC(allow_db_coalescing_on_t5,
57 "Allow DB Coalescing on T5 (default = 0)");
58
7730b4c7
HS		 59int c4iw_wr_log = 0;
60module_param(c4iw_wr_log, int, 0444);
61MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
62
65d4c01a 63static int c4iw_wr_log_size_order = 12;
7730b4c7
HS		 64module_param(c4iw_wr_log_size_order, int, 0444);
65MODULE_PARM_DESC(c4iw_wr_log_size_order,
66 "Number of entries (log2) in the work request timing log.");
67
2c974781
VP		 68struct uld_ctx {
69 struct list_head entry;
70 struct cxgb4_lld_info lldi;
71 struct c4iw_dev *dev;
72};
73
2f25e9a5 74static LIST_HEAD(uld_ctx_list);
cfdda9d7
SW		 75static DEFINE_MUTEX(dev_mutex);
76
05eb2389
SW		 77#define DB_FC_RESUME_SIZE 64
78#define DB_FC_RESUME_DELAY 1
79#define DB_FC_DRAIN_THRESH 0
80
cfdda9d7
SW		 81static struct dentry *c4iw_debugfs_root;
82
9e8d1fa3 83struct c4iw_debugfs_data {
cfdda9d7
SW		 84 struct c4iw_dev *devp;
85 char *buf;
86 int bufsize;
87 int pos;
88};
89
9eccfe10
SW		 90/* registered cxgb4 netlink callbacks */
91static struct ibnl_client_cbs c4iw_nl_cb_table[] = {
92 [RDMA_NL_IWPM_REG_PID] = {.dump = iwpm_register_pid_cb},
93 [RDMA_NL_IWPM_ADD_MAPPING] = {.dump = iwpm_add_mapping_cb},
94 [RDMA_NL_IWPM_QUERY_MAPPING] = {.dump = iwpm_add_and_query_mapping_cb},
95 [RDMA_NL_IWPM_HANDLE_ERR] = {.dump = iwpm_mapping_error_cb},
96 [RDMA_NL_IWPM_MAPINFO] = {.dump = iwpm_mapping_info_cb},
97 [RDMA_NL_IWPM_MAPINFO_NUM] = {.dump = iwpm_ack_mapping_info_cb}
98};
99
9e8d1fa3 100static int count_idrs(int id, void *p, void *data)
cfdda9d7 101{
cfdda9d7
SW		 102 int *countp = data;
103
cfdda9d7
SW		 104 *countp = *countp + 1;
105 return 0;
106}
107
9e8d1fa3
SW		 108static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
109 loff_t *ppos)
110{
111 struct c4iw_debugfs_data *d = file->private_data;
9e8d1fa3 112
3160977a 113 return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
9e8d1fa3
SW		 114}
115
7730b4c7
HS		 116void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
117{
118 struct wr_log_entry le;
119 int idx;
120
121 if (!wq->rdev->wr_log)
122 return;
123
124 idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
125 (wq->rdev->wr_log_size - 1);
126 le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
127 getnstimeofday(&le.poll_host_ts);
128 le.valid = 1;
129 le.cqe_sge_ts = CQE_TS(cqe);
130 if (SQ_TYPE(cqe)) {
131 le.qid = wq->sq.qid;
132 le.opcode = CQE_OPCODE(cqe);
133 le.post_host_ts = wq->sq.sw_sq[wq->sq.cidx].host_ts;
134 le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
135 le.wr_id = CQE_WRID_SQ_IDX(cqe);
136 } else {
137 le.qid = wq->rq.qid;
138 le.opcode = FW_RI_RECEIVE;
139 le.post_host_ts = wq->rq.sw_rq[wq->rq.cidx].host_ts;
140 le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
141 le.wr_id = CQE_WRID_MSN(cqe);
142 }
143 wq->rdev->wr_log[idx] = le;
144}
145
146static int wr_log_show(struct seq_file *seq, void *v)
147{
148 struct c4iw_dev *dev = seq->private;
149 struct timespec prev_ts = {0, 0};
150 struct wr_log_entry *lep;
151 int prev_ts_set = 0;
152 int idx, end;
153
da388973 154#define ts2ns(ts) div64_ul((ts) * dev->rdev.lldi.cclk_ps, 1000)
7730b4c7
HS		 155
156 idx = atomic_read(&dev->rdev.wr_log_idx) &
157 (dev->rdev.wr_log_size - 1);
158 end = idx - 1;
159 if (end < 0)
160 end = dev->rdev.wr_log_size - 1;
161 lep = &dev->rdev.wr_log[idx];
162 while (idx != end) {
163 if (lep->valid) {
164 if (!prev_ts_set) {
165 prev_ts_set = 1;
166 prev_ts = lep->poll_host_ts;
167 }
168 seq_printf(seq, "%04u: sec %lu nsec %lu qid %u opcode "
169 "%u %s 0x%x host_wr_delta sec %lu nsec %lu "
170 "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
171 "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
172 "cqe_poll_delta_ns %llu\n",
173 idx,
174 timespec_sub(lep->poll_host_ts,
175 prev_ts).tv_sec,
176 timespec_sub(lep->poll_host_ts,
177 prev_ts).tv_nsec,
178 lep->qid, lep->opcode,
179 lep->opcode == FW_RI_RECEIVE ?
180 "msn" : "wrid",
181 lep->wr_id,
182 timespec_sub(lep->poll_host_ts,
183 lep->post_host_ts).tv_sec,
184 timespec_sub(lep->poll_host_ts,
185 lep->post_host_ts).tv_nsec,
186 lep->post_sge_ts, lep->cqe_sge_ts,
187 lep->poll_sge_ts,
188 ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
189 ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
190 prev_ts = lep->poll_host_ts;
191 }
192 idx++;
193 if (idx > (dev->rdev.wr_log_size - 1))
194 idx = 0;
195 lep = &dev->rdev.wr_log[idx];
196 }
197#undef ts2ns
198 return 0;
199}
200
201static int wr_log_open(struct inode *inode, struct file *file)
202{
203 return single_open(file, wr_log_show, inode->i_private);
204}
205
206static ssize_t wr_log_clear(struct file *file, const char __user *buf,
207 size_t count, loff_t *pos)
208{
209 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
210 int i;
211
212 if (dev->rdev.wr_log)
213 for (i = 0; i < dev->rdev.wr_log_size; i++)
214 dev->rdev.wr_log[i].valid = 0;
215 return count;
216}
217
218static const struct file_operations wr_log_debugfs_fops = {
219 .owner = THIS_MODULE,
220 .open = wr_log_open,
221 .release = single_release,
222 .read = seq_read,
223 .llseek = seq_lseek,
224 .write = wr_log_clear,
225};
226
9e8d1fa3 227static int dump_qp(int id, void *p, void *data)
cfdda9d7
SW		 228{
229 struct c4iw_qp *qp = p;
9e8d1fa3 230 struct c4iw_debugfs_data *qpd = data;
cfdda9d7
SW		 231 int space;
232 int cc;
233
234 if (id != qp->wq.sq.qid)
235 return 0;
236
237 space = qpd->bufsize - qpd->pos - 1;
238 if (space == 0)
239 return 1;
240
830662f6
VP		 241 if (qp->ep) {
242 if (qp->ep->com.local_addr.ss_family == AF_INET) {
243 struct sockaddr_in *lsin = (struct sockaddr_in *)
244 &qp->ep->com.local_addr;
245 struct sockaddr_in *rsin = (struct sockaddr_in *)
246 &qp->ep->com.remote_addr;
9eccfe10
SW		 247 struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
248 &qp->ep->com.mapped_local_addr;
249 struct sockaddr_in *mapped_rsin = (struct sockaddr_in *)
250 &qp->ep->com.mapped_remote_addr;
830662f6
VP		 251
252 cc = snprintf(qpd->buf + qpd->pos, space,
253 "rc qp sq id %u rq id %u state %u "
254 "onchip %u ep tid %u state %u "
9eccfe10 255 "%pI4:%u/%u->%pI4:%u/%u\n",
830662f6
VP		 256 qp->wq.sq.qid, qp->wq.rq.qid,
257 (int)qp->attr.state,
258 qp->wq.sq.flags & T4_SQ_ONCHIP,
259 qp->ep->hwtid, (int)qp->ep->com.state,
260 &lsin->sin_addr, ntohs(lsin->sin_port),
9eccfe10
SW		 261 ntohs(mapped_lsin->sin_port),
262 &rsin->sin_addr, ntohs(rsin->sin_port),
263 ntohs(mapped_rsin->sin_port));
830662f6
VP		 264 } else {
265 struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
266 &qp->ep->com.local_addr;
267 struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *)
268 &qp->ep->com.remote_addr;
9eccfe10
SW		 269 struct sockaddr_in6 *mapped_lsin6 =
270 (struct sockaddr_in6 *)
271 &qp->ep->com.mapped_local_addr;
272 struct sockaddr_in6 *mapped_rsin6 =
273 (struct sockaddr_in6 *)
274 &qp->ep->com.mapped_remote_addr;
830662f6
VP		 275
276 cc = snprintf(qpd->buf + qpd->pos, space,
277 "rc qp sq id %u rq id %u state %u "
278 "onchip %u ep tid %u state %u "
9eccfe10 279 "%pI6:%u/%u->%pI6:%u/%u\n",
830662f6
VP		 280 qp->wq.sq.qid, qp->wq.rq.qid,
281 (int)qp->attr.state,
282 qp->wq.sq.flags & T4_SQ_ONCHIP,
283 qp->ep->hwtid, (int)qp->ep->com.state,
284 &lsin6->sin6_addr,
285 ntohs(lsin6->sin6_port),
9eccfe10 286 ntohs(mapped_lsin6->sin6_port),
830662f6 287 &rsin6->sin6_addr,
9eccfe10
SW		 288 ntohs(rsin6->sin6_port),
289 ntohs(mapped_rsin6->sin6_port));
830662f6
VP		 290 }
291 } else
db5d040d
SW		 292 cc = snprintf(qpd->buf + qpd->pos, space,
293 "qp sq id %u rq id %u state %u onchip %u\n",
294 qp->wq.sq.qid, qp->wq.rq.qid,
295 (int)qp->attr.state,
296 qp->wq.sq.flags & T4_SQ_ONCHIP);
cfdda9d7
SW		 297 if (cc < space)
298 qpd->pos += cc;
299 return 0;
300}
301
302static int qp_release(struct inode *inode, struct file *file)
303{
9e8d1fa3 304 struct c4iw_debugfs_data *qpd = file->private_data;
cfdda9d7
SW		 305 if (!qpd) {
306 printk(KERN_INFO "%s null qpd?\n", __func__);
307 return 0;
308 }
d716a2a0 309 vfree(qpd->buf);
cfdda9d7
SW		 310 kfree(qpd);
311 return 0;
312}
313
314static int qp_open(struct inode *inode, struct file *file)
315{
9e8d1fa3 316 struct c4iw_debugfs_data *qpd;
cfdda9d7
SW		 317 int ret = 0;
318 int count = 1;
319
320 qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
321 if (!qpd) {
322 ret = -ENOMEM;
323 goto out;
324 }
325 qpd->devp = inode->i_private;
326 qpd->pos = 0;
327
328 spin_lock_irq(&qpd->devp->lock);
9e8d1fa3 329 idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
cfdda9d7
SW		 330 spin_unlock_irq(&qpd->devp->lock);
331
332 qpd->bufsize = count * 128;
d716a2a0 333 qpd->buf = vmalloc(qpd->bufsize);
cfdda9d7
SW		 334 if (!qpd->buf) {
335 ret = -ENOMEM;
336 goto err1;
337 }
338
339 spin_lock_irq(&qpd->devp->lock);
9e8d1fa3 340 idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
cfdda9d7
SW		 341 spin_unlock_irq(&qpd->devp->lock);
342
343 qpd->buf[qpd->pos++] = 0;
344 file->private_data = qpd;
345 goto out;
346err1:
347 kfree(qpd);
348out:
349 return ret;
350}
351
9e8d1fa3
SW		 352static const struct file_operations qp_debugfs_fops = {
353 .owner = THIS_MODULE,
354 .open = qp_open,
355 .release = qp_release,
356 .read = debugfs_read,
8bbac892 357 .llseek = default_llseek,
9e8d1fa3
SW		 358};
359
360static int dump_stag(int id, void *p, void *data)
cfdda9d7 361{
9e8d1fa3
SW		 362 struct c4iw_debugfs_data *stagd = data;
363 int space;
364 int cc;
031cf476
HS		 365 struct fw_ri_tpte tpte;
366 int ret;
cfdda9d7 367
9e8d1fa3
SW		 368 space = stagd->bufsize - stagd->pos - 1;
369 if (space == 0)
370 return 1;
371
031cf476
HS		 372 ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
373 (__be32 *)&tpte);
374 if (ret) {
375 dev_err(&stagd->devp->rdev.lldi.pdev->dev,
376 "%s cxgb4_read_tpte err %d\n", __func__, ret);
377 return ret;
378 }
379 cc = snprintf(stagd->buf + stagd->pos, space,
380 "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
381 "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
382 (u32)id<<8,
cf7fe64a
HS		 383 FW_RI_TPTE_VALID_G(ntohl(tpte.valid_to_pdid)),
384 FW_RI_TPTE_STAGKEY_G(ntohl(tpte.valid_to_pdid)),
385 FW_RI_TPTE_STAGSTATE_G(ntohl(tpte.valid_to_pdid)),
386 FW_RI_TPTE_PDID_G(ntohl(tpte.valid_to_pdid)),
387 FW_RI_TPTE_PERM_G(ntohl(tpte.locread_to_qpid)),
388 FW_RI_TPTE_PS_G(ntohl(tpte.locread_to_qpid)),
031cf476
HS		 389 ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
390 ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
9e8d1fa3
SW		 391 if (cc < space)
392 stagd->pos += cc;
393 return 0;
394}
395
396static int stag_release(struct inode *inode, struct file *file)
397{
398 struct c4iw_debugfs_data *stagd = file->private_data;
399 if (!stagd) {
400 printk(KERN_INFO "%s null stagd?\n", __func__);
cfdda9d7 401 return 0;
9e8d1fa3 402 }
031cf476 403 vfree(stagd->buf);
9e8d1fa3
SW		 404 kfree(stagd);
405 return 0;
406}
cfdda9d7 407
9e8d1fa3
SW		 408static int stag_open(struct inode *inode, struct file *file)
409{
410 struct c4iw_debugfs_data *stagd;
411 int ret = 0;
412 int count = 1;
cfdda9d7 413
9e8d1fa3
SW		 414 stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
415 if (!stagd) {
416 ret = -ENOMEM;
417 goto out;
418 }
419 stagd->devp = inode->i_private;
420 stagd->pos = 0;
cfdda9d7 421
9e8d1fa3
SW		 422 spin_lock_irq(&stagd->devp->lock);
423 idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
424 spin_unlock_irq(&stagd->devp->lock);
425
031cf476
HS		 426 stagd->bufsize = count * 256;
427 stagd->buf = vmalloc(stagd->bufsize);
9e8d1fa3
SW		 428 if (!stagd->buf) {
429 ret = -ENOMEM;
430 goto err1;
cfdda9d7 431 }
9e8d1fa3
SW		 432
433 spin_lock_irq(&stagd->devp->lock);
434 idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
435 spin_unlock_irq(&stagd->devp->lock);
436
437 stagd->buf[stagd->pos++] = 0;
438 file->private_data = stagd;
439 goto out;
440err1:
441 kfree(stagd);
442out:
443 return ret;
cfdda9d7
SW		 444}
445
9e8d1fa3 446static const struct file_operations stag_debugfs_fops = {
cfdda9d7 447 .owner = THIS_MODULE,
9e8d1fa3
SW		 448 .open = stag_open,
449 .release = stag_release,
450 .read = debugfs_read,
8bbac892 451 .llseek = default_llseek,
cfdda9d7
SW		 452};
453
05eb2389 454static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
422eea0a 455
8d81ef34
VP		 456static int stats_show(struct seq_file *seq, void *v)
457{
458 struct c4iw_dev *dev = seq->private;
459
ec3eead2
VP		 460 seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
461 "Max", "Fail");
462 seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
8d81ef34 463 dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
ec3eead2
VP		 464 dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
465 seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
8d81ef34 466 dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
ec3eead2
VP		 467 dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
468 seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
8d81ef34 469 dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
ec3eead2
VP		 470 dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
471 seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
8d81ef34 472 dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
ec3eead2
VP		 473 dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
474 seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
8d81ef34 475 dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
ec3eead2
VP		 476 dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
477 seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
8d81ef34 478 dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
ec3eead2 479 dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
2c974781
VP		 480 seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
481 seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
482 seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
05eb2389 483 seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
422eea0a 484 db_state_str[dev->db_state],
05eb2389
SW		 485 dev->rdev.stats.db_state_transitions,
486 dev->rdev.stats.db_fc_interruptions);
1cab775c 487 seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
793dad94
VP		 488 seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
489 dev->rdev.stats.act_ofld_conn_fails);
490 seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
491 dev->rdev.stats.pas_ofld_conn_fails);
4c2c5763 492 seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
8d81ef34
VP		 493 return 0;
494}
495
496static int stats_open(struct inode *inode, struct file *file)
497{
498 return single_open(file, stats_show, inode->i_private);
499}
500
501static ssize_t stats_clear(struct file *file, const char __user *buf,
502 size_t count, loff_t *pos)
503{
504 struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
505
506 mutex_lock(&dev->rdev.stats.lock);
507 dev->rdev.stats.pd.max = 0;
ec3eead2 508 dev->rdev.stats.pd.fail = 0;
8d81ef34 509 dev->rdev.stats.qid.max = 0;
ec3eead2 510 dev->rdev.stats.qid.fail = 0;
8d81ef34 511 dev->rdev.stats.stag.max = 0;
ec3eead2 512 dev->rdev.stats.stag.fail = 0;
8d81ef34 513 dev->rdev.stats.pbl.max = 0;
ec3eead2 514 dev->rdev.stats.pbl.fail = 0;
8d81ef34 515 dev->rdev.stats.rqt.max = 0;
ec3eead2 516 dev->rdev.stats.rqt.fail = 0;
8d81ef34 517 dev->rdev.stats.ocqp.max = 0;
ec3eead2 518 dev->rdev.stats.ocqp.fail = 0;
2c974781
VP		 519 dev->rdev.stats.db_full = 0;
520 dev->rdev.stats.db_empty = 0;
521 dev->rdev.stats.db_drop = 0;
422eea0a 522 dev->rdev.stats.db_state_transitions = 0;
793dad94
VP		 523 dev->rdev.stats.tcam_full = 0;
524 dev->rdev.stats.act_ofld_conn_fails = 0;
525 dev->rdev.stats.pas_ofld_conn_fails = 0;
8d81ef34
VP		 526 mutex_unlock(&dev->rdev.stats.lock);
527 return count;
528}
529
530static const struct file_operations stats_debugfs_fops = {
531 .owner = THIS_MODULE,
532 .open = stats_open,
533 .release = single_release,
534 .read = seq_read,
535 .llseek = seq_lseek,
536 .write = stats_clear,
537};
538
793dad94
VP		 539static int dump_ep(int id, void *p, void *data)
540{
541 struct c4iw_ep *ep = p;
542 struct c4iw_debugfs_data *epd = data;
543 int space;
544 int cc;
545
546 space = epd->bufsize - epd->pos - 1;
547 if (space == 0)
548 return 1;
549
830662f6
VP		 550 if (ep->com.local_addr.ss_family == AF_INET) {
551 struct sockaddr_in *lsin = (struct sockaddr_in *)
552 &ep->com.local_addr;
553 struct sockaddr_in *rsin = (struct sockaddr_in *)
554 &ep->com.remote_addr;
9eccfe10
SW		 555 struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
556 &ep->com.mapped_local_addr;
557 struct sockaddr_in *mapped_rsin = (struct sockaddr_in *)
558 &ep->com.mapped_remote_addr;
830662f6
VP		 559
560 cc = snprintf(epd->buf + epd->pos, space,
561 "ep %p cm_id %p qp %p state %d flags 0x%lx "
562 "history 0x%lx hwtid %d atid %d "
9eccfe10 563 "%pI4:%d/%d <-> %pI4:%d/%d\n",
830662f6
VP		 564 ep, ep->com.cm_id, ep->com.qp,
565 (int)ep->com.state, ep->com.flags,
566 ep->com.history, ep->hwtid, ep->atid,
567 &lsin->sin_addr, ntohs(lsin->sin_port),
9eccfe10
SW		 568 ntohs(mapped_lsin->sin_port),
569 &rsin->sin_addr, ntohs(rsin->sin_port),
570 ntohs(mapped_rsin->sin_port));
830662f6
VP		 571 } else {
572 struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
573 &ep->com.local_addr;
574 struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *)
575 &ep->com.remote_addr;
9eccfe10
SW		 576 struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *)
577 &ep->com.mapped_local_addr;
578 struct sockaddr_in6 *mapped_rsin6 = (struct sockaddr_in6 *)
579 &ep->com.mapped_remote_addr;
830662f6
VP		 580
581 cc = snprintf(epd->buf + epd->pos, space,
582 "ep %p cm_id %p qp %p state %d flags 0x%lx "
583 "history 0x%lx hwtid %d atid %d "
9eccfe10 584 "%pI6:%d/%d <-> %pI6:%d/%d\n",
830662f6
VP		 585 ep, ep->com.cm_id, ep->com.qp,
586 (int)ep->com.state, ep->com.flags,
587 ep->com.history, ep->hwtid, ep->atid,
588 &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
9eccfe10
SW		 589 ntohs(mapped_lsin6->sin6_port),
590 &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
591 ntohs(mapped_rsin6->sin6_port));
830662f6 592 }
793dad94
VP		 593 if (cc < space)
594 epd->pos += cc;
595 return 0;
596}
597
598static int dump_listen_ep(int id, void *p, void *data)
599{
600 struct c4iw_listen_ep *ep = p;
601 struct c4iw_debugfs_data *epd = data;
602 int space;
603 int cc;
604
605 space = epd->bufsize - epd->pos - 1;
606 if (space == 0)
607 return 1;
608
830662f6
VP		 609 if (ep->com.local_addr.ss_family == AF_INET) {
610 struct sockaddr_in *lsin = (struct sockaddr_in *)
611 &ep->com.local_addr;
9eccfe10
SW		 612 struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
613 &ep->com.mapped_local_addr;
830662f6
VP		 614
615 cc = snprintf(epd->buf + epd->pos, space,
616 "ep %p cm_id %p state %d flags 0x%lx stid %d "
9eccfe10 617 "backlog %d %pI4:%d/%d\n",
830662f6
VP		 618 ep, ep->com.cm_id, (int)ep->com.state,
619 ep->com.flags, ep->stid, ep->backlog,
9eccfe10
SW		 620 &lsin->sin_addr, ntohs(lsin->sin_port),
621 ntohs(mapped_lsin->sin_port));
830662f6
VP		 622 } else {
623 struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
624 &ep->com.local_addr;
9eccfe10
SW		 625 struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *)
626 &ep->com.mapped_local_addr;
830662f6
VP		 627
628 cc = snprintf(epd->buf + epd->pos, space,
629 "ep %p cm_id %p state %d flags 0x%lx stid %d "
9eccfe10 630 "backlog %d %pI6:%d/%d\n",
830662f6
VP		 631 ep, ep->com.cm_id, (int)ep->com.state,
632 ep->com.flags, ep->stid, ep->backlog,
9eccfe10
SW		 633 &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
634 ntohs(mapped_lsin6->sin6_port));
830662f6 635 }
793dad94
VP		 636 if (cc < space)
637 epd->pos += cc;
638 return 0;
639}
640
641static int ep_release(struct inode *inode, struct file *file)
642{
643 struct c4iw_debugfs_data *epd = file->private_data;
644 if (!epd) {
645 pr_info("%s null qpd?\n", __func__);
646 return 0;
647 }
648 vfree(epd->buf);
649 kfree(epd);
650 return 0;
651}
652
653static int ep_open(struct inode *inode, struct file *file)
654{
655 struct c4iw_debugfs_data *epd;
656 int ret = 0;
657 int count = 1;
658
659 epd = kmalloc(sizeof(*epd), GFP_KERNEL);
660 if (!epd) {
661 ret = -ENOMEM;
662 goto out;
663 }
664 epd->devp = inode->i_private;
665 epd->pos = 0;
666
667 spin_lock_irq(&epd->devp->lock);
668 idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
669 idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
670 idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
671 spin_unlock_irq(&epd->devp->lock);
672
63a71ba6 673 epd->bufsize = count * 240;
793dad94
VP		 674 epd->buf = vmalloc(epd->bufsize);
675 if (!epd->buf) {
676 ret = -ENOMEM;
677 goto err1;
678 }
679
680 spin_lock_irq(&epd->devp->lock);
681 idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
682 idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
683 idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
684 spin_unlock_irq(&epd->devp->lock);
685
686 file->private_data = epd;
687 goto out;
688err1:
689 kfree(epd);
690out:
691 return ret;
692}
693
694static const struct file_operations ep_debugfs_fops = {
695 .owner = THIS_MODULE,
696 .open = ep_open,
697 .release = ep_release,
698 .read = debugfs_read,
699};
700
cfdda9d7
SW		 701static int setup_debugfs(struct c4iw_dev *devp)
702{
cfdda9d7
SW		 703 if (!devp->debugfs_root)
704 return -1;
705
e59b4e91
DH		 706 debugfs_create_file_size("qps", S_IWUSR, devp->debugfs_root,
707 (void *)devp, &qp_debugfs_fops, 4096);
708
709 debugfs_create_file_size("stags", S_IWUSR, devp->debugfs_root,
710 (void *)devp, &stag_debugfs_fops, 4096);
711
712 debugfs_create_file_size("stats", S_IWUSR, devp->debugfs_root,
713 (void *)devp, &stats_debugfs_fops, 4096);
714
715 debugfs_create_file_size("eps", S_IWUSR, devp->debugfs_root,
716 (void *)devp, &ep_debugfs_fops, 4096);
717
718 if (c4iw_wr_log)
719 debugfs_create_file_size("wr_log", S_IWUSR, devp->debugfs_root,
720 (void *)devp, &wr_log_debugfs_fops, 4096);
cfdda9d7
SW		 721 return 0;
722}
723
724void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
725 struct c4iw_dev_ucontext *uctx)
726{
727 struct list_head *pos, *nxt;
728 struct c4iw_qid_list *entry;
729
730 mutex_lock(&uctx->lock);
731 list_for_each_safe(pos, nxt, &uctx->qpids) {
732 entry = list_entry(pos, struct c4iw_qid_list, entry);
733 list_del_init(&entry->entry);
8d81ef34 734 if (!(entry->qid & rdev->qpmask)) {
ec3eead2
VP		 735 c4iw_put_resource(&rdev->resource.qid_table,
736 entry->qid);
8d81ef34
VP		 737 mutex_lock(&rdev->stats.lock);
738 rdev->stats.qid.cur -= rdev->qpmask + 1;
739 mutex_unlock(&rdev->stats.lock);
740 }
cfdda9d7
SW		 741 kfree(entry);
742 }
743
744 list_for_each_safe(pos, nxt, &uctx->qpids) {
745 entry = list_entry(pos, struct c4iw_qid_list, entry);
746 list_del_init(&entry->entry);
747 kfree(entry);
748 }
749 mutex_unlock(&uctx->lock);
750}
751
752void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
753 struct c4iw_dev_ucontext *uctx)
754{
755 INIT_LIST_HEAD(&uctx->qpids);
756 INIT_LIST_HEAD(&uctx->cqids);
757 mutex_init(&uctx->lock);
758}
759
760/* Caller takes care of locking if needed */
761static int c4iw_rdev_open(struct c4iw_rdev *rdev)
762{
763 int err;
764
765 c4iw_init_dev_ucontext(rdev, &rdev->uctx);
766
767 /*
768 * qpshift is the number of bits to shift the qpid left in order
769 * to get the correct address of the doorbell for that qp.
770 */
771 rdev->qpshift = PAGE_SHIFT - ilog2(rdev->lldi.udb_density);
772 rdev->qpmask = rdev->lldi.udb_density - 1;
773 rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density);
774 rdev->cqmask = rdev->lldi.ucq_density - 1;
775 PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d "
93fb72e4
SW		 776 "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x "
777 "qp qid start %u size %u cq qid start %u size %u\n",
cfdda9d7
SW		 778 __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
779 rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
780 rdev->lldi.vr->pbl.start,
781 rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
93fb72e4
SW		 782 rdev->lldi.vr->rq.size,
783 rdev->lldi.vr->qp.start,
784 rdev->lldi.vr->qp.size,
785 rdev->lldi.vr->cq.start,
786 rdev->lldi.vr->cq.size);
649fb5ec 787 PDBG("udb len 0x%x udb base %llx db_reg %p gts_reg %p qpshift %lu "
cfdda9d7
SW		 788 "qpmask 0x%x cqshift %lu cqmask 0x%x\n",
789 (unsigned)pci_resource_len(rdev->lldi.pdev, 2),
649fb5ec 790 (u64)pci_resource_start(rdev->lldi.pdev, 2),
cfdda9d7
SW		 791 rdev->lldi.db_reg,
792 rdev->lldi.gts_reg,
793 rdev->qpshift, rdev->qpmask,
794 rdev->cqshift, rdev->cqmask);
795
796 if (c4iw_num_stags(rdev) == 0) {
797 err = -EINVAL;
798 goto err1;
799 }
800
8d81ef34
VP		 801 rdev->stats.pd.total = T4_MAX_NUM_PD;
802 rdev->stats.stag.total = rdev->lldi.vr->stag.size;
803 rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
804 rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
805 rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
806 rdev->stats.qid.total = rdev->lldi.vr->qp.size;
807
cfdda9d7
SW		 808 err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
809 if (err) {
810 printk(KERN_ERR MOD "error %d initializing resources\n", err);
811 goto err1;
812 }
813 err = c4iw_pblpool_create(rdev);
814 if (err) {
815 printk(KERN_ERR MOD "error %d initializing pbl pool\n", err);
816 goto err2;
817 }
818 err = c4iw_rqtpool_create(rdev);
819 if (err) {
820 printk(KERN_ERR MOD "error %d initializing rqt pool\n", err);
821 goto err3;
822 }
c6d7b267
SW		 823 err = c4iw_ocqp_pool_create(rdev);
824 if (err) {
825 printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err);
826 goto err4;
827 }
05eb2389
SW		 828 rdev->status_page = (struct t4_dev_status_page *)
829 __get_free_page(GFP_KERNEL);
830 if (!rdev->status_page) {
831 pr_err(MOD "error allocating status page\n");
832 goto err4;
833 }
8fd90bb8 834
7730b4c7
HS		 835 if (c4iw_wr_log) {
836 rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) *
837 sizeof(*rdev->wr_log), GFP_KERNEL);
838 if (rdev->wr_log) {
839 rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
840 atomic_set(&rdev->wr_log_idx, 0);
841 } else {
842 pr_err(MOD "error allocating wr_log. Logging disabled\n");
843 }
844 }
8fd90bb8 845
6b54d54d 846 rdev->status_page->db_off = 0;
8fd90bb8 847
cfdda9d7 848 return 0;
c6d7b267
SW		 849err4:
850 c4iw_rqtpool_destroy(rdev);
cfdda9d7
SW		 851err3:
852 c4iw_pblpool_destroy(rdev);
853err2:
854 c4iw_destroy_resource(&rdev->resource);
855err1:
856 return err;
857}
858
859static void c4iw_rdev_close(struct c4iw_rdev *rdev)
860{
7730b4c7 861 kfree(rdev->wr_log);
05eb2389 862 free_page((unsigned long)rdev->status_page);
cfdda9d7
SW		 863 c4iw_pblpool_destroy(rdev);
864 c4iw_rqtpool_destroy(rdev);
865 c4iw_destroy_resource(&rdev->resource);
866}
867
9efe10a1 868static void c4iw_dealloc(struct uld_ctx *ctx)
cfdda9d7 869{
2f25e9a5
SW		 870 c4iw_rdev_close(&ctx->dev->rdev);
871 idr_destroy(&ctx->dev->cqidr);
872 idr_destroy(&ctx->dev->qpidr);
873 idr_destroy(&ctx->dev->mmidr);
793dad94
VP		 874 idr_destroy(&ctx->dev->hwtid_idr);
875 idr_destroy(&ctx->dev->stid_idr);
876 idr_destroy(&ctx->dev->atid_idr);
fa658a98
SW		 877 if (ctx->dev->rdev.bar2_kva)
878 iounmap(ctx->dev->rdev.bar2_kva);
879 if (ctx->dev->rdev.oc_mw_kva)
880 iounmap(ctx->dev->rdev.oc_mw_kva);
2f25e9a5
SW		 881 ib_dealloc_device(&ctx->dev->ibdev);
882 ctx->dev = NULL;
cfdda9d7
SW		 883}
884
9efe10a1
SW		 885static void c4iw_remove(struct uld_ctx *ctx)
886{
887 PDBG("%s c4iw_dev %p\n", __func__, ctx->dev);
888 c4iw_unregister_device(ctx->dev);
889 c4iw_dealloc(ctx);
890}
891
892static int rdma_supported(const struct cxgb4_lld_info *infop)
893{
894 return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
895 infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
f079af7a 896 infop->vr->cq.size > 0;
9efe10a1
SW		 897}
898
cfdda9d7
SW		 899static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
900{
901 struct c4iw_dev *devp;
902 int ret;
903
9efe10a1
SW		 904 if (!rdma_supported(infop)) {
905 printk(KERN_INFO MOD "%s: RDMA not supported on this device.\n",
906 pci_name(infop->pdev));
907 return ERR_PTR(-ENOSYS);
908 }
f079af7a
VP		 909 if (!ocqp_supported(infop))
910 pr_info("%s: On-Chip Queues not supported on this device.\n",
911 pci_name(infop->pdev));
80ccdd60 912
cfdda9d7
SW		 913 devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
914 if (!devp) {
915 printk(KERN_ERR MOD "Cannot allocate ib device\n");
bbe9a0a2 916 return ERR_PTR(-ENOMEM);
cfdda9d7
SW		 917 }
918 devp->rdev.lldi = *infop;
919
04e10e21
HS		 920 /* init various hw-queue params based on lld info */
921 PDBG("%s: Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
922 __func__, devp->rdev.lldi.sge_ingpadboundary,
923 devp->rdev.lldi.sge_egrstatuspagesize);
924
925 devp->rdev.hw_queue.t4_eq_status_entries =
926 devp->rdev.lldi.sge_ingpadboundary > 64 ? 2 : 1;
66eb19af
HS		 927 devp->rdev.hw_queue.t4_max_eq_size = 65520;
928 devp->rdev.hw_queue.t4_max_iq_size = 65520;
929 devp->rdev.hw_queue.t4_max_rq_size = 8192 -
930 devp->rdev.hw_queue.t4_eq_status_entries - 1;
04e10e21 931 devp->rdev.hw_queue.t4_max_sq_size =
66eb19af
HS		 932 devp->rdev.hw_queue.t4_max_eq_size -
933 devp->rdev.hw_queue.t4_eq_status_entries - 1;
04e10e21 934 devp->rdev.hw_queue.t4_max_qp_depth =
66eb19af 935 devp->rdev.hw_queue.t4_max_rq_size;
04e10e21 936 devp->rdev.hw_queue.t4_max_cq_depth =
66eb19af 937 devp->rdev.hw_queue.t4_max_iq_size - 2;
04e10e21
HS		 938 devp->rdev.hw_queue.t4_stat_len =
939 devp->rdev.lldi.sge_egrstatuspagesize;
940
fa658a98
SW		 941 /*
942 * For T5 devices, we map all of BAR2 with WC.
943 * For T4 devices with onchip qp mem, we map only that part
944 * of BAR2 with WC.
945 */
946 devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
947 if (is_t5(devp->rdev.lldi.adapter_type)) {
948 devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
949 pci_resource_len(devp->rdev.lldi.pdev, 2));
950 if (!devp->rdev.bar2_kva) {
951 pr_err(MOD "Unable to ioremap BAR2\n");
65b302ad 952 ib_dealloc_device(&devp->ibdev);
fa658a98
SW		 953 return ERR_PTR(-EINVAL);
954 }
955 } else if (ocqp_supported(infop)) {
956 devp->rdev.oc_mw_pa =
957 pci_resource_start(devp->rdev.lldi.pdev, 2) +
958 pci_resource_len(devp->rdev.lldi.pdev, 2) -
959 roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
960 devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
961 devp->rdev.lldi.vr->ocq.size);
962 if (!devp->rdev.oc_mw_kva) {
963 pr_err(MOD "Unable to ioremap onchip mem\n");
65b302ad 964 ib_dealloc_device(&devp->ibdev);
fa658a98
SW		 965 return ERR_PTR(-EINVAL);
966 }
967 }
c6d7b267 968
2f25e9a5 969 PDBG(KERN_INFO MOD "ocq memory: "
c6d7b267
SW		 970 "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
971 devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
972 devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
973
cfdda9d7
SW		 974 ret = c4iw_rdev_open(&devp->rdev);
975 if (ret) {
cfdda9d7
SW		 976 printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret);
977 ib_dealloc_device(&devp->ibdev);
bbe9a0a2 978 return ERR_PTR(ret);
cfdda9d7
SW		 979 }
980
981 idr_init(&devp->cqidr);
982 idr_init(&devp->qpidr);
983 idr_init(&devp->mmidr);
793dad94
VP		 984 idr_init(&devp->hwtid_idr);
985 idr_init(&devp->stid_idr);
986 idr_init(&devp->atid_idr);
cfdda9d7 987 spin_lock_init(&devp->lock);
8d81ef34 988 mutex_init(&devp->rdev.stats.lock);
2c974781 989 mutex_init(&devp->db_mutex);
05eb2389 990 INIT_LIST_HEAD(&devp->db_fc_list);
4c2c5763 991 devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
cfdda9d7 992
cfdda9d7
SW		 993 if (c4iw_debugfs_root) {
994 devp->debugfs_root = debugfs_create_dir(
995 pci_name(devp->rdev.lldi.pdev),
996 c4iw_debugfs_root);
997 setup_debugfs(devp);
998 }
9eccfe10 999
9eccfe10 1000
cfdda9d7
SW		 1001 return devp;
1002}
1003
1004static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
1005{
2f25e9a5 1006 struct uld_ctx *ctx;
cfdda9d7
SW		 1007 static int vers_printed;
1008 int i;
1009
1010 if (!vers_printed++)
f079af7a
VP		 1011 pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
1012 DRV_VERSION);
cfdda9d7 1013
2f25e9a5
SW		 1014 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1015 if (!ctx) {
1016 ctx = ERR_PTR(-ENOMEM);
cfdda9d7 1017 goto out;
2f25e9a5
SW		 1018 }
1019 ctx->lldi = *infop;
cfdda9d7
SW		 1020
1021 PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
2f25e9a5
SW		 1022 __func__, pci_name(ctx->lldi.pdev),
1023 ctx->lldi.nchan, ctx->lldi.nrxq,
1024 ctx->lldi.ntxq, ctx->lldi.nports);
1025
1026 mutex_lock(&dev_mutex);
1027 list_add_tail(&ctx->entry, &uld_ctx_list);
1028 mutex_unlock(&dev_mutex);
cfdda9d7 1029
2f25e9a5
SW		 1030 for (i = 0; i < ctx->lldi.nrxq; i++)
1031 PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
cfdda9d7 1032out:
2f25e9a5 1033 return ctx;
cfdda9d7
SW		 1034}
1035
1cab775c
VP		 1036static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
1037 const __be64 *rsp,
1038 u32 pktshift)
1039{
1040 struct sk_buff *skb;
1041
1042 /*
1043 * Allocate space for cpl_pass_accept_req which will be synthesized by
1044 * driver. Once the driver synthesizes the request the skb will go
1045 * through the regular cpl_pass_accept_req processing.
1046 * The math here assumes sizeof cpl_pass_accept_req >= sizeof
1047 * cpl_rx_pkt.
1048 */
1049 skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
1050 sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
1051 if (unlikely(!skb))
1052 return NULL;
1053
1054 __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
1055 sizeof(struct rss_header) - pktshift);
1056
1057 /*
1058 * This skb will contain:
1059 * rss_header from the rspq descriptor (1 flit)
1060 * cpl_rx_pkt struct from the rspq descriptor (2 flits)
1061 * space for the difference between the size of an
1062 * rx_pkt and pass_accept_req cpl (1 flit)
1063 * the packet data from the gl
1064 */
1065 skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
1066 sizeof(struct rss_header));
1067 skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
1068 sizeof(struct cpl_pass_accept_req),
1069 gl->va + pktshift,
1070 gl->tot_len - pktshift);
1071 return skb;
1072}
1073
1074static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
1075 const __be64 *rsp)
1076{
1077 unsigned int opcode = *(u8 *)rsp;
1078 struct sk_buff *skb;
1079
1080 if (opcode != CPL_RX_PKT)
1081 goto out;
1082
1083 skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
1084 if (skb == NULL)
1085 goto out;
1086
1087 if (c4iw_handlers[opcode] == NULL) {
1088 pr_info("%s no handler opcode 0x%x...\n", __func__,
1089 opcode);
1090 kfree_skb(skb);
1091 goto out;
1092 }
1093 c4iw_handlers[opcode](dev, skb);
1094 return 1;
1095out:
1096 return 0;
1097}
1098
cfdda9d7
SW		 1099static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
1100 const struct pkt_gl *gl)
1101{
2f25e9a5
SW		 1102 struct uld_ctx *ctx = handle;
1103 struct c4iw_dev *dev = ctx->dev;
cfdda9d7 1104 struct sk_buff *skb;
1cab775c 1105 u8 opcode;
cfdda9d7
SW		 1106
1107 if (gl == NULL) {
1108 /* omit RSS and rsp_ctrl at end of descriptor */
1109 unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
1110
1111 skb = alloc_skb(256, GFP_ATOMIC);
1112 if (!skb)
1113 goto nomem;
1114 __skb_put(skb, len);
1115 skb_copy_to_linear_data(skb, &rsp[1], len);
1116 } else if (gl == CXGB4_MSG_AN) {
1117 const struct rsp_ctrl *rc = (void *)rsp;
1118
1119 u32 qid = be32_to_cpu(rc->pldbuflen_qid);
1120 c4iw_ev_handler(dev, qid);
1cab775c
VP		 1121 return 0;
1122 } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
1123 if (recv_rx_pkt(dev, gl, rsp))
1124 return 0;
1125
1126 pr_info("%s: unexpected FL contents at %p, " \
1127 "RSS %#llx, FL %#llx, len %u\n",
1128 pci_name(ctx->lldi.pdev), gl->va,
1129 (unsigned long long)be64_to_cpu(*rsp),
ef5d6355
VP		 1130 (unsigned long long)be64_to_cpu(
1131 *(__force __be64 *)gl->va),
1cab775c
VP		 1132 gl->tot_len);
1133
cfdda9d7
SW		 1134 return 0;
1135 } else {
da411ba1 1136 skb = cxgb4_pktgl_to_skb(gl, 128, 128);
cfdda9d7
SW		 1137 if (unlikely(!skb))
1138 goto nomem;
1139 }
1140
1cab775c 1141 opcode = *(u8 *)rsp;
dbb084cc 1142 if (c4iw_handlers[opcode]) {
cfdda9d7 1143 c4iw_handlers[opcode](dev, skb);
dbb084cc 1144 } else {
1cab775c 1145 pr_info("%s no handler opcode 0x%x...\n", __func__,
cfdda9d7 1146 opcode);
dbb084cc
SW		 1147 kfree_skb(skb);
1148 }
cfdda9d7
SW		 1149
1150 return 0;
1151nomem:
1152 return -1;
1153}
1154
1155static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
1156{
2f25e9a5 1157 struct uld_ctx *ctx = handle;
1c01c538 1158
cfdda9d7 1159 PDBG("%s new_state %u\n", __func__, new_state);
1c01c538
SW		 1160 switch (new_state) {
1161 case CXGB4_STATE_UP:
2f25e9a5
SW		 1162 printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev));
1163 if (!ctx->dev) {
9efe10a1 1164 int ret;
2f25e9a5
SW		 1165
1166 ctx->dev = c4iw_alloc(&ctx->lldi);
9efe10a1
SW		 1167 if (IS_ERR(ctx->dev)) {
1168 printk(KERN_ERR MOD
1169 "%s: initialization failed: %ld\n",
1170 pci_name(ctx->lldi.pdev),
1171 PTR_ERR(ctx->dev));
1172 ctx->dev = NULL;
1173 break;
1174 }
1175 ret = c4iw_register_device(ctx->dev);
1176 if (ret) {
1c01c538
SW		 1177 printk(KERN_ERR MOD
1178 "%s: RDMA registration failed: %d\n",
2f25e9a5 1179 pci_name(ctx->lldi.pdev), ret);
9efe10a1
SW		 1180 c4iw_dealloc(ctx);
1181 }
1c01c538
SW		 1182 }
1183 break;
1184 case CXGB4_STATE_DOWN:
1185 printk(KERN_INFO MOD "%s: Down\n",
2f25e9a5
SW		 1186 pci_name(ctx->lldi.pdev));
1187 if (ctx->dev)
1188 c4iw_remove(ctx);
1c01c538
SW		 1189 break;
1190 case CXGB4_STATE_START_RECOVERY:
1191 printk(KERN_INFO MOD "%s: Fatal Error\n",
2f25e9a5
SW		 1192 pci_name(ctx->lldi.pdev));
1193 if (ctx->dev) {
767fbe81
SW		 1194 struct ib_event event;
1195
2f25e9a5 1196 ctx->dev->rdev.flags |= T4_FATAL_ERROR;
767fbe81
SW		 1197 memset(&event, 0, sizeof event);
1198 event.event = IB_EVENT_DEVICE_FATAL;
2f25e9a5 1199 event.device = &ctx->dev->ibdev;
767fbe81 1200 ib_dispatch_event(&event);
2f25e9a5 1201 c4iw_remove(ctx);
767fbe81 1202 }
1c01c538
SW		 1203 break;
1204 case CXGB4_STATE_DETACH:
1205 printk(KERN_INFO MOD "%s: Detach\n",
2f25e9a5
SW		 1206 pci_name(ctx->lldi.pdev));
1207 if (ctx->dev)
1208 c4iw_remove(ctx);
1c01c538
SW		 1209 break;
1210 }
cfdda9d7
SW		 1211 return 0;
1212}
1213
2c974781
VP		 1214static int disable_qp_db(int id, void *p, void *data)
1215{
1216 struct c4iw_qp *qp = p;
1217
1218 t4_disable_wq_db(&qp->wq);
1219 return 0;
1220}
1221
1222static void stop_queues(struct uld_ctx *ctx)
1223{
05eb2389
SW		 1224 unsigned long flags;
1225
1226 spin_lock_irqsave(&ctx->dev->lock, flags);
1227 ctx->dev->rdev.stats.db_state_transitions++;
1228 ctx->dev->db_state = STOPPED;
1229 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
422eea0a 1230 idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
05eb2389
SW		 1231 else
1232 ctx->dev->rdev.status_page->db_off = 1;
1233 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2c974781
VP		 1234}
1235
1236static int enable_qp_db(int id, void *p, void *data)
1237{
1238 struct c4iw_qp *qp = p;
1239
1240 t4_enable_wq_db(&qp->wq);
1241 return 0;
1242}
1243
05eb2389
SW		 1244static void resume_rc_qp(struct c4iw_qp *qp)
1245{
1246 spin_lock(&qp->lock);
fa658a98
SW		 1247 t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc,
1248 is_t5(qp->rhp->rdev.lldi.adapter_type), NULL);
05eb2389 1249 qp->wq.sq.wq_pidx_inc = 0;
fa658a98
SW		 1250 t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc,
1251 is_t5(qp->rhp->rdev.lldi.adapter_type), NULL);
05eb2389
SW		 1252 qp->wq.rq.wq_pidx_inc = 0;
1253 spin_unlock(&qp->lock);
1254}
1255
1256static void resume_a_chunk(struct uld_ctx *ctx)
1257{
1258 int i;
1259 struct c4iw_qp *qp;
1260
1261 for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
1262 qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
1263 db_fc_entry);
1264 list_del_init(&qp->db_fc_entry);
1265 resume_rc_qp(qp);
1266 if (list_empty(&ctx->dev->db_fc_list))
1267 break;
1268 }
1269}
1270
2c974781
VP		 1271static void resume_queues(struct uld_ctx *ctx)
1272{
1273 spin_lock_irq(&ctx->dev->lock);
05eb2389
SW		 1274 if (ctx->dev->db_state != STOPPED)
1275 goto out;
1276 ctx->dev->db_state = FLOW_CONTROL;
1277 while (1) {
1278 if (list_empty(&ctx->dev->db_fc_list)) {
1279 WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
1280 ctx->dev->db_state = NORMAL;
1281 ctx->dev->rdev.stats.db_state_transitions++;
1282 if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
1283 idr_for_each(&ctx->dev->qpidr, enable_qp_db,
1284 NULL);
1285 } else {
1286 ctx->dev->rdev.status_page->db_off = 0;
1287 }
1288 break;
1289 } else {
1290 if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
1291 < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
1292 DB_FC_DRAIN_THRESH)) {
1293 resume_a_chunk(ctx);
1294 }
1295 if (!list_empty(&ctx->dev->db_fc_list)) {
1296 spin_unlock_irq(&ctx->dev->lock);
1297 if (DB_FC_RESUME_DELAY) {
1298 set_current_state(TASK_UNINTERRUPTIBLE);
1299 schedule_timeout(DB_FC_RESUME_DELAY);
1300 }
1301 spin_lock_irq(&ctx->dev->lock);
1302 if (ctx->dev->db_state != FLOW_CONTROL)
1303 break;
1304 }
1305 }
422eea0a 1306 }
05eb2389
SW		 1307out:
1308 if (ctx->dev->db_state != NORMAL)
1309 ctx->dev->rdev.stats.db_fc_interruptions++;
422eea0a
VP		 1310 spin_unlock_irq(&ctx->dev->lock);
1311}
1312
1313struct qp_list {
1314 unsigned idx;
1315 struct c4iw_qp **qps;
1316};
1317
1318static int add_and_ref_qp(int id, void *p, void *data)
1319{
1320 struct qp_list *qp_listp = data;
1321 struct c4iw_qp *qp = p;
1322
1323 c4iw_qp_add_ref(&qp->ibqp);
1324 qp_listp->qps[qp_listp->idx++] = qp;
1325 return 0;
1326}
1327
1328static int count_qps(int id, void *p, void *data)
1329{
1330 unsigned *countp = data;
1331 (*countp)++;
1332 return 0;
1333}
1334
05eb2389 1335static void deref_qps(struct qp_list *qp_list)
422eea0a
VP		 1336{
1337 int idx;
1338
05eb2389
SW		 1339 for (idx = 0; idx < qp_list->idx; idx++)
1340 c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
422eea0a
VP		 1341}
1342
1343static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
1344{
1345 int idx;
1346 int ret;
1347
1348 for (idx = 0; idx < qp_list->idx; idx++) {
1349 struct c4iw_qp *qp = qp_list->qps[idx];
1350
05eb2389
SW		 1351 spin_lock_irq(&qp->rhp->lock);
1352 spin_lock(&qp->lock);
422eea0a
VP		 1353 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
1354 qp->wq.sq.qid,
1355 t4_sq_host_wq_pidx(&qp->wq),
1356 t4_sq_wq_size(&qp->wq));
1357 if (ret) {
05eb2389 1358 pr_err(KERN_ERR MOD "%s: Fatal error - "
422eea0a
VP		 1359 "DB overflow recovery failed - "
1360 "error syncing SQ qid %u\n",
1361 pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
05eb2389
SW		 1362 spin_unlock(&qp->lock);
1363 spin_unlock_irq(&qp->rhp->lock);
422eea0a
VP		 1364 return;
1365 }
05eb2389 1366 qp->wq.sq.wq_pidx_inc = 0;
422eea0a
VP		 1367
1368 ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
1369 qp->wq.rq.qid,
1370 t4_rq_host_wq_pidx(&qp->wq),
1371 t4_rq_wq_size(&qp->wq));
1372
1373 if (ret) {
05eb2389 1374 pr_err(KERN_ERR MOD "%s: Fatal error - "
422eea0a
VP		 1375 "DB overflow recovery failed - "
1376 "error syncing RQ qid %u\n",
1377 pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
05eb2389
SW		 1378 spin_unlock(&qp->lock);
1379 spin_unlock_irq(&qp->rhp->lock);
422eea0a
VP		 1380 return;
1381 }
05eb2389
SW		 1382 qp->wq.rq.wq_pidx_inc = 0;
1383 spin_unlock(&qp->lock);
1384 spin_unlock_irq(&qp->rhp->lock);
422eea0a
VP		 1385
1386 /* Wait for the dbfifo to drain */
1387 while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
1388 set_current_state(TASK_UNINTERRUPTIBLE);
1389 schedule_timeout(usecs_to_jiffies(10));
1390 }
1391 }
1392}
1393
1394static void recover_queues(struct uld_ctx *ctx)
1395{
1396 int count = 0;
1397 struct qp_list qp_list;
1398 int ret;
1399
422eea0a
VP		 1400 /* slow everybody down */
1401 set_current_state(TASK_UNINTERRUPTIBLE);
1402 schedule_timeout(usecs_to_jiffies(1000));
1403
422eea0a
VP		 1404 /* flush the SGE contexts */
1405 ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
1406 if (ret) {
1407 printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
1408 pci_name(ctx->lldi.pdev));
05eb2389 1409 return;
422eea0a
VP		 1410 }
1411
1412 /* Count active queues so we can build a list of queues to recover */
1413 spin_lock_irq(&ctx->dev->lock);
05eb2389
SW		 1414 WARN_ON(ctx->dev->db_state != STOPPED);
1415 ctx->dev->db_state = RECOVERY;
422eea0a
VP		 1416 idr_for_each(&ctx->dev->qpidr, count_qps, &count);
1417
1418 qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
1419 if (!qp_list.qps) {
1420 printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
1421 pci_name(ctx->lldi.pdev));
1422 spin_unlock_irq(&ctx->dev->lock);
05eb2389 1423 return;
422eea0a
VP		 1424 }
1425 qp_list.idx = 0;
1426
1427 /* add and ref each qp so it doesn't get freed */
1428 idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
1429
2c974781 1430 spin_unlock_irq(&ctx->dev->lock);
422eea0a
VP		 1431
1432 /* now traverse the list in a safe context to recover the db state*/
1433 recover_lost_dbs(ctx, &qp_list);
1434
1435 /* we're almost done! deref the qps and clean up */
05eb2389 1436 deref_qps(&qp_list);
422eea0a
VP		 1437 kfree(qp_list.qps);
1438
422eea0a 1439 spin_lock_irq(&ctx->dev->lock);
05eb2389
SW		 1440 WARN_ON(ctx->dev->db_state != RECOVERY);
1441 ctx->dev->db_state = STOPPED;
422eea0a 1442 spin_unlock_irq(&ctx->dev->lock);
2c974781
VP		 1443}
1444
1445static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
1446{
1447 struct uld_ctx *ctx = handle;
1448
1449 switch (control) {
1450 case CXGB4_CONTROL_DB_FULL:
1451 stop_queues(ctx);
2c974781 1452 ctx->dev->rdev.stats.db_full++;
2c974781
VP		 1453 break;
1454 case CXGB4_CONTROL_DB_EMPTY:
1455 resume_queues(ctx);
1456 mutex_lock(&ctx->dev->rdev.stats.lock);
1457 ctx->dev->rdev.stats.db_empty++;
1458 mutex_unlock(&ctx->dev->rdev.stats.lock);
1459 break;
1460 case CXGB4_CONTROL_DB_DROP:
422eea0a 1461 recover_queues(ctx);
2c974781
VP		 1462 mutex_lock(&ctx->dev->rdev.stats.lock);
1463 ctx->dev->rdev.stats.db_drop++;
1464 mutex_unlock(&ctx->dev->rdev.stats.lock);
1465 break;
1466 default:
1467 printk(KERN_WARNING MOD "%s: unknown control cmd %u\n",
1468 pci_name(ctx->lldi.pdev), control);
1469 break;
1470 }
1471 return 0;
1472}
1473
cfdda9d7
SW		 1474static struct cxgb4_uld_info c4iw_uld_info = {
1475 .name = DRV_NAME,
1476 .add = c4iw_uld_add,
1477 .rx_handler = c4iw_uld_rx_handler,
1478 .state_change = c4iw_uld_state_change,
2c974781 1479 .control = c4iw_uld_control,
cfdda9d7
SW		 1480};
1481
1482static int __init c4iw_init_module(void)
1483{
1484 int err;
1485
1486 err = c4iw_cm_init();
1487 if (err)
1488 return err;
1489
1490 c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
1491 if (!c4iw_debugfs_root)
1492 printk(KERN_WARNING MOD
1493 "could not create debugfs entry, continuing\n");
1494
9eccfe10
SW		 1495 if (ibnl_add_client(RDMA_NL_C4IW, RDMA_NL_IWPM_NUM_OPS,
1496 c4iw_nl_cb_table))
1497 pr_err("%s[%u]: Failed to add netlink callback\n"
1498 , __func__, __LINE__);
1499
46c1376d
SW		 1500 err = iwpm_init(RDMA_NL_C4IW);
1501 if (err) {
1502 pr_err("port mapper initialization failed with %d\n", err);
1503 ibnl_remove_client(RDMA_NL_C4IW);
1504 c4iw_cm_term();
1505 debugfs_remove_recursive(c4iw_debugfs_root);
1506 return err;
1507 }
1508
cfdda9d7
SW		 1509 cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
1510
1511 return 0;
1512}
1513
1514static void __exit c4iw_exit_module(void)
1515{
2f25e9a5 1516 struct uld_ctx *ctx, *tmp;
cfdda9d7 1517
cfdda9d7 1518 mutex_lock(&dev_mutex);
2f25e9a5
SW		 1519 list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
1520 if (ctx->dev)
1521 c4iw_remove(ctx);
1522 kfree(ctx);
cfdda9d7
SW		 1523 }
1524 mutex_unlock(&dev_mutex);
fd388ce6 1525 cxgb4_unregister_uld(CXGB4_ULD_RDMA);
46c1376d 1526 iwpm_exit(RDMA_NL_C4IW);
9eccfe10 1527 ibnl_remove_client(RDMA_NL_C4IW);
cfdda9d7
SW		 1528 c4iw_cm_term();
1529 debugfs_remove_recursive(c4iw_debugfs_root);
1530}
1531
1532module_init(c4iw_init_module);
1533module_exit(c4iw_exit_module);
Linux 6.x block layer and io_uring tree(s)