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09a642b7 GG |
1 | /* |
2 | * Copyright (C) 2012 Invensense, Inc. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | #include <linux/i2c.h> | |
51f97f6d | 14 | #include <linux/i2c-mux.h> |
09a642b7 GG |
15 | #include <linux/kfifo.h> |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/iio/iio.h> | |
18 | #include <linux/iio/buffer.h> | |
d430f3c3 | 19 | #include <linux/regmap.h> |
09a642b7 GG |
20 | #include <linux/iio/sysfs.h> |
21 | #include <linux/iio/kfifo_buf.h> | |
22 | #include <linux/iio/trigger.h> | |
23 | #include <linux/iio/triggered_buffer.h> | |
24 | #include <linux/iio/trigger_consumer.h> | |
25 | #include <linux/platform_data/invensense_mpu6050.h> | |
26 | ||
27 | /** | |
28 | * struct inv_mpu6050_reg_map - Notable registers. | |
29 | * @sample_rate_div: Divider applied to gyro output rate. | |
30 | * @lpf: Configures internal low pass filter. | |
31 | * @user_ctrl: Enables/resets the FIFO. | |
32 | * @fifo_en: Determines which data will appear in FIFO. | |
33 | * @gyro_config: gyro config register. | |
34 | * @accl_config: accel config register | |
35 | * @fifo_count_h: Upper byte of FIFO count. | |
36 | * @fifo_r_w: FIFO register. | |
37 | * @raw_gyro: Address of first gyro register. | |
38 | * @raw_accl: Address of first accel register. | |
39 | * @temperature: temperature register | |
40 | * @int_enable: Interrupt enable register. | |
41 | * @pwr_mgmt_1: Controls chip's power state and clock source. | |
42 | * @pwr_mgmt_2: Controls power state of individual sensors. | |
725f645d | 43 | * @int_pin_cfg; Controls interrupt pin configuration. |
d5098447 MR |
44 | * @accl_offset: Controls the accelerometer calibration offset. |
45 | * @gyro_offset: Controls the gyroscope calibration offset. | |
09a642b7 GG |
46 | */ |
47 | struct inv_mpu6050_reg_map { | |
48 | u8 sample_rate_div; | |
49 | u8 lpf; | |
50 | u8 user_ctrl; | |
51 | u8 fifo_en; | |
52 | u8 gyro_config; | |
53 | u8 accl_config; | |
54 | u8 fifo_count_h; | |
55 | u8 fifo_r_w; | |
56 | u8 raw_gyro; | |
57 | u8 raw_accl; | |
58 | u8 temperature; | |
59 | u8 int_enable; | |
60 | u8 pwr_mgmt_1; | |
61 | u8 pwr_mgmt_2; | |
3a2ecc3d | 62 | u8 int_pin_cfg; |
d5098447 MR |
63 | u8 accl_offset; |
64 | u8 gyro_offset; | |
09a642b7 GG |
65 | }; |
66 | ||
67 | /*device enum */ | |
68 | enum inv_devices { | |
69 | INV_MPU6050, | |
6f174fd3 | 70 | INV_MPU6500, |
fd64df16 | 71 | INV_MPU6000, |
fbced0e9 | 72 | INV_MPU9150, |
468c5620 | 73 | INV_ICM20608, |
09a642b7 GG |
74 | INV_NUM_PARTS |
75 | }; | |
76 | ||
77 | /** | |
78 | * struct inv_mpu6050_chip_config - Cached chip configuration data. | |
79 | * @fsr: Full scale range. | |
80 | * @lpf: Digital low pass filter frequency. | |
81 | * @accl_fs: accel full scale range. | |
82 | * @enable: master enable state. | |
83 | * @accl_fifo_enable: enable accel data output | |
84 | * @gyro_fifo_enable: enable gyro data output | |
85 | * @fifo_rate: FIFO update rate. | |
86 | */ | |
87 | struct inv_mpu6050_chip_config { | |
88 | unsigned int fsr:2; | |
89 | unsigned int lpf:3; | |
90 | unsigned int accl_fs:2; | |
91 | unsigned int enable:1; | |
92 | unsigned int accl_fifo_enable:1; | |
93 | unsigned int gyro_fifo_enable:1; | |
94 | u16 fifo_rate; | |
95 | }; | |
96 | ||
97 | /** | |
98 | * struct inv_mpu6050_hw - Other important hardware information. | |
cec01545 | 99 | * @whoami: Self identification byte from WHO_AM_I register |
09a642b7 GG |
100 | * @name: name of the chip. |
101 | * @reg: register map of the chip. | |
102 | * @config: configuration of the chip. | |
103 | */ | |
104 | struct inv_mpu6050_hw { | |
cec01545 | 105 | u8 whoami; |
09a642b7 GG |
106 | u8 *name; |
107 | const struct inv_mpu6050_reg_map *reg; | |
108 | const struct inv_mpu6050_chip_config *config; | |
109 | }; | |
110 | ||
111 | /* | |
112 | * struct inv_mpu6050_state - Driver state variables. | |
113 | * @TIMESTAMP_FIFO_SIZE: fifo size for timestamp. | |
114 | * @trig: IIO trigger. | |
115 | * @chip_config: Cached attribute information. | |
116 | * @reg: Map of important registers. | |
117 | * @hw: Other hardware-specific information. | |
118 | * @chip_type: chip type. | |
119 | * @time_stamp_lock: spin lock to time stamp. | |
eb379846 GB |
120 | * @plat_data: platform data (deprecated in favor of @orientation). |
121 | * @orientation: sensor chip orientation relative to main hardware. | |
09a642b7 | 122 | * @timestamps: kfifo queue to store time stamp. |
b3eea8da AR |
123 | * @map regmap pointer. |
124 | * @irq interrupt number. | |
09a642b7 GG |
125 | */ |
126 | struct inv_mpu6050_state { | |
127 | #define TIMESTAMP_FIFO_SIZE 16 | |
128 | struct iio_trigger *trig; | |
129 | struct inv_mpu6050_chip_config chip_config; | |
130 | const struct inv_mpu6050_reg_map *reg; | |
131 | const struct inv_mpu6050_hw *hw; | |
132 | enum inv_devices chip_type; | |
133 | spinlock_t time_stamp_lock; | |
51f97f6d | 134 | struct i2c_mux_core *muxc; |
a35c5d1a | 135 | struct i2c_client *mux_client; |
3a2ecc3d | 136 | unsigned int powerup_count; |
09a642b7 | 137 | struct inv_mpu6050_platform_data plat_data; |
eb379846 | 138 | struct iio_mount_matrix orientation; |
09a642b7 | 139 | DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE); |
d430f3c3 | 140 | struct regmap *map; |
b3eea8da | 141 | int irq; |
09a642b7 GG |
142 | }; |
143 | ||
144 | /*register and associated bit definition*/ | |
d5098447 MR |
145 | #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 |
146 | #define INV_MPU6050_REG_GYRO_OFFSET 0x13 | |
147 | ||
09a642b7 GG |
148 | #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 |
149 | #define INV_MPU6050_REG_CONFIG 0x1A | |
150 | #define INV_MPU6050_REG_GYRO_CONFIG 0x1B | |
7da773e6 | 151 | #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C |
09a642b7 GG |
152 | |
153 | #define INV_MPU6050_REG_FIFO_EN 0x23 | |
7da773e6 MS |
154 | #define INV_MPU6050_BIT_ACCEL_OUT 0x08 |
155 | #define INV_MPU6050_BITS_GYRO_OUT 0x70 | |
09a642b7 GG |
156 | |
157 | #define INV_MPU6050_REG_INT_ENABLE 0x38 | |
7da773e6 MS |
158 | #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 |
159 | #define INV_MPU6050_BIT_DMP_INT_EN 0x02 | |
09a642b7 GG |
160 | |
161 | #define INV_MPU6050_REG_RAW_ACCEL 0x3B | |
162 | #define INV_MPU6050_REG_TEMPERATURE 0x41 | |
163 | #define INV_MPU6050_REG_RAW_GYRO 0x43 | |
164 | ||
165 | #define INV_MPU6050_REG_USER_CTRL 0x6A | |
7da773e6 MS |
166 | #define INV_MPU6050_BIT_FIFO_RST 0x04 |
167 | #define INV_MPU6050_BIT_DMP_RST 0x08 | |
168 | #define INV_MPU6050_BIT_I2C_MST_EN 0x20 | |
169 | #define INV_MPU6050_BIT_FIFO_EN 0x40 | |
170 | #define INV_MPU6050_BIT_DMP_EN 0x80 | |
fd64df16 | 171 | #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 |
09a642b7 GG |
172 | |
173 | #define INV_MPU6050_REG_PWR_MGMT_1 0x6B | |
7da773e6 MS |
174 | #define INV_MPU6050_BIT_H_RESET 0x80 |
175 | #define INV_MPU6050_BIT_SLEEP 0x40 | |
176 | #define INV_MPU6050_BIT_CLK_MASK 0x7 | |
09a642b7 GG |
177 | |
178 | #define INV_MPU6050_REG_PWR_MGMT_2 0x6C | |
7da773e6 MS |
179 | #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 |
180 | #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 | |
09a642b7 GG |
181 | |
182 | #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 | |
183 | #define INV_MPU6050_REG_FIFO_R_W 0x74 | |
184 | ||
185 | #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 | |
186 | #define INV_MPU6050_FIFO_COUNT_BYTE 2 | |
187 | #define INV_MPU6050_FIFO_THRESHOLD 500 | |
8f356be3 | 188 | |
d5098447 MR |
189 | /* mpu6500 registers */ |
190 | #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 | |
191 | ||
8f356be3 | 192 | /* delay time in milliseconds */ |
09a642b7 GG |
193 | #define INV_MPU6050_POWER_UP_TIME 100 |
194 | #define INV_MPU6050_TEMP_UP_TIME 100 | |
195 | #define INV_MPU6050_SENSOR_UP_TIME 30 | |
8f356be3 MR |
196 | |
197 | /* delay time in microseconds */ | |
198 | #define INV_MPU6050_REG_UP_TIME_MIN 5000 | |
199 | #define INV_MPU6050_REG_UP_TIME_MAX 10000 | |
09a642b7 GG |
200 | |
201 | #define INV_MPU6050_TEMP_OFFSET 12421 | |
202 | #define INV_MPU6050_TEMP_SCALE 2941 | |
203 | #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 | |
204 | #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 | |
205 | #define INV_MPU6050_THREE_AXIS 3 | |
206 | #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 | |
207 | #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 | |
208 | ||
209 | /* 6 + 6 round up and plus 8 */ | |
210 | #define INV_MPU6050_OUTPUT_DATA_SIZE 24 | |
211 | ||
3a2ecc3d SP |
212 | #define INV_MPU6050_REG_INT_PIN_CFG 0x37 |
213 | #define INV_MPU6050_BIT_BYPASS_EN 0x2 | |
c278ac0e | 214 | #define INV_MPU6050_INT_PIN_CFG 0 |
3a2ecc3d | 215 | |
09a642b7 GG |
216 | /* init parameters */ |
217 | #define INV_MPU6050_INIT_FIFO_RATE 50 | |
7da773e6 MS |
218 | #define INV_MPU6050_TIME_STAMP_TOR 5 |
219 | #define INV_MPU6050_MAX_FIFO_RATE 1000 | |
220 | #define INV_MPU6050_MIN_FIFO_RATE 4 | |
221 | #define INV_MPU6050_ONE_K_HZ 1000 | |
09a642b7 | 222 | |
cec01545 CDL |
223 | #define INV_MPU6050_REG_WHOAMI 117 |
224 | ||
225 | #define INV_MPU6000_WHOAMI_VALUE 0x68 | |
226 | #define INV_MPU6050_WHOAMI_VALUE 0x68 | |
227 | #define INV_MPU6500_WHOAMI_VALUE 0x70 | |
fbced0e9 | 228 | #define INV_MPU9150_WHOAMI_VALUE 0x68 |
468c5620 | 229 | #define INV_ICM20608_WHOAMI_VALUE 0xAF |
cec01545 | 230 | |
09a642b7 GG |
231 | /* scan element definition */ |
232 | enum inv_mpu6050_scan { | |
233 | INV_MPU6050_SCAN_ACCL_X, | |
234 | INV_MPU6050_SCAN_ACCL_Y, | |
235 | INV_MPU6050_SCAN_ACCL_Z, | |
236 | INV_MPU6050_SCAN_GYRO_X, | |
237 | INV_MPU6050_SCAN_GYRO_Y, | |
238 | INV_MPU6050_SCAN_GYRO_Z, | |
239 | INV_MPU6050_SCAN_TIMESTAMP, | |
240 | }; | |
241 | ||
242 | enum inv_mpu6050_filter_e { | |
243 | INV_MPU6050_FILTER_256HZ_NOLPF2 = 0, | |
244 | INV_MPU6050_FILTER_188HZ, | |
245 | INV_MPU6050_FILTER_98HZ, | |
246 | INV_MPU6050_FILTER_42HZ, | |
247 | INV_MPU6050_FILTER_20HZ, | |
248 | INV_MPU6050_FILTER_10HZ, | |
249 | INV_MPU6050_FILTER_5HZ, | |
250 | INV_MPU6050_FILTER_2100HZ_NOLPF, | |
251 | NUM_MPU6050_FILTER | |
252 | }; | |
253 | ||
254 | /* IIO attribute address */ | |
255 | enum INV_MPU6050_IIO_ATTR_ADDR { | |
256 | ATTR_GYRO_MATRIX, | |
257 | ATTR_ACCL_MATRIX, | |
258 | }; | |
259 | ||
260 | enum inv_mpu6050_accl_fs_e { | |
261 | INV_MPU6050_FS_02G = 0, | |
262 | INV_MPU6050_FS_04G, | |
263 | INV_MPU6050_FS_08G, | |
264 | INV_MPU6050_FS_16G, | |
265 | NUM_ACCL_FSR | |
266 | }; | |
267 | ||
268 | enum inv_mpu6050_fsr_e { | |
269 | INV_MPU6050_FSR_250DPS = 0, | |
270 | INV_MPU6050_FSR_500DPS, | |
271 | INV_MPU6050_FSR_1000DPS, | |
272 | INV_MPU6050_FSR_2000DPS, | |
273 | NUM_MPU6050_FSR | |
274 | }; | |
275 | ||
276 | enum inv_mpu6050_clock_sel_e { | |
277 | INV_CLK_INTERNAL = 0, | |
278 | INV_CLK_PLL, | |
279 | NUM_CLK | |
280 | }; | |
281 | ||
282 | irqreturn_t inv_mpu6050_irq_handler(int irq, void *p); | |
283 | irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); | |
284 | int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev); | |
285 | void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st); | |
286 | int inv_reset_fifo(struct iio_dev *indio_dev); | |
287 | int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask); | |
288 | int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); | |
289 | int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); | |
b3eea8da AR |
290 | int inv_mpu_acpi_create_mux_client(struct i2c_client *client); |
291 | void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); | |
fd64df16 | 292 | int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, |
33da559f | 293 | int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); |
b3eea8da | 294 | int inv_mpu_core_remove(struct device *dev); |
fd64df16 | 295 | int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); |
b3eea8da | 296 | extern const struct dev_pm_ops inv_mpu_pmops; |