[linux-2.6-block.git] / drivers / iio / imu / inv_mpu6050 / inv_mpu_iio.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2012 Invensense, Inc.
*/
#include <linux/i2c.h>
#include <linux/i2c-mux.h>
#include <linux/mutex.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/regmap.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/kfifo_buf.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/platform_data/invensense_mpu6050.h>

/**
 *  struct inv_mpu6050_reg_map - Notable registers.
 *  @sample_rate_div:	Divider applied to gyro output rate.
 *  @lpf:		Configures internal low pass filter.
 *  @accel_lpf:		Configures accelerometer low pass filter.
 *  @user_ctrl:		Enables/resets the FIFO.
 *  @fifo_en:		Determines which data will appear in FIFO.
 *  @gyro_config:	gyro config register.
 *  @accl_config:	accel config register
 *  @fifo_count_h:	Upper byte of FIFO count.
 *  @fifo_r_w:		FIFO register.
 *  @raw_gyro:		Address of first gyro register.
 *  @raw_accl:		Address of first accel register.
 *  @temperature:	temperature register
 *  @int_enable:	Interrupt enable register.
 *  @int_status:	Interrupt status register.
 *  @pwr_mgmt_1:	Controls chip's power state and clock source.
 *  @pwr_mgmt_2:	Controls power state of individual sensors.
 *  @int_pin_cfg;	Controls interrupt pin configuration.
 *  @accl_offset:	Controls the accelerometer calibration offset.
 *  @gyro_offset:	Controls the gyroscope calibration offset.
 *  @i2c_if:		Controls the i2c interface
 */
struct inv_mpu6050_reg_map {
	u8 sample_rate_div;
	u8 lpf;
	u8 accel_lpf;
	u8 user_ctrl;
	u8 fifo_en;
	u8 gyro_config;
	u8 accl_config;
	u8 fifo_count_h;
	u8 fifo_r_w;
	u8 raw_gyro;
	u8 raw_accl;
	u8 temperature;
	u8 int_enable;
	u8 int_status;
	u8 pwr_mgmt_1;
	u8 pwr_mgmt_2;
	u8 int_pin_cfg;
	u8 accl_offset;
	u8 gyro_offset;
	u8 i2c_if;
};

/*device enum */
enum inv_devices {
	INV_MPU6050,
	INV_MPU6500,
	INV_MPU6515,
	INV_MPU6000,
	INV_MPU9150,
	INV_MPU9250,
	INV_MPU9255,
	INV_ICM20608,
	INV_ICM20602,
	INV_NUM_PARTS
};

/**
 *  struct inv_mpu6050_chip_config - Cached chip configuration data.
 *  @fsr:		Full scale range.
 *  @lpf:		Digital low pass filter frequency.
 *  @accl_fs:		accel full scale range.
 *  @accl_fifo_enable:	enable accel data output
 *  @gyro_fifo_enable:	enable gyro data output
 *  @divider:		chip sample rate divider (sample rate divider - 1)
 */
struct inv_mpu6050_chip_config {
	unsigned int fsr:2;
	unsigned int lpf:3;
	unsigned int accl_fs:2;
	unsigned int accl_fifo_enable:1;
	unsigned int gyro_fifo_enable:1;
	u8 divider;
	u8 user_ctrl;
};

/**
 *  struct inv_mpu6050_hw - Other important hardware information.
 *  @whoami:	Self identification byte from WHO_AM_I register
 *  @name:      name of the chip.
 *  @reg:   register map of the chip.
 *  @config:    configuration of the chip.
 */
struct inv_mpu6050_hw {
	u8 whoami;
	u8 *name;
	const struct inv_mpu6050_reg_map *reg;
	const struct inv_mpu6050_chip_config *config;
};

/*
 *  struct inv_mpu6050_state - Driver state variables.
 *  @lock:              Chip access lock.
 *  @trig:              IIO trigger.
 *  @chip_config:	Cached attribute information.
 *  @reg:		Map of important registers.
 *  @hw:		Other hardware-specific information.
 *  @chip_type:		chip type.
 *  @plat_data:		platform data (deprecated in favor of @orientation).
 *  @orientation:	sensor chip orientation relative to main hardware.
 *  @map		regmap pointer.
 *  @irq		interrupt number.
 *  @irq_mask		the int_pin_cfg mask to configure interrupt type.
 *  @chip_period:	chip internal period estimation (~1kHz).
 *  @it_timestamp:	timestamp from previous interrupt.
 *  @data_timestamp:	timestamp for next data sample.
 *  @vddio_supply	voltage regulator for the chip.
 */
struct inv_mpu6050_state {
	struct mutex lock;
	struct iio_trigger  *trig;
	struct inv_mpu6050_chip_config chip_config;
	const struct inv_mpu6050_reg_map *reg;
	const struct inv_mpu6050_hw *hw;
	enum   inv_devices chip_type;
	struct i2c_mux_core *muxc;
	struct i2c_client *mux_client;
	unsigned int powerup_count;
	struct inv_mpu6050_platform_data plat_data;
	struct iio_mount_matrix orientation;
	struct regmap *map;
	int irq;
	u8 irq_mask;
	unsigned skip_samples;
	s64 chip_period;
	s64 it_timestamp;
	s64 data_timestamp;
	struct regulator *vddio_supply;
};

/*register and associated bit definition*/
#define INV_MPU6050_REG_ACCEL_OFFSET        0x06
#define INV_MPU6050_REG_GYRO_OFFSET         0x13

#define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
#define INV_MPU6050_REG_CONFIG              0x1A
#define INV_MPU6050_REG_GYRO_CONFIG         0x1B
#define INV_MPU6050_REG_ACCEL_CONFIG        0x1C

#define INV_MPU6050_REG_FIFO_EN             0x23
#define INV_MPU6050_BIT_ACCEL_OUT           0x08
#define INV_MPU6050_BITS_GYRO_OUT           0x70

#define INV_MPU6050_REG_INT_ENABLE          0x38
#define INV_MPU6050_BIT_DATA_RDY_EN         0x01
#define INV_MPU6050_BIT_DMP_INT_EN          0x02

#define INV_MPU6050_REG_RAW_ACCEL           0x3B
#define INV_MPU6050_REG_TEMPERATURE         0x41
#define INV_MPU6050_REG_RAW_GYRO            0x43

#define INV_MPU6050_REG_INT_STATUS          0x3A
#define INV_MPU6050_BIT_FIFO_OVERFLOW_INT   0x10
#define INV_MPU6050_BIT_RAW_DATA_RDY_INT    0x01

#define INV_MPU6050_REG_USER_CTRL           0x6A
#define INV_MPU6050_BIT_FIFO_RST            0x04
#define INV_MPU6050_BIT_DMP_RST             0x08
#define INV_MPU6050_BIT_I2C_MST_EN          0x20
#define INV_MPU6050_BIT_FIFO_EN             0x40
#define INV_MPU6050_BIT_DMP_EN              0x80
#define INV_MPU6050_BIT_I2C_IF_DIS          0x10

#define INV_MPU6050_REG_PWR_MGMT_1          0x6B
#define INV_MPU6050_BIT_H_RESET             0x80
#define INV_MPU6050_BIT_SLEEP               0x40
#define INV_MPU6050_BIT_CLK_MASK            0x7

#define INV_MPU6050_REG_PWR_MGMT_2          0x6C
#define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
#define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07

/* ICM20602 register */
#define INV_ICM20602_REG_I2C_IF             0x70
#define INV_ICM20602_BIT_I2C_IF_DIS         0x40

#define INV_MPU6050_REG_FIFO_COUNT_H        0x72
#define INV_MPU6050_REG_FIFO_R_W            0x74

#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
#define INV_MPU6050_FIFO_COUNT_BYTE          2

/* ICM20602 FIFO samples include temperature readings */
#define INV_ICM20602_BYTES_PER_TEMP_SENSOR   2

/* mpu6500 registers */
#define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
#define INV_MPU6500_REG_ACCEL_OFFSET        0x77

/* delay time in milliseconds */
#define INV_MPU6050_POWER_UP_TIME            100
#define INV_MPU6050_TEMP_UP_TIME             100
#define INV_MPU6050_SENSOR_UP_TIME           30

/* delay time in microseconds */
#define INV_MPU6050_REG_UP_TIME_MIN          5000
#define INV_MPU6050_REG_UP_TIME_MAX          10000

#define INV_MPU6050_TEMP_OFFSET	             12421
#define INV_MPU6050_TEMP_SCALE               2941
#define INV_MPU6050_MAX_GYRO_FS_PARAM        3
#define INV_MPU6050_MAX_ACCL_FS_PARAM        3
#define INV_MPU6050_THREE_AXIS               3
#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3

#define INV_ICM20602_TEMP_OFFSET	     8170
#define INV_ICM20602_TEMP_SCALE		     3060

/* 6 + 6 round up and plus 8 */
#define INV_MPU6050_OUTPUT_DATA_SIZE         24

#define INV_MPU6050_REG_INT_PIN_CFG	0x37
#define INV_MPU6050_ACTIVE_HIGH		0x00
#define INV_MPU6050_ACTIVE_LOW		0x80
/* enable level triggering */
#define INV_MPU6050_LATCH_INT_EN	0x20
#define INV_MPU6050_BIT_BYPASS_EN	0x2

/* Allowed timestamp period jitter in percent */
#define INV_MPU6050_TS_PERIOD_JITTER	4

/* init parameters */
#define INV_MPU6050_INIT_FIFO_RATE           50
#define INV_MPU6050_MAX_FIFO_RATE            1000
#define INV_MPU6050_MIN_FIFO_RATE            4

/* chip internal frequency: 1KHz */
#define INV_MPU6050_INTERNAL_FREQ_HZ		1000
/* return the frequency divider (chip sample rate divider + 1) */
#define INV_MPU6050_FREQ_DIVIDER(st)					\
	((st)->chip_config.divider + 1)
/* chip sample rate divider to fifo rate */
#define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate)			\
	((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
#define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider)			\
	(INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))

#define INV_MPU6050_REG_WHOAMI			117

#define INV_MPU6000_WHOAMI_VALUE		0x68
#define INV_MPU6050_WHOAMI_VALUE		0x68
#define INV_MPU6500_WHOAMI_VALUE		0x70
#define INV_MPU9150_WHOAMI_VALUE		0x68
#define INV_MPU9250_WHOAMI_VALUE		0x71
#define INV_MPU9255_WHOAMI_VALUE		0x73
#define INV_MPU6515_WHOAMI_VALUE		0x74
#define INV_ICM20608_WHOAMI_VALUE		0xAF
#define INV_ICM20602_WHOAMI_VALUE		0x12

/* scan element definition for generic MPU6xxx devices */
enum inv_mpu6050_scan {
	INV_MPU6050_SCAN_ACCL_X,
	INV_MPU6050_SCAN_ACCL_Y,
	INV_MPU6050_SCAN_ACCL_Z,
	INV_MPU6050_SCAN_GYRO_X,
	INV_MPU6050_SCAN_GYRO_Y,
	INV_MPU6050_SCAN_GYRO_Z,
	INV_MPU6050_SCAN_TIMESTAMP,
};

/* scan element definition for ICM20602, which includes temperature */
enum inv_icm20602_scan {
	INV_ICM20602_SCAN_ACCL_X,
	INV_ICM20602_SCAN_ACCL_Y,
	INV_ICM20602_SCAN_ACCL_Z,
	INV_ICM20602_SCAN_TEMP,
	INV_ICM20602_SCAN_GYRO_X,
	INV_ICM20602_SCAN_GYRO_Y,
	INV_ICM20602_SCAN_GYRO_Z,
	INV_ICM20602_SCAN_TIMESTAMP,
};

enum inv_mpu6050_filter_e {
	INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
	INV_MPU6050_FILTER_188HZ,
	INV_MPU6050_FILTER_98HZ,
	INV_MPU6050_FILTER_42HZ,
	INV_MPU6050_FILTER_20HZ,
	INV_MPU6050_FILTER_10HZ,
	INV_MPU6050_FILTER_5HZ,
	INV_MPU6050_FILTER_2100HZ_NOLPF,
	NUM_MPU6050_FILTER
};

/* IIO attribute address */
enum INV_MPU6050_IIO_ATTR_ADDR {
	ATTR_GYRO_MATRIX,
	ATTR_ACCL_MATRIX,
};

enum inv_mpu6050_accl_fs_e {
	INV_MPU6050_FS_02G = 0,
	INV_MPU6050_FS_04G,
	INV_MPU6050_FS_08G,
	INV_MPU6050_FS_16G,
	NUM_ACCL_FSR
};

enum inv_mpu6050_fsr_e {
	INV_MPU6050_FSR_250DPS = 0,
	INV_MPU6050_FSR_500DPS,
	INV_MPU6050_FSR_1000DPS,
	INV_MPU6050_FSR_2000DPS,
	NUM_MPU6050_FSR
};

enum inv_mpu6050_clock_sel_e {
	INV_CLK_INTERNAL = 0,
	INV_CLK_PLL,
	NUM_CLK
};

irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
int inv_reset_fifo(struct iio_dev *indio_dev);
int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
		int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
extern const struct dev_pm_ops inv_mpu_pmops;
Commit	Line	Data
9c92ab61	1	/* SPDX-License-Identifier: GPL-2.0-only */
09a642b7 GG	2	/*
09a642b7 GG	3	* Copyright (C) 2012 Invensense, Inc.
09a642b7 GG	4	*/
09a642b7 GG	5	#include <linux/i2c.h>
51f97f6d	6	#include <linux/i2c-mux.h>
68cd6e5b	7	#include <linux/mutex.h>
09a642b7 GG	8	#include <linux/iio/iio.h>
09a642b7 GG	9	#include <linux/iio/buffer.h>
d430f3c3	10	#include <linux/regmap.h>
09a642b7 GG	11	#include <linux/iio/sysfs.h>
	12	#include <linux/iio/kfifo_buf.h>
	13	#include <linux/iio/trigger.h>
	14	#include <linux/iio/triggered_buffer.h>
	15	#include <linux/iio/trigger_consumer.h>
	16	#include <linux/platform_data/invensense_mpu6050.h>
	17
	18	/**
	19	* struct inv_mpu6050_reg_map - Notable registers.
	20	* @sample_rate_div: Divider applied to gyro output rate.
	21	* @lpf: Configures internal low pass filter.
948588e2	22	* @accel_lpf: Configures accelerometer low pass filter.
09a642b7 GG	23	* @user_ctrl: Enables/resets the FIFO.
	24	* @fifo_en: Determines which data will appear in FIFO.
	25	* @gyro_config: gyro config register.
	26	* @accl_config: accel config register
	27	* @fifo_count_h: Upper byte of FIFO count.
	28	* @fifo_r_w: FIFO register.
	29	* @raw_gyro: Address of first gyro register.
	30	* @raw_accl: Address of first accel register.
	31	* @temperature: temperature register
	32	* @int_enable: Interrupt enable register.
5ec6486d	33	* @int_status: Interrupt status register.
09a642b7 GG	34	* @pwr_mgmt_1: Controls chip's power state and clock source.
09a642b7 GG	35	* @pwr_mgmt_2: Controls power state of individual sensors.
725f645d	36	* @int_pin_cfg; Controls interrupt pin configuration.
d5098447 MR	37	* @accl_offset: Controls the accelerometer calibration offset.
d5098447 MR	38	* @gyro_offset: Controls the gyroscope calibration offset.
22904bdf	39	* @i2c_if: Controls the i2c interface
09a642b7 GG	40	*/
	41	struct inv_mpu6050_reg_map {
	42	u8 sample_rate_div;
	43	u8 lpf;
948588e2	44	u8 accel_lpf;
09a642b7 GG	45	u8 user_ctrl;
	46	u8 fifo_en;
	47	u8 gyro_config;
	48	u8 accl_config;
	49	u8 fifo_count_h;
	50	u8 fifo_r_w;
	51	u8 raw_gyro;
	52	u8 raw_accl;
	53	u8 temperature;
	54	u8 int_enable;
5ec6486d	55	u8 int_status;
09a642b7 GG	56	u8 pwr_mgmt_1;
09a642b7 GG	57	u8 pwr_mgmt_2;
3a2ecc3d	58	u8 int_pin_cfg;
d5098447 MR	59	u8 accl_offset;
d5098447 MR	60	u8 gyro_offset;
22904bdf	61	u8 i2c_if;
09a642b7 GG	62	};
	63
	64	/device enum /
	65	enum inv_devices {
	66	INV_MPU6050,
6f174fd3	67	INV_MPU6500,
de8df0b9	68	INV_MPU6515,
fd64df16	69	INV_MPU6000,
fbced0e9	70	INV_MPU9150,
0c8f492d	71	INV_MPU9250,
685cc61b	72	INV_MPU9255,
468c5620	73	INV_ICM20608,
22904bdf	74	INV_ICM20602,
09a642b7 GG	75	INV_NUM_PARTS
	76	};
	77
	78	/**
	79	* struct inv_mpu6050_chip_config - Cached chip configuration data.
	80	* @fsr: Full scale range.
	81	* @lpf: Digital low pass filter frequency.
	82	* @accl_fs: accel full scale range.
09a642b7 GG	83	* @accl_fifo_enable: enable accel data output
09a642b7 GG	84	* @gyro_fifo_enable: enable gyro data output
7b782508	85	* @divider: chip sample rate divider (sample rate divider - 1)
09a642b7 GG	86	*/
	87	struct inv_mpu6050_chip_config {
	88	unsigned int fsr:2;
	89	unsigned int lpf:3;
	90	unsigned int accl_fs:2;
09a642b7 GG	91	unsigned int accl_fifo_enable:1;
09a642b7 GG	92	unsigned int gyro_fifo_enable:1;
7b782508	93	u8 divider;
edddddd9	94	u8 user_ctrl;
09a642b7 GG	95	};
	96
	97	/**
	98	* struct inv_mpu6050_hw - Other important hardware information.
cec01545	99	* @whoami: Self identification byte from WHO_AM_I register
09a642b7 GG	100	* @name: name of the chip.
	101	* @reg: register map of the chip.
	102	* @config: configuration of the chip.
	103	*/
	104	struct inv_mpu6050_hw {
cec01545	105	u8 whoami;
09a642b7 GG	106	u8 *name;
	107	const struct inv_mpu6050_reg_map *reg;
	108	const struct inv_mpu6050_chip_config *config;
	109	};
	110
	111	/*
	112	* struct inv_mpu6050_state - Driver state variables.
68cd6e5b	113	* @lock: Chip access lock.
09a642b7 GG	114	* @trig: IIO trigger.
	115	* @chip_config: Cached attribute information.
	116	* @reg: Map of important registers.
	117	* @hw: Other hardware-specific information.
	118	* @chip_type: chip type.
eb379846 GB	119	* @plat_data: platform data (deprecated in favor of @orientation).
eb379846 GB	120	* @orientation: sensor chip orientation relative to main hardware.
b3eea8da AR	121	* @map regmap pointer.
b3eea8da AR	122	* @irq interrupt number.
5ec6486d	123	* @irq_mask the int_pin_cfg mask to configure interrupt type.
4bcc19f1 JBM	124	* @chip_period: chip internal period estimation (~1kHz).
	125	* @it_timestamp: timestamp from previous interrupt.
	126	* @data_timestamp: timestamp for next data sample.
07c12b1c	127	* @vddio_supply voltage regulator for the chip.
09a642b7 GG	128	*/
09a642b7 GG	129	struct inv_mpu6050_state {
68cd6e5b	130	struct mutex lock;
09a642b7 GG	131	struct iio_trigger *trig;
	132	struct inv_mpu6050_chip_config chip_config;
	133	const struct inv_mpu6050_reg_map *reg;
	134	const struct inv_mpu6050_hw *hw;
	135	enum inv_devices chip_type;
51f97f6d	136	struct i2c_mux_core *muxc;
a35c5d1a	137	struct i2c_client *mux_client;
3a2ecc3d	138	unsigned int powerup_count;
09a642b7	139	struct inv_mpu6050_platform_data plat_data;
eb379846	140	struct iio_mount_matrix orientation;
d430f3c3	141	struct regmap *map;
b3eea8da	142	int irq;
5ec6486d	143	u8 irq_mask;
c2b82a69	144	unsigned skip_samples;
4bcc19f1 JBM	145	s64 chip_period;
	146	s64 it_timestamp;
	147	s64 data_timestamp;
07c12b1c	148	struct regulator *vddio_supply;
09a642b7 GG	149	};
	150
	151	/register and associated bit definition/
d5098447 MR	152	#define INV_MPU6050_REG_ACCEL_OFFSET 0x06
	153	#define INV_MPU6050_REG_GYRO_OFFSET 0x13
	154
09a642b7 GG	155	#define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19
	156	#define INV_MPU6050_REG_CONFIG 0x1A
	157	#define INV_MPU6050_REG_GYRO_CONFIG 0x1B
7da773e6	158	#define INV_MPU6050_REG_ACCEL_CONFIG 0x1C
09a642b7 GG	159
09a642b7 GG	160	#define INV_MPU6050_REG_FIFO_EN 0x23
7da773e6 MS	161	#define INV_MPU6050_BIT_ACCEL_OUT 0x08
7da773e6 MS	162	#define INV_MPU6050_BITS_GYRO_OUT 0x70
09a642b7 GG	163
09a642b7 GG	164	#define INV_MPU6050_REG_INT_ENABLE 0x38
7da773e6 MS	165	#define INV_MPU6050_BIT_DATA_RDY_EN 0x01
7da773e6 MS	166	#define INV_MPU6050_BIT_DMP_INT_EN 0x02
09a642b7 GG	167
	168	#define INV_MPU6050_REG_RAW_ACCEL 0x3B
	169	#define INV_MPU6050_REG_TEMPERATURE 0x41
	170	#define INV_MPU6050_REG_RAW_GYRO 0x43
	171
5ec6486d	172	#define INV_MPU6050_REG_INT_STATUS 0x3A
f5057e7b	173	#define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10
5ec6486d MK	174	#define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01
5ec6486d MK	175
09a642b7	176	#define INV_MPU6050_REG_USER_CTRL 0x6A
7da773e6 MS	177	#define INV_MPU6050_BIT_FIFO_RST 0x04
	178	#define INV_MPU6050_BIT_DMP_RST 0x08
	179	#define INV_MPU6050_BIT_I2C_MST_EN 0x20
	180	#define INV_MPU6050_BIT_FIFO_EN 0x40
	181	#define INV_MPU6050_BIT_DMP_EN 0x80
fd64df16	182	#define INV_MPU6050_BIT_I2C_IF_DIS 0x10
09a642b7 GG	183
09a642b7 GG	184	#define INV_MPU6050_REG_PWR_MGMT_1 0x6B
7da773e6 MS	185	#define INV_MPU6050_BIT_H_RESET 0x80
	186	#define INV_MPU6050_BIT_SLEEP 0x40
	187	#define INV_MPU6050_BIT_CLK_MASK 0x7
09a642b7 GG	188
09a642b7 GG	189	#define INV_MPU6050_REG_PWR_MGMT_2 0x6C
7da773e6 MS	190	#define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38
7da773e6 MS	191	#define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07
09a642b7	192
22904bdf RM	193	/* ICM20602 register */
	194	#define INV_ICM20602_REG_I2C_IF 0x70
	195	#define INV_ICM20602_BIT_I2C_IF_DIS 0x40
	196
09a642b7 GG	197	#define INV_MPU6050_REG_FIFO_COUNT_H 0x72
	198	#define INV_MPU6050_REG_FIFO_R_W 0x74
	199
	200	#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6
	201	#define INV_MPU6050_FIFO_COUNT_BYTE 2
8f356be3	202
1615fe41 SM	203	/* ICM20602 FIFO samples include temperature readings */
	204	#define INV_ICM20602_BYTES_PER_TEMP_SENSOR 2
	205
d5098447	206	/* mpu6500 registers */
948588e2	207	#define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D
d5098447 MR	208	#define INV_MPU6500_REG_ACCEL_OFFSET 0x77
d5098447 MR	209
8f356be3	210	/* delay time in milliseconds */
09a642b7 GG	211	#define INV_MPU6050_POWER_UP_TIME 100
	212	#define INV_MPU6050_TEMP_UP_TIME 100
	213	#define INV_MPU6050_SENSOR_UP_TIME 30
8f356be3 MR	214
	215	/* delay time in microseconds */
	216	#define INV_MPU6050_REG_UP_TIME_MIN 5000
	217	#define INV_MPU6050_REG_UP_TIME_MAX 10000
09a642b7 GG	218
	219	#define INV_MPU6050_TEMP_OFFSET 12421
	220	#define INV_MPU6050_TEMP_SCALE 2941
	221	#define INV_MPU6050_MAX_GYRO_FS_PARAM 3
	222	#define INV_MPU6050_MAX_ACCL_FS_PARAM 3
	223	#define INV_MPU6050_THREE_AXIS 3
	224	#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3
	225	#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3
	226
1615fe41 SM	227	#define INV_ICM20602_TEMP_OFFSET 8170
	228	#define INV_ICM20602_TEMP_SCALE 3060
	229
09a642b7 GG	230	/* 6 + 6 round up and plus 8 */
	231	#define INV_MPU6050_OUTPUT_DATA_SIZE 24
	232
3a2ecc3d	233	#define INV_MPU6050_REG_INT_PIN_CFG 0x37
5ec6486d MK	234	#define INV_MPU6050_ACTIVE_HIGH 0x00
	235	#define INV_MPU6050_ACTIVE_LOW 0x80
	236	/* enable level triggering */
	237	#define INV_MPU6050_LATCH_INT_EN 0x20
3a2ecc3d	238	#define INV_MPU6050_BIT_BYPASS_EN 0x2
5ec6486d	239
4bcc19f1 JBM	240	/* Allowed timestamp period jitter in percent */
4bcc19f1 JBM	241	#define INV_MPU6050_TS_PERIOD_JITTER 4
3a2ecc3d	242
09a642b7 GG	243	/* init parameters */
09a642b7 GG	244	#define INV_MPU6050_INIT_FIFO_RATE 50
7da773e6 MS	245	#define INV_MPU6050_MAX_FIFO_RATE 1000
7da773e6 MS	246	#define INV_MPU6050_MIN_FIFO_RATE 4
7b782508 JBM	247
	248	/* chip internal frequency: 1KHz */
	249	#define INV_MPU6050_INTERNAL_FREQ_HZ 1000
	250	/* return the frequency divider (chip sample rate divider + 1) */
	251	#define INV_MPU6050_FREQ_DIVIDER(st) \
	252	((st)->chip_config.divider + 1)
	253	/* chip sample rate divider to fifo rate */
	254	#define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \
	255	((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
	256	#define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \
	257	(INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
09a642b7	258
cec01545 CDL	259	#define INV_MPU6050_REG_WHOAMI 117
	260
	261	#define INV_MPU6000_WHOAMI_VALUE 0x68
	262	#define INV_MPU6050_WHOAMI_VALUE 0x68
	263	#define INV_MPU6500_WHOAMI_VALUE 0x70
fbced0e9	264	#define INV_MPU9150_WHOAMI_VALUE 0x68
0c8f492d	265	#define INV_MPU9250_WHOAMI_VALUE 0x71
685cc61b	266	#define INV_MPU9255_WHOAMI_VALUE 0x73
de8df0b9	267	#define INV_MPU6515_WHOAMI_VALUE 0x74
468c5620	268	#define INV_ICM20608_WHOAMI_VALUE 0xAF
22904bdf	269	#define INV_ICM20602_WHOAMI_VALUE 0x12
cec01545	270
1615fe41	271	/* scan element definition for generic MPU6xxx devices */
09a642b7 GG	272	enum inv_mpu6050_scan {
	273	INV_MPU6050_SCAN_ACCL_X,
	274	INV_MPU6050_SCAN_ACCL_Y,
	275	INV_MPU6050_SCAN_ACCL_Z,
	276	INV_MPU6050_SCAN_GYRO_X,
	277	INV_MPU6050_SCAN_GYRO_Y,
	278	INV_MPU6050_SCAN_GYRO_Z,
	279	INV_MPU6050_SCAN_TIMESTAMP,
	280	};
	281
1615fe41 SM	282	/* scan element definition for ICM20602, which includes temperature */
	283	enum inv_icm20602_scan {
	284	INV_ICM20602_SCAN_ACCL_X,
	285	INV_ICM20602_SCAN_ACCL_Y,
	286	INV_ICM20602_SCAN_ACCL_Z,
	287	INV_ICM20602_SCAN_TEMP,
	288	INV_ICM20602_SCAN_GYRO_X,
	289	INV_ICM20602_SCAN_GYRO_Y,
	290	INV_ICM20602_SCAN_GYRO_Z,
	291	INV_ICM20602_SCAN_TIMESTAMP,
	292	};
	293
09a642b7 GG	294	enum inv_mpu6050_filter_e {
	295	INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
	296	INV_MPU6050_FILTER_188HZ,
	297	INV_MPU6050_FILTER_98HZ,
	298	INV_MPU6050_FILTER_42HZ,
	299	INV_MPU6050_FILTER_20HZ,
	300	INV_MPU6050_FILTER_10HZ,
	301	INV_MPU6050_FILTER_5HZ,
	302	INV_MPU6050_FILTER_2100HZ_NOLPF,
	303	NUM_MPU6050_FILTER
	304	};
	305
	306	/* IIO attribute address */
	307	enum INV_MPU6050_IIO_ATTR_ADDR {
	308	ATTR_GYRO_MATRIX,
	309	ATTR_ACCL_MATRIX,
	310	};
	311
	312	enum inv_mpu6050_accl_fs_e {
	313	INV_MPU6050_FS_02G = 0,
	314	INV_MPU6050_FS_04G,
	315	INV_MPU6050_FS_08G,
	316	INV_MPU6050_FS_16G,
	317	NUM_ACCL_FSR
	318	};
	319
	320	enum inv_mpu6050_fsr_e {
	321	INV_MPU6050_FSR_250DPS = 0,
	322	INV_MPU6050_FSR_500DPS,
	323	INV_MPU6050_FSR_1000DPS,
	324	INV_MPU6050_FSR_2000DPS,
	325	NUM_MPU6050_FSR
	326	};
	327
	328	enum inv_mpu6050_clock_sel_e {
	329	INV_CLK_INTERNAL = 0,
	330	INV_CLK_PLL,
	331	NUM_CLK
	332	};
	333
09a642b7	334	irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
5ec6486d	335	int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
09a642b7 GG	336	int inv_reset_fifo(struct iio_dev *indio_dev);
	337	int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
	338	int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
	339	int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
b3eea8da AR	340	int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
b3eea8da AR	341	void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
fd64df16	342	int inv_mpu_core_probe(struct regmap regmap, int irq, const char name,
33da559f	343	int (inv_mpu_bus_setup)(struct iio_dev ), int chip_type);
b3eea8da	344	extern const struct dev_pm_ops inv_mpu_pmops;