Commit | Line | Data |
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e31166f0 MH |
1 | /* |
2 | * ADF4350/ADF4351 SPI Wideband Synthesizer driver | |
3 | * | |
4 | * Copyright 2012 Analog Devices Inc. | |
5 | * | |
6 | * Licensed under the GPL-2. | |
7 | */ | |
8 | ||
9 | #include <linux/device.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/sysfs.h> | |
13 | #include <linux/spi/spi.h> | |
14 | #include <linux/regulator/consumer.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/gcd.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <asm/div64.h> | |
20 | ||
21 | #include <linux/iio/iio.h> | |
22 | #include <linux/iio/sysfs.h> | |
23 | #include <linux/iio/frequency/adf4350.h> | |
24 | ||
25 | enum { | |
26 | ADF4350_FREQ, | |
27 | ADF4350_FREQ_REFIN, | |
28 | ADF4350_FREQ_RESOLUTION, | |
29 | ADF4350_PWRDOWN, | |
30 | }; | |
31 | ||
32 | struct adf4350_state { | |
33 | struct spi_device *spi; | |
34 | struct regulator *reg; | |
35 | struct adf4350_platform_data *pdata; | |
36 | unsigned long clkin; | |
37 | unsigned long chspc; /* Channel Spacing */ | |
38 | unsigned long fpfd; /* Phase Frequency Detector */ | |
39 | unsigned long min_out_freq; | |
40 | unsigned r0_fract; | |
41 | unsigned r0_int; | |
42 | unsigned r1_mod; | |
43 | unsigned r4_rf_div_sel; | |
44 | unsigned long regs[6]; | |
45 | unsigned long regs_hw[6]; | |
46 | ||
47 | /* | |
48 | * DMA (thus cache coherency maintenance) requires the | |
49 | * transfer buffers to live in their own cache lines. | |
50 | */ | |
51 | __be32 val ____cacheline_aligned; | |
52 | }; | |
53 | ||
54 | static struct adf4350_platform_data default_pdata = { | |
55 | .clkin = 122880000, | |
56 | .channel_spacing = 10000, | |
e86ee142 | 57 | .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS | |
e31166f0 MH |
58 | ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500), |
59 | .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0), | |
60 | .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) | | |
61 | ADF4350_REG4_MUTE_TILL_LOCK_EN, | |
62 | .gpio_lock_detect = -1, | |
63 | }; | |
64 | ||
65 | static int adf4350_sync_config(struct adf4350_state *st) | |
66 | { | |
67 | int ret, i, doublebuf = 0; | |
68 | ||
69 | for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { | |
70 | if ((st->regs_hw[i] != st->regs[i]) || | |
71 | ((i == ADF4350_REG0) && doublebuf)) { | |
72 | ||
73 | switch (i) { | |
74 | case ADF4350_REG1: | |
75 | case ADF4350_REG4: | |
76 | doublebuf = 1; | |
77 | break; | |
78 | } | |
79 | ||
80 | st->val = cpu_to_be32(st->regs[i] | i); | |
81 | ret = spi_write(st->spi, &st->val, 4); | |
82 | if (ret < 0) | |
83 | return ret; | |
84 | st->regs_hw[i] = st->regs[i]; | |
85 | dev_dbg(&st->spi->dev, "[%d] 0x%X\n", | |
86 | i, (u32)st->regs[i] | i); | |
87 | } | |
88 | } | |
89 | return 0; | |
90 | } | |
91 | ||
92 | static int adf4350_reg_access(struct iio_dev *indio_dev, | |
93 | unsigned reg, unsigned writeval, | |
94 | unsigned *readval) | |
95 | { | |
96 | struct adf4350_state *st = iio_priv(indio_dev); | |
97 | int ret; | |
98 | ||
99 | if (reg > ADF4350_REG5) | |
100 | return -EINVAL; | |
101 | ||
102 | mutex_lock(&indio_dev->mlock); | |
103 | if (readval == NULL) { | |
104 | st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); | |
105 | ret = adf4350_sync_config(st); | |
106 | } else { | |
107 | *readval = st->regs_hw[reg]; | |
108 | ret = 0; | |
109 | } | |
110 | mutex_unlock(&indio_dev->mlock); | |
111 | ||
112 | return ret; | |
113 | } | |
114 | ||
115 | static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt) | |
116 | { | |
117 | struct adf4350_platform_data *pdata = st->pdata; | |
118 | ||
119 | do { | |
120 | r_cnt++; | |
121 | st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) / | |
122 | (r_cnt * (pdata->ref_div2_en ? 2 : 1)); | |
123 | } while (st->fpfd > ADF4350_MAX_FREQ_PFD); | |
124 | ||
125 | return r_cnt; | |
126 | } | |
127 | ||
128 | static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) | |
129 | { | |
130 | struct adf4350_platform_data *pdata = st->pdata; | |
131 | u64 tmp; | |
8857df3a | 132 | u32 div_gcd, prescaler, chspc; |
e31166f0 MH |
133 | u16 mdiv, r_cnt = 0; |
134 | u8 band_sel_div; | |
135 | ||
136 | if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq) | |
137 | return -EINVAL; | |
138 | ||
139 | if (freq > ADF4350_MAX_FREQ_45_PRESC) { | |
140 | prescaler = ADF4350_REG1_PRESCALER; | |
141 | mdiv = 75; | |
142 | } else { | |
143 | prescaler = 0; | |
144 | mdiv = 23; | |
145 | } | |
146 | ||
147 | st->r4_rf_div_sel = 0; | |
148 | ||
149 | while (freq < ADF4350_MIN_VCO_FREQ) { | |
150 | freq <<= 1; | |
151 | st->r4_rf_div_sel++; | |
152 | } | |
153 | ||
154 | /* | |
155 | * Allow a predefined reference division factor | |
156 | * if not set, compute our own | |
157 | */ | |
158 | if (pdata->ref_div_factor) | |
159 | r_cnt = pdata->ref_div_factor - 1; | |
160 | ||
8857df3a | 161 | chspc = st->chspc; |
e31166f0 | 162 | |
8857df3a MH |
163 | do { |
164 | do { | |
165 | do { | |
166 | r_cnt = adf4350_tune_r_cnt(st, r_cnt); | |
167 | st->r1_mod = st->fpfd / chspc; | |
168 | if (r_cnt > ADF4350_MAX_R_CNT) { | |
169 | /* try higher spacing values */ | |
170 | chspc++; | |
171 | r_cnt = 0; | |
172 | } | |
173 | } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt); | |
174 | } while (r_cnt == 0); | |
e31166f0 | 175 | |
1690970d | 176 | tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1); |
e31166f0 MH |
177 | do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */ |
178 | st->r0_fract = do_div(tmp, st->r1_mod); | |
179 | st->r0_int = tmp; | |
180 | } while (mdiv > st->r0_int); | |
181 | ||
182 | band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK); | |
183 | ||
184 | if (st->r0_fract && st->r1_mod) { | |
185 | div_gcd = gcd(st->r1_mod, st->r0_fract); | |
186 | st->r1_mod /= div_gcd; | |
187 | st->r0_fract /= div_gcd; | |
188 | } else { | |
189 | st->r0_fract = 0; | |
190 | st->r1_mod = 1; | |
191 | } | |
192 | ||
193 | dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n" | |
194 | "REF_DIV %d, R0_INT %d, R0_FRACT %d\n" | |
195 | "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n", | |
196 | freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod, | |
197 | 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5", | |
198 | band_sel_div); | |
199 | ||
200 | st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) | | |
201 | ADF4350_REG0_FRACT(st->r0_fract); | |
202 | ||
8857df3a | 203 | st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) | |
e31166f0 MH |
204 | ADF4350_REG1_MOD(st->r1_mod) | |
205 | prescaler; | |
206 | ||
207 | st->regs[ADF4350_REG2] = | |
208 | ADF4350_REG2_10BIT_R_CNT(r_cnt) | | |
209 | ADF4350_REG2_DOUBLE_BUFF_EN | | |
210 | (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) | | |
211 | (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) | | |
212 | (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS | | |
213 | ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N | | |
214 | ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) | | |
2eb3a81e | 215 | ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3))); |
e31166f0 MH |
216 | |
217 | st->regs[ADF4350_REG3] = pdata->r3_user_settings & | |
218 | (ADF4350_REG3_12BIT_CLKDIV(0xFFF) | | |
219 | ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) | | |
220 | ADF4350_REG3_12BIT_CSR_EN | | |
221 | ADF4351_REG3_CHARGE_CANCELLATION_EN | | |
222 | ADF4351_REG3_ANTI_BACKLASH_3ns_EN | | |
223 | ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH); | |
224 | ||
225 | st->regs[ADF4350_REG4] = | |
226 | ADF4350_REG4_FEEDBACK_FUND | | |
227 | ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) | | |
228 | ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) | | |
229 | ADF4350_REG4_RF_OUT_EN | | |
230 | (pdata->r4_user_settings & | |
231 | (ADF4350_REG4_OUTPUT_PWR(0x3) | | |
232 | ADF4350_REG4_AUX_OUTPUT_PWR(0x3) | | |
233 | ADF4350_REG4_AUX_OUTPUT_EN | | |
234 | ADF4350_REG4_AUX_OUTPUT_FUND | | |
235 | ADF4350_REG4_MUTE_TILL_LOCK_EN)); | |
236 | ||
237 | st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL; | |
238 | ||
239 | return adf4350_sync_config(st); | |
240 | } | |
241 | ||
242 | static ssize_t adf4350_write(struct iio_dev *indio_dev, | |
243 | uintptr_t private, | |
244 | const struct iio_chan_spec *chan, | |
245 | const char *buf, size_t len) | |
246 | { | |
247 | struct adf4350_state *st = iio_priv(indio_dev); | |
248 | unsigned long long readin; | |
249 | int ret; | |
250 | ||
251 | ret = kstrtoull(buf, 10, &readin); | |
252 | if (ret) | |
253 | return ret; | |
254 | ||
255 | mutex_lock(&indio_dev->mlock); | |
256 | switch ((u32)private) { | |
257 | case ADF4350_FREQ: | |
258 | ret = adf4350_set_freq(st, readin); | |
259 | break; | |
260 | case ADF4350_FREQ_REFIN: | |
261 | if (readin > ADF4350_MAX_FREQ_REFIN) | |
262 | ret = -EINVAL; | |
263 | else | |
264 | st->clkin = readin; | |
265 | break; | |
266 | case ADF4350_FREQ_RESOLUTION: | |
267 | if (readin == 0) | |
268 | ret = -EINVAL; | |
269 | else | |
270 | st->chspc = readin; | |
271 | break; | |
272 | case ADF4350_PWRDOWN: | |
273 | if (readin) | |
274 | st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; | |
275 | else | |
276 | st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN; | |
277 | ||
278 | adf4350_sync_config(st); | |
279 | break; | |
280 | default: | |
1a135d1a | 281 | ret = -EINVAL; |
e31166f0 MH |
282 | } |
283 | mutex_unlock(&indio_dev->mlock); | |
284 | ||
285 | return ret ? ret : len; | |
286 | } | |
287 | ||
288 | static ssize_t adf4350_read(struct iio_dev *indio_dev, | |
289 | uintptr_t private, | |
290 | const struct iio_chan_spec *chan, | |
291 | char *buf) | |
292 | { | |
293 | struct adf4350_state *st = iio_priv(indio_dev); | |
294 | unsigned long long val; | |
295 | int ret = 0; | |
296 | ||
297 | mutex_lock(&indio_dev->mlock); | |
298 | switch ((u32)private) { | |
299 | case ADF4350_FREQ: | |
300 | val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) * | |
301 | (u64)st->fpfd; | |
302 | do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel)); | |
303 | /* PLL unlocked? return error */ | |
304 | if (gpio_is_valid(st->pdata->gpio_lock_detect)) | |
305 | if (!gpio_get_value(st->pdata->gpio_lock_detect)) { | |
306 | dev_dbg(&st->spi->dev, "PLL un-locked\n"); | |
307 | ret = -EBUSY; | |
308 | } | |
309 | break; | |
310 | case ADF4350_FREQ_REFIN: | |
311 | val = st->clkin; | |
312 | break; | |
313 | case ADF4350_FREQ_RESOLUTION: | |
314 | val = st->chspc; | |
315 | break; | |
316 | case ADF4350_PWRDOWN: | |
317 | val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); | |
318 | break; | |
a21e6bfe | 319 | default: |
1a135d1a | 320 | ret = -EINVAL; |
e31166f0 MH |
321 | } |
322 | mutex_unlock(&indio_dev->mlock); | |
323 | ||
324 | return ret < 0 ? ret : sprintf(buf, "%llu\n", val); | |
325 | } | |
326 | ||
327 | #define _ADF4350_EXT_INFO(_name, _ident) { \ | |
328 | .name = _name, \ | |
329 | .read = adf4350_read, \ | |
330 | .write = adf4350_write, \ | |
331 | .private = _ident, \ | |
332 | } | |
333 | ||
334 | static const struct iio_chan_spec_ext_info adf4350_ext_info[] = { | |
335 | /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are | |
336 | * values > 2^32 in order to support the entire frequency range | |
337 | * in Hz. Using scale is a bit ugly. | |
338 | */ | |
339 | _ADF4350_EXT_INFO("frequency", ADF4350_FREQ), | |
340 | _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION), | |
341 | _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN), | |
342 | _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN), | |
343 | { }, | |
344 | }; | |
345 | ||
346 | static const struct iio_chan_spec adf4350_chan = { | |
347 | .type = IIO_ALTVOLTAGE, | |
348 | .indexed = 1, | |
349 | .output = 1, | |
350 | .ext_info = adf4350_ext_info, | |
351 | }; | |
352 | ||
353 | static const struct iio_info adf4350_info = { | |
354 | .debugfs_reg_access = &adf4350_reg_access, | |
355 | .driver_module = THIS_MODULE, | |
356 | }; | |
357 | ||
fc52692c | 358 | static int adf4350_probe(struct spi_device *spi) |
e31166f0 MH |
359 | { |
360 | struct adf4350_platform_data *pdata = spi->dev.platform_data; | |
361 | struct iio_dev *indio_dev; | |
362 | struct adf4350_state *st; | |
363 | int ret; | |
364 | ||
365 | if (!pdata) { | |
366 | dev_warn(&spi->dev, "no platform data? using default\n"); | |
367 | ||
368 | pdata = &default_pdata; | |
369 | } | |
370 | ||
371 | indio_dev = iio_device_alloc(sizeof(*st)); | |
372 | if (indio_dev == NULL) | |
373 | return -ENOMEM; | |
374 | ||
375 | st = iio_priv(indio_dev); | |
376 | ||
377 | st->reg = regulator_get(&spi->dev, "vcc"); | |
378 | if (!IS_ERR(st->reg)) { | |
379 | ret = regulator_enable(st->reg); | |
380 | if (ret) | |
381 | goto error_put_reg; | |
382 | } | |
383 | ||
384 | spi_set_drvdata(spi, indio_dev); | |
385 | st->spi = spi; | |
386 | st->pdata = pdata; | |
387 | ||
388 | indio_dev->dev.parent = &spi->dev; | |
389 | indio_dev->name = (pdata->name[0] != 0) ? pdata->name : | |
390 | spi_get_device_id(spi)->name; | |
391 | ||
392 | indio_dev->info = &adf4350_info; | |
393 | indio_dev->modes = INDIO_DIRECT_MODE; | |
394 | indio_dev->channels = &adf4350_chan; | |
395 | indio_dev->num_channels = 1; | |
396 | ||
397 | st->chspc = pdata->channel_spacing; | |
398 | st->clkin = pdata->clkin; | |
399 | ||
400 | st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ? | |
401 | ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ; | |
402 | ||
403 | memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); | |
404 | ||
405 | if (gpio_is_valid(pdata->gpio_lock_detect)) { | |
406 | ret = gpio_request(pdata->gpio_lock_detect, indio_dev->name); | |
407 | if (ret) { | |
408 | dev_err(&spi->dev, "fail to request lock detect GPIO-%d", | |
409 | pdata->gpio_lock_detect); | |
410 | goto error_disable_reg; | |
411 | } | |
412 | gpio_direction_input(pdata->gpio_lock_detect); | |
413 | } | |
414 | ||
415 | if (pdata->power_up_frequency) { | |
416 | ret = adf4350_set_freq(st, pdata->power_up_frequency); | |
417 | if (ret) | |
418 | goto error_free_gpio; | |
419 | } | |
420 | ||
421 | ret = iio_device_register(indio_dev); | |
422 | if (ret) | |
423 | goto error_free_gpio; | |
424 | ||
425 | return 0; | |
426 | ||
427 | error_free_gpio: | |
428 | if (gpio_is_valid(pdata->gpio_lock_detect)) | |
429 | gpio_free(pdata->gpio_lock_detect); | |
430 | ||
431 | error_disable_reg: | |
432 | if (!IS_ERR(st->reg)) | |
433 | regulator_disable(st->reg); | |
434 | error_put_reg: | |
435 | if (!IS_ERR(st->reg)) | |
436 | regulator_put(st->reg); | |
437 | ||
438 | iio_device_free(indio_dev); | |
439 | ||
440 | return ret; | |
441 | } | |
442 | ||
fc52692c | 443 | static int adf4350_remove(struct spi_device *spi) |
e31166f0 MH |
444 | { |
445 | struct iio_dev *indio_dev = spi_get_drvdata(spi); | |
446 | struct adf4350_state *st = iio_priv(indio_dev); | |
447 | struct regulator *reg = st->reg; | |
448 | ||
449 | st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; | |
450 | adf4350_sync_config(st); | |
451 | ||
452 | iio_device_unregister(indio_dev); | |
453 | ||
454 | if (!IS_ERR(reg)) { | |
455 | regulator_disable(reg); | |
456 | regulator_put(reg); | |
457 | } | |
458 | ||
459 | if (gpio_is_valid(st->pdata->gpio_lock_detect)) | |
460 | gpio_free(st->pdata->gpio_lock_detect); | |
461 | ||
462 | iio_device_free(indio_dev); | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static const struct spi_device_id adf4350_id[] = { | |
468 | {"adf4350", 4350}, | |
469 | {"adf4351", 4351}, | |
470 | {} | |
471 | }; | |
472 | ||
473 | static struct spi_driver adf4350_driver = { | |
474 | .driver = { | |
475 | .name = "adf4350", | |
476 | .owner = THIS_MODULE, | |
477 | }, | |
478 | .probe = adf4350_probe, | |
fc52692c | 479 | .remove = adf4350_remove, |
e31166f0 MH |
480 | .id_table = adf4350_id, |
481 | }; | |
482 | module_spi_driver(adf4350_driver); | |
483 | ||
484 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); | |
485 | MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL"); | |
486 | MODULE_LICENSE("GPL v2"); |