[linux-block.git] / drivers / iio / frequency / adf4350.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * ADF4350/ADF4351 SPI Wideband Synthesizer driver
 *
 * Copyright 2012-2013 Analog Devices Inc.
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/gcd.h>
#include <linux/gpio/consumer.h>
#include <asm/div64.h>
#include <linux/clk.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/frequency/adf4350.h>

enum {
	ADF4350_FREQ,
	ADF4350_FREQ_REFIN,
	ADF4350_FREQ_RESOLUTION,
	ADF4350_PWRDOWN,
};

struct adf4350_state {
	struct spi_device		*spi;
	struct regulator		*reg;
	struct gpio_desc		*lock_detect_gpiod;
	struct adf4350_platform_data	*pdata;
	struct clk			*clk;
	unsigned long			clkin;
	unsigned long			chspc; /* Channel Spacing */
	unsigned long			fpfd; /* Phase Frequency Detector */
	unsigned long			min_out_freq;
	unsigned			r0_fract;
	unsigned			r0_int;
	unsigned			r1_mod;
	unsigned			r4_rf_div_sel;
	unsigned long			regs[6];
	unsigned long			regs_hw[6];
	unsigned long long		freq_req;
	/*
	 * Lock to protect the state of the device from potential concurrent
	 * writes. The device is configured via a sequence of SPI writes,
	 * and this lock is meant to prevent the start of another sequence
	 * before another one has finished.
	 */
	struct mutex			lock;
	/*
	 * DMA (thus cache coherency maintenance) may require that
	 * transfer buffers live in their own cache lines.
	 */
	__be32				val __aligned(IIO_DMA_MINALIGN);
};

static struct adf4350_platform_data default_pdata = {
	.channel_spacing = 10000,
	.r2_user_settings = ADF4350_REG2_PD_POLARITY_POS |
			    ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
	.r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
	.r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) |
			    ADF4350_REG4_MUTE_TILL_LOCK_EN,
};

static int adf4350_sync_config(struct adf4350_state *st)
{
	int ret, i, doublebuf = 0;

	for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
		if ((st->regs_hw[i] != st->regs[i]) ||
			((i == ADF4350_REG0) && doublebuf)) {
			switch (i) {
			case ADF4350_REG1:
			case ADF4350_REG4:
				doublebuf = 1;
				break;
			}

			st->val  = cpu_to_be32(st->regs[i] | i);
			ret = spi_write(st->spi, &st->val, 4);
			if (ret < 0)
				return ret;
			st->regs_hw[i] = st->regs[i];
			dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
				i, (u32)st->regs[i] | i);
		}
	}
	return 0;
}

static int adf4350_reg_access(struct iio_dev *indio_dev,
			      unsigned reg, unsigned writeval,
			      unsigned *readval)
{
	struct adf4350_state *st = iio_priv(indio_dev);
	int ret;

	if (reg > ADF4350_REG5)
		return -EINVAL;

	mutex_lock(&st->lock);
	if (readval == NULL) {
		st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2));
		ret = adf4350_sync_config(st);
	} else {
		*readval =  st->regs_hw[reg];
		ret = 0;
	}
	mutex_unlock(&st->lock);

	return ret;
}

static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
{
	struct adf4350_platform_data *pdata = st->pdata;

	do {
		r_cnt++;
		st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
			   (r_cnt * (pdata->ref_div2_en ? 2 : 1));
	} while (st->fpfd > ADF4350_MAX_FREQ_PFD);

	return r_cnt;
}

static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
{
	struct adf4350_platform_data *pdata = st->pdata;
	u64 tmp;
	u32 div_gcd, prescaler, chspc;
	u16 mdiv, r_cnt = 0;
	u8 band_sel_div;

	if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq)
		return -EINVAL;

	if (freq > ADF4350_MAX_FREQ_45_PRESC) {
		prescaler = ADF4350_REG1_PRESCALER;
		mdiv = 75;
	} else {
		prescaler = 0;
		mdiv = 23;
	}

	st->r4_rf_div_sel = 0;

	while (freq < ADF4350_MIN_VCO_FREQ) {
		freq <<= 1;
		st->r4_rf_div_sel++;
	}

	/*
	 * Allow a predefined reference division factor
	 * if not set, compute our own
	 */
	if (pdata->ref_div_factor)
		r_cnt = pdata->ref_div_factor - 1;

	chspc = st->chspc;

	do  {
		do {
			do {
				r_cnt = adf4350_tune_r_cnt(st, r_cnt);
				st->r1_mod = st->fpfd / chspc;
				if (r_cnt > ADF4350_MAX_R_CNT) {
					/* try higher spacing values */
					chspc++;
					r_cnt = 0;
				}
			} while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt);
		} while (r_cnt == 0);

		tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1);
		do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
		st->r0_fract = do_div(tmp, st->r1_mod);
		st->r0_int = tmp;
	} while (mdiv > st->r0_int);

	band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);

	if (st->r0_fract && st->r1_mod) {
		div_gcd = gcd(st->r1_mod, st->r0_fract);
		st->r1_mod /= div_gcd;
		st->r0_fract /= div_gcd;
	} else {
		st->r0_fract = 0;
		st->r1_mod = 1;
	}

	dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
		"REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
		"R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
		freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
		1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
		band_sel_div);

	st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) |
				 ADF4350_REG0_FRACT(st->r0_fract);

	st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) |
				 ADF4350_REG1_MOD(st->r1_mod) |
				 prescaler;

	st->regs[ADF4350_REG2] =
		ADF4350_REG2_10BIT_R_CNT(r_cnt) |
		ADF4350_REG2_DOUBLE_BUFF_EN |
		(pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) |
		(pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) |
		(pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
		ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
		ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
		ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));

	st->regs[ADF4350_REG3] = pdata->r3_user_settings &
				 (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
				 ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) |
				 ADF4350_REG3_12BIT_CSR_EN |
				 ADF4351_REG3_CHARGE_CANCELLATION_EN |
				 ADF4351_REG3_ANTI_BACKLASH_3ns_EN |
				 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);

	st->regs[ADF4350_REG4] =
		ADF4350_REG4_FEEDBACK_FUND |
		ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) |
		ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) |
		ADF4350_REG4_RF_OUT_EN |
		(pdata->r4_user_settings &
		(ADF4350_REG4_OUTPUT_PWR(0x3) |
		ADF4350_REG4_AUX_OUTPUT_PWR(0x3) |
		ADF4350_REG4_AUX_OUTPUT_EN |
		ADF4350_REG4_AUX_OUTPUT_FUND |
		ADF4350_REG4_MUTE_TILL_LOCK_EN));

	st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
	st->freq_req = freq;

	return adf4350_sync_config(st);
}

static ssize_t adf4350_write(struct iio_dev *indio_dev,
				    uintptr_t private,
				    const struct iio_chan_spec *chan,
				    const char *buf, size_t len)
{
	struct adf4350_state *st = iio_priv(indio_dev);
	unsigned long long readin;
	unsigned long tmp;
	int ret;

	ret = kstrtoull(buf, 10, &readin);
	if (ret)
		return ret;

	mutex_lock(&st->lock);
	switch ((u32)private) {
	case ADF4350_FREQ:
		ret = adf4350_set_freq(st, readin);
		break;
	case ADF4350_FREQ_REFIN:
		if (readin > ADF4350_MAX_FREQ_REFIN) {
			ret = -EINVAL;
			break;
		}

		if (st->clk) {
			tmp = clk_round_rate(st->clk, readin);
			if (tmp != readin) {
				ret = -EINVAL;
				break;
			}
			ret = clk_set_rate(st->clk, tmp);
			if (ret < 0)
				break;
		}
		st->clkin = readin;
		ret = adf4350_set_freq(st, st->freq_req);
		break;
	case ADF4350_FREQ_RESOLUTION:
		if (readin == 0)
			ret = -EINVAL;
		else
			st->chspc = readin;
		break;
	case ADF4350_PWRDOWN:
		if (readin)
			st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
		else
			st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;

		adf4350_sync_config(st);
		break;
	default:
		ret = -EINVAL;
	}
	mutex_unlock(&st->lock);

	return ret ? ret : len;
}

static ssize_t adf4350_read(struct iio_dev *indio_dev,
				   uintptr_t private,
				   const struct iio_chan_spec *chan,
				   char *buf)
{
	struct adf4350_state *st = iio_priv(indio_dev);
	unsigned long long val;
	int ret = 0;

	mutex_lock(&st->lock);
	switch ((u32)private) {
	case ADF4350_FREQ:
		val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
			(u64)st->fpfd;
		do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
		/* PLL unlocked? return error */
		if (st->lock_detect_gpiod)
			if (!gpiod_get_value(st->lock_detect_gpiod)) {
				dev_dbg(&st->spi->dev, "PLL un-locked\n");
				ret = -EBUSY;
			}
		break;
	case ADF4350_FREQ_REFIN:
		if (st->clk)
			st->clkin = clk_get_rate(st->clk);

		val = st->clkin;
		break;
	case ADF4350_FREQ_RESOLUTION:
		val = st->chspc;
		break;
	case ADF4350_PWRDOWN:
		val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
		break;
	default:
		ret = -EINVAL;
		val = 0;
	}
	mutex_unlock(&st->lock);

	return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
}

#define _ADF4350_EXT_INFO(_name, _ident) { \
	.name = _name, \
	.read = adf4350_read, \
	.write = adf4350_write, \
	.private = _ident, \
	.shared = IIO_SEPARATE, \
}

static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
	/* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
	 * values > 2^32 in order to support the entire frequency range
	 * in Hz. Using scale is a bit ugly.
	 */
	_ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
	_ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
	_ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
	_ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
	{ },
};

static const struct iio_chan_spec adf4350_chan = {
	.type = IIO_ALTVOLTAGE,
	.indexed = 1,
	.output = 1,
	.ext_info = adf4350_ext_info,
};

static const struct iio_info adf4350_info = {
	.debugfs_reg_access = &adf4350_reg_access,
};

static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
{
	struct adf4350_platform_data *pdata;
	unsigned int tmp;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	snprintf(pdata->name, sizeof(pdata->name), "%pfw", dev_fwnode(dev));

	tmp = 10000;
	device_property_read_u32(dev, "adi,channel-spacing", &tmp);
	pdata->channel_spacing = tmp;

	tmp = 0;
	device_property_read_u32(dev, "adi,power-up-frequency", &tmp);
	pdata->power_up_frequency = tmp;

	tmp = 0;
	device_property_read_u32(dev, "adi,reference-div-factor", &tmp);
	pdata->ref_div_factor = tmp;

	pdata->ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable");
	pdata->ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable");

	/* r2_user_settings */
	pdata->r2_user_settings = 0;
	if (device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable"))
		pdata->r2_user_settings |= ADF4350_REG2_PD_POLARITY_POS;
	if (device_property_read_bool(dev, "adi,lock-detect-precision-6ns-enable"))
		pdata->r2_user_settings |= ADF4350_REG2_LDP_6ns;
	if (device_property_read_bool(dev, "adi,lock-detect-function-integer-n-enable"))
		pdata->r2_user_settings |= ADF4350_REG2_LDF_INT_N;

	tmp = 2500;
	device_property_read_u32(dev, "adi,charge-pump-current", &tmp);
	pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp);

	tmp = 0;
	device_property_read_u32(dev, "adi,muxout-select", &tmp);
	pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp);

	if (device_property_read_bool(dev, "adi,low-spur-mode-enable"))
		pdata->r2_user_settings |= ADF4350_REG2_NOISE_MODE(0x3);

	/* r3_user_settings */

	pdata->r3_user_settings = 0;
	if (device_property_read_bool(dev, "adi,cycle-slip-reduction-enable"))
		pdata->r3_user_settings |= ADF4350_REG3_12BIT_CSR_EN;
	if (device_property_read_bool(dev, "adi,charge-cancellation-enable"))
		pdata->r3_user_settings |= ADF4351_REG3_CHARGE_CANCELLATION_EN;
	if (device_property_read_bool(dev, "adi,anti-backlash-3ns-enable"))
		pdata->r3_user_settings |= ADF4351_REG3_ANTI_BACKLASH_3ns_EN;
	if (device_property_read_bool(dev, "adi,band-select-clock-mode-high-enable"))
		pdata->r3_user_settings |= ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH;

	tmp = 0;
	device_property_read_u32(dev, "adi,12bit-clk-divider", &tmp);
	pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp);

	tmp = 0;
	device_property_read_u32(dev, "adi,clk-divider-mode", &tmp);
	pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp);

	/* r4_user_settings */

	pdata->r4_user_settings = 0;
	if (device_property_read_bool(dev, "adi,aux-output-enable"))
		pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_EN;
	if (device_property_read_bool(dev, "adi,aux-output-fundamental-enable"))
		pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_FUND;
	if (device_property_read_bool(dev, "adi,mute-till-lock-enable"))
		pdata->r4_user_settings |= ADF4350_REG4_MUTE_TILL_LOCK_EN;

	tmp = 0;
	device_property_read_u32(dev, "adi,output-power", &tmp);
	pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp);

	tmp = 0;
	device_property_read_u32(dev, "adi,aux-output-power", &tmp);
	pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp);

	return pdata;
}

static int adf4350_probe(struct spi_device *spi)
{
	struct adf4350_platform_data *pdata;
	struct iio_dev *indio_dev;
	struct adf4350_state *st;
	struct clk *clk = NULL;
	int ret;

	if (dev_fwnode(&spi->dev)) {
		pdata = adf4350_parse_dt(&spi->dev);
		if (pdata == NULL)
			return -EINVAL;
	} else {
		pdata = spi->dev.platform_data;
	}

	if (!pdata) {
		dev_warn(&spi->dev, "no platform data? using default\n");
		pdata = &default_pdata;
	}

	if (!pdata->clkin) {
		clk = devm_clk_get(&spi->dev, "clkin");
		if (IS_ERR(clk))
			return -EPROBE_DEFER;

		ret = clk_prepare_enable(clk);
		if (ret < 0)
			return ret;
	}

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (indio_dev == NULL) {
		ret =  -ENOMEM;
		goto error_disable_clk;
	}

	st = iio_priv(indio_dev);

	st->reg = devm_regulator_get(&spi->dev, "vcc");
	if (!IS_ERR(st->reg)) {
		ret = regulator_enable(st->reg);
		if (ret)
			goto error_disable_clk;
	}

	spi_set_drvdata(spi, indio_dev);
	st->spi = spi;
	st->pdata = pdata;

	indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
		spi_get_device_id(spi)->name;

	indio_dev->info = &adf4350_info;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = &adf4350_chan;
	indio_dev->num_channels = 1;

	mutex_init(&st->lock);

	st->chspc = pdata->channel_spacing;
	if (clk) {
		st->clk = clk;
		st->clkin = clk_get_rate(clk);
	} else {
		st->clkin = pdata->clkin;
	}

	st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
		ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;

	memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));

	st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL,
							GPIOD_IN);
	if (IS_ERR(st->lock_detect_gpiod)) {
		ret = PTR_ERR(st->lock_detect_gpiod);
		goto error_disable_reg;
	}

	if (pdata->power_up_frequency) {
		ret = adf4350_set_freq(st, pdata->power_up_frequency);
		if (ret)
			goto error_disable_reg;
	}

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_disable_reg;

	return 0;

error_disable_reg:
	if (!IS_ERR(st->reg))
		regulator_disable(st->reg);
error_disable_clk:
	clk_disable_unprepare(clk);

	return ret;
}

static void adf4350_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct adf4350_state *st = iio_priv(indio_dev);
	struct regulator *reg = st->reg;

	st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
	adf4350_sync_config(st);

	iio_device_unregister(indio_dev);

	clk_disable_unprepare(st->clk);

	if (!IS_ERR(reg))
		regulator_disable(reg);
}

static const struct of_device_id adf4350_of_match[] = {
	{ .compatible = "adi,adf4350", },
	{ .compatible = "adi,adf4351", },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, adf4350_of_match);

static const struct spi_device_id adf4350_id[] = {
	{"adf4350", 4350},
	{"adf4351", 4351},
	{}
};
MODULE_DEVICE_TABLE(spi, adf4350_id);

static struct spi_driver adf4350_driver = {
	.driver = {
		.name	= "adf4350",
		.of_match_table = adf4350_of_match,
	},
	.probe		= adf4350_probe,
	.remove		= adf4350_remove,
	.id_table	= adf4350_id,
};
module_spi_driver(adf4350_driver);

MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
fda8d26e	1	// SPDX-License-Identifier: GPL-2.0-only
e31166f0 MH	2	/*
	3	* ADF4350/ADF4351 SPI Wideband Synthesizer driver
	4	*
9404fa15	5	* Copyright 2012-2013 Analog Devices Inc.
e31166f0 MH	6	*/
	7
	8	#include <linux/device.h>
	9	#include <linux/kernel.h>
130650e8 AS	10	#include <linux/mod_devicetable.h>
	11	#include <linux/module.h>
	12	#include <linux/property.h>
e31166f0 MH	13	#include <linux/slab.h>
	14	#include <linux/sysfs.h>
	15	#include <linux/spi/spi.h>
	16	#include <linux/regulator/consumer.h>
	17	#include <linux/err.h>
e31166f0	18	#include <linux/gcd.h>
4a89d2f4	19	#include <linux/gpio/consumer.h>
e31166f0	20	#include <asm/div64.h>
9404fa15	21	#include <linux/clk.h>
e31166f0 MH	22
	23	#include <linux/iio/iio.h>
	24	#include <linux/iio/sysfs.h>
	25	#include <linux/iio/frequency/adf4350.h>
	26
	27	enum {
	28	ADF4350_FREQ,
	29	ADF4350_FREQ_REFIN,
	30	ADF4350_FREQ_RESOLUTION,
	31	ADF4350_PWRDOWN,
	32	};
	33
	34	struct adf4350_state {
	35	struct spi_device *spi;
	36	struct regulator *reg;
4a89d2f4	37	struct gpio_desc *lock_detect_gpiod;
e31166f0	38	struct adf4350_platform_data *pdata;
9404fa15	39	struct clk *clk;
e31166f0 MH	40	unsigned long clkin;
	41	unsigned long chspc; /* Channel Spacing */
	42	unsigned long fpfd; /* Phase Frequency Detector */
	43	unsigned long min_out_freq;
	44	unsigned r0_fract;
	45	unsigned r0_int;
	46	unsigned r1_mod;
	47	unsigned r4_rf_div_sel;
	48	unsigned long regs[6];
	49	unsigned long regs_hw[6];
9404fa15	50	unsigned long long freq_req;
f0e64305 SC	51	/*
	52	* Lock to protect the state of the device from potential concurrent
	53	* writes. The device is configured via a sequence of SPI writes,
	54	* and this lock is meant to prevent the start of another sequence
	55	* before another one has finished.
	56	*/
	57	struct mutex lock;
e31166f0	58	/*
389b8972 JC	59	* DMA (thus cache coherency maintenance) may require that
389b8972 JC	60	* transfer buffers live in their own cache lines.
e31166f0	61	*/
389b8972	62	__be32 val __aligned(IIO_DMA_MINALIGN);
e31166f0 MH	63	};
	64
	65	static struct adf4350_platform_data default_pdata = {
e31166f0	66	.channel_spacing = 10000,
e86ee142	67	.r2_user_settings = ADF4350_REG2_PD_POLARITY_POS \|
e31166f0 MH	68	ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
	69	.r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
	70	.r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) \|
	71	ADF4350_REG4_MUTE_TILL_LOCK_EN,
e31166f0 MH	72	};
	73
	74	static int adf4350_sync_config(struct adf4350_state *st)
	75	{
	76	int ret, i, doublebuf = 0;
	77
	78	for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
	79	if ((st->regs_hw[i] != st->regs[i]) \|\|
	80	((i == ADF4350_REG0) && doublebuf)) {
e31166f0 MH	81	switch (i) {
	82	case ADF4350_REG1:
	83	case ADF4350_REG4:
	84	doublebuf = 1;
	85	break;
	86	}
	87
	88	st->val = cpu_to_be32(st->regs[i] \| i);
	89	ret = spi_write(st->spi, &st->val, 4);
	90	if (ret < 0)
	91	return ret;
	92	st->regs_hw[i] = st->regs[i];
	93	dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
	94	i, (u32)st->regs[i] \| i);
	95	}
	96	}
	97	return 0;
	98	}
	99
	100	static int adf4350_reg_access(struct iio_dev *indio_dev,
	101	unsigned reg, unsigned writeval,
	102	unsigned *readval)
	103	{
	104	struct adf4350_state *st = iio_priv(indio_dev);
	105	int ret;
	106
	107	if (reg > ADF4350_REG5)
	108	return -EINVAL;
	109
f0e64305	110	mutex_lock(&st->lock);
e31166f0 MH	111	if (readval == NULL) {
	112	st->regs[reg] = writeval & ~(BIT(0) \| BIT(1) \| BIT(2));
	113	ret = adf4350_sync_config(st);
	114	} else {
	115	*readval = st->regs_hw[reg];
	116	ret = 0;
	117	}
f0e64305	118	mutex_unlock(&st->lock);
e31166f0 MH	119
	120	return ret;
	121	}
	122
	123	static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
	124	{
	125	struct adf4350_platform_data *pdata = st->pdata;
	126
	127	do {
	128	r_cnt++;
	129	st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
	130	(r_cnt * (pdata->ref_div2_en ? 2 : 1));
	131	} while (st->fpfd > ADF4350_MAX_FREQ_PFD);
	132
	133	return r_cnt;
	134	}
	135
	136	static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
	137	{
	138	struct adf4350_platform_data *pdata = st->pdata;
	139	u64 tmp;
8857df3a	140	u32 div_gcd, prescaler, chspc;
e31166f0 MH	141	u16 mdiv, r_cnt = 0;
	142	u8 band_sel_div;
	143
	144	if (freq > ADF4350_MAX_OUT_FREQ \|\| freq < st->min_out_freq)
	145	return -EINVAL;
	146
	147	if (freq > ADF4350_MAX_FREQ_45_PRESC) {
	148	prescaler = ADF4350_REG1_PRESCALER;
	149	mdiv = 75;
	150	} else {
	151	prescaler = 0;
	152	mdiv = 23;
	153	}
	154
	155	st->r4_rf_div_sel = 0;
	156
	157	while (freq < ADF4350_MIN_VCO_FREQ) {
	158	freq <<= 1;
	159	st->r4_rf_div_sel++;
	160	}
	161
	162	/*
	163	* Allow a predefined reference division factor
	164	* if not set, compute our own
	165	*/
	166	if (pdata->ref_div_factor)
	167	r_cnt = pdata->ref_div_factor - 1;
	168
8857df3a	169	chspc = st->chspc;
e31166f0	170
8857df3a MH	171	do {
	172	do {
	173	do {
	174	r_cnt = adf4350_tune_r_cnt(st, r_cnt);
	175	st->r1_mod = st->fpfd / chspc;
	176	if (r_cnt > ADF4350_MAX_R_CNT) {
	177	/* try higher spacing values */
	178	chspc++;
	179	r_cnt = 0;
	180	}
	181	} while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt);
	182	} while (r_cnt == 0);
e31166f0	183
1690970d	184	tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1);
e31166f0 MH	185	do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
	186	st->r0_fract = do_div(tmp, st->r1_mod);
	187	st->r0_int = tmp;
	188	} while (mdiv > st->r0_int);
	189
	190	band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);
	191
	192	if (st->r0_fract && st->r1_mod) {
	193	div_gcd = gcd(st->r1_mod, st->r0_fract);
	194	st->r1_mod /= div_gcd;
	195	st->r0_fract /= div_gcd;
	196	} else {
	197	st->r0_fract = 0;
	198	st->r1_mod = 1;
	199	}
	200
	201	dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
	202	"REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
	203	"R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
	204	freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
	205	1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
	206	band_sel_div);
	207
	208	st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) \|
	209	ADF4350_REG0_FRACT(st->r0_fract);
	210
8857df3a	211	st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) \|
e31166f0 MH	212	ADF4350_REG1_MOD(st->r1_mod) \|
	213	prescaler;
	214
	215	st->regs[ADF4350_REG2] =
	216	ADF4350_REG2_10BIT_R_CNT(r_cnt) \|
	217	ADF4350_REG2_DOUBLE_BUFF_EN \|
	218	(pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) \|
	219	(pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) \|
	220	(pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS \|
	221	ADF4350_REG2_LDP_6ns \| ADF4350_REG2_LDF_INT_N \|
	222	ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) \|
2eb3a81e	223	ADF4350_REG2_MUXOUT(0x7) \| ADF4350_REG2_NOISE_MODE(0x3)));
e31166f0 MH	224
	225	st->regs[ADF4350_REG3] = pdata->r3_user_settings &
	226	(ADF4350_REG3_12BIT_CLKDIV(0xFFF) \|
	227	ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) \|
	228	ADF4350_REG3_12BIT_CSR_EN \|
	229	ADF4351_REG3_CHARGE_CANCELLATION_EN \|
	230	ADF4351_REG3_ANTI_BACKLASH_3ns_EN \|
	231	ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);
	232
	233	st->regs[ADF4350_REG4] =
	234	ADF4350_REG4_FEEDBACK_FUND \|
	235	ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) \|
	236	ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) \|
	237	ADF4350_REG4_RF_OUT_EN \|
	238	(pdata->r4_user_settings &
	239	(ADF4350_REG4_OUTPUT_PWR(0x3) \|
	240	ADF4350_REG4_AUX_OUTPUT_PWR(0x3) \|
	241	ADF4350_REG4_AUX_OUTPUT_EN \|
	242	ADF4350_REG4_AUX_OUTPUT_FUND \|
	243	ADF4350_REG4_MUTE_TILL_LOCK_EN));
	244
	245	st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
9404fa15	246	st->freq_req = freq;
e31166f0 MH	247
	248	return adf4350_sync_config(st);
	249	}
	250
	251	static ssize_t adf4350_write(struct iio_dev *indio_dev,
	252	uintptr_t private,
	253	const struct iio_chan_spec *chan,
	254	const char *buf, size_t len)
	255	{
	256	struct adf4350_state *st = iio_priv(indio_dev);
	257	unsigned long long readin;
9404fa15	258	unsigned long tmp;
e31166f0 MH	259	int ret;
	260
	261	ret = kstrtoull(buf, 10, &readin);
	262	if (ret)
	263	return ret;
	264
f0e64305	265	mutex_lock(&st->lock);
e31166f0 MH	266	switch ((u32)private) {
	267	case ADF4350_FREQ:
	268	ret = adf4350_set_freq(st, readin);
	269	break;
	270	case ADF4350_FREQ_REFIN:
9404fa15	271	if (readin > ADF4350_MAX_FREQ_REFIN) {
e31166f0	272	ret = -EINVAL;
9404fa15 MH	273	break;
	274	}
	275
	276	if (st->clk) {
	277	tmp = clk_round_rate(st->clk, readin);
	278	if (tmp != readin) {
	279	ret = -EINVAL;
	280	break;
	281	}
	282	ret = clk_set_rate(st->clk, tmp);
	283	if (ret < 0)
	284	break;
	285	}
	286	st->clkin = readin;
	287	ret = adf4350_set_freq(st, st->freq_req);
e31166f0 MH	288	break;
	289	case ADF4350_FREQ_RESOLUTION:
	290	if (readin == 0)
	291	ret = -EINVAL;
	292	else
	293	st->chspc = readin;
	294	break;
	295	case ADF4350_PWRDOWN:
	296	if (readin)
	297	st->regs[ADF4350_REG2] \|= ADF4350_REG2_POWER_DOWN_EN;
	298	else
	299	st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
	300
	301	adf4350_sync_config(st);
	302	break;
	303	default:
1a135d1a	304	ret = -EINVAL;
e31166f0	305	}
f0e64305	306	mutex_unlock(&st->lock);
e31166f0 MH	307
	308	return ret ? ret : len;
	309	}
	310
	311	static ssize_t adf4350_read(struct iio_dev *indio_dev,
	312	uintptr_t private,
	313	const struct iio_chan_spec *chan,
	314	char *buf)
	315	{
	316	struct adf4350_state *st = iio_priv(indio_dev);
	317	unsigned long long val;
	318	int ret = 0;
	319
f0e64305	320	mutex_lock(&st->lock);
e31166f0 MH	321	switch ((u32)private) {
	322	case ADF4350_FREQ:
	323	val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
	324	(u64)st->fpfd;
	325	do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
	326	/* PLL unlocked? return error */
4a89d2f4 LW	327	if (st->lock_detect_gpiod)
4a89d2f4 LW	328	if (!gpiod_get_value(st->lock_detect_gpiod)) {
e31166f0 MH	329	dev_dbg(&st->spi->dev, "PLL un-locked\n");
	330	ret = -EBUSY;
	331	}
	332	break;
	333	case ADF4350_FREQ_REFIN:
9404fa15 MH	334	if (st->clk)
	335	st->clkin = clk_get_rate(st->clk);
	336
e31166f0 MH	337	val = st->clkin;
	338	break;
	339	case ADF4350_FREQ_RESOLUTION:
	340	val = st->chspc;
	341	break;
	342	case ADF4350_PWRDOWN:
	343	val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
	344	break;
a21e6bfe	345	default:
1a135d1a	346	ret = -EINVAL;
9404fa15	347	val = 0;
e31166f0	348	}
f0e64305	349	mutex_unlock(&st->lock);
e31166f0 MH	350
	351	return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
	352	}
	353
	354	#define _ADF4350_EXT_INFO(_name, _ident) { \
	355	.name = _name, \
	356	.read = adf4350_read, \
	357	.write = adf4350_write, \
	358	.private = _ident, \
3704432f	359	.shared = IIO_SEPARATE, \
e31166f0 MH	360	}
	361
	362	static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
	363	/* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
	364	* values > 2^32 in order to support the entire frequency range
	365	* in Hz. Using scale is a bit ugly.
	366	*/
	367	_ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
	368	_ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
	369	_ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
	370	_ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
	371	{ },
	372	};
	373
	374	static const struct iio_chan_spec adf4350_chan = {
	375	.type = IIO_ALTVOLTAGE,
	376	.indexed = 1,
	377	.output = 1,
	378	.ext_info = adf4350_ext_info,
	379	};
	380
	381	static const struct iio_info adf4350_info = {
	382	.debugfs_reg_access = &adf4350_reg_access,
e31166f0 MH	383	};
e31166f0 MH	384
e764df67 MH	385	static struct adf4350_platform_data adf4350_parse_dt(struct device dev)
e764df67 MH	386	{
e764df67 MH	387	struct adf4350_platform_data *pdata;
e764df67 MH	388	unsigned int tmp;
e764df67 MH	389
e764df67 MH	390	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
d9d0ac96	391	if (!pdata)
e764df67	392	return NULL;
e764df67	393
130650e8	394	snprintf(pdata->name, sizeof(pdata->name), "%pfw", dev_fwnode(dev));
e764df67 MH	395
e764df67 MH	396	tmp = 10000;
130650e8	397	device_property_read_u32(dev, "adi,channel-spacing", &tmp);
e764df67 MH	398	pdata->channel_spacing = tmp;
	399
	400	tmp = 0;
130650e8	401	device_property_read_u32(dev, "adi,power-up-frequency", &tmp);
e764df67 MH	402	pdata->power_up_frequency = tmp;
	403
	404	tmp = 0;
130650e8	405	device_property_read_u32(dev, "adi,reference-div-factor", &tmp);
e764df67 MH	406	pdata->ref_div_factor = tmp;
e764df67 MH	407
130650e8 AS	408	pdata->ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable");
130650e8 AS	409	pdata->ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable");
e764df67 MH	410
e764df67 MH	411	/* r2_user_settings */
130650e8 AS	412	pdata->r2_user_settings = 0;
	413	if (device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable"))
	414	pdata->r2_user_settings \|= ADF4350_REG2_PD_POLARITY_POS;
	415	if (device_property_read_bool(dev, "adi,lock-detect-precision-6ns-enable"))
	416	pdata->r2_user_settings \|= ADF4350_REG2_LDP_6ns;
	417	if (device_property_read_bool(dev, "adi,lock-detect-function-integer-n-enable"))
	418	pdata->r2_user_settings \|= ADF4350_REG2_LDF_INT_N;
e764df67 MH	419
e764df67 MH	420	tmp = 2500;
130650e8	421	device_property_read_u32(dev, "adi,charge-pump-current", &tmp);
e764df67 MH	422	pdata->r2_user_settings \|= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp);
	423
	424	tmp = 0;
130650e8	425	device_property_read_u32(dev, "adi,muxout-select", &tmp);
e764df67 MH	426	pdata->r2_user_settings \|= ADF4350_REG2_MUXOUT(tmp);
e764df67 MH	427
130650e8 AS	428	if (device_property_read_bool(dev, "adi,low-spur-mode-enable"))
130650e8 AS	429	pdata->r2_user_settings \|= ADF4350_REG2_NOISE_MODE(0x3);
e764df67 MH	430
	431	/* r3_user_settings */
	432
130650e8 AS	433	pdata->r3_user_settings = 0;
	434	if (device_property_read_bool(dev, "adi,cycle-slip-reduction-enable"))
	435	pdata->r3_user_settings \|= ADF4350_REG3_12BIT_CSR_EN;
	436	if (device_property_read_bool(dev, "adi,charge-cancellation-enable"))
	437	pdata->r3_user_settings \|= ADF4351_REG3_CHARGE_CANCELLATION_EN;
	438	if (device_property_read_bool(dev, "adi,anti-backlash-3ns-enable"))
	439	pdata->r3_user_settings \|= ADF4351_REG3_ANTI_BACKLASH_3ns_EN;
	440	if (device_property_read_bool(dev, "adi,band-select-clock-mode-high-enable"))
	441	pdata->r3_user_settings \|= ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH;
e764df67 MH	442
e764df67 MH	443	tmp = 0;
130650e8	444	device_property_read_u32(dev, "adi,12bit-clk-divider", &tmp);
e764df67 MH	445	pdata->r3_user_settings \|= ADF4350_REG3_12BIT_CLKDIV(tmp);
	446
	447	tmp = 0;
130650e8	448	device_property_read_u32(dev, "adi,clk-divider-mode", &tmp);
e764df67 MH	449	pdata->r3_user_settings \|= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp);
	450
	451	/* r4_user_settings */
	452
130650e8 AS	453	pdata->r4_user_settings = 0;
	454	if (device_property_read_bool(dev, "adi,aux-output-enable"))
	455	pdata->r4_user_settings \|= ADF4350_REG4_AUX_OUTPUT_EN;
	456	if (device_property_read_bool(dev, "adi,aux-output-fundamental-enable"))
	457	pdata->r4_user_settings \|= ADF4350_REG4_AUX_OUTPUT_FUND;
	458	if (device_property_read_bool(dev, "adi,mute-till-lock-enable"))
	459	pdata->r4_user_settings \|= ADF4350_REG4_MUTE_TILL_LOCK_EN;
e764df67 MH	460
e764df67 MH	461	tmp = 0;
130650e8	462	device_property_read_u32(dev, "adi,output-power", &tmp);
e764df67 MH	463	pdata->r4_user_settings \|= ADF4350_REG4_OUTPUT_PWR(tmp);
	464
	465	tmp = 0;
130650e8	466	device_property_read_u32(dev, "adi,aux-output-power", &tmp);
e764df67 MH	467	pdata->r4_user_settings \|= ADF4350_REG4_AUX_OUTPUT_PWR(tmp);
	468
	469	return pdata;
	470	}
e764df67	471
fc52692c	472	static int adf4350_probe(struct spi_device *spi)
e31166f0	473	{
e764df67	474	struct adf4350_platform_data *pdata;
e31166f0 MH	475	struct iio_dev *indio_dev;
e31166f0 MH	476	struct adf4350_state *st;
9404fa15	477	struct clk *clk = NULL;
e31166f0 MH	478	int ret;
e31166f0 MH	479
130650e8	480	if (dev_fwnode(&spi->dev)) {
e764df67 MH	481	pdata = adf4350_parse_dt(&spi->dev);
	482	if (pdata == NULL)
	483	return -EINVAL;
	484	} else {
	485	pdata = spi->dev.platform_data;
	486	}
	487
e31166f0 MH	488	if (!pdata) {
e31166f0 MH	489	dev_warn(&spi->dev, "no platform data? using default\n");
e31166f0 MH	490	pdata = &default_pdata;
	491	}
	492
9404fa15	493	if (!pdata->clkin) {
a8b168a1	494	clk = devm_clk_get(&spi->dev, "clkin");
9404fa15 MH	495	if (IS_ERR(clk))
	496	return -EPROBE_DEFER;
	497
	498	ret = clk_prepare_enable(clk);
	499	if (ret < 0)
	500	return ret;
	501	}
	502
a8b168a1	503	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
00bfacfe WY	504	if (indio_dev == NULL) {
	505	ret = -ENOMEM;
	506	goto error_disable_clk;
	507	}
e31166f0 MH	508
	509	st = iio_priv(indio_dev);
	510
a8b168a1	511	st->reg = devm_regulator_get(&spi->dev, "vcc");
e31166f0 MH	512	if (!IS_ERR(st->reg)) {
	513	ret = regulator_enable(st->reg);
	514	if (ret)
a8b168a1	515	goto error_disable_clk;
e31166f0 MH	516	}
	517
	518	spi_set_drvdata(spi, indio_dev);
	519	st->spi = spi;
	520	st->pdata = pdata;
	521
e31166f0 MH	522	indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
	523	spi_get_device_id(spi)->name;
	524
	525	indio_dev->info = &adf4350_info;
	526	indio_dev->modes = INDIO_DIRECT_MODE;
	527	indio_dev->channels = &adf4350_chan;
	528	indio_dev->num_channels = 1;
	529
f0e64305 SC	530	mutex_init(&st->lock);
f0e64305 SC	531
e31166f0	532	st->chspc = pdata->channel_spacing;
9404fa15 MH	533	if (clk) {
	534	st->clk = clk;
	535	st->clkin = clk_get_rate(clk);
	536	} else {
	537	st->clkin = pdata->clkin;
	538	}
e31166f0 MH	539
	540	st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
	541	ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;
	542
	543	memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
	544
4a89d2f4 LW	545	st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL,
4a89d2f4 LW	546	GPIOD_IN);
c8cc4cf6 YY	547	if (IS_ERR(st->lock_detect_gpiod)) {
	548	ret = PTR_ERR(st->lock_detect_gpiod);
	549	goto error_disable_reg;
	550	}
e31166f0 MH	551
	552	if (pdata->power_up_frequency) {
	553	ret = adf4350_set_freq(st, pdata->power_up_frequency);
	554	if (ret)
a8b168a1	555	goto error_disable_reg;
e31166f0 MH	556	}
	557
	558	ret = iio_device_register(indio_dev);
	559	if (ret)
a8b168a1	560	goto error_disable_reg;
e31166f0 MH	561
	562	return 0;
	563
e31166f0 MH	564	error_disable_reg:
	565	if (!IS_ERR(st->reg))
	566	regulator_disable(st->reg);
a8b168a1	567	error_disable_clk:
07fe995f	568	clk_disable_unprepare(clk);
e31166f0 MH	569
	570	return ret;
	571	}
	572
a0386bba	573	static void adf4350_remove(struct spi_device *spi)
e31166f0 MH	574	{
	575	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	576	struct adf4350_state *st = iio_priv(indio_dev);
	577	struct regulator *reg = st->reg;
	578
	579	st->regs[ADF4350_REG2] \|= ADF4350_REG2_POWER_DOWN_EN;
	580	adf4350_sync_config(st);
	581
	582	iio_device_unregister(indio_dev);
	583
07fe995f	584	clk_disable_unprepare(st->clk);
9404fa15	585
762c4da3	586	if (!IS_ERR(reg))
e31166f0	587	regulator_disable(reg);
e31166f0 MH	588	}
e31166f0 MH	589
9c68be3e JMC	590	static const struct of_device_id adf4350_of_match[] = {
	591	{ .compatible = "adi,adf4350", },
	592	{ .compatible = "adi,adf4351", },
	593	{ /* sentinel */ },
	594	};
	595	MODULE_DEVICE_TABLE(of, adf4350_of_match);
	596
e31166f0 MH	597	static const struct spi_device_id adf4350_id[] = {
	598	{"adf4350", 4350},
	599	{"adf4351", 4351},
	600	{}
	601	};
ed199a11	602	MODULE_DEVICE_TABLE(spi, adf4350_id);
e31166f0 MH	603
	604	static struct spi_driver adf4350_driver = {
	605	.driver = {
	606	.name = "adf4350",
130650e8	607	.of_match_table = adf4350_of_match,
e31166f0 MH	608	},
e31166f0 MH	609	.probe = adf4350_probe,
fc52692c	610	.remove = adf4350_remove,
e31166f0 MH	611	.id_table = adf4350_id,
	612	};
	613	module_spi_driver(adf4350_driver);
	614
9404fa15	615	MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
e31166f0 MH	616	MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
e31166f0 MH	617	MODULE_LICENSE("GPL v2");