Commit | Line | Data |
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cd1678f9 MH |
1 | /* |
2 | * AD9523 SPI Low Jitter Clock Generator | |
3 | * | |
4 | * Copyright 2012 Analog Devices Inc. | |
5 | * | |
6 | * Licensed under the GPL-2. | |
7 | */ | |
8 | ||
9 | #include <linux/device.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/sysfs.h> | |
13 | #include <linux/spi/spi.h> | |
14 | #include <linux/regulator/consumer.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/delay.h> | |
18 | ||
19 | #include <linux/iio/iio.h> | |
20 | #include <linux/iio/sysfs.h> | |
21 | #include <linux/iio/frequency/ad9523.h> | |
22 | ||
23 | #define AD9523_READ (1 << 15) | |
24 | #define AD9523_WRITE (0 << 15) | |
25 | #define AD9523_CNT(x) (((x) - 1) << 13) | |
26 | #define AD9523_ADDR(x) ((x) & 0xFFF) | |
27 | ||
28 | #define AD9523_R1B (1 << 16) | |
29 | #define AD9523_R2B (2 << 16) | |
30 | #define AD9523_R3B (3 << 16) | |
31 | #define AD9523_TRANSF_LEN(x) ((x) >> 16) | |
32 | ||
33 | #define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0) | |
34 | #define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2) | |
35 | #define AD9523_PART_REGISTER (AD9523_R1B | 0x3) | |
36 | #define AD9523_READBACK_CTRL (AD9523_R1B | 0x4) | |
37 | ||
38 | #define AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B | 0x6) | |
39 | ||
40 | #define AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B | 0x11) | |
41 | #define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13) | |
42 | #define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14) | |
43 | #define AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B | 0x17) | |
44 | #define AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B | 0x19) | |
45 | #define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A) | |
46 | #define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B) | |
47 | #define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C) | |
48 | #define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D) | |
49 | ||
50 | #define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0) | |
51 | #define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1) | |
52 | #define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2) | |
53 | #define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3) | |
54 | #define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4) | |
55 | #define AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B | 0xF6) | |
56 | #define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7) | |
57 | ||
58 | #define AD9523_CHANNEL_CLOCK_DIST(ch) (AD9523_R3B | (0x192 + 3 * ch)) | |
59 | ||
60 | #define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA) | |
61 | #define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB) | |
62 | ||
63 | #define AD9523_READBACK_0 (AD9523_R1B | 0x22C) | |
64 | #define AD9523_READBACK_1 (AD9523_R1B | 0x22D) | |
65 | ||
66 | #define AD9523_STATUS_SIGNALS (AD9523_R3B | 0x232) | |
67 | #define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233) | |
68 | #define AD9523_IO_UPDATE (AD9523_R1B | 0x234) | |
69 | ||
70 | #define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00) | |
71 | #define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01) | |
72 | #define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02) | |
73 | #define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03) | |
74 | ||
75 | /* AD9523_SERIAL_PORT_CONFIG */ | |
76 | ||
77 | #define AD9523_SER_CONF_SDO_ACTIVE (1 << 7) | |
78 | #define AD9523_SER_CONF_SOFT_RESET (1 << 5) | |
79 | ||
80 | /* AD9523_READBACK_CTRL */ | |
81 | #define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0) | |
82 | ||
83 | /* AD9523_PLL1_CHARGE_PUMP_CTRL */ | |
84 | #define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F) | |
85 | #define AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7) | |
86 | #define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8) | |
87 | #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8) | |
88 | #define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8) | |
89 | #define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8) | |
90 | #define AD9523_PLL1_BACKLASH_PW_MIN (0 << 10) | |
91 | #define AD9523_PLL1_BACKLASH_PW_LOW (1 << 10) | |
92 | #define AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10) | |
93 | #define AD9523_PLL1_BACKLASH_PW_MAX (3 << 10) | |
94 | ||
95 | /* AD9523_PLL1_INPUT_RECEIVERS_CTRL */ | |
96 | #define AD9523_PLL1_REF_TEST_RCV_EN (1 << 7) | |
97 | #define AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6) | |
98 | #define AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5) | |
99 | #define AD9523_PLL1_REFB_RCV_EN (1 << 4) | |
100 | #define AD9523_PLL1_REFA_RCV_EN (1 << 3) | |
101 | #define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2) | |
102 | #define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1) | |
103 | #define AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0) | |
104 | ||
105 | /* AD9523_PLL1_REF_CTRL */ | |
106 | #define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7) | |
107 | #define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6) | |
108 | #define AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5) | |
109 | #define AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5) | |
110 | #define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4) | |
111 | #define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3) | |
112 | #define AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2) | |
113 | #define AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1) | |
114 | #define AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0) | |
115 | ||
116 | /* AD9523_PLL1_MISC_CTRL */ | |
117 | #define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7) | |
118 | #define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6) | |
119 | #define AD9523_PLL1_REF_MODE(x) ((x) << 2) | |
120 | #define AD9523_PLL1_BYPASS_REFB_DIV (1 << 1) | |
121 | #define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0) | |
122 | ||
123 | /* AD9523_PLL1_LOOP_FILTER_CTRL */ | |
124 | #define AD9523_PLL1_LOOP_FILTER_RZERO(x) ((x) & 0xF) | |
125 | ||
126 | /* AD9523_PLL2_CHARGE_PUMP */ | |
127 | #define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500) | |
128 | ||
129 | /* AD9523_PLL2_FEEDBACK_DIVIDER_AB */ | |
130 | #define AD9523_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6) | |
131 | #define AD9523_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0) | |
132 | #define AD9523_PLL2_FB_NDIV(a, b) (4 * (b) + (a)) | |
133 | ||
134 | /* AD9523_PLL2_CTRL */ | |
135 | #define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0) | |
136 | #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0) | |
137 | #define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0) | |
138 | #define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0) | |
139 | #define AD9523_PLL2_BACKLASH_PW_MIN (0 << 2) | |
140 | #define AD9523_PLL2_BACKLASH_PW_LOW (1 << 2) | |
141 | #define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2) | |
142 | #define AD9523_PLL2_BACKLASH_PW_MAX (3 << 1) | |
143 | #define AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4) | |
144 | #define AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5) | |
145 | #define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7) | |
146 | ||
147 | /* AD9523_PLL2_VCO_CTRL */ | |
148 | #define AD9523_PLL2_VCO_CALIBRATE (1 << 1) | |
149 | #define AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2) | |
150 | #define AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3) | |
151 | #define AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4) | |
152 | ||
153 | /* AD9523_PLL2_VCO_DIVIDER */ | |
154 | #define AD9523_PLL2_VCO_DIV_M1(x) ((((x) - 3) & 0x3) << 0) | |
155 | #define AD9523_PLL2_VCO_DIV_M2(x) ((((x) - 3) & 0x3) << 4) | |
156 | #define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2) | |
157 | #define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6) | |
158 | ||
159 | /* AD9523_PLL2_LOOP_FILTER_CTRL */ | |
160 | #define AD9523_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0) | |
161 | #define AD9523_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3) | |
162 | #define AD9523_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x7) << 6) | |
163 | #define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8) | |
164 | ||
165 | /* AD9523_PLL2_R2_DIVIDER */ | |
166 | #define AD9523_PLL2_R2_DIVIDER_VAL(x) (((x) & 0x1F) << 0) | |
167 | ||
168 | /* AD9523_CHANNEL_CLOCK_DIST */ | |
169 | #define AD9523_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 18) | |
170 | #define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F) | |
171 | #define AD9523_CLK_DIST_DIV(x) ((((x) - 1) & 0x3FF) << 8) | |
172 | #define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1) | |
173 | #define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7) | |
174 | #define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6) | |
175 | #define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5) | |
176 | #define AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4) | |
177 | #define AD9523_CLK_DIST_DRIVER_MODE(x) (((x) & 0xF) << 0) | |
178 | ||
179 | /* AD9523_PLL1_OUTPUT_CTRL */ | |
180 | #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7) | |
181 | #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6) | |
182 | #define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5) | |
183 | #define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4) | |
184 | #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0) | |
185 | #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0) | |
186 | #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0) | |
187 | #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0) | |
188 | #define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0) | |
189 | ||
190 | /* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */ | |
191 | #define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7) | |
192 | #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6) | |
193 | #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5) | |
194 | #define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4) | |
195 | #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3) | |
196 | #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2) | |
197 | #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1) | |
198 | #define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0) | |
199 | ||
200 | /* AD9523_READBACK_0 */ | |
201 | #define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7) | |
202 | #define AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6) | |
203 | #define AD9523_READBACK_0_STAT_VCXO (1 << 5) | |
204 | #define AD9523_READBACK_0_STAT_REF_TEST (1 << 4) | |
205 | #define AD9523_READBACK_0_STAT_REFB (1 << 3) | |
206 | #define AD9523_READBACK_0_STAT_REFA (1 << 2) | |
207 | #define AD9523_READBACK_0_STAT_PLL2_LD (1 << 1) | |
208 | #define AD9523_READBACK_0_STAT_PLL1_LD (1 << 0) | |
209 | ||
210 | /* AD9523_READBACK_1 */ | |
211 | #define AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3) | |
212 | #define AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2) | |
213 | #define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0) | |
214 | ||
215 | /* AD9523_STATUS_SIGNALS */ | |
216 | #define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16) | |
217 | #define AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302) | |
218 | /* AD9523_POWER_DOWN_CTRL */ | |
219 | #define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2) | |
220 | #define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1) | |
221 | #define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0) | |
222 | ||
223 | /* AD9523_IO_UPDATE */ | |
224 | #define AD9523_IO_UPDATE_EN (1 << 0) | |
225 | ||
226 | /* AD9523_EEPROM_DATA_XFER_STATUS */ | |
227 | #define AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0) | |
228 | ||
229 | /* AD9523_EEPROM_ERROR_READBACK */ | |
230 | #define AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0) | |
231 | ||
232 | /* AD9523_EEPROM_CTRL1 */ | |
233 | #define AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1) | |
234 | #define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0) | |
235 | ||
236 | /* AD9523_EEPROM_CTRL2 */ | |
237 | #define AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0) | |
238 | ||
239 | #define AD9523_NUM_CHAN 14 | |
240 | #define AD9523_NUM_CHAN_ALT_CLK_SRC 10 | |
241 | ||
242 | /* Helpers to avoid excess line breaks */ | |
243 | #define AD_IFE(_pde, _a, _b) ((pdata->_pde) ? _a : _b) | |
244 | #define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0) | |
245 | ||
246 | enum { | |
247 | AD9523_STAT_PLL1_LD, | |
248 | AD9523_STAT_PLL2_LD, | |
249 | AD9523_STAT_REFA, | |
250 | AD9523_STAT_REFB, | |
251 | AD9523_STAT_REF_TEST, | |
252 | AD9523_STAT_VCXO, | |
253 | AD9523_STAT_PLL2_FB_CLK, | |
254 | AD9523_STAT_PLL2_REF_CLK, | |
255 | AD9523_SYNC, | |
256 | AD9523_EEPROM, | |
257 | }; | |
258 | ||
259 | enum { | |
260 | AD9523_VCO1, | |
261 | AD9523_VCO2, | |
262 | AD9523_VCXO, | |
263 | AD9523_NUM_CLK_SRC, | |
264 | }; | |
265 | ||
266 | struct ad9523_state { | |
267 | struct spi_device *spi; | |
268 | struct regulator *reg; | |
269 | struct ad9523_platform_data *pdata; | |
270 | struct iio_chan_spec ad9523_channels[AD9523_NUM_CHAN]; | |
271 | ||
272 | unsigned long vcxo_freq; | |
273 | unsigned long vco_freq; | |
274 | unsigned long vco_out_freq[AD9523_NUM_CLK_SRC]; | |
275 | unsigned char vco_out_map[AD9523_NUM_CHAN_ALT_CLK_SRC]; | |
276 | ||
69f894c3 LPC |
277 | /* |
278 | * Lock for accessing device registers. Some operations require | |
279 | * multiple consecutive R/W operations, during which the device | |
280 | * shouldn't be interrupted. The buffers are also shared across | |
281 | * all operations so need to be protected on stand alone reads and | |
282 | * writes. | |
283 | */ | |
284 | struct mutex lock; | |
285 | ||
cd1678f9 MH |
286 | /* |
287 | * DMA (thus cache coherency maintenance) requires the | |
288 | * transfer buffers to live in their own cache lines. | |
289 | */ | |
290 | union { | |
291 | __be32 d32; | |
292 | u8 d8[4]; | |
293 | } data[2] ____cacheline_aligned; | |
294 | }; | |
295 | ||
98a52530 | 296 | static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr) |
cd1678f9 MH |
297 | { |
298 | struct ad9523_state *st = iio_priv(indio_dev); | |
cd1678f9 MH |
299 | int ret; |
300 | ||
301 | /* We encode the register size 1..3 bytes into the register address. | |
302 | * On transfer we get the size from the register datum, and make sure | |
303 | * the result is properly aligned. | |
304 | */ | |
305 | ||
306 | struct spi_transfer t[] = { | |
307 | { | |
308 | .tx_buf = &st->data[0].d8[2], | |
309 | .len = 2, | |
310 | }, { | |
311 | .rx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)], | |
312 | .len = AD9523_TRANSF_LEN(addr), | |
313 | }, | |
314 | }; | |
315 | ||
cd1678f9 MH |
316 | st->data[0].d32 = cpu_to_be32(AD9523_READ | |
317 | AD9523_CNT(AD9523_TRANSF_LEN(addr)) | | |
318 | AD9523_ADDR(addr)); | |
319 | ||
14543a00 | 320 | ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); |
cd1678f9 MH |
321 | if (ret < 0) |
322 | dev_err(&indio_dev->dev, "read failed (%d)", ret); | |
323 | else | |
324 | ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >> | |
325 | (8 * (3 - AD9523_TRANSF_LEN(addr)))); | |
326 | ||
327 | return ret; | |
328 | }; | |
329 | ||
98a52530 SS |
330 | static int ad9523_write(struct iio_dev *indio_dev, |
331 | unsigned int addr, unsigned int val) | |
cd1678f9 MH |
332 | { |
333 | struct ad9523_state *st = iio_priv(indio_dev); | |
cd1678f9 MH |
334 | int ret; |
335 | struct spi_transfer t[] = { | |
336 | { | |
337 | .tx_buf = &st->data[0].d8[2], | |
338 | .len = 2, | |
339 | }, { | |
340 | .tx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)], | |
341 | .len = AD9523_TRANSF_LEN(addr), | |
342 | }, | |
343 | }; | |
344 | ||
cd1678f9 MH |
345 | st->data[0].d32 = cpu_to_be32(AD9523_WRITE | |
346 | AD9523_CNT(AD9523_TRANSF_LEN(addr)) | | |
347 | AD9523_ADDR(addr)); | |
348 | st->data[1].d32 = cpu_to_be32(val); | |
349 | ||
14543a00 | 350 | ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); |
cd1678f9 MH |
351 | |
352 | if (ret < 0) | |
353 | dev_err(&indio_dev->dev, "write failed (%d)", ret); | |
354 | ||
355 | return ret; | |
356 | } | |
357 | ||
358 | static int ad9523_io_update(struct iio_dev *indio_dev) | |
359 | { | |
360 | return ad9523_write(indio_dev, AD9523_IO_UPDATE, AD9523_IO_UPDATE_EN); | |
361 | } | |
362 | ||
363 | static int ad9523_vco_out_map(struct iio_dev *indio_dev, | |
98a52530 | 364 | unsigned int ch, unsigned int out) |
cd1678f9 MH |
365 | { |
366 | struct ad9523_state *st = iio_priv(indio_dev); | |
367 | int ret; | |
98a52530 | 368 | unsigned int mask; |
cd1678f9 MH |
369 | |
370 | switch (ch) { | |
371 | case 0 ... 3: | |
372 | ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL); | |
373 | if (ret < 0) | |
374 | break; | |
375 | mask = AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 << ch; | |
376 | if (out) { | |
377 | ret |= mask; | |
378 | out = 2; | |
379 | } else { | |
380 | ret &= ~mask; | |
381 | } | |
382 | ret = ad9523_write(indio_dev, | |
383 | AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret); | |
384 | break; | |
385 | case 4 ... 6: | |
386 | ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL); | |
387 | if (ret < 0) | |
388 | break; | |
389 | mask = AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 << (ch - 4); | |
390 | if (out) | |
391 | ret |= mask; | |
392 | else | |
393 | ret &= ~mask; | |
394 | ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret); | |
395 | break; | |
396 | case 7 ... 9: | |
397 | ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL); | |
398 | if (ret < 0) | |
399 | break; | |
400 | mask = AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 << (ch - 7); | |
401 | if (out) | |
402 | ret |= mask; | |
403 | else | |
404 | ret &= ~mask; | |
405 | ret = ad9523_write(indio_dev, | |
406 | AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret); | |
407 | break; | |
408 | default: | |
409 | return 0; | |
410 | } | |
411 | ||
412 | st->vco_out_map[ch] = out; | |
413 | ||
414 | return ret; | |
415 | } | |
416 | ||
417 | static int ad9523_set_clock_provider(struct iio_dev *indio_dev, | |
98a52530 | 418 | unsigned int ch, unsigned long freq) |
cd1678f9 MH |
419 | { |
420 | struct ad9523_state *st = iio_priv(indio_dev); | |
421 | long tmp1, tmp2; | |
422 | bool use_alt_clk_src; | |
423 | ||
424 | switch (ch) { | |
425 | case 0 ... 3: | |
426 | use_alt_clk_src = (freq == st->vco_out_freq[AD9523_VCXO]); | |
427 | break; | |
428 | case 4 ... 9: | |
429 | tmp1 = st->vco_out_freq[AD9523_VCO1] / freq; | |
430 | tmp2 = st->vco_out_freq[AD9523_VCO2] / freq; | |
431 | tmp1 *= freq; | |
432 | tmp2 *= freq; | |
433 | use_alt_clk_src = (abs(tmp1 - freq) > abs(tmp2 - freq)); | |
434 | break; | |
435 | default: | |
436 | /* Ch 10..14: No action required, return success */ | |
437 | return 0; | |
438 | } | |
439 | ||
440 | return ad9523_vco_out_map(indio_dev, ch, use_alt_clk_src); | |
441 | } | |
442 | ||
443 | static int ad9523_store_eeprom(struct iio_dev *indio_dev) | |
444 | { | |
445 | int ret, tmp; | |
446 | ||
447 | ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, | |
448 | AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS); | |
449 | if (ret < 0) | |
450 | return ret; | |
451 | ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2, | |
452 | AD9523_EEPROM_CTRL2_REG2EEPROM); | |
453 | if (ret < 0) | |
454 | return ret; | |
455 | ||
456 | tmp = 4; | |
457 | do { | |
e904ce7e | 458 | msleep(20); |
cd1678f9 MH |
459 | ret = ad9523_read(indio_dev, |
460 | AD9523_EEPROM_DATA_XFER_STATUS); | |
461 | if (ret < 0) | |
462 | return ret; | |
463 | } while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--); | |
464 | ||
465 | ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0); | |
466 | if (ret < 0) | |
467 | return ret; | |
468 | ||
469 | ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK); | |
470 | if (ret < 0) | |
471 | return ret; | |
472 | ||
473 | if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) { | |
474 | dev_err(&indio_dev->dev, "Verify EEPROM failed"); | |
475 | ret = -EIO; | |
476 | } | |
477 | ||
478 | return ret; | |
479 | } | |
480 | ||
481 | static int ad9523_sync(struct iio_dev *indio_dev) | |
482 | { | |
483 | int ret, tmp; | |
484 | ||
485 | ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS); | |
486 | if (ret < 0) | |
487 | return ret; | |
488 | ||
489 | tmp = ret; | |
490 | tmp |= AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL; | |
491 | ||
492 | ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp); | |
493 | if (ret < 0) | |
494 | return ret; | |
495 | ||
496 | ad9523_io_update(indio_dev); | |
497 | tmp &= ~AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL; | |
498 | ||
499 | ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp); | |
500 | if (ret < 0) | |
501 | return ret; | |
502 | ||
503 | return ad9523_io_update(indio_dev); | |
504 | } | |
505 | ||
506 | static ssize_t ad9523_store(struct device *dev, | |
507 | struct device_attribute *attr, | |
508 | const char *buf, size_t len) | |
509 | { | |
510 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | |
511 | struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); | |
69f894c3 | 512 | struct ad9523_state *st = iio_priv(indio_dev); |
cd1678f9 MH |
513 | bool state; |
514 | int ret; | |
515 | ||
516 | ret = strtobool(buf, &state); | |
517 | if (ret < 0) | |
518 | return ret; | |
519 | ||
520 | if (!state) | |
521 | return 0; | |
522 | ||
69f894c3 | 523 | mutex_lock(&st->lock); |
cd1678f9 MH |
524 | switch ((u32)this_attr->address) { |
525 | case AD9523_SYNC: | |
526 | ret = ad9523_sync(indio_dev); | |
527 | break; | |
528 | case AD9523_EEPROM: | |
529 | ret = ad9523_store_eeprom(indio_dev); | |
530 | break; | |
531 | default: | |
532 | ret = -ENODEV; | |
533 | } | |
69f894c3 | 534 | mutex_unlock(&st->lock); |
cd1678f9 MH |
535 | |
536 | return ret ? ret : len; | |
537 | } | |
538 | ||
539 | static ssize_t ad9523_show(struct device *dev, | |
540 | struct device_attribute *attr, | |
541 | char *buf) | |
542 | { | |
543 | struct iio_dev *indio_dev = dev_to_iio_dev(dev); | |
544 | struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); | |
69f894c3 | 545 | struct ad9523_state *st = iio_priv(indio_dev); |
cd1678f9 MH |
546 | int ret; |
547 | ||
69f894c3 | 548 | mutex_lock(&st->lock); |
cd1678f9 MH |
549 | ret = ad9523_read(indio_dev, AD9523_READBACK_0); |
550 | if (ret >= 0) { | |
551 | ret = sprintf(buf, "%d\n", !!(ret & (1 << | |
552 | (u32)this_attr->address))); | |
553 | } | |
69f894c3 | 554 | mutex_unlock(&st->lock); |
cd1678f9 MH |
555 | |
556 | return ret; | |
557 | } | |
558 | ||
559 | static IIO_DEVICE_ATTR(pll1_locked, S_IRUGO, | |
560 | ad9523_show, | |
561 | NULL, | |
562 | AD9523_STAT_PLL1_LD); | |
563 | ||
564 | static IIO_DEVICE_ATTR(pll2_locked, S_IRUGO, | |
565 | ad9523_show, | |
566 | NULL, | |
567 | AD9523_STAT_PLL2_LD); | |
568 | ||
569 | static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, S_IRUGO, | |
570 | ad9523_show, | |
571 | NULL, | |
572 | AD9523_STAT_REFA); | |
573 | ||
574 | static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, S_IRUGO, | |
575 | ad9523_show, | |
576 | NULL, | |
577 | AD9523_STAT_REFB); | |
578 | ||
579 | static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, S_IRUGO, | |
580 | ad9523_show, | |
581 | NULL, | |
582 | AD9523_STAT_REF_TEST); | |
583 | ||
584 | static IIO_DEVICE_ATTR(vcxo_clk_present, S_IRUGO, | |
585 | ad9523_show, | |
586 | NULL, | |
587 | AD9523_STAT_VCXO); | |
588 | ||
589 | static IIO_DEVICE_ATTR(pll2_feedback_clk_present, S_IRUGO, | |
590 | ad9523_show, | |
591 | NULL, | |
592 | AD9523_STAT_PLL2_FB_CLK); | |
593 | ||
594 | static IIO_DEVICE_ATTR(pll2_reference_clk_present, S_IRUGO, | |
595 | ad9523_show, | |
596 | NULL, | |
597 | AD9523_STAT_PLL2_REF_CLK); | |
598 | ||
599 | static IIO_DEVICE_ATTR(sync_dividers, S_IWUSR, | |
600 | NULL, | |
601 | ad9523_store, | |
602 | AD9523_SYNC); | |
603 | ||
604 | static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR, | |
605 | NULL, | |
606 | ad9523_store, | |
607 | AD9523_EEPROM); | |
608 | ||
609 | static struct attribute *ad9523_attributes[] = { | |
610 | &iio_dev_attr_sync_dividers.dev_attr.attr, | |
611 | &iio_dev_attr_store_eeprom.dev_attr.attr, | |
612 | &iio_dev_attr_pll2_feedback_clk_present.dev_attr.attr, | |
613 | &iio_dev_attr_pll2_reference_clk_present.dev_attr.attr, | |
614 | &iio_dev_attr_pll1_reference_clk_a_present.dev_attr.attr, | |
615 | &iio_dev_attr_pll1_reference_clk_b_present.dev_attr.attr, | |
616 | &iio_dev_attr_pll1_reference_clk_test_present.dev_attr.attr, | |
617 | &iio_dev_attr_vcxo_clk_present.dev_attr.attr, | |
618 | &iio_dev_attr_pll1_locked.dev_attr.attr, | |
619 | &iio_dev_attr_pll2_locked.dev_attr.attr, | |
620 | NULL, | |
621 | }; | |
622 | ||
623 | static const struct attribute_group ad9523_attribute_group = { | |
624 | .attrs = ad9523_attributes, | |
625 | }; | |
626 | ||
627 | static int ad9523_read_raw(struct iio_dev *indio_dev, | |
628 | struct iio_chan_spec const *chan, | |
629 | int *val, | |
630 | int *val2, | |
631 | long m) | |
632 | { | |
633 | struct ad9523_state *st = iio_priv(indio_dev); | |
98a52530 | 634 | unsigned int code; |
cd1678f9 MH |
635 | int ret; |
636 | ||
69f894c3 | 637 | mutex_lock(&st->lock); |
cd1678f9 | 638 | ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel)); |
69f894c3 | 639 | mutex_unlock(&st->lock); |
cd1678f9 MH |
640 | |
641 | if (ret < 0) | |
642 | return ret; | |
643 | ||
644 | switch (m) { | |
645 | case IIO_CHAN_INFO_RAW: | |
646 | *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN); | |
647 | return IIO_VAL_INT; | |
648 | case IIO_CHAN_INFO_FREQUENCY: | |
649 | *val = st->vco_out_freq[st->vco_out_map[chan->channel]] / | |
650 | AD9523_CLK_DIST_DIV_REV(ret); | |
651 | return IIO_VAL_INT; | |
652 | case IIO_CHAN_INFO_PHASE: | |
653 | code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) / | |
654 | AD9523_CLK_DIST_DIV_REV(ret); | |
655 | *val = code / 1000000; | |
656 | *val2 = (code % 1000000) * 10; | |
657 | return IIO_VAL_INT_PLUS_MICRO; | |
658 | default: | |
659 | return -EINVAL; | |
660 | } | |
661 | }; | |
662 | ||
663 | static int ad9523_write_raw(struct iio_dev *indio_dev, | |
664 | struct iio_chan_spec const *chan, | |
665 | int val, | |
666 | int val2, | |
667 | long mask) | |
668 | { | |
669 | struct ad9523_state *st = iio_priv(indio_dev); | |
98a52530 | 670 | unsigned int reg; |
cd1678f9 MH |
671 | int ret, tmp, code; |
672 | ||
69f894c3 | 673 | mutex_lock(&st->lock); |
cd1678f9 MH |
674 | ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel)); |
675 | if (ret < 0) | |
676 | goto out; | |
677 | ||
678 | reg = ret; | |
679 | ||
680 | switch (mask) { | |
681 | case IIO_CHAN_INFO_RAW: | |
682 | if (val) | |
683 | reg &= ~AD9523_CLK_DIST_PWR_DOWN_EN; | |
684 | else | |
685 | reg |= AD9523_CLK_DIST_PWR_DOWN_EN; | |
686 | break; | |
687 | case IIO_CHAN_INFO_FREQUENCY: | |
688 | if (val <= 0) { | |
689 | ret = -EINVAL; | |
690 | goto out; | |
691 | } | |
692 | ret = ad9523_set_clock_provider(indio_dev, chan->channel, val); | |
693 | if (ret < 0) | |
694 | goto out; | |
695 | tmp = st->vco_out_freq[st->vco_out_map[chan->channel]] / val; | |
696 | tmp = clamp(tmp, 1, 1024); | |
697 | reg &= ~(0x3FF << 8); | |
698 | reg |= AD9523_CLK_DIST_DIV(tmp); | |
699 | break; | |
700 | case IIO_CHAN_INFO_PHASE: | |
701 | code = val * 1000000 + val2 % 1000000; | |
702 | tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592; | |
703 | tmp = clamp(tmp, 0, 63); | |
704 | reg &= ~AD9523_CLK_DIST_DIV_PHASE(~0); | |
705 | reg |= AD9523_CLK_DIST_DIV_PHASE(tmp); | |
706 | break; | |
707 | default: | |
708 | ret = -EINVAL; | |
709 | goto out; | |
710 | } | |
711 | ||
712 | ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel), | |
713 | reg); | |
714 | if (ret < 0) | |
715 | goto out; | |
716 | ||
717 | ad9523_io_update(indio_dev); | |
718 | out: | |
69f894c3 | 719 | mutex_unlock(&st->lock); |
cd1678f9 MH |
720 | return ret; |
721 | } | |
722 | ||
723 | static int ad9523_reg_access(struct iio_dev *indio_dev, | |
98a52530 SS |
724 | unsigned int reg, unsigned int writeval, |
725 | unsigned int *readval) | |
cd1678f9 | 726 | { |
69f894c3 | 727 | struct ad9523_state *st = iio_priv(indio_dev); |
cd1678f9 MH |
728 | int ret; |
729 | ||
69f894c3 | 730 | mutex_lock(&st->lock); |
cd1678f9 MH |
731 | if (readval == NULL) { |
732 | ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval); | |
733 | ad9523_io_update(indio_dev); | |
734 | } else { | |
735 | ret = ad9523_read(indio_dev, reg | AD9523_R1B); | |
736 | if (ret < 0) | |
17c88eb6 | 737 | goto out_unlock; |
cd1678f9 MH |
738 | *readval = ret; |
739 | ret = 0; | |
740 | } | |
17c88eb6 DC |
741 | |
742 | out_unlock: | |
69f894c3 | 743 | mutex_unlock(&st->lock); |
cd1678f9 MH |
744 | |
745 | return ret; | |
746 | } | |
747 | ||
748 | static const struct iio_info ad9523_info = { | |
749 | .read_raw = &ad9523_read_raw, | |
750 | .write_raw = &ad9523_write_raw, | |
751 | .debugfs_reg_access = &ad9523_reg_access, | |
752 | .attrs = &ad9523_attribute_group, | |
cd1678f9 MH |
753 | }; |
754 | ||
755 | static int ad9523_setup(struct iio_dev *indio_dev) | |
756 | { | |
757 | struct ad9523_state *st = iio_priv(indio_dev); | |
758 | struct ad9523_platform_data *pdata = st->pdata; | |
759 | struct ad9523_channel_spec *chan; | |
760 | unsigned long active_mask = 0; | |
761 | int ret, i; | |
762 | ||
763 | ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG, | |
764 | AD9523_SER_CONF_SOFT_RESET | | |
765 | (st->spi->mode & SPI_3WIRE ? 0 : | |
766 | AD9523_SER_CONF_SDO_ACTIVE)); | |
767 | if (ret < 0) | |
768 | return ret; | |
769 | ||
770 | ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL, | |
771 | AD9523_READBACK_CTRL_READ_BUFFERED); | |
772 | if (ret < 0) | |
773 | return ret; | |
774 | ||
775 | ret = ad9523_io_update(indio_dev); | |
776 | if (ret < 0) | |
777 | return ret; | |
778 | ||
779 | /* | |
780 | * PLL1 Setup | |
781 | */ | |
782 | ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER, | |
783 | pdata->refa_r_div); | |
784 | if (ret < 0) | |
785 | return ret; | |
786 | ||
787 | ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER, | |
788 | pdata->refb_r_div); | |
789 | if (ret < 0) | |
790 | return ret; | |
791 | ||
792 | ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER, | |
793 | pdata->pll1_feedback_div); | |
794 | if (ret < 0) | |
795 | return ret; | |
796 | ||
797 | ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL, | |
798 | AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata-> | |
799 | pll1_charge_pump_current_nA) | | |
800 | AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL | | |
801 | AD9523_PLL1_BACKLASH_PW_MIN); | |
802 | if (ret < 0) | |
803 | return ret; | |
804 | ||
805 | ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL, | |
806 | AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_RCV_EN) | | |
807 | AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_RCV_EN) | | |
808 | AD_IF(osc_in_diff_en, AD9523_PLL1_OSC_IN_DIFF_EN) | | |
809 | AD_IF(osc_in_cmos_neg_inp_en, | |
810 | AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN) | | |
811 | AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_DIFF_RCV_EN) | | |
812 | AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_DIFF_RCV_EN)); | |
813 | if (ret < 0) | |
814 | return ret; | |
815 | ||
816 | ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL, | |
817 | AD_IF(zd_in_diff_en, AD9523_PLL1_ZD_IN_DIFF_EN) | | |
818 | AD_IF(zd_in_cmos_neg_inp_en, | |
819 | AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN) | | |
820 | AD_IF(zero_delay_mode_internal_en, | |
821 | AD9523_PLL1_ZERO_DELAY_MODE_INT) | | |
822 | AD_IF(osc_in_feedback_en, AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN) | | |
823 | AD_IF(refa_cmos_neg_inp_en, AD9523_PLL1_REFA_CMOS_NEG_INP_EN) | | |
824 | AD_IF(refb_cmos_neg_inp_en, AD9523_PLL1_REFB_CMOS_NEG_INP_EN)); | |
825 | if (ret < 0) | |
826 | return ret; | |
827 | ||
828 | ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL, | |
829 | AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN | | |
830 | AD9523_PLL1_REF_MODE(pdata->ref_mode)); | |
831 | if (ret < 0) | |
832 | return ret; | |
833 | ||
834 | ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL, | |
835 | AD9523_PLL1_LOOP_FILTER_RZERO(pdata->pll1_loop_filter_rzero)); | |
836 | if (ret < 0) | |
837 | return ret; | |
838 | /* | |
839 | * PLL2 Setup | |
840 | */ | |
841 | ||
842 | ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP, | |
843 | AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata-> | |
844 | pll2_charge_pump_current_nA)); | |
845 | if (ret < 0) | |
846 | return ret; | |
847 | ||
848 | ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB, | |
849 | AD9523_PLL2_FB_NDIV_A_CNT(pdata->pll2_ndiv_a_cnt) | | |
850 | AD9523_PLL2_FB_NDIV_B_CNT(pdata->pll2_ndiv_b_cnt)); | |
851 | if (ret < 0) | |
852 | return ret; | |
853 | ||
854 | ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL, | |
855 | AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL | | |
856 | AD9523_PLL2_BACKLASH_CTRL_EN | | |
857 | AD_IF(pll2_freq_doubler_en, AD9523_PLL2_FREQ_DOUBLER_EN)); | |
858 | if (ret < 0) | |
859 | return ret; | |
860 | ||
861 | st->vco_freq = (pdata->vcxo_freq * (pdata->pll2_freq_doubler_en ? 2 : 1) | |
862 | / pdata->pll2_r2_div) * AD9523_PLL2_FB_NDIV(pdata-> | |
863 | pll2_ndiv_a_cnt, pdata->pll2_ndiv_b_cnt); | |
864 | ||
865 | ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL, | |
866 | AD9523_PLL2_VCO_CALIBRATE); | |
867 | if (ret < 0) | |
868 | return ret; | |
869 | ||
870 | ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER, | |
871 | AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_diff_m1) | | |
872 | AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_diff_m2) | | |
873 | AD_IFE(pll2_vco_diff_m1, 0, | |
874 | AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) | | |
875 | AD_IFE(pll2_vco_diff_m2, 0, | |
876 | AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN)); | |
877 | if (ret < 0) | |
878 | return ret; | |
879 | ||
880 | if (pdata->pll2_vco_diff_m1) | |
881 | st->vco_out_freq[AD9523_VCO1] = | |
882 | st->vco_freq / pdata->pll2_vco_diff_m1; | |
883 | ||
884 | if (pdata->pll2_vco_diff_m2) | |
885 | st->vco_out_freq[AD9523_VCO2] = | |
886 | st->vco_freq / pdata->pll2_vco_diff_m2; | |
887 | ||
888 | st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq; | |
889 | ||
890 | ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER, | |
891 | AD9523_PLL2_R2_DIVIDER_VAL(pdata->pll2_r2_div)); | |
892 | if (ret < 0) | |
893 | return ret; | |
894 | ||
895 | ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL, | |
896 | AD9523_PLL2_LOOP_FILTER_CPOLE1(pdata->cpole1) | | |
897 | AD9523_PLL2_LOOP_FILTER_RZERO(pdata->rzero) | | |
898 | AD9523_PLL2_LOOP_FILTER_RPOLE2(pdata->rpole2) | | |
899 | AD_IF(rzero_bypass_en, | |
900 | AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN)); | |
901 | if (ret < 0) | |
902 | return ret; | |
903 | ||
904 | for (i = 0; i < pdata->num_channels; i++) { | |
905 | chan = &pdata->channels[i]; | |
906 | if (chan->channel_num < AD9523_NUM_CHAN) { | |
907 | __set_bit(chan->channel_num, &active_mask); | |
908 | ret = ad9523_write(indio_dev, | |
909 | AD9523_CHANNEL_CLOCK_DIST(chan->channel_num), | |
910 | AD9523_CLK_DIST_DRIVER_MODE(chan->driver_mode) | | |
911 | AD9523_CLK_DIST_DIV(chan->channel_divider) | | |
912 | AD9523_CLK_DIST_DIV_PHASE(chan->divider_phase) | | |
913 | (chan->sync_ignore_en ? | |
914 | AD9523_CLK_DIST_IGNORE_SYNC_EN : 0) | | |
915 | (chan->divider_output_invert_en ? | |
916 | AD9523_CLK_DIST_INV_DIV_OUTPUT_EN : 0) | | |
917 | (chan->low_power_mode_en ? | |
918 | AD9523_CLK_DIST_LOW_PWR_MODE_EN : 0) | | |
919 | (chan->output_dis ? | |
920 | AD9523_CLK_DIST_PWR_DOWN_EN : 0)); | |
921 | if (ret < 0) | |
922 | return ret; | |
923 | ||
924 | ret = ad9523_vco_out_map(indio_dev, chan->channel_num, | |
925 | chan->use_alt_clock_src); | |
926 | if (ret < 0) | |
927 | return ret; | |
928 | ||
929 | st->ad9523_channels[i].type = IIO_ALTVOLTAGE; | |
930 | st->ad9523_channels[i].output = 1; | |
931 | st->ad9523_channels[i].indexed = 1; | |
932 | st->ad9523_channels[i].channel = chan->channel_num; | |
933 | st->ad9523_channels[i].extend_name = | |
934 | chan->extended_name; | |
beacbaac JC |
935 | st->ad9523_channels[i].info_mask_separate = |
936 | BIT(IIO_CHAN_INFO_RAW) | | |
937 | BIT(IIO_CHAN_INFO_PHASE) | | |
938 | BIT(IIO_CHAN_INFO_FREQUENCY); | |
cd1678f9 MH |
939 | } |
940 | } | |
941 | ||
942 | for_each_clear_bit(i, &active_mask, AD9523_NUM_CHAN) | |
943 | ad9523_write(indio_dev, | |
944 | AD9523_CHANNEL_CLOCK_DIST(i), | |
945 | AD9523_CLK_DIST_DRIVER_MODE(TRISTATE) | | |
946 | AD9523_CLK_DIST_PWR_DOWN_EN); | |
947 | ||
948 | ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0); | |
949 | if (ret < 0) | |
950 | return ret; | |
951 | ||
952 | ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, | |
953 | AD9523_STATUS_MONITOR_01_PLL12_LOCKED); | |
954 | if (ret < 0) | |
955 | return ret; | |
956 | ||
957 | ret = ad9523_io_update(indio_dev); | |
958 | if (ret < 0) | |
959 | return ret; | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
fc52692c | 964 | static int ad9523_probe(struct spi_device *spi) |
cd1678f9 MH |
965 | { |
966 | struct ad9523_platform_data *pdata = spi->dev.platform_data; | |
967 | struct iio_dev *indio_dev; | |
968 | struct ad9523_state *st; | |
969 | int ret; | |
970 | ||
971 | if (!pdata) { | |
972 | dev_err(&spi->dev, "no platform data?\n"); | |
973 | return -EINVAL; | |
974 | } | |
975 | ||
b46400c6 | 976 | indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); |
cd1678f9 MH |
977 | if (indio_dev == NULL) |
978 | return -ENOMEM; | |
979 | ||
980 | st = iio_priv(indio_dev); | |
981 | ||
69f894c3 LPC |
982 | mutex_init(&st->lock); |
983 | ||
b46400c6 | 984 | st->reg = devm_regulator_get(&spi->dev, "vcc"); |
cd1678f9 MH |
985 | if (!IS_ERR(st->reg)) { |
986 | ret = regulator_enable(st->reg); | |
987 | if (ret) | |
b46400c6 | 988 | return ret; |
cd1678f9 MH |
989 | } |
990 | ||
991 | spi_set_drvdata(spi, indio_dev); | |
992 | st->spi = spi; | |
993 | st->pdata = pdata; | |
994 | ||
995 | indio_dev->dev.parent = &spi->dev; | |
996 | indio_dev->name = (pdata->name[0] != 0) ? pdata->name : | |
997 | spi_get_device_id(spi)->name; | |
998 | indio_dev->info = &ad9523_info; | |
999 | indio_dev->modes = INDIO_DIRECT_MODE; | |
1000 | indio_dev->channels = st->ad9523_channels; | |
1001 | indio_dev->num_channels = pdata->num_channels; | |
1002 | ||
1003 | ret = ad9523_setup(indio_dev); | |
1004 | if (ret < 0) | |
1005 | goto error_disable_reg; | |
1006 | ||
1007 | ret = iio_device_register(indio_dev); | |
1008 | if (ret) | |
1009 | goto error_disable_reg; | |
1010 | ||
1011 | dev_info(&spi->dev, "probed %s\n", indio_dev->name); | |
1012 | ||
1013 | return 0; | |
1014 | ||
1015 | error_disable_reg: | |
1016 | if (!IS_ERR(st->reg)) | |
1017 | regulator_disable(st->reg); | |
cd1678f9 MH |
1018 | |
1019 | return ret; | |
1020 | } | |
1021 | ||
fc52692c | 1022 | static int ad9523_remove(struct spi_device *spi) |
cd1678f9 MH |
1023 | { |
1024 | struct iio_dev *indio_dev = spi_get_drvdata(spi); | |
1025 | struct ad9523_state *st = iio_priv(indio_dev); | |
1026 | ||
1027 | iio_device_unregister(indio_dev); | |
1028 | ||
b46400c6 | 1029 | if (!IS_ERR(st->reg)) |
cd1678f9 | 1030 | regulator_disable(st->reg); |
cd1678f9 MH |
1031 | |
1032 | return 0; | |
1033 | } | |
1034 | ||
1035 | static const struct spi_device_id ad9523_id[] = { | |
1036 | {"ad9523-1", 9523}, | |
1037 | {} | |
1038 | }; | |
1039 | MODULE_DEVICE_TABLE(spi, ad9523_id); | |
1040 | ||
1041 | static struct spi_driver ad9523_driver = { | |
1042 | .driver = { | |
1043 | .name = "ad9523", | |
cd1678f9 MH |
1044 | }, |
1045 | .probe = ad9523_probe, | |
fc52692c | 1046 | .remove = ad9523_remove, |
cd1678f9 MH |
1047 | .id_table = ad9523_id, |
1048 | }; | |
1049 | module_spi_driver(ad9523_driver); | |
1050 | ||
1051 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); | |
1052 | MODULE_DESCRIPTION("Analog Devices AD9523 CLOCKDIST/PLL"); | |
1053 | MODULE_LICENSE("GPL v2"); |