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cbd5dd38 | 1 | // SPDX-License-Identifier: GPL-2.0 |
c2f37c8d MH |
2 | /* |
3 | * AD5686R, AD5685R, AD5684R Digital to analog converters driver | |
4 | * | |
5 | * Copyright 2011 Analog Devices Inc. | |
c2f37c8d MH |
6 | */ |
7 | ||
8 | #include <linux/interrupt.h> | |
c2f37c8d MH |
9 | #include <linux/fs.h> |
10 | #include <linux/device.h> | |
99c97852 | 11 | #include <linux/module.h> |
c2f37c8d | 12 | #include <linux/kernel.h> |
c2f37c8d MH |
13 | #include <linux/slab.h> |
14 | #include <linux/sysfs.h> | |
15 | #include <linux/regulator/consumer.h> | |
16 | ||
06458e27 JC |
17 | #include <linux/iio/iio.h> |
18 | #include <linux/iio/sysfs.h> | |
c2f37c8d | 19 | |
0357e488 | 20 | #include "ad5686.h" |
c2f37c8d | 21 | |
fe4586a8 LPC |
22 | static const char * const ad5686_powerdown_modes[] = { |
23 | "1kohm_to_gnd", | |
24 | "100kohm_to_gnd", | |
25 | "three_state" | |
26 | }; | |
27 | ||
28 | static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev, | |
25ffba7a | 29 | const struct iio_chan_spec *chan) |
c2f37c8d | 30 | { |
c2f37c8d | 31 | struct ad5686_state *st = iio_priv(indio_dev); |
c2f37c8d | 32 | |
fe4586a8 | 33 | return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1; |
c2f37c8d MH |
34 | } |
35 | ||
fe4586a8 | 36 | static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev, |
25ffba7a SP |
37 | const struct iio_chan_spec *chan, |
38 | unsigned int mode) | |
c2f37c8d | 39 | { |
c2f37c8d | 40 | struct ad5686_state *st = iio_priv(indio_dev); |
c2f37c8d | 41 | |
fe4586a8 LPC |
42 | st->pwr_down_mode &= ~(0x3 << (chan->channel * 2)); |
43 | st->pwr_down_mode |= ((mode + 1) << (chan->channel * 2)); | |
c2f37c8d | 44 | |
fe4586a8 | 45 | return 0; |
c2f37c8d MH |
46 | } |
47 | ||
fe4586a8 LPC |
48 | static const struct iio_enum ad5686_powerdown_mode_enum = { |
49 | .items = ad5686_powerdown_modes, | |
50 | .num_items = ARRAY_SIZE(ad5686_powerdown_modes), | |
51 | .get = ad5686_get_powerdown_mode, | |
52 | .set = ad5686_set_powerdown_mode, | |
53 | }; | |
54 | ||
55 | static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev, | |
25ffba7a | 56 | uintptr_t private, const struct iio_chan_spec *chan, char *buf) |
c2f37c8d | 57 | { |
c2f37c8d | 58 | struct ad5686_state *st = iio_priv(indio_dev); |
c2f37c8d | 59 | |
f46ac009 | 60 | return sysfs_emit(buf, "%d\n", !!(st->pwr_down_mask & |
25ffba7a | 61 | (0x3 << (chan->channel * 2)))); |
c2f37c8d MH |
62 | } |
63 | ||
fe4586a8 | 64 | static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev, |
25ffba7a SP |
65 | uintptr_t private, |
66 | const struct iio_chan_spec *chan, | |
67 | const char *buf, | |
68 | size_t len) | |
c2f37c8d MH |
69 | { |
70 | bool readin; | |
71 | int ret; | |
c2f37c8d | 72 | struct ad5686_state *st = iio_priv(indio_dev); |
be1b24d2 | 73 | unsigned int val, ref_bit_msk; |
192778fb | 74 | u8 shift, address = 0; |
c2f37c8d | 75 | |
74f582ec | 76 | ret = kstrtobool(buf, &readin); |
c2f37c8d MH |
77 | if (ret) |
78 | return ret; | |
79 | ||
7737fa6d | 80 | if (readin) |
fe4586a8 | 81 | st->pwr_down_mask |= (0x3 << (chan->channel * 2)); |
c2f37c8d | 82 | else |
fe4586a8 | 83 | st->pwr_down_mask &= ~(0x3 << (chan->channel * 2)); |
c2f37c8d | 84 | |
be1b24d2 | 85 | switch (st->chip_info->regmap_type) { |
12d323cf SP |
86 | case AD5310_REGMAP: |
87 | shift = 9; | |
88 | ref_bit_msk = AD5310_REF_BIT_MSK; | |
89 | break; | |
1dbae4c6 SP |
90 | case AD5683_REGMAP: |
91 | shift = 13; | |
92 | ref_bit_msk = AD5683_REF_BIT_MSK; | |
93 | break; | |
be1b24d2 SP |
94 | case AD5686_REGMAP: |
95 | shift = 0; | |
96 | ref_bit_msk = 0; | |
192778fb MC |
97 | /* AD5674R/AD5679R have 16 channels and 2 powerdown registers */ |
98 | if (chan->channel > 0x7) | |
99 | address = 0x8; | |
be1b24d2 SP |
100 | break; |
101 | case AD5693_REGMAP: | |
102 | shift = 13; | |
103 | ref_bit_msk = AD5693_REF_BIT_MSK; | |
104 | break; | |
105 | default: | |
106 | return -EINVAL; | |
107 | } | |
108 | ||
109 | val = ((st->pwr_down_mask & st->pwr_down_mode) << shift); | |
110 | if (!st->use_internal_vref) | |
111 | val |= ref_bit_msk; | |
0357e488 | 112 | |
192778fb MC |
113 | ret = st->write(st, AD5686_CMD_POWERDOWN_DAC, |
114 | address, val >> (address * 2)); | |
c2f37c8d MH |
115 | |
116 | return ret ? ret : len; | |
117 | } | |
118 | ||
c2f37c8d MH |
119 | static int ad5686_read_raw(struct iio_dev *indio_dev, |
120 | struct iio_chan_spec const *chan, | |
121 | int *val, | |
122 | int *val2, | |
123 | long m) | |
124 | { | |
125 | struct ad5686_state *st = iio_priv(indio_dev); | |
c2f37c8d MH |
126 | int ret; |
127 | ||
128 | switch (m) { | |
09f4eb40 | 129 | case IIO_CHAN_INFO_RAW: |
0b2884ef | 130 | mutex_lock(&st->lock); |
0357e488 | 131 | ret = st->read(st, chan->address); |
0b2884ef | 132 | mutex_unlock(&st->lock); |
c2f37c8d MH |
133 | if (ret < 0) |
134 | return ret; | |
0e76df5c MC |
135 | *val = (ret >> chan->scan_type.shift) & |
136 | GENMASK(chan->scan_type.realbits - 1, 0); | |
c2f37c8d | 137 | return IIO_VAL_INT; |
c8a9f805 | 138 | case IIO_CHAN_INFO_SCALE: |
ecc7e948 LPC |
139 | *val = st->vref_mv; |
140 | *val2 = chan->scan_type.realbits; | |
141 | return IIO_VAL_FRACTIONAL_LOG2; | |
c2f37c8d MH |
142 | } |
143 | return -EINVAL; | |
144 | } | |
145 | ||
146 | static int ad5686_write_raw(struct iio_dev *indio_dev, | |
25ffba7a SP |
147 | struct iio_chan_spec const *chan, |
148 | int val, | |
149 | int val2, | |
150 | long mask) | |
c2f37c8d MH |
151 | { |
152 | struct ad5686_state *st = iio_priv(indio_dev); | |
153 | int ret; | |
154 | ||
155 | switch (mask) { | |
09f4eb40 | 156 | case IIO_CHAN_INFO_RAW: |
cd8eca6f | 157 | if (val > (1 << chan->scan_type.realbits) || val < 0) |
c2f37c8d MH |
158 | return -EINVAL; |
159 | ||
0b2884ef | 160 | mutex_lock(&st->lock); |
0357e488 SP |
161 | ret = st->write(st, |
162 | AD5686_CMD_WRITE_INPUT_N_UPDATE_N, | |
163 | chan->address, | |
164 | val << chan->scan_type.shift); | |
0b2884ef | 165 | mutex_unlock(&st->lock); |
c2f37c8d MH |
166 | break; |
167 | default: | |
168 | ret = -EINVAL; | |
169 | } | |
170 | ||
171 | return ret; | |
172 | } | |
173 | ||
174 | static const struct iio_info ad5686_info = { | |
175 | .read_raw = ad5686_read_raw, | |
176 | .write_raw = ad5686_write_raw, | |
c2f37c8d MH |
177 | }; |
178 | ||
fe4586a8 LPC |
179 | static const struct iio_chan_spec_ext_info ad5686_ext_info[] = { |
180 | { | |
181 | .name = "powerdown", | |
182 | .read = ad5686_read_dac_powerdown, | |
183 | .write = ad5686_write_dac_powerdown, | |
3704432f | 184 | .shared = IIO_SEPARATE, |
fe4586a8 | 185 | }, |
3704432f | 186 | IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum), |
ffc7c517 | 187 | IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5686_powerdown_mode_enum), |
fe4586a8 LPC |
188 | { }, |
189 | }; | |
190 | ||
f4a27306 | 191 | #define AD5868_CHANNEL(chan, addr, bits, _shift) { \ |
fe4586a8 LPC |
192 | .type = IIO_VOLTAGE, \ |
193 | .indexed = 1, \ | |
194 | .output = 1, \ | |
195 | .channel = chan, \ | |
d87a1d78 JC |
196 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
197 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\ | |
f4a27306 | 198 | .address = addr, \ |
44ba1593 JC |
199 | .scan_type = { \ |
200 | .sign = 'u', \ | |
201 | .realbits = (bits), \ | |
202 | .storagebits = 16, \ | |
203 | .shift = (_shift), \ | |
204 | }, \ | |
fe4586a8 LPC |
205 | .ext_info = ad5686_ext_info, \ |
206 | } | |
207 | ||
be1b24d2 | 208 | #define DECLARE_AD5693_CHANNELS(name, bits, _shift) \ |
59713492 | 209 | static const struct iio_chan_spec name[] = { \ |
be1b24d2 SP |
210 | AD5868_CHANNEL(0, 0, bits, _shift), \ |
211 | } | |
212 | ||
7dc8faea MA |
213 | #define DECLARE_AD5338_CHANNELS(name, bits, _shift) \ |
214 | static const struct iio_chan_spec name[] = { \ | |
215 | AD5868_CHANNEL(0, 1, bits, _shift), \ | |
216 | AD5868_CHANNEL(1, 8, bits, _shift), \ | |
217 | } | |
218 | ||
f4a27306 | 219 | #define DECLARE_AD5686_CHANNELS(name, bits, _shift) \ |
59713492 | 220 | static const struct iio_chan_spec name[] = { \ |
f4a27306 SP |
221 | AD5868_CHANNEL(0, 1, bits, _shift), \ |
222 | AD5868_CHANNEL(1, 2, bits, _shift), \ | |
223 | AD5868_CHANNEL(2, 4, bits, _shift), \ | |
224 | AD5868_CHANNEL(3, 8, bits, _shift), \ | |
225 | } | |
226 | ||
98baf78e | 227 | #define DECLARE_AD5676_CHANNELS(name, bits, _shift) \ |
59713492 | 228 | static const struct iio_chan_spec name[] = { \ |
98baf78e SP |
229 | AD5868_CHANNEL(0, 0, bits, _shift), \ |
230 | AD5868_CHANNEL(1, 1, bits, _shift), \ | |
231 | AD5868_CHANNEL(2, 2, bits, _shift), \ | |
232 | AD5868_CHANNEL(3, 3, bits, _shift), \ | |
233 | AD5868_CHANNEL(4, 4, bits, _shift), \ | |
234 | AD5868_CHANNEL(5, 5, bits, _shift), \ | |
235 | AD5868_CHANNEL(6, 6, bits, _shift), \ | |
236 | AD5868_CHANNEL(7, 7, bits, _shift), \ | |
237 | } | |
238 | ||
192778fb | 239 | #define DECLARE_AD5679_CHANNELS(name, bits, _shift) \ |
59713492 | 240 | static const struct iio_chan_spec name[] = { \ |
192778fb MC |
241 | AD5868_CHANNEL(0, 0, bits, _shift), \ |
242 | AD5868_CHANNEL(1, 1, bits, _shift), \ | |
243 | AD5868_CHANNEL(2, 2, bits, _shift), \ | |
244 | AD5868_CHANNEL(3, 3, bits, _shift), \ | |
245 | AD5868_CHANNEL(4, 4, bits, _shift), \ | |
246 | AD5868_CHANNEL(5, 5, bits, _shift), \ | |
247 | AD5868_CHANNEL(6, 6, bits, _shift), \ | |
248 | AD5868_CHANNEL(7, 7, bits, _shift), \ | |
249 | AD5868_CHANNEL(8, 8, bits, _shift), \ | |
250 | AD5868_CHANNEL(9, 9, bits, _shift), \ | |
251 | AD5868_CHANNEL(10, 10, bits, _shift), \ | |
252 | AD5868_CHANNEL(11, 11, bits, _shift), \ | |
253 | AD5868_CHANNEL(12, 12, bits, _shift), \ | |
254 | AD5868_CHANNEL(13, 13, bits, _shift), \ | |
255 | AD5868_CHANNEL(14, 14, bits, _shift), \ | |
256 | AD5868_CHANNEL(15, 15, bits, _shift), \ | |
257 | } | |
258 | ||
12d323cf | 259 | DECLARE_AD5693_CHANNELS(ad5310r_channels, 10, 2); |
d8084a04 | 260 | DECLARE_AD5693_CHANNELS(ad5311r_channels, 10, 6); |
58c26300 | 261 | DECLARE_AD5338_CHANNELS(ad5337r_channels, 8, 8); |
7dc8faea | 262 | DECLARE_AD5338_CHANNELS(ad5338r_channels, 10, 6); |
98baf78e | 263 | DECLARE_AD5676_CHANNELS(ad5672_channels, 12, 4); |
192778fb | 264 | DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4); |
98baf78e | 265 | DECLARE_AD5676_CHANNELS(ad5676_channels, 16, 0); |
192778fb | 266 | DECLARE_AD5679_CHANNELS(ad5679r_channels, 16, 0); |
f4a27306 SP |
267 | DECLARE_AD5686_CHANNELS(ad5684_channels, 12, 4); |
268 | DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2); | |
269 | DECLARE_AD5686_CHANNELS(ad5686_channels, 16, 0); | |
be1b24d2 SP |
270 | DECLARE_AD5693_CHANNELS(ad5693_channels, 16, 0); |
271 | DECLARE_AD5693_CHANNELS(ad5692r_channels, 14, 2); | |
272 | DECLARE_AD5693_CHANNELS(ad5691r_channels, 12, 4); | |
f4a27306 | 273 | |
fe4586a8 | 274 | static const struct ad5686_chip_info ad5686_chip_info_tbl[] = { |
12d323cf SP |
275 | [ID_AD5310R] = { |
276 | .channels = ad5310r_channels, | |
277 | .int_vref_mv = 2500, | |
278 | .num_channels = 1, | |
279 | .regmap_type = AD5310_REGMAP, | |
280 | }, | |
d8084a04 SP |
281 | [ID_AD5311R] = { |
282 | .channels = ad5311r_channels, | |
283 | .int_vref_mv = 2500, | |
284 | .num_channels = 1, | |
285 | .regmap_type = AD5693_REGMAP, | |
286 | }, | |
58c26300 FE |
287 | [ID_AD5337R] = { |
288 | .channels = ad5337r_channels, | |
289 | .int_vref_mv = 2500, | |
290 | .num_channels = 2, | |
291 | .regmap_type = AD5686_REGMAP, | |
292 | }, | |
7dc8faea MA |
293 | [ID_AD5338R] = { |
294 | .channels = ad5338r_channels, | |
295 | .int_vref_mv = 2500, | |
296 | .num_channels = 2, | |
297 | .regmap_type = AD5686_REGMAP, | |
298 | }, | |
4177381b SP |
299 | [ID_AD5671R] = { |
300 | .channels = ad5672_channels, | |
301 | .int_vref_mv = 2500, | |
302 | .num_channels = 8, | |
be1b24d2 | 303 | .regmap_type = AD5686_REGMAP, |
4177381b | 304 | }, |
98baf78e SP |
305 | [ID_AD5672R] = { |
306 | .channels = ad5672_channels, | |
307 | .int_vref_mv = 2500, | |
308 | .num_channels = 8, | |
be1b24d2 | 309 | .regmap_type = AD5686_REGMAP, |
98baf78e | 310 | }, |
477bd010 MC |
311 | [ID_AD5673R] = { |
312 | .channels = ad5674r_channels, | |
313 | .int_vref_mv = 2500, | |
314 | .num_channels = 16, | |
315 | .regmap_type = AD5686_REGMAP, | |
316 | }, | |
192778fb MC |
317 | [ID_AD5674R] = { |
318 | .channels = ad5674r_channels, | |
319 | .int_vref_mv = 2500, | |
320 | .num_channels = 16, | |
321 | .regmap_type = AD5686_REGMAP, | |
322 | }, | |
4177381b SP |
323 | [ID_AD5675R] = { |
324 | .channels = ad5676_channels, | |
325 | .int_vref_mv = 2500, | |
326 | .num_channels = 8, | |
be1b24d2 | 327 | .regmap_type = AD5686_REGMAP, |
4177381b | 328 | }, |
98baf78e SP |
329 | [ID_AD5676] = { |
330 | .channels = ad5676_channels, | |
331 | .num_channels = 8, | |
be1b24d2 | 332 | .regmap_type = AD5686_REGMAP, |
98baf78e SP |
333 | }, |
334 | [ID_AD5676R] = { | |
335 | .channels = ad5676_channels, | |
336 | .int_vref_mv = 2500, | |
337 | .num_channels = 8, | |
be1b24d2 | 338 | .regmap_type = AD5686_REGMAP, |
98baf78e | 339 | }, |
477bd010 MC |
340 | [ID_AD5677R] = { |
341 | .channels = ad5679r_channels, | |
342 | .int_vref_mv = 2500, | |
343 | .num_channels = 16, | |
344 | .regmap_type = AD5686_REGMAP, | |
345 | }, | |
192778fb MC |
346 | [ID_AD5679R] = { |
347 | .channels = ad5679r_channels, | |
348 | .int_vref_mv = 2500, | |
349 | .num_channels = 16, | |
350 | .regmap_type = AD5686_REGMAP, | |
351 | }, | |
1dbae4c6 SP |
352 | [ID_AD5681R] = { |
353 | .channels = ad5691r_channels, | |
354 | .int_vref_mv = 2500, | |
355 | .num_channels = 1, | |
356 | .regmap_type = AD5683_REGMAP, | |
357 | }, | |
358 | [ID_AD5682R] = { | |
359 | .channels = ad5692r_channels, | |
360 | .int_vref_mv = 2500, | |
361 | .num_channels = 1, | |
362 | .regmap_type = AD5683_REGMAP, | |
363 | }, | |
364 | [ID_AD5683] = { | |
365 | .channels = ad5693_channels, | |
366 | .num_channels = 1, | |
367 | .regmap_type = AD5683_REGMAP, | |
368 | }, | |
369 | [ID_AD5683R] = { | |
370 | .channels = ad5693_channels, | |
371 | .int_vref_mv = 2500, | |
372 | .num_channels = 1, | |
373 | .regmap_type = AD5683_REGMAP, | |
374 | }, | |
fe4586a8 | 375 | [ID_AD5684] = { |
f4a27306 SP |
376 | .channels = ad5684_channels, |
377 | .num_channels = 4, | |
be1b24d2 | 378 | .regmap_type = AD5686_REGMAP, |
98baf78e SP |
379 | }, |
380 | [ID_AD5684R] = { | |
381 | .channels = ad5684_channels, | |
fe4586a8 | 382 | .int_vref_mv = 2500, |
98baf78e | 383 | .num_channels = 4, |
be1b24d2 | 384 | .regmap_type = AD5686_REGMAP, |
fe4586a8 | 385 | }, |
fe642e2d | 386 | [ID_AD5685R] = { |
f4a27306 | 387 | .channels = ad5685r_channels, |
fe4586a8 | 388 | .int_vref_mv = 2500, |
f4a27306 | 389 | .num_channels = 4, |
be1b24d2 | 390 | .regmap_type = AD5686_REGMAP, |
fe4586a8 LPC |
391 | }, |
392 | [ID_AD5686] = { | |
f4a27306 SP |
393 | .channels = ad5686_channels, |
394 | .num_channels = 4, | |
be1b24d2 | 395 | .regmap_type = AD5686_REGMAP, |
98baf78e SP |
396 | }, |
397 | [ID_AD5686R] = { | |
398 | .channels = ad5686_channels, | |
fe4586a8 | 399 | .int_vref_mv = 2500, |
98baf78e | 400 | .num_channels = 4, |
be1b24d2 SP |
401 | .regmap_type = AD5686_REGMAP, |
402 | }, | |
403 | [ID_AD5691R] = { | |
404 | .channels = ad5691r_channels, | |
405 | .int_vref_mv = 2500, | |
406 | .num_channels = 1, | |
407 | .regmap_type = AD5693_REGMAP, | |
408 | }, | |
409 | [ID_AD5692R] = { | |
410 | .channels = ad5692r_channels, | |
411 | .int_vref_mv = 2500, | |
412 | .num_channels = 1, | |
413 | .regmap_type = AD5693_REGMAP, | |
414 | }, | |
415 | [ID_AD5693] = { | |
416 | .channels = ad5693_channels, | |
417 | .num_channels = 1, | |
418 | .regmap_type = AD5693_REGMAP, | |
419 | }, | |
420 | [ID_AD5693R] = { | |
421 | .channels = ad5693_channels, | |
422 | .int_vref_mv = 2500, | |
423 | .num_channels = 1, | |
424 | .regmap_type = AD5693_REGMAP, | |
fe4586a8 | 425 | }, |
4177381b SP |
426 | [ID_AD5694] = { |
427 | .channels = ad5684_channels, | |
428 | .num_channels = 4, | |
be1b24d2 | 429 | .regmap_type = AD5686_REGMAP, |
4177381b SP |
430 | }, |
431 | [ID_AD5694R] = { | |
432 | .channels = ad5684_channels, | |
433 | .int_vref_mv = 2500, | |
434 | .num_channels = 4, | |
be1b24d2 | 435 | .regmap_type = AD5686_REGMAP, |
4177381b SP |
436 | }, |
437 | [ID_AD5696] = { | |
438 | .channels = ad5686_channels, | |
439 | .num_channels = 4, | |
be1b24d2 | 440 | .regmap_type = AD5686_REGMAP, |
4177381b SP |
441 | }, |
442 | [ID_AD5696R] = { | |
443 | .channels = ad5686_channels, | |
444 | .int_vref_mv = 2500, | |
445 | .num_channels = 4, | |
be1b24d2 | 446 | .regmap_type = AD5686_REGMAP, |
4177381b | 447 | }, |
fe4586a8 LPC |
448 | }; |
449 | ||
0357e488 SP |
450 | int ad5686_probe(struct device *dev, |
451 | enum ad5686_supported_device_ids chip_type, | |
452 | const char *name, ad5686_write_func write, | |
453 | ad5686_read_func read) | |
c2f37c8d MH |
454 | { |
455 | struct ad5686_state *st; | |
456 | struct iio_dev *indio_dev; | |
be1b24d2 SP |
457 | unsigned int val, ref_bit_msk; |
458 | u8 cmd; | |
459 | int ret, i, voltage_uv = 0; | |
c2f37c8d | 460 | |
0357e488 | 461 | indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); |
c2f37c8d MH |
462 | if (indio_dev == NULL) |
463 | return -ENOMEM; | |
464 | ||
465 | st = iio_priv(indio_dev); | |
0357e488 SP |
466 | dev_set_drvdata(dev, indio_dev); |
467 | ||
468 | st->dev = dev; | |
469 | st->write = write; | |
470 | st->read = read; | |
c2f37c8d | 471 | |
0357e488 | 472 | st->reg = devm_regulator_get_optional(dev, "vcc"); |
c2f37c8d MH |
473 | if (!IS_ERR(st->reg)) { |
474 | ret = regulator_enable(st->reg); | |
475 | if (ret) | |
edf3fd41 | 476 | return ret; |
c2f37c8d | 477 | |
359570ad AL |
478 | ret = regulator_get_voltage(st->reg); |
479 | if (ret < 0) | |
480 | goto error_disable_reg; | |
481 | ||
482 | voltage_uv = ret; | |
c2f37c8d MH |
483 | } |
484 | ||
0357e488 | 485 | st->chip_info = &ad5686_chip_info_tbl[chip_type]; |
c2f37c8d MH |
486 | |
487 | if (voltage_uv) | |
488 | st->vref_mv = voltage_uv / 1000; | |
489 | else | |
490 | st->vref_mv = st->chip_info->int_vref_mv; | |
491 | ||
fe4586a8 | 492 | /* Set all the power down mode for all channels to 1K pulldown */ |
be1b24d2 SP |
493 | for (i = 0; i < st->chip_info->num_channels; i++) |
494 | st->pwr_down_mode |= (0x01 << (i * 2)); | |
fe4586a8 | 495 | |
0357e488 | 496 | indio_dev->name = name; |
c2f37c8d MH |
497 | indio_dev->info = &ad5686_info; |
498 | indio_dev->modes = INDIO_DIRECT_MODE; | |
f4a27306 SP |
499 | indio_dev->channels = st->chip_info->channels; |
500 | indio_dev->num_channels = st->chip_info->num_channels; | |
c2f37c8d | 501 | |
0b2884ef SC |
502 | mutex_init(&st->lock); |
503 | ||
be1b24d2 | 504 | switch (st->chip_info->regmap_type) { |
12d323cf SP |
505 | case AD5310_REGMAP: |
506 | cmd = AD5686_CMD_CONTROL_REG; | |
507 | ref_bit_msk = AD5310_REF_BIT_MSK; | |
508 | st->use_internal_vref = !voltage_uv; | |
509 | break; | |
1dbae4c6 SP |
510 | case AD5683_REGMAP: |
511 | cmd = AD5686_CMD_CONTROL_REG; | |
512 | ref_bit_msk = AD5683_REF_BIT_MSK; | |
513 | st->use_internal_vref = !voltage_uv; | |
514 | break; | |
be1b24d2 SP |
515 | case AD5686_REGMAP: |
516 | cmd = AD5686_CMD_INTERNAL_REFER_SETUP; | |
517 | ref_bit_msk = 0; | |
518 | break; | |
519 | case AD5693_REGMAP: | |
520 | cmd = AD5686_CMD_CONTROL_REG; | |
521 | ref_bit_msk = AD5693_REF_BIT_MSK; | |
522 | st->use_internal_vref = !voltage_uv; | |
523 | break; | |
524 | default: | |
525 | ret = -EINVAL; | |
526 | goto error_disable_reg; | |
527 | } | |
528 | ||
529 | val = (voltage_uv | ref_bit_msk); | |
530 | ||
531 | ret = st->write(st, cmd, 0, !!val); | |
c2f37c8d MH |
532 | if (ret) |
533 | goto error_disable_reg; | |
534 | ||
26d25ae3 JC |
535 | ret = iio_device_register(indio_dev); |
536 | if (ret) | |
537 | goto error_disable_reg; | |
538 | ||
c2f37c8d MH |
539 | return 0; |
540 | ||
541 | error_disable_reg: | |
542 | if (!IS_ERR(st->reg)) | |
543 | regulator_disable(st->reg); | |
c2f37c8d MH |
544 | return ret; |
545 | } | |
2ebc23b3 | 546 | EXPORT_SYMBOL_NS_GPL(ad5686_probe, IIO_AD5686); |
c2f37c8d | 547 | |
3ceed021 | 548 | void ad5686_remove(struct device *dev) |
c2f37c8d | 549 | { |
0357e488 | 550 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
c2f37c8d | 551 | struct ad5686_state *st = iio_priv(indio_dev); |
c2f37c8d | 552 | |
d2fffd6c | 553 | iio_device_unregister(indio_dev); |
edf3fd41 | 554 | if (!IS_ERR(st->reg)) |
26a54797 | 555 | regulator_disable(st->reg); |
c2f37c8d | 556 | } |
2ebc23b3 | 557 | EXPORT_SYMBOL_NS_GPL(ad5686_remove, IIO_AD5686); |
c2f37c8d | 558 | |
9920ed25 | 559 | MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); |
c2f37c8d MH |
560 | MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC"); |
561 | MODULE_LICENSE("GPL v2"); |