[linux-block.git] / drivers / iio / dac / ad5686.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * AD5686R, AD5685R, AD5684R Digital to analog converters  driver
 *
 * Copyright 2011 Analog Devices Inc.
 */

#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>

#include "ad5686.h"

static const char * const ad5686_powerdown_modes[] = {
	"1kohm_to_gnd",
	"100kohm_to_gnd",
	"three_state"
};

static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev,
				     const struct iio_chan_spec *chan)
{
	struct ad5686_state *st = iio_priv(indio_dev);

	return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1;
}

static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev,
				     const struct iio_chan_spec *chan,
				     unsigned int mode)
{
	struct ad5686_state *st = iio_priv(indio_dev);

	st->pwr_down_mode &= ~(0x3 << (chan->channel * 2));
	st->pwr_down_mode |= ((mode + 1) << (chan->channel * 2));

	return 0;
}

static const struct iio_enum ad5686_powerdown_mode_enum = {
	.items = ad5686_powerdown_modes,
	.num_items = ARRAY_SIZE(ad5686_powerdown_modes),
	.get = ad5686_get_powerdown_mode,
	.set = ad5686_set_powerdown_mode,
};

static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev,
		uintptr_t private, const struct iio_chan_spec *chan, char *buf)
{
	struct ad5686_state *st = iio_priv(indio_dev);

	return sprintf(buf, "%d\n", !!(st->pwr_down_mask &
				       (0x3 << (chan->channel * 2))));
}

static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev,
					  uintptr_t private,
					  const struct iio_chan_spec *chan,
					  const char *buf,
					  size_t len)
{
	bool readin;
	int ret;
	struct ad5686_state *st = iio_priv(indio_dev);
	unsigned int val, ref_bit_msk;
	u8 shift;

	ret = strtobool(buf, &readin);
	if (ret)
		return ret;

	if (readin)
		st->pwr_down_mask |= (0x3 << (chan->channel * 2));
	else
		st->pwr_down_mask &= ~(0x3 << (chan->channel * 2));

	switch (st->chip_info->regmap_type) {
	case AD5683_REGMAP:
		shift = 13;
		ref_bit_msk = AD5683_REF_BIT_MSK;
		break;
	case AD5686_REGMAP:
		shift = 0;
		ref_bit_msk = 0;
		break;
	case AD5693_REGMAP:
		shift = 13;
		ref_bit_msk = AD5693_REF_BIT_MSK;
		break;
	default:
		return -EINVAL;
	}

	val = ((st->pwr_down_mask & st->pwr_down_mode) << shift);
	if (!st->use_internal_vref)
		val |= ref_bit_msk;

	ret = st->write(st, AD5686_CMD_POWERDOWN_DAC, 0, val);

	return ret ? ret : len;
}

static int ad5686_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	struct ad5686_state *st = iio_priv(indio_dev);
	int ret;

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		mutex_lock(&indio_dev->mlock);
		ret = st->read(st, chan->address);
		mutex_unlock(&indio_dev->mlock);
		if (ret < 0)
			return ret;
		*val = ret;
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		*val = st->vref_mv;
		*val2 = chan->scan_type.realbits;
		return IIO_VAL_FRACTIONAL_LOG2;
	}
	return -EINVAL;
}

static int ad5686_write_raw(struct iio_dev *indio_dev,
			    struct iio_chan_spec const *chan,
			    int val,
			    int val2,
			    long mask)
{
	struct ad5686_state *st = iio_priv(indio_dev);
	int ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		if (val > (1 << chan->scan_type.realbits) || val < 0)
			return -EINVAL;

		mutex_lock(&indio_dev->mlock);
		ret = st->write(st,
				AD5686_CMD_WRITE_INPUT_N_UPDATE_N,
				chan->address,
				val << chan->scan_type.shift);
		mutex_unlock(&indio_dev->mlock);
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static const struct iio_info ad5686_info = {
	.read_raw = ad5686_read_raw,
	.write_raw = ad5686_write_raw,
};

static const struct iio_chan_spec_ext_info ad5686_ext_info[] = {
	{
		.name = "powerdown",
		.read = ad5686_read_dac_powerdown,
		.write = ad5686_write_dac_powerdown,
		.shared = IIO_SEPARATE,
	},
	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum),
	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5686_powerdown_mode_enum),
	{ },
};

#define AD5868_CHANNEL(chan, addr, bits, _shift) {		\
		.type = IIO_VOLTAGE,				\
		.indexed = 1,					\
		.output = 1,					\
		.channel = chan,				\
		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\
		.address = addr,				\
		.scan_type = {					\
			.sign = 'u',				\
			.realbits = (bits),			\
			.storagebits = 16,			\
			.shift = (_shift),			\
		},						\
		.ext_info = ad5686_ext_info,			\
}

#define DECLARE_AD5693_CHANNELS(name, bits, _shift)		\
static struct iio_chan_spec name[] = {				\
		AD5868_CHANNEL(0, 0, bits, _shift),		\
}

#define DECLARE_AD5686_CHANNELS(name, bits, _shift)		\
static struct iio_chan_spec name[] = {				\
		AD5868_CHANNEL(0, 1, bits, _shift),		\
		AD5868_CHANNEL(1, 2, bits, _shift),		\
		AD5868_CHANNEL(2, 4, bits, _shift),		\
		AD5868_CHANNEL(3, 8, bits, _shift),		\
}

#define DECLARE_AD5676_CHANNELS(name, bits, _shift)		\
static struct iio_chan_spec name[] = {				\
		AD5868_CHANNEL(0, 0, bits, _shift),		\
		AD5868_CHANNEL(1, 1, bits, _shift),		\
		AD5868_CHANNEL(2, 2, bits, _shift),		\
		AD5868_CHANNEL(3, 3, bits, _shift),		\
		AD5868_CHANNEL(4, 4, bits, _shift),		\
		AD5868_CHANNEL(5, 5, bits, _shift),		\
		AD5868_CHANNEL(6, 6, bits, _shift),		\
		AD5868_CHANNEL(7, 7, bits, _shift),		\
}

DECLARE_AD5693_CHANNELS(ad5311r_channels, 10, 6);
DECLARE_AD5676_CHANNELS(ad5672_channels, 12, 4);
DECLARE_AD5676_CHANNELS(ad5676_channels, 16, 0);
DECLARE_AD5686_CHANNELS(ad5684_channels, 12, 4);
DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2);
DECLARE_AD5686_CHANNELS(ad5686_channels, 16, 0);
DECLARE_AD5693_CHANNELS(ad5693_channels, 16, 0);
DECLARE_AD5693_CHANNELS(ad5692r_channels, 14, 2);
DECLARE_AD5693_CHANNELS(ad5691r_channels, 12, 4);

static const struct ad5686_chip_info ad5686_chip_info_tbl[] = {
	[ID_AD5311R] = {
		.channels = ad5311r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5693_REGMAP,
	},
	[ID_AD5671R] = {
		.channels = ad5672_channels,
		.int_vref_mv = 2500,
		.num_channels = 8,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5672R] = {
		.channels = ad5672_channels,
		.int_vref_mv = 2500,
		.num_channels = 8,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5675R] = {
		.channels = ad5676_channels,
		.int_vref_mv = 2500,
		.num_channels = 8,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5676] = {
		.channels = ad5676_channels,
		.num_channels = 8,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5676R] = {
		.channels = ad5676_channels,
		.int_vref_mv = 2500,
		.num_channels = 8,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5681R] = {
		.channels = ad5691r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5683_REGMAP,
	},
	[ID_AD5682R] = {
		.channels = ad5692r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5683_REGMAP,
	},
	[ID_AD5683] = {
		.channels = ad5693_channels,
		.num_channels = 1,
		.regmap_type = AD5683_REGMAP,
	},
	[ID_AD5683R] = {
		.channels = ad5693_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5683_REGMAP,
	},
	[ID_AD5684] = {
		.channels = ad5684_channels,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5684R] = {
		.channels = ad5684_channels,
		.int_vref_mv = 2500,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5685R] = {
		.channels = ad5685r_channels,
		.int_vref_mv = 2500,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5686] = {
		.channels = ad5686_channels,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5686R] = {
		.channels = ad5686_channels,
		.int_vref_mv = 2500,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5691R] = {
		.channels = ad5691r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5693_REGMAP,
	},
	[ID_AD5692R] = {
		.channels = ad5692r_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5693_REGMAP,
	},
	[ID_AD5693] = {
		.channels = ad5693_channels,
		.num_channels = 1,
		.regmap_type = AD5693_REGMAP,
	},
	[ID_AD5693R] = {
		.channels = ad5693_channels,
		.int_vref_mv = 2500,
		.num_channels = 1,
		.regmap_type = AD5693_REGMAP,
	},
	[ID_AD5694] = {
		.channels = ad5684_channels,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5694R] = {
		.channels = ad5684_channels,
		.int_vref_mv = 2500,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5696] = {
		.channels = ad5686_channels,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
	[ID_AD5696R] = {
		.channels = ad5686_channels,
		.int_vref_mv = 2500,
		.num_channels = 4,
		.regmap_type = AD5686_REGMAP,
	},
};

int ad5686_probe(struct device *dev,
		 enum ad5686_supported_device_ids chip_type,
		 const char *name, ad5686_write_func write,
		 ad5686_read_func read)
{
	struct ad5686_state *st;
	struct iio_dev *indio_dev;
	unsigned int val, ref_bit_msk;
	u8 cmd;
	int ret, i, voltage_uv = 0;

	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
	if (indio_dev == NULL)
		return  -ENOMEM;

	st = iio_priv(indio_dev);
	dev_set_drvdata(dev, indio_dev);

	st->dev = dev;
	st->write = write;
	st->read = read;

	st->reg = devm_regulator_get_optional(dev, "vcc");
	if (!IS_ERR(st->reg)) {
		ret = regulator_enable(st->reg);
		if (ret)
			return ret;

		ret = regulator_get_voltage(st->reg);
		if (ret < 0)
			goto error_disable_reg;

		voltage_uv = ret;
	}

	st->chip_info = &ad5686_chip_info_tbl[chip_type];

	if (voltage_uv)
		st->vref_mv = voltage_uv / 1000;
	else
		st->vref_mv = st->chip_info->int_vref_mv;

	/* Set all the power down mode for all channels to 1K pulldown */
	for (i = 0; i < st->chip_info->num_channels; i++)
		st->pwr_down_mode |= (0x01 << (i * 2));

	indio_dev->dev.parent = dev;
	indio_dev->name = name;
	indio_dev->info = &ad5686_info;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = st->chip_info->channels;
	indio_dev->num_channels = st->chip_info->num_channels;

	switch (st->chip_info->regmap_type) {
	case AD5683_REGMAP:
		cmd = AD5686_CMD_CONTROL_REG;
		ref_bit_msk = AD5683_REF_BIT_MSK;
		st->use_internal_vref = !voltage_uv;
		break;
	case AD5686_REGMAP:
		cmd = AD5686_CMD_INTERNAL_REFER_SETUP;
		ref_bit_msk = 0;
		break;
	case AD5693_REGMAP:
		cmd = AD5686_CMD_CONTROL_REG;
		ref_bit_msk = AD5693_REF_BIT_MSK;
		st->use_internal_vref = !voltage_uv;
		break;
	default:
		ret = -EINVAL;
		goto error_disable_reg;
	}

	val = (voltage_uv | ref_bit_msk);

	ret = st->write(st, cmd, 0, !!val);
	if (ret)
		goto error_disable_reg;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_disable_reg;

	return 0;

error_disable_reg:
	if (!IS_ERR(st->reg))
		regulator_disable(st->reg);
	return ret;
}
EXPORT_SYMBOL_GPL(ad5686_probe);

int ad5686_remove(struct device *dev)
{
	struct iio_dev *indio_dev = dev_get_drvdata(dev);
	struct ad5686_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	if (!IS_ERR(st->reg))
		regulator_disable(st->reg);

	return 0;
}
EXPORT_SYMBOL_GPL(ad5686_remove);

MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
16a3c175	1	// SPDX-License-Identifier: GPL-2.0+
c2f37c8d MH	2	/*
	3	* AD5686R, AD5685R, AD5684R Digital to analog converters driver
	4	*
	5	* Copyright 2011 Analog Devices Inc.
c2f37c8d MH	6	*/
	7
	8	#include <linux/interrupt.h>
c2f37c8d MH	9	#include <linux/fs.h>
c2f37c8d MH	10	#include <linux/device.h>
99c97852	11	#include <linux/module.h>
c2f37c8d	12	#include <linux/kernel.h>
c2f37c8d MH	13	#include <linux/slab.h>
	14	#include <linux/sysfs.h>
	15	#include <linux/regulator/consumer.h>
	16
06458e27 JC	17	#include <linux/iio/iio.h>
06458e27 JC	18	#include <linux/iio/sysfs.h>
c2f37c8d	19
0357e488	20	#include "ad5686.h"
c2f37c8d	21
fe4586a8 LPC	22	static const char * const ad5686_powerdown_modes[] = {
	23	"1kohm_to_gnd",
	24	"100kohm_to_gnd",
	25	"three_state"
	26	};
	27
	28	static int ad5686_get_powerdown_mode(struct iio_dev *indio_dev,
25ffba7a	29	const struct iio_chan_spec *chan)
c2f37c8d	30	{
c2f37c8d	31	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d	32
fe4586a8	33	return ((st->pwr_down_mode >> (chan->channel * 2)) & 0x3) - 1;
c2f37c8d MH	34	}
c2f37c8d MH	35
fe4586a8	36	static int ad5686_set_powerdown_mode(struct iio_dev *indio_dev,
25ffba7a SP	37	const struct iio_chan_spec *chan,
25ffba7a SP	38	unsigned int mode)
c2f37c8d	39	{
c2f37c8d	40	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d	41
fe4586a8 LPC	42	st->pwr_down_mode &= ~(0x3 << (chan->channel * 2));
fe4586a8 LPC	43	st->pwr_down_mode \|= ((mode + 1) << (chan->channel * 2));
c2f37c8d	44
fe4586a8	45	return 0;
c2f37c8d MH	46	}
c2f37c8d MH	47
fe4586a8 LPC	48	static const struct iio_enum ad5686_powerdown_mode_enum = {
	49	.items = ad5686_powerdown_modes,
	50	.num_items = ARRAY_SIZE(ad5686_powerdown_modes),
	51	.get = ad5686_get_powerdown_mode,
	52	.set = ad5686_set_powerdown_mode,
	53	};
	54
	55	static ssize_t ad5686_read_dac_powerdown(struct iio_dev *indio_dev,
25ffba7a	56	uintptr_t private, const struct iio_chan_spec chan, char buf)
c2f37c8d	57	{
c2f37c8d	58	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d MH	59
c2f37c8d MH	60	return sprintf(buf, "%d\n", !!(st->pwr_down_mask &
25ffba7a	61	(0x3 << (chan->channel * 2))));
c2f37c8d MH	62	}
c2f37c8d MH	63
fe4586a8	64	static ssize_t ad5686_write_dac_powerdown(struct iio_dev *indio_dev,
25ffba7a SP	65	uintptr_t private,
	66	const struct iio_chan_spec *chan,
	67	const char *buf,
	68	size_t len)
c2f37c8d MH	69	{
	70	bool readin;
	71	int ret;
c2f37c8d	72	struct ad5686_state *st = iio_priv(indio_dev);
be1b24d2 SP	73	unsigned int val, ref_bit_msk;
be1b24d2 SP	74	u8 shift;
c2f37c8d MH	75
	76	ret = strtobool(buf, &readin);
	77	if (ret)
	78	return ret;
	79
7737fa6d	80	if (readin)
fe4586a8	81	st->pwr_down_mask \|= (0x3 << (chan->channel * 2));
c2f37c8d	82	else
fe4586a8	83	st->pwr_down_mask &= ~(0x3 << (chan->channel * 2));
c2f37c8d	84
be1b24d2	85	switch (st->chip_info->regmap_type) {
1dbae4c6 SP	86	case AD5683_REGMAP:
	87	shift = 13;
	88	ref_bit_msk = AD5683_REF_BIT_MSK;
	89	break;
be1b24d2 SP	90	case AD5686_REGMAP:
	91	shift = 0;
	92	ref_bit_msk = 0;
	93	break;
	94	case AD5693_REGMAP:
	95	shift = 13;
	96	ref_bit_msk = AD5693_REF_BIT_MSK;
	97	break;
	98	default:
	99	return -EINVAL;
	100	}
	101
	102	val = ((st->pwr_down_mask & st->pwr_down_mode) << shift);
	103	if (!st->use_internal_vref)
	104	val \|= ref_bit_msk;
0357e488	105
be1b24d2	106	ret = st->write(st, AD5686_CMD_POWERDOWN_DAC, 0, val);
c2f37c8d MH	107
	108	return ret ? ret : len;
	109	}
	110
c2f37c8d MH	111	static int ad5686_read_raw(struct iio_dev *indio_dev,
	112	struct iio_chan_spec const *chan,
	113	int *val,
	114	int *val2,
	115	long m)
	116	{
	117	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d MH	118	int ret;
	119
	120	switch (m) {
09f4eb40	121	case IIO_CHAN_INFO_RAW:
c2f37c8d	122	mutex_lock(&indio_dev->mlock);
0357e488	123	ret = st->read(st, chan->address);
c2f37c8d MH	124	mutex_unlock(&indio_dev->mlock);
	125	if (ret < 0)
	126	return ret;
	127	*val = ret;
	128	return IIO_VAL_INT;
c8a9f805	129	case IIO_CHAN_INFO_SCALE:
ecc7e948 LPC	130	*val = st->vref_mv;
	131	*val2 = chan->scan_type.realbits;
	132	return IIO_VAL_FRACTIONAL_LOG2;
c2f37c8d MH	133	}
	134	return -EINVAL;
	135	}
	136
	137	static int ad5686_write_raw(struct iio_dev *indio_dev,
25ffba7a SP	138	struct iio_chan_spec const *chan,
	139	int val,
	140	int val2,
	141	long mask)
c2f37c8d MH	142	{
	143	struct ad5686_state *st = iio_priv(indio_dev);
	144	int ret;
	145
	146	switch (mask) {
09f4eb40	147	case IIO_CHAN_INFO_RAW:
cd8eca6f	148	if (val > (1 << chan->scan_type.realbits) \|\| val < 0)
c2f37c8d MH	149	return -EINVAL;
	150
	151	mutex_lock(&indio_dev->mlock);
0357e488 SP	152	ret = st->write(st,
	153	AD5686_CMD_WRITE_INPUT_N_UPDATE_N,
	154	chan->address,
	155	val << chan->scan_type.shift);
c2f37c8d MH	156	mutex_unlock(&indio_dev->mlock);
	157	break;
	158	default:
	159	ret = -EINVAL;
	160	}
	161
	162	return ret;
	163	}
	164
	165	static const struct iio_info ad5686_info = {
	166	.read_raw = ad5686_read_raw,
	167	.write_raw = ad5686_write_raw,
c2f37c8d MH	168	};
c2f37c8d MH	169
fe4586a8 LPC	170	static const struct iio_chan_spec_ext_info ad5686_ext_info[] = {
	171	{
	172	.name = "powerdown",
	173	.read = ad5686_read_dac_powerdown,
	174	.write = ad5686_write_dac_powerdown,
3704432f	175	.shared = IIO_SEPARATE,
fe4586a8	176	},
3704432f	177	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5686_powerdown_mode_enum),
fe4586a8 LPC	178	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5686_powerdown_mode_enum),
	179	{ },
	180	};
	181
f4a27306	182	#define AD5868_CHANNEL(chan, addr, bits, _shift) { \
fe4586a8 LPC	183	.type = IIO_VOLTAGE, \
	184	.indexed = 1, \
	185	.output = 1, \
	186	.channel = chan, \
d87a1d78 JC	187	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
d87a1d78 JC	188	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\
f4a27306	189	.address = addr, \
44ba1593 JC	190	.scan_type = { \
	191	.sign = 'u', \
	192	.realbits = (bits), \
	193	.storagebits = 16, \
	194	.shift = (_shift), \
	195	}, \
fe4586a8 LPC	196	.ext_info = ad5686_ext_info, \
	197	}
	198
be1b24d2 SP	199	#define DECLARE_AD5693_CHANNELS(name, bits, _shift) \
	200	static struct iio_chan_spec name[] = { \
	201	AD5868_CHANNEL(0, 0, bits, _shift), \
	202	}
	203
f4a27306 SP	204	#define DECLARE_AD5686_CHANNELS(name, bits, _shift) \
	205	static struct iio_chan_spec name[] = { \
	206	AD5868_CHANNEL(0, 1, bits, _shift), \
	207	AD5868_CHANNEL(1, 2, bits, _shift), \
	208	AD5868_CHANNEL(2, 4, bits, _shift), \
	209	AD5868_CHANNEL(3, 8, bits, _shift), \
	210	}
	211
98baf78e SP	212	#define DECLARE_AD5676_CHANNELS(name, bits, _shift) \
	213	static struct iio_chan_spec name[] = { \
	214	AD5868_CHANNEL(0, 0, bits, _shift), \
	215	AD5868_CHANNEL(1, 1, bits, _shift), \
	216	AD5868_CHANNEL(2, 2, bits, _shift), \
	217	AD5868_CHANNEL(3, 3, bits, _shift), \
	218	AD5868_CHANNEL(4, 4, bits, _shift), \
	219	AD5868_CHANNEL(5, 5, bits, _shift), \
	220	AD5868_CHANNEL(6, 6, bits, _shift), \
	221	AD5868_CHANNEL(7, 7, bits, _shift), \
	222	}
	223
d8084a04	224	DECLARE_AD5693_CHANNELS(ad5311r_channels, 10, 6);
98baf78e SP	225	DECLARE_AD5676_CHANNELS(ad5672_channels, 12, 4);
98baf78e SP	226	DECLARE_AD5676_CHANNELS(ad5676_channels, 16, 0);
f4a27306 SP	227	DECLARE_AD5686_CHANNELS(ad5684_channels, 12, 4);
	228	DECLARE_AD5686_CHANNELS(ad5685r_channels, 14, 2);
	229	DECLARE_AD5686_CHANNELS(ad5686_channels, 16, 0);
be1b24d2 SP	230	DECLARE_AD5693_CHANNELS(ad5693_channels, 16, 0);
	231	DECLARE_AD5693_CHANNELS(ad5692r_channels, 14, 2);
	232	DECLARE_AD5693_CHANNELS(ad5691r_channels, 12, 4);
f4a27306	233
fe4586a8	234	static const struct ad5686_chip_info ad5686_chip_info_tbl[] = {
d8084a04 SP	235	[ID_AD5311R] = {
	236	.channels = ad5311r_channels,
	237	.int_vref_mv = 2500,
	238	.num_channels = 1,
	239	.regmap_type = AD5693_REGMAP,
	240	},
4177381b SP	241	[ID_AD5671R] = {
	242	.channels = ad5672_channels,
	243	.int_vref_mv = 2500,
	244	.num_channels = 8,
be1b24d2	245	.regmap_type = AD5686_REGMAP,
4177381b	246	},
98baf78e SP	247	[ID_AD5672R] = {
	248	.channels = ad5672_channels,
	249	.int_vref_mv = 2500,
	250	.num_channels = 8,
be1b24d2	251	.regmap_type = AD5686_REGMAP,
98baf78e	252	},
4177381b SP	253	[ID_AD5675R] = {
	254	.channels = ad5676_channels,
	255	.int_vref_mv = 2500,
	256	.num_channels = 8,
be1b24d2	257	.regmap_type = AD5686_REGMAP,
4177381b	258	},
98baf78e SP	259	[ID_AD5676] = {
	260	.channels = ad5676_channels,
	261	.num_channels = 8,
be1b24d2	262	.regmap_type = AD5686_REGMAP,
98baf78e SP	263	},
	264	[ID_AD5676R] = {
	265	.channels = ad5676_channels,
	266	.int_vref_mv = 2500,
	267	.num_channels = 8,
be1b24d2	268	.regmap_type = AD5686_REGMAP,
98baf78e	269	},
1dbae4c6 SP	270	[ID_AD5681R] = {
	271	.channels = ad5691r_channels,
	272	.int_vref_mv = 2500,
	273	.num_channels = 1,
	274	.regmap_type = AD5683_REGMAP,
	275	},
	276	[ID_AD5682R] = {
	277	.channels = ad5692r_channels,
	278	.int_vref_mv = 2500,
	279	.num_channels = 1,
	280	.regmap_type = AD5683_REGMAP,
	281	},
	282	[ID_AD5683] = {
	283	.channels = ad5693_channels,
	284	.num_channels = 1,
	285	.regmap_type = AD5683_REGMAP,
	286	},
	287	[ID_AD5683R] = {
	288	.channels = ad5693_channels,
	289	.int_vref_mv = 2500,
	290	.num_channels = 1,
	291	.regmap_type = AD5683_REGMAP,
	292	},
fe4586a8	293	[ID_AD5684] = {
f4a27306 SP	294	.channels = ad5684_channels,
f4a27306 SP	295	.num_channels = 4,
be1b24d2	296	.regmap_type = AD5686_REGMAP,
98baf78e SP	297	},
	298	[ID_AD5684R] = {
	299	.channels = ad5684_channels,
fe4586a8	300	.int_vref_mv = 2500,
98baf78e	301	.num_channels = 4,
be1b24d2	302	.regmap_type = AD5686_REGMAP,
fe4586a8	303	},
fe642e2d	304	[ID_AD5685R] = {
f4a27306	305	.channels = ad5685r_channels,
fe4586a8	306	.int_vref_mv = 2500,
f4a27306	307	.num_channels = 4,
be1b24d2	308	.regmap_type = AD5686_REGMAP,
fe4586a8 LPC	309	},
fe4586a8 LPC	310	[ID_AD5686] = {
f4a27306 SP	311	.channels = ad5686_channels,
f4a27306 SP	312	.num_channels = 4,
be1b24d2	313	.regmap_type = AD5686_REGMAP,
98baf78e SP	314	},
	315	[ID_AD5686R] = {
	316	.channels = ad5686_channels,
fe4586a8	317	.int_vref_mv = 2500,
98baf78e	318	.num_channels = 4,
be1b24d2 SP	319	.regmap_type = AD5686_REGMAP,
	320	},
	321	[ID_AD5691R] = {
	322	.channels = ad5691r_channels,
	323	.int_vref_mv = 2500,
	324	.num_channels = 1,
	325	.regmap_type = AD5693_REGMAP,
	326	},
	327	[ID_AD5692R] = {
	328	.channels = ad5692r_channels,
	329	.int_vref_mv = 2500,
	330	.num_channels = 1,
	331	.regmap_type = AD5693_REGMAP,
	332	},
	333	[ID_AD5693] = {
	334	.channels = ad5693_channels,
	335	.num_channels = 1,
	336	.regmap_type = AD5693_REGMAP,
	337	},
	338	[ID_AD5693R] = {
	339	.channels = ad5693_channels,
	340	.int_vref_mv = 2500,
	341	.num_channels = 1,
	342	.regmap_type = AD5693_REGMAP,
fe4586a8	343	},
4177381b SP	344	[ID_AD5694] = {
	345	.channels = ad5684_channels,
	346	.num_channels = 4,
be1b24d2	347	.regmap_type = AD5686_REGMAP,
4177381b SP	348	},
	349	[ID_AD5694R] = {
	350	.channels = ad5684_channels,
	351	.int_vref_mv = 2500,
	352	.num_channels = 4,
be1b24d2	353	.regmap_type = AD5686_REGMAP,
4177381b SP	354	},
	355	[ID_AD5696] = {
	356	.channels = ad5686_channels,
	357	.num_channels = 4,
be1b24d2	358	.regmap_type = AD5686_REGMAP,
4177381b SP	359	},
	360	[ID_AD5696R] = {
	361	.channels = ad5686_channels,
	362	.int_vref_mv = 2500,
	363	.num_channels = 4,
be1b24d2	364	.regmap_type = AD5686_REGMAP,
4177381b	365	},
fe4586a8 LPC	366	};
fe4586a8 LPC	367
0357e488 SP	368	int ad5686_probe(struct device *dev,
	369	enum ad5686_supported_device_ids chip_type,
	370	const char *name, ad5686_write_func write,
	371	ad5686_read_func read)
c2f37c8d MH	372	{
	373	struct ad5686_state *st;
	374	struct iio_dev *indio_dev;
be1b24d2 SP	375	unsigned int val, ref_bit_msk;
	376	u8 cmd;
	377	int ret, i, voltage_uv = 0;
c2f37c8d	378
0357e488	379	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
c2f37c8d MH	380	if (indio_dev == NULL)
	381	return -ENOMEM;
	382
	383	st = iio_priv(indio_dev);
0357e488 SP	384	dev_set_drvdata(dev, indio_dev);
	385
	386	st->dev = dev;
	387	st->write = write;
	388	st->read = read;
c2f37c8d	389
0357e488	390	st->reg = devm_regulator_get_optional(dev, "vcc");
c2f37c8d MH	391	if (!IS_ERR(st->reg)) {
	392	ret = regulator_enable(st->reg);
	393	if (ret)
edf3fd41	394	return ret;
c2f37c8d	395
359570ad AL	396	ret = regulator_get_voltage(st->reg);
	397	if (ret < 0)
	398	goto error_disable_reg;
	399
	400	voltage_uv = ret;
c2f37c8d MH	401	}
c2f37c8d MH	402
0357e488	403	st->chip_info = &ad5686_chip_info_tbl[chip_type];
c2f37c8d MH	404
	405	if (voltage_uv)
	406	st->vref_mv = voltage_uv / 1000;
	407	else
	408	st->vref_mv = st->chip_info->int_vref_mv;
	409
fe4586a8	410	/* Set all the power down mode for all channels to 1K pulldown */
be1b24d2 SP	411	for (i = 0; i < st->chip_info->num_channels; i++)
be1b24d2 SP	412	st->pwr_down_mode \|= (0x01 << (i * 2));
fe4586a8	413
0357e488 SP	414	indio_dev->dev.parent = dev;
0357e488 SP	415	indio_dev->name = name;
c2f37c8d MH	416	indio_dev->info = &ad5686_info;
c2f37c8d MH	417	indio_dev->modes = INDIO_DIRECT_MODE;
f4a27306 SP	418	indio_dev->channels = st->chip_info->channels;
f4a27306 SP	419	indio_dev->num_channels = st->chip_info->num_channels;
c2f37c8d	420
be1b24d2	421	switch (st->chip_info->regmap_type) {
1dbae4c6 SP	422	case AD5683_REGMAP:
	423	cmd = AD5686_CMD_CONTROL_REG;
	424	ref_bit_msk = AD5683_REF_BIT_MSK;
	425	st->use_internal_vref = !voltage_uv;
	426	break;
be1b24d2 SP	427	case AD5686_REGMAP:
	428	cmd = AD5686_CMD_INTERNAL_REFER_SETUP;
	429	ref_bit_msk = 0;
	430	break;
	431	case AD5693_REGMAP:
	432	cmd = AD5686_CMD_CONTROL_REG;
	433	ref_bit_msk = AD5693_REF_BIT_MSK;
	434	st->use_internal_vref = !voltage_uv;
	435	break;
	436	default:
	437	ret = -EINVAL;
	438	goto error_disable_reg;
	439	}
	440
	441	val = (voltage_uv \| ref_bit_msk);
	442
	443	ret = st->write(st, cmd, 0, !!val);
c2f37c8d MH	444	if (ret)
	445	goto error_disable_reg;
	446
26d25ae3 JC	447	ret = iio_device_register(indio_dev);
	448	if (ret)
	449	goto error_disable_reg;
	450
c2f37c8d MH	451	return 0;
	452
	453	error_disable_reg:
	454	if (!IS_ERR(st->reg))
	455	regulator_disable(st->reg);
c2f37c8d MH	456	return ret;
c2f37c8d MH	457	}
0357e488	458	EXPORT_SYMBOL_GPL(ad5686_probe);
c2f37c8d	459
0357e488	460	int ad5686_remove(struct device *dev)
c2f37c8d	461	{
0357e488	462	struct iio_dev *indio_dev = dev_get_drvdata(dev);
c2f37c8d	463	struct ad5686_state *st = iio_priv(indio_dev);
c2f37c8d	464
d2fffd6c	465	iio_device_unregister(indio_dev);
edf3fd41	466	if (!IS_ERR(st->reg))
26a54797	467	regulator_disable(st->reg);
c2f37c8d MH	468
	469	return 0;
	470	}
0357e488	471	EXPORT_SYMBOL_GPL(ad5686_remove);
c2f37c8d	472
9920ed25	473	MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
c2f37c8d MH	474	MODULE_DESCRIPTION("Analog Devices AD5686/85/84 DAC");
c2f37c8d MH	475	MODULE_LICENSE("GPL v2");