Commit | Line | Data |
---|---|---|
fcf265d6 | 1 | /* |
6a17a076 LPC |
2 | * AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5628, AD5629R, |
3 | * AD5648, AD5666, AD5668, AD5669R Digital to analog converters driver | |
fcf265d6 LPC |
4 | * |
5 | * Copyright 2011 Analog Devices Inc. | |
6 | * | |
7 | * Licensed under the GPL-2. | |
8 | */ | |
9 | ||
10 | #include <linux/device.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/spi/spi.h> | |
6a17a076 | 15 | #include <linux/i2c.h> |
fcf265d6 LPC |
16 | #include <linux/slab.h> |
17 | #include <linux/sysfs.h> | |
18 | #include <linux/regulator/consumer.h> | |
6a17a076 | 19 | #include <asm/unaligned.h> |
fcf265d6 | 20 | |
06458e27 JC |
21 | #include <linux/iio/iio.h> |
22 | #include <linux/iio/sysfs.h> | |
fcf265d6 | 23 | |
bb92ff3e | 24 | #define AD5064_MAX_DAC_CHANNELS 8 |
83c169d5 | 25 | #define AD5064_MAX_VREFS 4 |
fcf265d6 LPC |
26 | |
27 | #define AD5064_ADDR(x) ((x) << 20) | |
28 | #define AD5064_CMD(x) ((x) << 24) | |
29 | ||
30 | #define AD5064_ADDR_DAC(chan) (chan) | |
31 | #define AD5064_ADDR_ALL_DAC 0xF | |
32 | ||
33 | #define AD5064_CMD_WRITE_INPUT_N 0x0 | |
34 | #define AD5064_CMD_UPDATE_DAC_N 0x1 | |
35 | #define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2 | |
36 | #define AD5064_CMD_WRITE_INPUT_N_UPDATE_N 0x3 | |
37 | #define AD5064_CMD_POWERDOWN_DAC 0x4 | |
38 | #define AD5064_CMD_CLEAR 0x5 | |
39 | #define AD5064_CMD_LDAC_MASK 0x6 | |
40 | #define AD5064_CMD_RESET 0x7 | |
bb92ff3e LPC |
41 | #define AD5064_CMD_CONFIG 0x8 |
42 | ||
43 | #define AD5064_CONFIG_DAISY_CHAIN_ENABLE BIT(1) | |
44 | #define AD5064_CONFIG_INT_VREF_ENABLE BIT(0) | |
fcf265d6 LPC |
45 | |
46 | #define AD5064_LDAC_PWRDN_NONE 0x0 | |
47 | #define AD5064_LDAC_PWRDN_1K 0x1 | |
48 | #define AD5064_LDAC_PWRDN_100K 0x2 | |
49 | #define AD5064_LDAC_PWRDN_3STATE 0x3 | |
50 | ||
51 | /** | |
52 | * struct ad5064_chip_info - chip specific information | |
53 | * @shared_vref: whether the vref supply is shared between channels | |
bb92ff3e LPC |
54 | * @internal_vref: internal reference voltage. 0 if the chip has no internal |
55 | * vref. | |
fcf265d6 | 56 | * @channel: channel specification |
83c169d5 LPC |
57 | * @num_channels: number of channels |
58 | */ | |
fcf265d6 LPC |
59 | |
60 | struct ad5064_chip_info { | |
61 | bool shared_vref; | |
bb92ff3e | 62 | unsigned long internal_vref; |
83c169d5 LPC |
63 | const struct iio_chan_spec *channels; |
64 | unsigned int num_channels; | |
fcf265d6 LPC |
65 | }; |
66 | ||
6a17a076 LPC |
67 | struct ad5064_state; |
68 | ||
69 | typedef int (*ad5064_write_func)(struct ad5064_state *st, unsigned int cmd, | |
70 | unsigned int addr, unsigned int val); | |
71 | ||
fcf265d6 LPC |
72 | /** |
73 | * struct ad5064_state - driver instance specific data | |
6a17a076 | 74 | * @dev: the device for this driver instance |
fcf265d6 LPC |
75 | * @chip_info: chip model specific constants, available modes etc |
76 | * @vref_reg: vref supply regulators | |
77 | * @pwr_down: whether channel is powered down | |
78 | * @pwr_down_mode: channel's current power down mode | |
79 | * @dac_cache: current DAC raw value (chip does not support readback) | |
bb92ff3e LPC |
80 | * @use_internal_vref: set to true if the internal reference voltage should be |
81 | * used. | |
6a17a076 LPC |
82 | * @write: register write callback |
83 | * @data: i2c/spi transfer buffers | |
fcf265d6 LPC |
84 | */ |
85 | ||
86 | struct ad5064_state { | |
6a17a076 | 87 | struct device *dev; |
fcf265d6 | 88 | const struct ad5064_chip_info *chip_info; |
83c169d5 LPC |
89 | struct regulator_bulk_data vref_reg[AD5064_MAX_VREFS]; |
90 | bool pwr_down[AD5064_MAX_DAC_CHANNELS]; | |
91 | u8 pwr_down_mode[AD5064_MAX_DAC_CHANNELS]; | |
92 | unsigned int dac_cache[AD5064_MAX_DAC_CHANNELS]; | |
bb92ff3e | 93 | bool use_internal_vref; |
fcf265d6 | 94 | |
6a17a076 LPC |
95 | ad5064_write_func write; |
96 | ||
fcf265d6 LPC |
97 | /* |
98 | * DMA (thus cache coherency maintenance) requires the | |
99 | * transfer buffers to live in their own cache lines. | |
100 | */ | |
6a17a076 LPC |
101 | union { |
102 | u8 i2c[3]; | |
103 | __be32 spi; | |
104 | } data ____cacheline_aligned; | |
fcf265d6 LPC |
105 | }; |
106 | ||
107 | enum ad5064_type { | |
108 | ID_AD5024, | |
f8be4af1 | 109 | ID_AD5025, |
fcf265d6 | 110 | ID_AD5044, |
f8be4af1 | 111 | ID_AD5045, |
fcf265d6 LPC |
112 | ID_AD5064, |
113 | ID_AD5064_1, | |
f8be4af1 | 114 | ID_AD5065, |
bb92ff3e LPC |
115 | ID_AD5628_1, |
116 | ID_AD5628_2, | |
117 | ID_AD5648_1, | |
118 | ID_AD5648_2, | |
64f4eaa5 LPC |
119 | ID_AD5666_1, |
120 | ID_AD5666_2, | |
bb92ff3e LPC |
121 | ID_AD5668_1, |
122 | ID_AD5668_2, | |
fcf265d6 LPC |
123 | }; |
124 | ||
6a17a076 | 125 | static int ad5064_write(struct ad5064_state *st, unsigned int cmd, |
fcf265d6 LPC |
126 | unsigned int addr, unsigned int val, unsigned int shift) |
127 | { | |
128 | val <<= shift; | |
129 | ||
6a17a076 | 130 | return st->write(st, cmd, addr, val); |
fcf265d6 LPC |
131 | } |
132 | ||
133 | static int ad5064_sync_powerdown_mode(struct ad5064_state *st, | |
134 | unsigned int channel) | |
135 | { | |
136 | unsigned int val; | |
137 | int ret; | |
138 | ||
139 | val = (0x1 << channel); | |
140 | ||
141 | if (st->pwr_down[channel]) | |
142 | val |= st->pwr_down_mode[channel] << 8; | |
143 | ||
6a17a076 | 144 | ret = ad5064_write(st, AD5064_CMD_POWERDOWN_DAC, 0, val, 0); |
fcf265d6 LPC |
145 | |
146 | return ret; | |
147 | } | |
148 | ||
26628f6b LPC |
149 | static const char * const ad5064_powerdown_modes[] = { |
150 | "1kohm_to_gnd", | |
151 | "100kohm_to_gnd", | |
152 | "three_state", | |
fcf265d6 LPC |
153 | }; |
154 | ||
26628f6b LPC |
155 | static int ad5064_get_powerdown_mode(struct iio_dev *indio_dev, |
156 | const struct iio_chan_spec *chan) | |
fcf265d6 | 157 | { |
fcf265d6 LPC |
158 | struct ad5064_state *st = iio_priv(indio_dev); |
159 | ||
26628f6b | 160 | return st->pwr_down_mode[chan->channel] - 1; |
fcf265d6 LPC |
161 | } |
162 | ||
26628f6b LPC |
163 | static int ad5064_set_powerdown_mode(struct iio_dev *indio_dev, |
164 | const struct iio_chan_spec *chan, unsigned int mode) | |
fcf265d6 | 165 | { |
fcf265d6 | 166 | struct ad5064_state *st = iio_priv(indio_dev); |
fcf265d6 LPC |
167 | int ret; |
168 | ||
fcf265d6 | 169 | mutex_lock(&indio_dev->mlock); |
26628f6b | 170 | st->pwr_down_mode[chan->channel] = mode + 1; |
fcf265d6 | 171 | |
1d0d8794 | 172 | ret = ad5064_sync_powerdown_mode(st, chan->channel); |
fcf265d6 LPC |
173 | mutex_unlock(&indio_dev->mlock); |
174 | ||
26628f6b | 175 | return ret; |
fcf265d6 LPC |
176 | } |
177 | ||
26628f6b LPC |
178 | static const struct iio_enum ad5064_powerdown_mode_enum = { |
179 | .items = ad5064_powerdown_modes, | |
180 | .num_items = ARRAY_SIZE(ad5064_powerdown_modes), | |
181 | .get = ad5064_get_powerdown_mode, | |
182 | .set = ad5064_set_powerdown_mode, | |
183 | }; | |
184 | ||
1d0d8794 | 185 | static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev, |
fc6d1139 | 186 | uintptr_t private, const struct iio_chan_spec *chan, char *buf) |
fcf265d6 | 187 | { |
fcf265d6 | 188 | struct ad5064_state *st = iio_priv(indio_dev); |
fcf265d6 | 189 | |
1d0d8794 | 190 | return sprintf(buf, "%d\n", st->pwr_down[chan->channel]); |
fcf265d6 LPC |
191 | } |
192 | ||
1d0d8794 | 193 | static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev, |
fc6d1139 MH |
194 | uintptr_t private, const struct iio_chan_spec *chan, const char *buf, |
195 | size_t len) | |
fcf265d6 | 196 | { |
fcf265d6 | 197 | struct ad5064_state *st = iio_priv(indio_dev); |
fcf265d6 LPC |
198 | bool pwr_down; |
199 | int ret; | |
200 | ||
201 | ret = strtobool(buf, &pwr_down); | |
202 | if (ret) | |
203 | return ret; | |
204 | ||
205 | mutex_lock(&indio_dev->mlock); | |
1d0d8794 | 206 | st->pwr_down[chan->channel] = pwr_down; |
fcf265d6 | 207 | |
1d0d8794 | 208 | ret = ad5064_sync_powerdown_mode(st, chan->channel); |
fcf265d6 LPC |
209 | mutex_unlock(&indio_dev->mlock); |
210 | return ret ? ret : len; | |
211 | } | |
212 | ||
bb92ff3e LPC |
213 | static int ad5064_get_vref(struct ad5064_state *st, |
214 | struct iio_chan_spec const *chan) | |
215 | { | |
216 | unsigned int i; | |
217 | ||
218 | if (st->use_internal_vref) | |
219 | return st->chip_info->internal_vref; | |
220 | ||
221 | i = st->chip_info->shared_vref ? 0 : chan->channel; | |
222 | return regulator_get_voltage(st->vref_reg[i].consumer); | |
223 | } | |
224 | ||
fcf265d6 LPC |
225 | static int ad5064_read_raw(struct iio_dev *indio_dev, |
226 | struct iio_chan_spec const *chan, | |
227 | int *val, | |
228 | int *val2, | |
229 | long m) | |
230 | { | |
231 | struct ad5064_state *st = iio_priv(indio_dev); | |
23a3b8cc | 232 | int scale_uv; |
fcf265d6 LPC |
233 | |
234 | switch (m) { | |
09f4eb40 | 235 | case IIO_CHAN_INFO_RAW: |
fcf265d6 LPC |
236 | *val = st->dac_cache[chan->channel]; |
237 | return IIO_VAL_INT; | |
c8a9f805 | 238 | case IIO_CHAN_INFO_SCALE: |
bb92ff3e | 239 | scale_uv = ad5064_get_vref(st, chan); |
fcf265d6 LPC |
240 | if (scale_uv < 0) |
241 | return scale_uv; | |
242 | ||
243 | scale_uv = (scale_uv * 100) >> chan->scan_type.realbits; | |
244 | *val = scale_uv / 100000; | |
245 | *val2 = (scale_uv % 100000) * 10; | |
246 | return IIO_VAL_INT_PLUS_MICRO; | |
247 | default: | |
248 | break; | |
249 | } | |
250 | return -EINVAL; | |
251 | } | |
252 | ||
253 | static int ad5064_write_raw(struct iio_dev *indio_dev, | |
254 | struct iio_chan_spec const *chan, int val, int val2, long mask) | |
255 | { | |
256 | struct ad5064_state *st = iio_priv(indio_dev); | |
257 | int ret; | |
258 | ||
259 | switch (mask) { | |
09f4eb40 | 260 | case IIO_CHAN_INFO_RAW: |
fcf265d6 LPC |
261 | if (val > (1 << chan->scan_type.realbits) || val < 0) |
262 | return -EINVAL; | |
263 | ||
264 | mutex_lock(&indio_dev->mlock); | |
6a17a076 | 265 | ret = ad5064_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N, |
fcf265d6 LPC |
266 | chan->address, val, chan->scan_type.shift); |
267 | if (ret == 0) | |
268 | st->dac_cache[chan->channel] = val; | |
269 | mutex_unlock(&indio_dev->mlock); | |
270 | break; | |
271 | default: | |
272 | ret = -EINVAL; | |
273 | } | |
274 | ||
275 | return ret; | |
276 | } | |
277 | ||
278 | static const struct iio_info ad5064_info = { | |
279 | .read_raw = ad5064_read_raw, | |
280 | .write_raw = ad5064_write_raw, | |
fcf265d6 LPC |
281 | .driver_module = THIS_MODULE, |
282 | }; | |
283 | ||
26628f6b | 284 | static const struct iio_chan_spec_ext_info ad5064_ext_info[] = { |
1d0d8794 LPC |
285 | { |
286 | .name = "powerdown", | |
287 | .read = ad5064_read_dac_powerdown, | |
288 | .write = ad5064_write_dac_powerdown, | |
289 | }, | |
26628f6b LPC |
290 | IIO_ENUM("powerdown_mode", false, &ad5064_powerdown_mode_enum), |
291 | IIO_ENUM_AVAILABLE("powerdown_mode", &ad5064_powerdown_mode_enum), | |
1d0d8794 LPC |
292 | { }, |
293 | }; | |
294 | ||
295 | #define AD5064_CHANNEL(chan, bits) { \ | |
296 | .type = IIO_VOLTAGE, \ | |
297 | .indexed = 1, \ | |
298 | .output = 1, \ | |
299 | .channel = (chan), \ | |
09f4eb40 JC |
300 | .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \ |
301 | IIO_CHAN_INFO_SCALE_SEPARATE_BIT, \ | |
1d0d8794 LPC |
302 | .address = AD5064_ADDR_DAC(chan), \ |
303 | .scan_type = IIO_ST('u', (bits), 16, 20 - (bits)), \ | |
304 | .ext_info = ad5064_ext_info, \ | |
305 | } | |
306 | ||
83c169d5 LPC |
307 | #define DECLARE_AD5064_CHANNELS(name, bits) \ |
308 | const struct iio_chan_spec name[] = { \ | |
309 | AD5064_CHANNEL(0, bits), \ | |
310 | AD5064_CHANNEL(1, bits), \ | |
311 | AD5064_CHANNEL(2, bits), \ | |
312 | AD5064_CHANNEL(3, bits), \ | |
bb92ff3e LPC |
313 | AD5064_CHANNEL(4, bits), \ |
314 | AD5064_CHANNEL(5, bits), \ | |
315 | AD5064_CHANNEL(6, bits), \ | |
316 | AD5064_CHANNEL(7, bits), \ | |
83c169d5 LPC |
317 | } |
318 | ||
319 | static DECLARE_AD5064_CHANNELS(ad5024_channels, 12); | |
320 | static DECLARE_AD5064_CHANNELS(ad5044_channels, 14); | |
321 | static DECLARE_AD5064_CHANNELS(ad5064_channels, 16); | |
322 | ||
1d0d8794 LPC |
323 | static const struct ad5064_chip_info ad5064_chip_info_tbl[] = { |
324 | [ID_AD5024] = { | |
325 | .shared_vref = false, | |
83c169d5 LPC |
326 | .channels = ad5024_channels, |
327 | .num_channels = 4, | |
1d0d8794 | 328 | }, |
f8be4af1 LPC |
329 | [ID_AD5025] = { |
330 | .shared_vref = false, | |
331 | .channels = ad5024_channels, | |
332 | .num_channels = 2, | |
333 | }, | |
1d0d8794 LPC |
334 | [ID_AD5044] = { |
335 | .shared_vref = false, | |
83c169d5 LPC |
336 | .channels = ad5044_channels, |
337 | .num_channels = 4, | |
1d0d8794 | 338 | }, |
f8be4af1 LPC |
339 | [ID_AD5045] = { |
340 | .shared_vref = false, | |
341 | .channels = ad5044_channels, | |
342 | .num_channels = 2, | |
343 | }, | |
1d0d8794 LPC |
344 | [ID_AD5064] = { |
345 | .shared_vref = false, | |
83c169d5 LPC |
346 | .channels = ad5064_channels, |
347 | .num_channels = 4, | |
1d0d8794 LPC |
348 | }, |
349 | [ID_AD5064_1] = { | |
350 | .shared_vref = true, | |
83c169d5 LPC |
351 | .channels = ad5064_channels, |
352 | .num_channels = 4, | |
1d0d8794 | 353 | }, |
f8be4af1 LPC |
354 | [ID_AD5065] = { |
355 | .shared_vref = false, | |
356 | .channels = ad5064_channels, | |
357 | .num_channels = 2, | |
358 | }, | |
bb92ff3e LPC |
359 | [ID_AD5628_1] = { |
360 | .shared_vref = true, | |
361 | .internal_vref = 2500000, | |
362 | .channels = ad5024_channels, | |
363 | .num_channels = 8, | |
364 | }, | |
365 | [ID_AD5628_2] = { | |
366 | .shared_vref = true, | |
367 | .internal_vref = 5000000, | |
368 | .channels = ad5024_channels, | |
369 | .num_channels = 8, | |
370 | }, | |
371 | [ID_AD5648_1] = { | |
372 | .shared_vref = true, | |
373 | .internal_vref = 2500000, | |
374 | .channels = ad5044_channels, | |
375 | .num_channels = 8, | |
376 | }, | |
377 | [ID_AD5648_2] = { | |
378 | .shared_vref = true, | |
379 | .internal_vref = 5000000, | |
380 | .channels = ad5044_channels, | |
381 | .num_channels = 8, | |
382 | }, | |
64f4eaa5 LPC |
383 | [ID_AD5666_1] = { |
384 | .shared_vref = true, | |
385 | .internal_vref = 2500000, | |
386 | .channels = ad5064_channels, | |
387 | .num_channels = 4, | |
388 | }, | |
389 | [ID_AD5666_2] = { | |
390 | .shared_vref = true, | |
391 | .internal_vref = 5000000, | |
392 | .channels = ad5064_channels, | |
393 | .num_channels = 4, | |
394 | }, | |
bb92ff3e LPC |
395 | [ID_AD5668_1] = { |
396 | .shared_vref = true, | |
397 | .internal_vref = 2500000, | |
398 | .channels = ad5064_channels, | |
399 | .num_channels = 8, | |
400 | }, | |
401 | [ID_AD5668_2] = { | |
402 | .shared_vref = true, | |
403 | .internal_vref = 5000000, | |
404 | .channels = ad5064_channels, | |
405 | .num_channels = 8, | |
406 | }, | |
1d0d8794 LPC |
407 | }; |
408 | ||
fcf265d6 LPC |
409 | static inline unsigned int ad5064_num_vref(struct ad5064_state *st) |
410 | { | |
83c169d5 | 411 | return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels; |
fcf265d6 LPC |
412 | } |
413 | ||
414 | static const char * const ad5064_vref_names[] = { | |
415 | "vrefA", | |
416 | "vrefB", | |
417 | "vrefC", | |
418 | "vrefD", | |
419 | }; | |
420 | ||
421 | static const char * const ad5064_vref_name(struct ad5064_state *st, | |
422 | unsigned int vref) | |
423 | { | |
424 | return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref]; | |
425 | } | |
426 | ||
fc52692c GKH |
427 | static int ad5064_probe(struct device *dev, enum ad5064_type type, |
428 | const char *name, ad5064_write_func write) | |
fcf265d6 | 429 | { |
fcf265d6 LPC |
430 | struct iio_dev *indio_dev; |
431 | struct ad5064_state *st; | |
432 | unsigned int i; | |
433 | int ret; | |
434 | ||
7cbb7537 | 435 | indio_dev = iio_device_alloc(sizeof(*st)); |
fcf265d6 LPC |
436 | if (indio_dev == NULL) |
437 | return -ENOMEM; | |
438 | ||
439 | st = iio_priv(indio_dev); | |
6a17a076 | 440 | dev_set_drvdata(dev, indio_dev); |
fcf265d6 LPC |
441 | |
442 | st->chip_info = &ad5064_chip_info_tbl[type]; | |
6a17a076 LPC |
443 | st->dev = dev; |
444 | st->write = write; | |
fcf265d6 LPC |
445 | |
446 | for (i = 0; i < ad5064_num_vref(st); ++i) | |
447 | st->vref_reg[i].supply = ad5064_vref_name(st, i); | |
448 | ||
6a17a076 | 449 | ret = regulator_bulk_get(dev, ad5064_num_vref(st), |
fcf265d6 | 450 | st->vref_reg); |
bb92ff3e LPC |
451 | if (ret) { |
452 | if (!st->chip_info->internal_vref) | |
453 | goto error_free; | |
454 | st->use_internal_vref = true; | |
6a17a076 | 455 | ret = ad5064_write(st, AD5064_CMD_CONFIG, 0, |
bb92ff3e LPC |
456 | AD5064_CONFIG_INT_VREF_ENABLE, 0); |
457 | if (ret) { | |
6a17a076 | 458 | dev_err(dev, "Failed to enable internal vref: %d\n", |
bb92ff3e LPC |
459 | ret); |
460 | goto error_free; | |
461 | } | |
462 | } else { | |
463 | ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg); | |
464 | if (ret) | |
465 | goto error_free_reg; | |
466 | } | |
fcf265d6 | 467 | |
83c169d5 | 468 | for (i = 0; i < st->chip_info->num_channels; ++i) { |
fcf265d6 LPC |
469 | st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K; |
470 | st->dac_cache[i] = 0x8000; | |
471 | } | |
472 | ||
6a17a076 LPC |
473 | indio_dev->dev.parent = dev; |
474 | indio_dev->name = name; | |
fcf265d6 LPC |
475 | indio_dev->info = &ad5064_info; |
476 | indio_dev->modes = INDIO_DIRECT_MODE; | |
83c169d5 LPC |
477 | indio_dev->channels = st->chip_info->channels; |
478 | indio_dev->num_channels = st->chip_info->num_channels; | |
fcf265d6 LPC |
479 | |
480 | ret = iio_device_register(indio_dev); | |
481 | if (ret) | |
482 | goto error_disable_reg; | |
483 | ||
484 | return 0; | |
485 | ||
486 | error_disable_reg: | |
bb92ff3e LPC |
487 | if (!st->use_internal_vref) |
488 | regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg); | |
fcf265d6 | 489 | error_free_reg: |
bb92ff3e LPC |
490 | if (!st->use_internal_vref) |
491 | regulator_bulk_free(ad5064_num_vref(st), st->vref_reg); | |
fcf265d6 | 492 | error_free: |
7cbb7537 | 493 | iio_device_free(indio_dev); |
fcf265d6 LPC |
494 | |
495 | return ret; | |
496 | } | |
497 | ||
fc52692c | 498 | static int ad5064_remove(struct device *dev) |
fcf265d6 | 499 | { |
6a17a076 | 500 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
fcf265d6 LPC |
501 | struct ad5064_state *st = iio_priv(indio_dev); |
502 | ||
503 | iio_device_unregister(indio_dev); | |
504 | ||
bb92ff3e LPC |
505 | if (!st->use_internal_vref) { |
506 | regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg); | |
507 | regulator_bulk_free(ad5064_num_vref(st), st->vref_reg); | |
508 | } | |
fcf265d6 | 509 | |
7cbb7537 | 510 | iio_device_free(indio_dev); |
fcf265d6 LPC |
511 | |
512 | return 0; | |
513 | } | |
514 | ||
6a17a076 LPC |
515 | #if IS_ENABLED(CONFIG_SPI_MASTER) |
516 | ||
9660ac70 LPC |
517 | static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd, |
518 | unsigned int addr, unsigned int val) | |
519 | { | |
520 | struct spi_device *spi = to_spi_device(st->dev); | |
521 | ||
522 | st->data.spi = cpu_to_be32(AD5064_CMD(cmd) | AD5064_ADDR(addr) | val); | |
523 | return spi_write(spi, &st->data.spi, sizeof(st->data.spi)); | |
524 | } | |
525 | ||
fc52692c | 526 | static int ad5064_spi_probe(struct spi_device *spi) |
6a17a076 LPC |
527 | { |
528 | const struct spi_device_id *id = spi_get_device_id(spi); | |
529 | ||
530 | return ad5064_probe(&spi->dev, id->driver_data, id->name, | |
531 | ad5064_spi_write); | |
532 | } | |
533 | ||
fc52692c | 534 | static int ad5064_spi_remove(struct spi_device *spi) |
6a17a076 LPC |
535 | { |
536 | return ad5064_remove(&spi->dev); | |
537 | } | |
538 | ||
539 | static const struct spi_device_id ad5064_spi_ids[] = { | |
fcf265d6 | 540 | {"ad5024", ID_AD5024}, |
f8be4af1 | 541 | {"ad5025", ID_AD5025}, |
fcf265d6 | 542 | {"ad5044", ID_AD5044}, |
f8be4af1 | 543 | {"ad5045", ID_AD5045}, |
fcf265d6 LPC |
544 | {"ad5064", ID_AD5064}, |
545 | {"ad5064-1", ID_AD5064_1}, | |
f8be4af1 | 546 | {"ad5065", ID_AD5065}, |
bb92ff3e LPC |
547 | {"ad5628-1", ID_AD5628_1}, |
548 | {"ad5628-2", ID_AD5628_2}, | |
549 | {"ad5648-1", ID_AD5648_1}, | |
550 | {"ad5648-2", ID_AD5648_2}, | |
64f4eaa5 LPC |
551 | {"ad5666-1", ID_AD5666_1}, |
552 | {"ad5666-2", ID_AD5666_2}, | |
bb92ff3e LPC |
553 | {"ad5668-1", ID_AD5668_1}, |
554 | {"ad5668-2", ID_AD5668_2}, | |
555 | {"ad5668-3", ID_AD5668_2}, /* similar enough to ad5668-2 */ | |
fcf265d6 LPC |
556 | {} |
557 | }; | |
6a17a076 | 558 | MODULE_DEVICE_TABLE(spi, ad5064_spi_ids); |
fcf265d6 | 559 | |
6a17a076 | 560 | static struct spi_driver ad5064_spi_driver = { |
fcf265d6 LPC |
561 | .driver = { |
562 | .name = "ad5064", | |
563 | .owner = THIS_MODULE, | |
564 | }, | |
6a17a076 | 565 | .probe = ad5064_spi_probe, |
fc52692c | 566 | .remove = ad5064_spi_remove, |
6a17a076 | 567 | .id_table = ad5064_spi_ids, |
fcf265d6 | 568 | }; |
6a17a076 LPC |
569 | |
570 | static int __init ad5064_spi_register_driver(void) | |
571 | { | |
572 | return spi_register_driver(&ad5064_spi_driver); | |
573 | } | |
574 | ||
21fa54e4 | 575 | static void ad5064_spi_unregister_driver(void) |
6a17a076 LPC |
576 | { |
577 | spi_unregister_driver(&ad5064_spi_driver); | |
578 | } | |
579 | ||
580 | #else | |
581 | ||
582 | static inline int ad5064_spi_register_driver(void) { return 0; } | |
583 | static inline void ad5064_spi_unregister_driver(void) { } | |
584 | ||
585 | #endif | |
586 | ||
587 | #if IS_ENABLED(CONFIG_I2C) | |
588 | ||
9660ac70 LPC |
589 | static int ad5064_i2c_write(struct ad5064_state *st, unsigned int cmd, |
590 | unsigned int addr, unsigned int val) | |
591 | { | |
592 | struct i2c_client *i2c = to_i2c_client(st->dev); | |
593 | ||
594 | st->data.i2c[0] = (cmd << 4) | addr; | |
595 | put_unaligned_be16(val, &st->data.i2c[1]); | |
596 | return i2c_master_send(i2c, st->data.i2c, 3); | |
597 | } | |
598 | ||
fc52692c | 599 | static int ad5064_i2c_probe(struct i2c_client *i2c, |
6a17a076 LPC |
600 | const struct i2c_device_id *id) |
601 | { | |
602 | return ad5064_probe(&i2c->dev, id->driver_data, id->name, | |
603 | ad5064_i2c_write); | |
604 | } | |
605 | ||
fc52692c | 606 | static int ad5064_i2c_remove(struct i2c_client *i2c) |
6a17a076 LPC |
607 | { |
608 | return ad5064_remove(&i2c->dev); | |
609 | } | |
610 | ||
611 | static const struct i2c_device_id ad5064_i2c_ids[] = { | |
612 | {"ad5629-1", ID_AD5628_1}, | |
613 | {"ad5629-2", ID_AD5628_2}, | |
614 | {"ad5629-3", ID_AD5628_2}, /* similar enough to ad5629-2 */ | |
615 | {"ad5669-1", ID_AD5668_1}, | |
616 | {"ad5669-2", ID_AD5668_2}, | |
617 | {"ad5669-3", ID_AD5668_2}, /* similar enough to ad5669-2 */ | |
618 | {} | |
619 | }; | |
620 | MODULE_DEVICE_TABLE(i2c, ad5064_i2c_ids); | |
621 | ||
622 | static struct i2c_driver ad5064_i2c_driver = { | |
623 | .driver = { | |
624 | .name = "ad5064", | |
625 | .owner = THIS_MODULE, | |
626 | }, | |
627 | .probe = ad5064_i2c_probe, | |
fc52692c | 628 | .remove = ad5064_i2c_remove, |
6a17a076 LPC |
629 | .id_table = ad5064_i2c_ids, |
630 | }; | |
631 | ||
632 | static int __init ad5064_i2c_register_driver(void) | |
633 | { | |
634 | return i2c_add_driver(&ad5064_i2c_driver); | |
635 | } | |
636 | ||
637 | static void __exit ad5064_i2c_unregister_driver(void) | |
638 | { | |
639 | i2c_del_driver(&ad5064_i2c_driver); | |
640 | } | |
641 | ||
642 | #else | |
643 | ||
644 | static inline int ad5064_i2c_register_driver(void) { return 0; } | |
645 | static inline void ad5064_i2c_unregister_driver(void) { } | |
646 | ||
647 | #endif | |
648 | ||
649 | static int __init ad5064_init(void) | |
650 | { | |
651 | int ret; | |
652 | ||
653 | ret = ad5064_spi_register_driver(); | |
654 | if (ret) | |
655 | return ret; | |
656 | ||
657 | ret = ad5064_i2c_register_driver(); | |
658 | if (ret) { | |
659 | ad5064_spi_unregister_driver(); | |
660 | return ret; | |
661 | } | |
662 | ||
663 | return 0; | |
664 | } | |
665 | module_init(ad5064_init); | |
666 | ||
667 | static void __exit ad5064_exit(void) | |
668 | { | |
669 | ad5064_i2c_unregister_driver(); | |
670 | ad5064_spi_unregister_driver(); | |
671 | } | |
672 | module_exit(ad5064_exit); | |
fcf265d6 LPC |
673 | |
674 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); | |
6a17a076 | 675 | MODULE_DESCRIPTION("Analog Devices AD5024 and similar multi-channel DACs"); |
fcf265d6 | 676 | MODULE_LICENSE("GPL v2"); |