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iio: adc: vf610_adc: add helper function to read samples
[linux-2.6-block.git] / drivers / iio / adc / vf610_adc.c
CommitLineData
74ba9207 1// SPDX-License-Identifier: GPL-2.0-or-later
a7754276
FD		 2/*
3 * Freescale Vybrid vf610 ADC driver
4 *
5 * Copyright 2013 Freescale Semiconductor, Inc.
a7754276
FD		 6 */
7
3cc6a67b 8#include <linux/mod_devicetable.h>
a7754276 9#include <linux/module.h>
3cc6a67b 10#include <linux/property.h>
a7754276
FD		 11#include <linux/platform_device.h>
12#include <linux/interrupt.h>
13#include <linux/delay.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/clk.h>
18#include <linux/completion.h>
a7754276 19#include <linux/regulator/consumer.h>
a7754276
FD		 20#include <linux/err.h>
21
22#include <linux/iio/iio.h>
0010d6b4 23#include <linux/iio/buffer.h>
a7754276 24#include <linux/iio/sysfs.h>
0010d6b4
SM		 25#include <linux/iio/trigger.h>
26#include <linux/iio/trigger_consumer.h>
27#include <linux/iio/triggered_buffer.h>
a7754276
FD		 28
29/* This will be the driver name the kernel reports */
30#define DRIVER_NAME "vf610-adc"
31
32/* Vybrid/IMX ADC registers */
33#define VF610_REG_ADC_HC0 0x00
34#define VF610_REG_ADC_HC1 0x04
35#define VF610_REG_ADC_HS 0x08
36#define VF610_REG_ADC_R0 0x0c
37#define VF610_REG_ADC_R1 0x10
38#define VF610_REG_ADC_CFG 0x14
39#define VF610_REG_ADC_GC 0x18
40#define VF610_REG_ADC_GS 0x1c
41#define VF610_REG_ADC_CV 0x20
42#define VF610_REG_ADC_OFS 0x24
43#define VF610_REG_ADC_CAL 0x28
44#define VF610_REG_ADC_PCTL 0x30
45
46/* Configuration register field define */
47#define VF610_ADC_MODE_BIT8 0x00
48#define VF610_ADC_MODE_BIT10 0x04
49#define VF610_ADC_MODE_BIT12 0x08
50#define VF610_ADC_MODE_MASK 0x0c
51#define VF610_ADC_BUSCLK2_SEL 0x01
52#define VF610_ADC_ALTCLK_SEL 0x02
53#define VF610_ADC_ADACK_SEL 0x03
54#define VF610_ADC_ADCCLK_MASK 0x03
55#define VF610_ADC_CLK_DIV2 0x20
56#define VF610_ADC_CLK_DIV4 0x40
57#define VF610_ADC_CLK_DIV8 0x60
58#define VF610_ADC_CLK_MASK 0x60
59#define VF610_ADC_ADLSMP_LONG 0x10
5e9972cd
SM		 60#define VF610_ADC_ADSTS_SHORT 0x100
61#define VF610_ADC_ADSTS_NORMAL 0x200
62#define VF610_ADC_ADSTS_LONG 0x300
a7754276
FD		 63#define VF610_ADC_ADSTS_MASK 0x300
64#define VF610_ADC_ADLPC_EN 0x80
65#define VF610_ADC_ADHSC_EN 0x400
d466d3c1 66#define VF610_ADC_REFSEL_VALT 0x800
a7754276
FD		 67#define VF610_ADC_REFSEL_VBG 0x1000
68#define VF610_ADC_ADTRG_HARD 0x2000
69#define VF610_ADC_AVGS_8 0x4000
70#define VF610_ADC_AVGS_16 0x8000
71#define VF610_ADC_AVGS_32 0xC000
72#define VF610_ADC_AVGS_MASK 0xC000
73#define VF610_ADC_OVWREN 0x10000
74
75/* General control register field define */
76#define VF610_ADC_ADACKEN 0x1
77#define VF610_ADC_DMAEN 0x2
78#define VF610_ADC_ACREN 0x4
79#define VF610_ADC_ACFGT 0x8
80#define VF610_ADC_ACFE 0x10
81#define VF610_ADC_AVGEN 0x20
82#define VF610_ADC_ADCON 0x40
83#define VF610_ADC_CAL 0x80
84
85/* Other field define */
774623ca 86#define VF610_ADC_ADCHC(x) ((x) & 0x1F)
a7754276
FD		 87#define VF610_ADC_AIEN (0x1 << 7)
88#define VF610_ADC_CONV_DISABLE 0x1F
89#define VF610_ADC_HS_COCO0 0x1
90#define VF610_ADC_CALF 0x2
91#define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
92
5e9972cd
SM		 93#define DEFAULT_SAMPLE_TIME 1000
94
6219f432
BD		 95/* V at 25°C of 696 mV */
96#define VF610_VTEMP25_3V0 950
97/* V at 25°C of 699 mV */
98#define VF610_VTEMP25_3V3 867
99/* Typical sensor slope coefficient at all temperatures */
100#define VF610_TEMP_SLOPE_COEFF 1840
101
a7754276
FD		 102enum clk_sel {
103 VF610_ADCIOC_BUSCLK_SET,
104 VF610_ADCIOC_ALTCLK_SET,
105 VF610_ADCIOC_ADACK_SET,
106};
107
108enum vol_ref {
109 VF610_ADCIOC_VR_VREF_SET,
110 VF610_ADCIOC_VR_VALT_SET,
111 VF610_ADCIOC_VR_VBG_SET,
112};
113
114enum average_sel {
115 VF610_ADC_SAMPLE_1,
116 VF610_ADC_SAMPLE_4,
117 VF610_ADC_SAMPLE_8,
118 VF610_ADC_SAMPLE_16,
119 VF610_ADC_SAMPLE_32,
120};
121
bf04c1a3
SA		 122enum conversion_mode_sel {
123 VF610_ADC_CONV_NORMAL,
124 VF610_ADC_CONV_HIGH_SPEED,
125 VF610_ADC_CONV_LOW_POWER,
126};
127
5e9972cd
SM		 128enum lst_adder_sel {
129 VF610_ADCK_CYCLES_3,
130 VF610_ADCK_CYCLES_5,
131 VF610_ADCK_CYCLES_7,
132 VF610_ADCK_CYCLES_9,
133 VF610_ADCK_CYCLES_13,
134 VF610_ADCK_CYCLES_17,
135 VF610_ADCK_CYCLES_21,
136 VF610_ADCK_CYCLES_25,
137};
138
a7754276
FD		 139struct vf610_adc_feature {
140 enum clk_sel clk_sel;
141 enum vol_ref vol_ref;
bf04c1a3 142 enum conversion_mode_sel conv_mode;
a7754276
FD		 143
144 int clk_div;
145 int sample_rate;
146 int res_mode;
5e9972cd
SM		 147 u32 lst_adder_index;
148 u32 default_sample_time;
a7754276 149
a7754276
FD		 150 bool calibration;
151 bool ovwren;
152};
153
154struct vf610_adc {
155 struct device *dev;
156 void __iomem *regs;
157 struct clk *clk;
158
159 u32 vref_uv;
160 u32 value;
161 struct regulator *vref;
bf04c1a3
SA		 162
163 u32 max_adck_rate[3];
a7754276
FD		 164 struct vf610_adc_feature adc_feature;
165
f54e9f2b
SA		 166 u32 sample_freq_avail[5];
167
a7754276 168 struct completion completion;
7765dfaa
JC		 169 /* Ensure the timestamp is naturally aligned */
170 struct {
171 u16 chan;
172 s64 timestamp __aligned(8);
173 } scan;
a7754276
FD		 174};
175
f54e9f2b 176static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
5e9972cd 177static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
f54e9f2b 178
f54e9f2b
SA		 179static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
180{
bf04c1a3 181 struct vf610_adc_feature *adc_feature = &info->adc_feature;
f54e9f2b 182 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
5e9972cd 183 u32 adck_period, lst_addr_min;
bf04c1a3
SA		 184 int divisor, i;
185
186 adck_rate = info->max_adck_rate[adc_feature->conv_mode];
187
188 if (adck_rate) {
189 /* calculate clk divider which is within specification */
190 divisor = ipg_rate / adck_rate;
191 adc_feature->clk_div = 1 << fls(divisor + 1);
192 } else {
193 /* fall-back value using a safe divisor */
194 adc_feature->clk_div = 8;
195 }
f54e9f2b 196
8546d2e5
SM		 197 adck_rate = ipg_rate / adc_feature->clk_div;
198
5e9972cd
SM		 199 /*
200 * Determine the long sample time adder value to be used based
201 * on the default minimum sample time provided.
202 */
203 adck_period = NSEC_PER_SEC / adck_rate;
204 lst_addr_min = adc_feature->default_sample_time / adck_period;
205 for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
206 if (vf610_lst_adder[i] > lst_addr_min) {
207 adc_feature->lst_adder_index = i;
208 break;
209 }
210 }
211
f54e9f2b
SA		 212 /*
213 * Calculate ADC sample frequencies
214 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
215 * which is the same as bus clock.
216 *
217 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
218 * SFCAdder: fixed to 6 ADCK cycles
219 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
220 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
5e9972cd 221 * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
f54e9f2b 222 */
f54e9f2b
SA		 223 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
224 info->sample_freq_avail[i] =
5e9972cd
SM		 225 adck_rate / (6 + vf610_hw_avgs[i] *
226 (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
f54e9f2b 227}
a7754276
FD		 228
229static inline void vf610_adc_cfg_init(struct vf610_adc *info)
230{
f54e9f2b
SA		 231 struct vf610_adc_feature *adc_feature = &info->adc_feature;
232
a7754276 233 /* set default Configuration for ADC controller */
f54e9f2b
SA		 234 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
235 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
236
237 adc_feature->calibration = true;
238 adc_feature->ovwren = true;
239
240 adc_feature->res_mode = 12;
241 adc_feature->sample_rate = 1;
a7754276 242
bf04c1a3 243 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
a7754276 244
f54e9f2b 245 vf610_adc_calculate_rates(info);
a7754276
FD		 246}
247
248static void vf610_adc_cfg_post_set(struct vf610_adc *info)
249{
250 struct vf610_adc_feature *adc_feature = &info->adc_feature;
251 int cfg_data = 0;
252 int gc_data = 0;
253
254 switch (adc_feature->clk_sel) {
255 case VF610_ADCIOC_ALTCLK_SET:
256 cfg_data |= VF610_ADC_ALTCLK_SEL;
257 break;
258 case VF610_ADCIOC_ADACK_SET:
259 cfg_data |= VF610_ADC_ADACK_SEL;
260 break;
261 default:
262 break;
263 }
264
265 /* low power set for calibration */
266 cfg_data |= VF610_ADC_ADLPC_EN;
267
268 /* enable high speed for calibration */
269 cfg_data |= VF610_ADC_ADHSC_EN;
270
271 /* voltage reference */
272 switch (adc_feature->vol_ref) {
273 case VF610_ADCIOC_VR_VREF_SET:
274 break;
275 case VF610_ADCIOC_VR_VALT_SET:
276 cfg_data |= VF610_ADC_REFSEL_VALT;
277 break;
278 case VF610_ADCIOC_VR_VBG_SET:
279 cfg_data |= VF610_ADC_REFSEL_VBG;
280 break;
281 default:
282 dev_err(info->dev, "error voltage reference\n");
283 }
284
285 /* data overwrite enable */
286 if (adc_feature->ovwren)
287 cfg_data |= VF610_ADC_OVWREN;
288
289 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
290 writel(gc_data, info->regs + VF610_REG_ADC_GC);
291}
292
293static void vf610_adc_calibration(struct vf610_adc *info)
294{
295 int adc_gc, hc_cfg;
a7754276
FD		 296
297 if (!info->adc_feature.calibration)
298 return;
299
300 /* enable calibration interrupt */
301 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
302 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
303
304 adc_gc = readl(info->regs + VF610_REG_ADC_GC);
305 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
306
ee3ac290 307 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
a7754276
FD		 308 dev_err(info->dev, "Timeout for adc calibration\n");
309
310 adc_gc = readl(info->regs + VF610_REG_ADC_GS);
311 if (adc_gc & VF610_ADC_CALF)
312 dev_err(info->dev, "ADC calibration failed\n");
313
314 info->adc_feature.calibration = false;
315}
316
317static void vf610_adc_cfg_set(struct vf610_adc *info)
318{
319 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
320 int cfg_data;
321
322 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
323
a7754276 324 cfg_data &= ~VF610_ADC_ADLPC_EN;
bf04c1a3 325 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
a7754276
FD		 326 cfg_data |= VF610_ADC_ADLPC_EN;
327
a7754276 328 cfg_data &= ~VF610_ADC_ADHSC_EN;
bf04c1a3
SA		 329 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
330 cfg_data |= VF610_ADC_ADHSC_EN;
a7754276
FD		 331
332 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
333}
334
335static void vf610_adc_sample_set(struct vf610_adc *info)
336{
337 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
338 int cfg_data, gc_data;
339
340 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
341 gc_data = readl(info->regs + VF610_REG_ADC_GC);
342
343 /* resolution mode */
344 cfg_data &= ~VF610_ADC_MODE_MASK;
345 switch (adc_feature->res_mode) {
346 case 8:
347 cfg_data |= VF610_ADC_MODE_BIT8;
348 break;
349 case 10:
350 cfg_data |= VF610_ADC_MODE_BIT10;
351 break;
352 case 12:
353 cfg_data |= VF610_ADC_MODE_BIT12;
354 break;
355 default:
356 dev_err(info->dev, "error resolution mode\n");
357 break;
358 }
359
360 /* clock select and clock divider */
361 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
362 switch (adc_feature->clk_div) {
363 case 1:
364 break;
365 case 2:
366 cfg_data |= VF610_ADC_CLK_DIV2;
367 break;
368 case 4:
369 cfg_data |= VF610_ADC_CLK_DIV4;
370 break;
371 case 8:
372 cfg_data |= VF610_ADC_CLK_DIV8;
373 break;
374 case 16:
375 switch (adc_feature->clk_sel) {
376 case VF610_ADCIOC_BUSCLK_SET:
377 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
378 break;
379 default:
380 dev_err(info->dev, "error clk divider\n");
381 break;
382 }
383 break;
384 }
385
5e9972cd
SM		 386 /*
387 * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
388 * determined.
389 */
390 switch (adc_feature->lst_adder_index) {
391 case VF610_ADCK_CYCLES_3:
392 break;
393 case VF610_ADCK_CYCLES_5:
394 cfg_data |= VF610_ADC_ADSTS_SHORT;
395 break;
396 case VF610_ADCK_CYCLES_7:
397 cfg_data |= VF610_ADC_ADSTS_NORMAL;
398 break;
399 case VF610_ADCK_CYCLES_9:
400 cfg_data |= VF610_ADC_ADSTS_LONG;
401 break;
402 case VF610_ADCK_CYCLES_13:
403 cfg_data |= VF610_ADC_ADLSMP_LONG;
404 break;
405 case VF610_ADCK_CYCLES_17:
406 cfg_data |= VF610_ADC_ADLSMP_LONG;
407 cfg_data |= VF610_ADC_ADSTS_SHORT;
408 break;
409 case VF610_ADCK_CYCLES_21:
410 cfg_data |= VF610_ADC_ADLSMP_LONG;
411 cfg_data |= VF610_ADC_ADSTS_NORMAL;
412 break;
413 case VF610_ADCK_CYCLES_25:
414 cfg_data |= VF610_ADC_ADLSMP_LONG;
415 cfg_data |= VF610_ADC_ADSTS_NORMAL;
416 break;
417 default:
418 dev_err(info->dev, "error in sample time select\n");
419 }
a7754276
FD		 420
421 /* update hardware average selection */
422 cfg_data &= ~VF610_ADC_AVGS_MASK;
423 gc_data &= ~VF610_ADC_AVGEN;
424 switch (adc_feature->sample_rate) {
425 case VF610_ADC_SAMPLE_1:
426 break;
427 case VF610_ADC_SAMPLE_4:
428 gc_data |= VF610_ADC_AVGEN;
429 break;
430 case VF610_ADC_SAMPLE_8:
431 gc_data |= VF610_ADC_AVGEN;
432 cfg_data |= VF610_ADC_AVGS_8;
433 break;
434 case VF610_ADC_SAMPLE_16:
435 gc_data |= VF610_ADC_AVGEN;
436 cfg_data |= VF610_ADC_AVGS_16;
437 break;
438 case VF610_ADC_SAMPLE_32:
439 gc_data |= VF610_ADC_AVGEN;
440 cfg_data |= VF610_ADC_AVGS_32;
441 break;
442 default:
443 dev_err(info->dev,
444 "error hardware sample average select\n");
445 }
446
447 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
448 writel(gc_data, info->regs + VF610_REG_ADC_GC);
449}
450
451static void vf610_adc_hw_init(struct vf610_adc *info)
452{
453 /* CFG: Feature set */
454 vf610_adc_cfg_post_set(info);
455 vf610_adc_sample_set(info);
456
457 /* adc calibration */
458 vf610_adc_calibration(info);
459
460 /* CFG: power and speed set */
461 vf610_adc_cfg_set(info);
462}
463
bf04c1a3
SA		 464static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
465 const struct iio_chan_spec *chan,
466 unsigned int mode)
467{
468 struct vf610_adc *info = iio_priv(indio_dev);
469
470 mutex_lock(&indio_dev->mlock);
471 info->adc_feature.conv_mode = mode;
472 vf610_adc_calculate_rates(info);
473 vf610_adc_hw_init(info);
474 mutex_unlock(&indio_dev->mlock);
475
476 return 0;
477}
478
479static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
480 const struct iio_chan_spec *chan)
481{
482 struct vf610_adc *info = iio_priv(indio_dev);
483
484 return info->adc_feature.conv_mode;
485}
486
487static const char * const vf610_conv_modes[] = { "normal", "high-speed",
488 "low-power" };
489
490static const struct iio_enum vf610_conversion_mode = {
491 .items = vf610_conv_modes,
492 .num_items = ARRAY_SIZE(vf610_conv_modes),
493 .get = vf610_get_conversion_mode,
494 .set = vf610_set_conversion_mode,
495};
496
497static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
498 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
499 {},
500};
501
502#define VF610_ADC_CHAN(_idx, _chan_type) { \
503 .type = (_chan_type), \
504 .indexed = 1, \
505 .channel = (_idx), \
506 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
507 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
508 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
509 .ext_info = vf610_ext_info, \
0010d6b4
SM		 510 .scan_index = (_idx), \
511 .scan_type = { \
512 .sign = 'u', \
513 .realbits = 12, \
514 .storagebits = 16, \
515 }, \
bf04c1a3
SA		 516}
517
518#define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
519 .type = (_chan_type), \
520 .channel = (_idx), \
521 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
0010d6b4
SM		 522 .scan_index = (_idx), \
523 .scan_type = { \
524 .sign = 'u', \
525 .realbits = 12, \
526 .storagebits = 16, \
527 }, \
bf04c1a3
SA		 528}
529
530static const struct iio_chan_spec vf610_adc_iio_channels[] = {
531 VF610_ADC_CHAN(0, IIO_VOLTAGE),
532 VF610_ADC_CHAN(1, IIO_VOLTAGE),
533 VF610_ADC_CHAN(2, IIO_VOLTAGE),
534 VF610_ADC_CHAN(3, IIO_VOLTAGE),
535 VF610_ADC_CHAN(4, IIO_VOLTAGE),
536 VF610_ADC_CHAN(5, IIO_VOLTAGE),
537 VF610_ADC_CHAN(6, IIO_VOLTAGE),
538 VF610_ADC_CHAN(7, IIO_VOLTAGE),
539 VF610_ADC_CHAN(8, IIO_VOLTAGE),
540 VF610_ADC_CHAN(9, IIO_VOLTAGE),
541 VF610_ADC_CHAN(10, IIO_VOLTAGE),
542 VF610_ADC_CHAN(11, IIO_VOLTAGE),
543 VF610_ADC_CHAN(12, IIO_VOLTAGE),
544 VF610_ADC_CHAN(13, IIO_VOLTAGE),
545 VF610_ADC_CHAN(14, IIO_VOLTAGE),
546 VF610_ADC_CHAN(15, IIO_VOLTAGE),
547 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
0010d6b4 548 IIO_CHAN_SOFT_TIMESTAMP(32),
bf04c1a3
SA		 549 /* sentinel */
550};
551
a7754276
FD		 552static int vf610_adc_read_data(struct vf610_adc *info)
553{
554 int result;
555
556 result = readl(info->regs + VF610_REG_ADC_R0);
557
558 switch (info->adc_feature.res_mode) {
559 case 8:
560 result &= 0xFF;
561 break;
562 case 10:
563 result &= 0x3FF;
564 break;
565 case 12:
566 result &= 0xFFF;
567 break;
568 default:
569 break;
570 }
571
572 return result;
573}
574
575static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
576{
0b568b3c 577 struct iio_dev *indio_dev = dev_id;
0010d6b4 578 struct vf610_adc *info = iio_priv(indio_dev);
a7754276
FD		 579 int coco;
580
581 coco = readl(info->regs + VF610_REG_ADC_HS);
582 if (coco & VF610_ADC_HS_COCO0) {
583 info->value = vf610_adc_read_data(info);
0010d6b4 584 if (iio_buffer_enabled(indio_dev)) {
7765dfaa 585 info->scan.chan = info->value;
0010d6b4 586 iio_push_to_buffers_with_timestamp(indio_dev,
7765dfaa 587 &info->scan,
bc2b7dab 588 iio_get_time_ns(indio_dev));
0010d6b4
SM		 589 iio_trigger_notify_done(indio_dev->trig);
590 } else
591 complete(&info->completion);
a7754276
FD		 592 }
593
594 return IRQ_HANDLED;
595}
596
f54e9f2b
SA		 597static ssize_t vf610_show_samp_freq_avail(struct device *dev,
598 struct device_attribute *attr, char *buf)
599{
600 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
601 size_t len = 0;
602 int i;
603
604 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
605 len += scnprintf(buf + len, PAGE_SIZE - len,
606 "%u ", info->sample_freq_avail[i]);
607
608 /* replace trailing space by newline */
609 buf[len - 1] = '\n';
610
611 return len;
612}
613
614static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
a7754276
FD		 615
616static struct attribute *vf610_attributes[] = {
f54e9f2b 617 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
a7754276
FD		 618 NULL
619};
620
621static const struct attribute_group vf610_attribute_group = {
622 .attrs = vf610_attributes,
623};
624
f2bdea86
NS		 625static int vf610_read_sample(struct iio_dev *indio_dev,
626 struct iio_chan_spec const *chan, int *val)
627{
628 struct vf610_adc *info = iio_priv(indio_dev);
629 unsigned int hc_cfg;
630 int ret;
631
632 mutex_lock(&indio_dev->mlock);
633 if (iio_buffer_enabled(indio_dev)) {
634 ret = -EBUSY;
635 goto out_unlock;
636 }
637
638 reinit_completion(&info->completion);
639 hc_cfg = VF610_ADC_ADCHC(chan->channel);
640 hc_cfg |= VF610_ADC_AIEN;
641 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
642 ret = wait_for_completion_interruptible_timeout(&info->completion,
643 VF610_ADC_TIMEOUT);
644 if (ret == 0) {
645 ret = -ETIMEDOUT;
646 goto out_unlock;
647 }
648
649 if (ret < 0)
650 goto out_unlock;
651
652 switch (chan->type) {
653 case IIO_VOLTAGE:
654 *val = info->value;
655 break;
656 case IIO_TEMP:
657 /*
658 * Calculate in degree Celsius times 1000
659 * Using the typical sensor slope of 1.84 mV/°C
660 * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
661 */
662 *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
663 1000000 / VF610_TEMP_SLOPE_COEFF;
664
665 break;
666 default:
667 ret = -EINVAL;
668 break;
669 }
670
671out_unlock:
672 mutex_unlock(&indio_dev->mlock);
673
674 return ret;
675}
676
a7754276
FD		 677static int vf610_read_raw(struct iio_dev *indio_dev,
678 struct iio_chan_spec const *chan,
679 int *val,
680 int *val2,
681 long mask)
682{
683 struct vf610_adc *info = iio_priv(indio_dev);
db8fa731 684 long ret;
a7754276
FD		 685
686 switch (mask) {
687 case IIO_CHAN_INFO_RAW:
774623ca 688 case IIO_CHAN_INFO_PROCESSED:
f2bdea86
NS		 689 ret = vf610_read_sample(indio_dev, chan, val);
690 if (ret < 0)
a7754276 691 return ret;
774623ca 692
a7754276
FD		 693 return IIO_VAL_INT;
694
695 case IIO_CHAN_INFO_SCALE:
696 *val = info->vref_uv / 1000;
697 *val2 = info->adc_feature.res_mode;
698 return IIO_VAL_FRACTIONAL_LOG2;
699
700 case IIO_CHAN_INFO_SAMP_FREQ:
f54e9f2b 701 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
a7754276
FD		 702 *val2 = 0;
703 return IIO_VAL_INT;
704
705 default:
706 break;
707 }
708
709 return -EINVAL;
710}
711
712static int vf610_write_raw(struct iio_dev *indio_dev,
713 struct iio_chan_spec const *chan,
714 int val,
715 int val2,
716 long mask)
717{
718 struct vf610_adc *info = iio_priv(indio_dev);
719 int i;
720
721 switch (mask) {
37dd441e
SS		 722 case IIO_CHAN_INFO_SAMP_FREQ:
723 for (i = 0;
724 i < ARRAY_SIZE(info->sample_freq_avail);
725 i++)
726 if (val == info->sample_freq_avail[i]) {
727 info->adc_feature.sample_rate = i;
728 vf610_adc_sample_set(info);
729 return 0;
730 }
731 break;
a7754276 732
37dd441e
SS		 733 default:
734 break;
a7754276
FD		 735 }
736
737 return -EINVAL;
738}
739
0010d6b4
SM		 740static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
741{
742 struct vf610_adc *info = iio_priv(indio_dev);
743 unsigned int channel;
0010d6b4
SM		 744 int val;
745
0010d6b4
SM		 746 val = readl(info->regs + VF610_REG_ADC_GC);
747 val |= VF610_ADC_ADCON;
748 writel(val, info->regs + VF610_REG_ADC_GC);
749
750 channel = find_first_bit(indio_dev->active_scan_mask,
751 indio_dev->masklength);
752
753 val = VF610_ADC_ADCHC(channel);
754 val |= VF610_ADC_AIEN;
755
756 writel(val, info->regs + VF610_REG_ADC_HC0);
757
758 return 0;
759}
760
761static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
762{
763 struct vf610_adc *info = iio_priv(indio_dev);
764 unsigned int hc_cfg = 0;
36736cc6 765 int val;
0010d6b4
SM		 766
767 val = readl(info->regs + VF610_REG_ADC_GC);
768 val &= ~VF610_ADC_ADCON;
769 writel(val, info->regs + VF610_REG_ADC_GC);
770
771 hc_cfg |= VF610_ADC_CONV_DISABLE;
772 hc_cfg &= ~VF610_ADC_AIEN;
773
774 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
775
f11d59d8 776 return 0;
0010d6b4
SM		 777}
778
779static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
780 .postenable = &vf610_adc_buffer_postenable,
781 .predisable = &vf610_adc_buffer_predisable,
782 .validate_scan_mask = &iio_validate_scan_mask_onehot,
783};
784
a7754276
FD		 785static int vf610_adc_reg_access(struct iio_dev *indio_dev,
786 unsigned reg, unsigned writeval,
787 unsigned *readval)
788{
789 struct vf610_adc *info = iio_priv(indio_dev);
790
791 if ((readval == NULL) ||
bf604a4c 792 ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
a7754276
FD		 793 return -EINVAL;
794
795 *readval = readl(info->regs + reg);
796
797 return 0;
798}
799
800static const struct iio_info vf610_adc_iio_info = {
a7754276
FD		 801 .read_raw = &vf610_read_raw,
802 .write_raw = &vf610_write_raw,
803 .debugfs_reg_access = &vf610_adc_reg_access,
804 .attrs = &vf610_attribute_group,
805};
806
807static const struct of_device_id vf610_adc_match[] = {
808 { .compatible = "fsl,vf610-adc", },
809 { /* sentinel */ }
810};
811MODULE_DEVICE_TABLE(of, vf610_adc_match);
812
813static int vf610_adc_probe(struct platform_device *pdev)
814{
3cc6a67b 815 struct device *dev = &pdev->dev;
a7754276
FD		 816 struct vf610_adc *info;
817 struct iio_dev *indio_dev;
a7754276
FD		 818 int irq;
819 int ret;
820
821 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
822 if (!indio_dev) {
823 dev_err(&pdev->dev, "Failed allocating iio device\n");
824 return -ENOMEM;
825 }
826
827 info = iio_priv(indio_dev);
828 info->dev = &pdev->dev;
829
afac22e3 830 info->regs = devm_platform_ioremap_resource(pdev, 0);
a7754276
FD		 831 if (IS_ERR(info->regs))
832 return PTR_ERR(info->regs);
833
834 irq = platform_get_irq(pdev, 0);
7c279229 835 if (irq < 0)
8552befa 836 return irq;
a7754276
FD		 837
838 ret = devm_request_irq(info->dev, irq,
839 vf610_adc_isr, 0,
0010d6b4 840 dev_name(&pdev->dev), indio_dev);
a7754276
FD		 841 if (ret < 0) {
842 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
843 return ret;
844 }
845
846 info->clk = devm_clk_get(&pdev->dev, "adc");
847 if (IS_ERR(info->clk)) {
848 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
849 PTR_ERR(info->clk));
2e3d6675 850 return PTR_ERR(info->clk);
a7754276
FD		 851 }
852
853 info->vref = devm_regulator_get(&pdev->dev, "vref");
854 if (IS_ERR(info->vref))
855 return PTR_ERR(info->vref);
856
857 ret = regulator_enable(info->vref);
858 if (ret)
859 return ret;
860
861 info->vref_uv = regulator_get_voltage(info->vref);
862
3cc6a67b 863 device_property_read_u32_array(dev, "fsl,adck-max-frequency", info->max_adck_rate, 3);
bf04c1a3 864
3cc6a67b
AS		 865 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
866 device_property_read_u32(dev, "min-sample-time", &info->adc_feature.default_sample_time);
5e9972cd 867
a7754276
FD		 868 platform_set_drvdata(pdev, indio_dev);
869
870 init_completion(&info->completion);
871
872 indio_dev->name = dev_name(&pdev->dev);
a7754276
FD		 873 indio_dev->info = &vf610_adc_iio_info;
874 indio_dev->modes = INDIO_DIRECT_MODE;
875 indio_dev->channels = vf610_adc_iio_channels;
876 indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
877
878 ret = clk_prepare_enable(info->clk);
879 if (ret) {
880 dev_err(&pdev->dev,
881 "Could not prepare or enable the clock.\n");
882 goto error_adc_clk_enable;
883 }
884
885 vf610_adc_cfg_init(info);
886 vf610_adc_hw_init(info);
887
0010d6b4
SM		 888 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
889 NULL, &iio_triggered_buffer_setup_ops);
890 if (ret < 0) {
891 dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
892 goto error_iio_device_register;
893 }
894
a7754276
FD		 895 ret = iio_device_register(indio_dev);
896 if (ret) {
897 dev_err(&pdev->dev, "Couldn't register the device.\n");
0010d6b4 898 goto error_adc_buffer_init;
a7754276
FD		 899 }
900
901 return 0;
902
0010d6b4
SM		 903error_adc_buffer_init:
904 iio_triggered_buffer_cleanup(indio_dev);
a7754276
FD		 905error_iio_device_register:
906 clk_disable_unprepare(info->clk);
907error_adc_clk_enable:
908 regulator_disable(info->vref);
909
910 return ret;
911}
912
913static int vf610_adc_remove(struct platform_device *pdev)
914{
915 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
916 struct vf610_adc *info = iio_priv(indio_dev);
917
918 iio_device_unregister(indio_dev);
0010d6b4 919 iio_triggered_buffer_cleanup(indio_dev);
a7754276
FD		 920 regulator_disable(info->vref);
921 clk_disable_unprepare(info->clk);
922
923 return 0;
924}
925
a7754276
FD		 926static int vf610_adc_suspend(struct device *dev)
927{
928 struct iio_dev *indio_dev = dev_get_drvdata(dev);
929 struct vf610_adc *info = iio_priv(indio_dev);
930 int hc_cfg;
931
932 /* ADC controller enters to stop mode */
933 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
934 hc_cfg |= VF610_ADC_CONV_DISABLE;
935 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
936
937 clk_disable_unprepare(info->clk);
938 regulator_disable(info->vref);
939
940 return 0;
941}
942
943static int vf610_adc_resume(struct device *dev)
944{
945 struct iio_dev *indio_dev = dev_get_drvdata(dev);
946 struct vf610_adc *info = iio_priv(indio_dev);
947 int ret;
948
949 ret = regulator_enable(info->vref);
950 if (ret)
951 return ret;
952
953 ret = clk_prepare_enable(info->clk);
954 if (ret)
9da64c25 955 goto disable_reg;
a7754276
FD		 956
957 vf610_adc_hw_init(info);
958
959 return 0;
9da64c25
FE		 960
961disable_reg:
962 regulator_disable(info->vref);
963 return ret;
a7754276 964}
a7754276 965
9cbeee0f
JC		 966static DEFINE_SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend,
967 vf610_adc_resume);
a7754276
FD		 968
969static struct platform_driver vf610_adc_driver = {
970 .probe = vf610_adc_probe,
971 .remove = vf610_adc_remove,
972 .driver = {
973 .name = DRIVER_NAME,
a7754276 974 .of_match_table = vf610_adc_match,
9cbeee0f 975 .pm = pm_sleep_ptr(&vf610_adc_pm_ops),
a7754276
FD		 976 },
977};
978
979module_platform_driver(vf610_adc_driver);
980
981MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
982MODULE_DESCRIPTION("Freescale VF610 ADC driver");
983MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)