Commit | Line | Data |
---|---|---|
aaf71200 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5e53a69b PR |
2 | /* |
3 | * TI ADC MFD driver | |
4 | * | |
3593cd53 | 5 | * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
5e53a69b PR |
6 | */ |
7 | ||
5e53a69b PR |
8 | #include <linux/kernel.h> |
9 | #include <linux/err.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/iio/iio.h> | |
6f39ac4e PR |
16 | #include <linux/of.h> |
17 | #include <linux/of_device.h> | |
c80df483 PA |
18 | #include <linux/iio/machine.h> |
19 | #include <linux/iio/driver.h> | |
8bed0166 | 20 | #include <linux/iopoll.h> |
5e53a69b PR |
21 | |
22 | #include <linux/mfd/ti_am335x_tscadc.h> | |
ca9a5638 ZL |
23 | #include <linux/iio/buffer.h> |
24 | #include <linux/iio/kfifo_buf.h> | |
5e53a69b | 25 | |
f438b9da M |
26 | #include <linux/dmaengine.h> |
27 | #include <linux/dma-mapping.h> | |
28 | ||
29 | #define DMA_BUFFER_SIZE SZ_2K | |
30 | ||
31 | struct tiadc_dma { | |
32 | struct dma_slave_config conf; | |
33 | struct dma_chan *chan; | |
34 | dma_addr_t addr; | |
35 | dma_cookie_t cookie; | |
36 | u8 *buf; | |
37 | int current_period; | |
38 | int period_size; | |
39 | u8 fifo_thresh; | |
40 | }; | |
41 | ||
5e53a69b PR |
42 | struct tiadc_device { |
43 | struct ti_tscadc_dev *mfd_tscadc; | |
f438b9da | 44 | struct tiadc_dma dma; |
90c43ec6 | 45 | struct mutex fifo1_lock; /* to protect fifo access */ |
5e53a69b | 46 | int channels; |
f438b9da | 47 | int total_ch_enabled; |
18926ede SAS |
48 | u8 channel_line[8]; |
49 | u8 channel_step[8]; | |
ca9a5638 | 50 | int buffer_en_ch_steps; |
ca9a5638 | 51 | u16 data[8]; |
5dc11e81 | 52 | u32 open_delay[8], sample_delay[8], step_avg[8]; |
5e53a69b PR |
53 | }; |
54 | ||
55 | static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg) | |
56 | { | |
57 | return readl(adc->mfd_tscadc->tscadc_base + reg); | |
58 | } | |
59 | ||
60 | static void tiadc_writel(struct tiadc_device *adc, unsigned int reg, | |
9cac0a02 | 61 | unsigned int val) |
5e53a69b PR |
62 | { |
63 | writel(val, adc->mfd_tscadc->tscadc_base + reg); | |
64 | } | |
65 | ||
abeccee4 PR |
66 | static u32 get_adc_step_mask(struct tiadc_device *adc_dev) |
67 | { | |
68 | u32 step_en; | |
69 | ||
70 | step_en = ((1 << adc_dev->channels) - 1); | |
71 | step_en <<= TOTAL_STEPS - adc_dev->channels + 1; | |
72 | return step_en; | |
73 | } | |
74 | ||
7ca6740c | 75 | static u32 get_adc_chan_step_mask(struct tiadc_device *adc_dev, |
9cac0a02 | 76 | struct iio_chan_spec const *chan) |
7ca6740c SAS |
77 | { |
78 | int i; | |
79 | ||
80 | for (i = 0; i < ARRAY_SIZE(adc_dev->channel_step); i++) { | |
81 | if (chan->channel == adc_dev->channel_line[i]) { | |
82 | u32 step; | |
83 | ||
84 | step = adc_dev->channel_step[i]; | |
85 | /* +1 for the charger */ | |
86 | return 1 << (step + 1); | |
87 | } | |
88 | } | |
89 | WARN_ON(1); | |
90 | return 0; | |
91 | } | |
92 | ||
ca9a5638 | 93 | static u32 get_adc_step_bit(struct tiadc_device *adc_dev, int chan) |
5e53a69b | 94 | { |
ca9a5638 ZL |
95 | return 1 << adc_dev->channel_step[chan]; |
96 | } | |
97 | ||
8bed0166 MR |
98 | static int tiadc_wait_idle(struct tiadc_device *adc_dev) |
99 | { | |
100 | u32 val; | |
101 | ||
102 | return readl_poll_timeout(adc_dev->mfd_tscadc->tscadc_base + REG_ADCFSM, | |
103 | val, !(val & SEQ_STATUS), 10, | |
789e5ebc | 104 | IDLE_TIMEOUT_MS * 1000 * adc_dev->channels); |
8bed0166 MR |
105 | } |
106 | ||
ca9a5638 ZL |
107 | static void tiadc_step_config(struct iio_dev *indio_dev) |
108 | { | |
109 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
5e53a69b | 110 | unsigned int stepconfig; |
3a59684c | 111 | int i, steps = 0; |
5e53a69b PR |
112 | |
113 | /* | |
114 | * There are 16 configurable steps and 8 analog input | |
115 | * lines available which are shared between Touchscreen and ADC. | |
116 | * | |
3a59684c | 117 | * Steps forwards i.e. from 0 towards 16 are used by ADC |
5e53a69b PR |
118 | * depending on number of input lines needed. |
119 | * Channel would represent which analog input | |
120 | * needs to be given to ADC to digitalize data. | |
121 | */ | |
18926ede SAS |
122 | for (i = 0; i < adc_dev->channels; i++) { |
123 | int chan; | |
124 | ||
125 | chan = adc_dev->channel_line[i]; | |
5dc11e81 | 126 | |
5dc11e81 | 127 | if (adc_dev->step_avg[i]) |
9cac0a02 MR |
128 | stepconfig = STEPCONFIG_AVG(ffs(adc_dev->step_avg[i]) - 1) | |
129 | STEPCONFIG_FIFO1; | |
5dc11e81 V |
130 | else |
131 | stepconfig = STEPCONFIG_FIFO1; | |
132 | ||
133 | if (iio_buffer_enabled(indio_dev)) | |
134 | stepconfig |= STEPCONFIG_MODE_SWCNT; | |
135 | ||
18926ede | 136 | tiadc_writel(adc_dev, REG_STEPCONFIG(steps), |
9cac0a02 MR |
137 | stepconfig | STEPCONFIG_INP(chan) | |
138 | STEPCONFIG_INM_ADCREFM | STEPCONFIG_RFP_VREFP | | |
139 | STEPCONFIG_RFM_VREFN); | |
5dc11e81 | 140 | |
18926ede | 141 | tiadc_writel(adc_dev, REG_STEPDELAY(steps), |
9cac0a02 MR |
142 | STEPDELAY_OPEN(adc_dev->open_delay[i]) | |
143 | STEPDELAY_SAMPLE(adc_dev->sample_delay[i])); | |
5dc11e81 | 144 | |
18926ede SAS |
145 | adc_dev->channel_step[i] = steps; |
146 | steps++; | |
5e53a69b | 147 | } |
ca9a5638 ZL |
148 | } |
149 | ||
150 | static irqreturn_t tiadc_irq_h(int irq, void *private) | |
151 | { | |
152 | struct iio_dev *indio_dev = private; | |
153 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
e83bb3e6 ME |
154 | unsigned int status, config, adc_fsm; |
155 | unsigned short count = 0; | |
156 | ||
ca9a5638 ZL |
157 | status = tiadc_readl(adc_dev, REG_IRQSTATUS); |
158 | ||
159 | /* | |
160 | * ADC and touchscreen share the IRQ line. | |
161 | * FIFO0 interrupts are used by TSC. Handle FIFO1 IRQs here only | |
162 | */ | |
163 | if (status & IRQENB_FIFO1OVRRUN) { | |
164 | /* FIFO Overrun. Clear flag. Disable/Enable ADC to recover */ | |
165 | config = tiadc_readl(adc_dev, REG_CTRL); | |
c3e36b5d | 166 | config &= ~(CNTRLREG_SSENB); |
ca9a5638 | 167 | tiadc_writel(adc_dev, REG_CTRL, config); |
9cac0a02 MR |
168 | tiadc_writel(adc_dev, REG_IRQSTATUS, |
169 | IRQENB_FIFO1OVRRUN | IRQENB_FIFO1UNDRFLW | | |
170 | IRQENB_FIFO1THRES); | |
e83bb3e6 | 171 | |
9cac0a02 MR |
172 | /* |
173 | * Wait for the idle state. | |
e83bb3e6 ME |
174 | * ADC needs to finish the current conversion |
175 | * before disabling the module | |
176 | */ | |
177 | do { | |
178 | adc_fsm = tiadc_readl(adc_dev, REG_ADCFSM); | |
179 | } while (adc_fsm != 0x10 && count++ < 100); | |
180 | ||
c3e36b5d | 181 | tiadc_writel(adc_dev, REG_CTRL, (config | CNTRLREG_SSENB)); |
ca9a5638 ZL |
182 | return IRQ_HANDLED; |
183 | } else if (status & IRQENB_FIFO1THRES) { | |
184 | /* Disable irq and wake worker thread */ | |
185 | tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES); | |
186 | return IRQ_WAKE_THREAD; | |
187 | } | |
188 | ||
189 | return IRQ_NONE; | |
190 | } | |
191 | ||
192 | static irqreturn_t tiadc_worker_h(int irq, void *private) | |
193 | { | |
194 | struct iio_dev *indio_dev = private; | |
195 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
196 | int i, k, fifo1count, read; | |
197 | u16 *data = adc_dev->data; | |
198 | ||
199 | fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); | |
200 | for (k = 0; k < fifo1count; k = k + i) { | |
9cac0a02 | 201 | for (i = 0; i < indio_dev->scan_bytes / 2; i++) { |
ca9a5638 ZL |
202 | read = tiadc_readl(adc_dev, REG_FIFO1); |
203 | data[i] = read & FIFOREAD_DATA_MASK; | |
204 | } | |
9cac0a02 | 205 | iio_push_to_buffers(indio_dev, (u8 *)data); |
ca9a5638 ZL |
206 | } |
207 | ||
208 | tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES); | |
209 | tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES); | |
210 | ||
211 | return IRQ_HANDLED; | |
212 | } | |
213 | ||
f438b9da M |
214 | static void tiadc_dma_rx_complete(void *param) |
215 | { | |
216 | struct iio_dev *indio_dev = param; | |
217 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
218 | struct tiadc_dma *dma = &adc_dev->dma; | |
219 | u8 *data; | |
220 | int i; | |
221 | ||
222 | data = dma->buf + dma->current_period * dma->period_size; | |
223 | dma->current_period = 1 - dma->current_period; /* swap the buffer ID */ | |
224 | ||
225 | for (i = 0; i < dma->period_size; i += indio_dev->scan_bytes) { | |
226 | iio_push_to_buffers(indio_dev, data); | |
227 | data += indio_dev->scan_bytes; | |
228 | } | |
229 | } | |
230 | ||
231 | static int tiadc_start_dma(struct iio_dev *indio_dev) | |
232 | { | |
233 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
234 | struct tiadc_dma *dma = &adc_dev->dma; | |
235 | struct dma_async_tx_descriptor *desc; | |
236 | ||
237 | dma->current_period = 0; /* We start to fill period 0 */ | |
9cac0a02 | 238 | |
f438b9da M |
239 | /* |
240 | * Make the fifo thresh as the multiple of total number of | |
241 | * channels enabled, so make sure that cyclic DMA period | |
242 | * length is also a multiple of total number of channels | |
243 | * enabled. This ensures that no invalid data is reported | |
244 | * to the stack via iio_push_to_buffers(). | |
245 | */ | |
246 | dma->fifo_thresh = rounddown(FIFO1_THRESHOLD + 1, | |
247 | adc_dev->total_ch_enabled) - 1; | |
9cac0a02 | 248 | |
f438b9da M |
249 | /* Make sure that period length is multiple of fifo thresh level */ |
250 | dma->period_size = rounddown(DMA_BUFFER_SIZE / 2, | |
9cac0a02 | 251 | (dma->fifo_thresh + 1) * sizeof(u16)); |
f438b9da M |
252 | |
253 | dma->conf.src_maxburst = dma->fifo_thresh + 1; | |
254 | dmaengine_slave_config(dma->chan, &dma->conf); | |
255 | ||
256 | desc = dmaengine_prep_dma_cyclic(dma->chan, dma->addr, | |
257 | dma->period_size * 2, | |
258 | dma->period_size, DMA_DEV_TO_MEM, | |
259 | DMA_PREP_INTERRUPT); | |
260 | if (!desc) | |
261 | return -EBUSY; | |
262 | ||
263 | desc->callback = tiadc_dma_rx_complete; | |
264 | desc->callback_param = indio_dev; | |
265 | ||
266 | dma->cookie = dmaengine_submit(desc); | |
267 | ||
268 | dma_async_issue_pending(dma->chan); | |
269 | ||
270 | tiadc_writel(adc_dev, REG_FIFO1THR, dma->fifo_thresh); | |
271 | tiadc_writel(adc_dev, REG_DMA1REQ, dma->fifo_thresh); | |
272 | tiadc_writel(adc_dev, REG_DMAENABLE_SET, DMA_FIFO1); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
ca9a5638 ZL |
277 | static int tiadc_buffer_preenable(struct iio_dev *indio_dev) |
278 | { | |
279 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
f83d87a0 | 280 | int i, fifo1count; |
8bed0166 MR |
281 | int ret; |
282 | ||
283 | ret = tiadc_wait_idle(adc_dev); | |
284 | if (ret) | |
285 | return ret; | |
ca9a5638 | 286 | |
9cac0a02 MR |
287 | tiadc_writel(adc_dev, REG_IRQCLR, |
288 | IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN | | |
289 | IRQENB_FIFO1UNDRFLW); | |
ca9a5638 ZL |
290 | |
291 | /* Flush FIFO. Needed in corner cases in simultaneous tsc/adc use */ | |
292 | fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); | |
293 | for (i = 0; i < fifo1count; i++) | |
f83d87a0 | 294 | tiadc_readl(adc_dev, REG_FIFO1); |
ca9a5638 | 295 | |
24adaf79 | 296 | return 0; |
ca9a5638 ZL |
297 | } |
298 | ||
299 | static int tiadc_buffer_postenable(struct iio_dev *indio_dev) | |
300 | { | |
301 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
f438b9da M |
302 | struct tiadc_dma *dma = &adc_dev->dma; |
303 | unsigned int irq_enable; | |
ca9a5638 ZL |
304 | unsigned int enb = 0; |
305 | u8 bit; | |
306 | ||
307 | tiadc_step_config(indio_dev); | |
f438b9da | 308 | for_each_set_bit(bit, indio_dev->active_scan_mask, adc_dev->channels) { |
ca9a5638 | 309 | enb |= (get_adc_step_bit(adc_dev, bit) << 1); |
f438b9da M |
310 | adc_dev->total_ch_enabled++; |
311 | } | |
ca9a5638 ZL |
312 | adc_dev->buffer_en_ch_steps = enb; |
313 | ||
f438b9da M |
314 | if (dma->chan) |
315 | tiadc_start_dma(indio_dev); | |
316 | ||
7e170c6e | 317 | am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, enb); |
ca9a5638 | 318 | |
9cac0a02 MR |
319 | tiadc_writel(adc_dev, REG_IRQSTATUS, |
320 | IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN | | |
321 | IRQENB_FIFO1UNDRFLW); | |
f438b9da M |
322 | |
323 | irq_enable = IRQENB_FIFO1OVRRUN; | |
324 | if (!dma->chan) | |
325 | irq_enable |= IRQENB_FIFO1THRES; | |
326 | tiadc_writel(adc_dev, REG_IRQENABLE, irq_enable); | |
ca9a5638 ZL |
327 | |
328 | return 0; | |
329 | } | |
330 | ||
331 | static int tiadc_buffer_predisable(struct iio_dev *indio_dev) | |
332 | { | |
333 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
f438b9da | 334 | struct tiadc_dma *dma = &adc_dev->dma; |
f83d87a0 | 335 | int fifo1count, i; |
ca9a5638 | 336 | |
9cac0a02 MR |
337 | tiadc_writel(adc_dev, REG_IRQCLR, |
338 | IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN | | |
339 | IRQENB_FIFO1UNDRFLW); | |
ca9a5638 | 340 | am335x_tsc_se_clr(adc_dev->mfd_tscadc, adc_dev->buffer_en_ch_steps); |
3954b7bf | 341 | adc_dev->buffer_en_ch_steps = 0; |
f438b9da M |
342 | adc_dev->total_ch_enabled = 0; |
343 | if (dma->chan) { | |
344 | tiadc_writel(adc_dev, REG_DMAENABLE_CLEAR, 0x2); | |
345 | dmaengine_terminate_async(dma->chan); | |
346 | } | |
b1451e54 | 347 | |
ca9a5638 ZL |
348 | /* Flush FIFO of leftover data in the time it takes to disable adc */ |
349 | fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); | |
350 | for (i = 0; i < fifo1count; i++) | |
f83d87a0 | 351 | tiadc_readl(adc_dev, REG_FIFO1); |
ca9a5638 ZL |
352 | |
353 | return 0; | |
5e53a69b PR |
354 | } |
355 | ||
ca9a5638 ZL |
356 | static int tiadc_buffer_postdisable(struct iio_dev *indio_dev) |
357 | { | |
358 | tiadc_step_config(indio_dev); | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | static const struct iio_buffer_setup_ops tiadc_buffer_setup_ops = { | |
364 | .preenable = &tiadc_buffer_preenable, | |
365 | .postenable = &tiadc_buffer_postenable, | |
366 | .predisable = &tiadc_buffer_predisable, | |
367 | .postdisable = &tiadc_buffer_postdisable, | |
368 | }; | |
369 | ||
3c530805 | 370 | static int tiadc_iio_buffered_hardware_setup(struct device *dev, |
9cac0a02 MR |
371 | struct iio_dev *indio_dev, |
372 | irqreturn_t (*pollfunc_bh)(int irq, void *p), | |
373 | irqreturn_t (*pollfunc_th)(int irq, void *p), | |
374 | int irq, unsigned long flags, | |
375 | const struct iio_buffer_setup_ops *setup_ops) | |
ca9a5638 ZL |
376 | { |
377 | int ret; | |
378 | ||
f67c6c73 | 379 | ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, setup_ops); |
ca9a5638 | 380 | if (ret) |
7e6d9788 | 381 | return ret; |
ca9a5638 | 382 | |
17395ce2 | 383 | return devm_request_threaded_irq(dev, irq, pollfunc_th, pollfunc_bh, |
9cac0a02 | 384 | flags, indio_dev->name, indio_dev); |
ca9a5638 ZL |
385 | } |
386 | ||
c80df483 PA |
387 | static const char * const chan_name_ain[] = { |
388 | "AIN0", | |
389 | "AIN1", | |
390 | "AIN2", | |
391 | "AIN3", | |
392 | "AIN4", | |
393 | "AIN5", | |
394 | "AIN6", | |
395 | "AIN7", | |
396 | }; | |
397 | ||
6ff0199a AA |
398 | static int tiadc_channel_init(struct device *dev, struct iio_dev *indio_dev, |
399 | int channels) | |
5e53a69b | 400 | { |
c80df483 | 401 | struct tiadc_device *adc_dev = iio_priv(indio_dev); |
5e53a69b | 402 | struct iio_chan_spec *chan_array; |
c80df483 | 403 | struct iio_chan_spec *chan; |
5e53a69b PR |
404 | int i; |
405 | ||
406 | indio_dev->num_channels = channels; | |
6ff0199a AA |
407 | chan_array = devm_kcalloc(dev, channels, sizeof(*chan_array), |
408 | GFP_KERNEL); | |
9cac0a02 | 409 | if (!chan_array) |
5e53a69b PR |
410 | return -ENOMEM; |
411 | ||
c80df483 PA |
412 | chan = chan_array; |
413 | for (i = 0; i < channels; i++, chan++) { | |
5e53a69b PR |
414 | chan->type = IIO_VOLTAGE; |
415 | chan->indexed = 1; | |
18926ede | 416 | chan->channel = adc_dev->channel_line[i]; |
6c572522 | 417 | chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); |
3af99354 | 418 | chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); |
18926ede | 419 | chan->datasheet_name = chan_name_ain[chan->channel]; |
ca9a5638 | 420 | chan->scan_index = i; |
c80df483 PA |
421 | chan->scan_type.sign = 'u'; |
422 | chan->scan_type.realbits = 12; | |
0f6fc7d5 | 423 | chan->scan_type.storagebits = 16; |
5e53a69b PR |
424 | } |
425 | ||
426 | indio_dev->channels = chan_array; | |
427 | ||
c80df483 | 428 | return 0; |
5e53a69b PR |
429 | } |
430 | ||
5e53a69b | 431 | static int tiadc_read_raw(struct iio_dev *indio_dev, |
9cac0a02 MR |
432 | struct iio_chan_spec const *chan, int *val, int *val2, |
433 | long mask) | |
5e53a69b PR |
434 | { |
435 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
b1451e54 PR |
436 | int i, map_val; |
437 | unsigned int fifo1count, read, stepid; | |
1460c152 | 438 | bool found = false; |
b1451e54 | 439 | u32 step_en; |
7ca6740c | 440 | unsigned long timeout; |
8bed0166 | 441 | int ret; |
ca9a5638 | 442 | |
3af99354 MR |
443 | switch (mask) { |
444 | case IIO_CHAN_INFO_RAW: | |
445 | break; | |
446 | case IIO_CHAN_INFO_SCALE: | |
447 | switch (chan->type) { | |
448 | case IIO_VOLTAGE: | |
449 | *val = 1800; | |
450 | *val2 = chan->scan_type.realbits; | |
451 | return IIO_VAL_FRACTIONAL_LOG2; | |
452 | default: | |
453 | return -EINVAL; | |
454 | } | |
455 | break; | |
456 | default: | |
457 | return -EINVAL; | |
458 | } | |
459 | ||
ca9a5638 ZL |
460 | if (iio_buffer_enabled(indio_dev)) |
461 | return -EBUSY; | |
462 | ||
7ca6740c SAS |
463 | step_en = get_adc_chan_step_mask(adc_dev, chan); |
464 | if (!step_en) | |
465 | return -EINVAL; | |
466 | ||
90c43ec6 | 467 | mutex_lock(&adc_dev->fifo1_lock); |
8bed0166 MR |
468 | |
469 | ret = tiadc_wait_idle(adc_dev); | |
470 | if (ret) | |
471 | goto err_unlock; | |
472 | ||
7ca6740c SAS |
473 | fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); |
474 | while (fifo1count--) | |
475 | tiadc_readl(adc_dev, REG_FIFO1); | |
476 | ||
7e170c6e | 477 | am335x_tsc_se_set_once(adc_dev->mfd_tscadc, step_en); |
b1451e54 | 478 | |
7ca6740c | 479 | /* Wait for Fifo threshold interrupt */ |
789e5ebc | 480 | timeout = jiffies + msecs_to_jiffies(IDLE_TIMEOUT_MS * adc_dev->channels); |
7ca6740c SAS |
481 | while (1) { |
482 | fifo1count = tiadc_readl(adc_dev, REG_FIFO1CNT); | |
483 | if (fifo1count) | |
484 | break; | |
485 | ||
486 | if (time_after(jiffies, timeout)) { | |
487 | am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); | |
90c43ec6 V |
488 | ret = -EAGAIN; |
489 | goto err_unlock; | |
b1451e54 | 490 | } |
fb7f8ce3 | 491 | } |
9cac0a02 | 492 | |
baa3c652 | 493 | map_val = adc_dev->channel_step[chan->scan_index]; |
5e53a69b PR |
494 | |
495 | /* | |
7ca6740c SAS |
496 | * We check the complete FIFO. We programmed just one entry but in case |
497 | * something went wrong we left empty handed (-EAGAIN previously) and | |
498 | * then the value apeared somehow in the FIFO we would have two entries. | |
499 | * Therefore we read every item and keep only the latest version of the | |
500 | * requested channel. | |
5e53a69b | 501 | */ |
5e53a69b | 502 | for (i = 0; i < fifo1count; i++) { |
18926ede | 503 | read = tiadc_readl(adc_dev, REG_FIFO1); |
b1451e54 PR |
504 | stepid = read & FIFOREAD_CHNLID_MASK; |
505 | stepid = stepid >> 0x10; | |
506 | ||
507 | if (stepid == map_val) { | |
508 | read = read & FIFOREAD_DATA_MASK; | |
1460c152 | 509 | found = true; |
9cac0a02 | 510 | *val = (u16)read; |
1460c152 | 511 | } |
5e53a69b | 512 | } |
9cac0a02 | 513 | |
7ca6740c | 514 | am335x_tsc_se_adc_done(adc_dev->mfd_tscadc); |
b1451e54 | 515 | |
a540243f | 516 | if (!found) |
9cac0a02 | 517 | ret = -EBUSY; |
90c43ec6 V |
518 | |
519 | err_unlock: | |
520 | mutex_unlock(&adc_dev->fifo1_lock); | |
8bed0166 | 521 | return ret ? ret : IIO_VAL_INT; |
5e53a69b PR |
522 | } |
523 | ||
524 | static const struct iio_info tiadc_info = { | |
525 | .read_raw = &tiadc_read_raw, | |
526 | }; | |
527 | ||
f438b9da M |
528 | static int tiadc_request_dma(struct platform_device *pdev, |
529 | struct tiadc_device *adc_dev) | |
530 | { | |
531 | struct tiadc_dma *dma = &adc_dev->dma; | |
532 | dma_cap_mask_t mask; | |
533 | ||
534 | /* Default slave configuration parameters */ | |
535 | dma->conf.direction = DMA_DEV_TO_MEM; | |
536 | dma->conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
537 | dma->conf.src_addr = adc_dev->mfd_tscadc->tscadc_phys_base + REG_FIFO1; | |
538 | ||
539 | dma_cap_zero(mask); | |
540 | dma_cap_set(DMA_CYCLIC, mask); | |
541 | ||
542 | /* Get a channel for RX */ | |
543 | dma->chan = dma_request_chan(adc_dev->mfd_tscadc->dev, "fifo1"); | |
544 | if (IS_ERR(dma->chan)) { | |
545 | int ret = PTR_ERR(dma->chan); | |
546 | ||
547 | dma->chan = NULL; | |
548 | return ret; | |
549 | } | |
550 | ||
551 | /* RX buffer */ | |
552 | dma->buf = dma_alloc_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, | |
553 | &dma->addr, GFP_KERNEL); | |
554 | if (!dma->buf) | |
555 | goto err; | |
556 | ||
557 | return 0; | |
9cac0a02 | 558 | |
f438b9da M |
559 | err: |
560 | dma_release_channel(dma->chan); | |
561 | return -ENOMEM; | |
562 | } | |
563 | ||
dee1f550 V |
564 | static int tiadc_parse_dt(struct platform_device *pdev, |
565 | struct tiadc_device *adc_dev) | |
566 | { | |
567 | struct device_node *node = pdev->dev.of_node; | |
568 | struct property *prop; | |
569 | const __be32 *cur; | |
570 | int channels = 0; | |
571 | u32 val; | |
b61a9d32 | 572 | int i; |
dee1f550 V |
573 | |
574 | of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { | |
575 | adc_dev->channel_line[channels] = val; | |
5dc11e81 V |
576 | |
577 | /* Set Default values for optional DT parameters */ | |
578 | adc_dev->open_delay[channels] = STEPCONFIG_OPENDLY; | |
579 | adc_dev->sample_delay[channels] = STEPCONFIG_SAMPLEDLY; | |
580 | adc_dev->step_avg[channels] = 16; | |
581 | ||
dee1f550 V |
582 | channels++; |
583 | } | |
584 | ||
b61a9d32 MR |
585 | adc_dev->channels = channels; |
586 | ||
5dc11e81 V |
587 | of_property_read_u32_array(node, "ti,chan-step-avg", |
588 | adc_dev->step_avg, channels); | |
589 | of_property_read_u32_array(node, "ti,chan-step-opendelay", | |
590 | adc_dev->open_delay, channels); | |
591 | of_property_read_u32_array(node, "ti,chan-step-sampledelay", | |
592 | adc_dev->sample_delay, channels); | |
593 | ||
b61a9d32 MR |
594 | for (i = 0; i < adc_dev->channels; i++) { |
595 | int chan; | |
596 | ||
597 | chan = adc_dev->channel_line[i]; | |
598 | ||
599 | if (adc_dev->step_avg[i] > STEPCONFIG_AVG_16) { | |
600 | dev_warn(&pdev->dev, | |
601 | "chan %d: wrong step avg, truncated to %ld\n", | |
602 | chan, STEPCONFIG_AVG_16); | |
603 | adc_dev->step_avg[i] = STEPCONFIG_AVG_16; | |
604 | } | |
605 | ||
606 | if (adc_dev->open_delay[i] > STEPCONFIG_MAX_OPENDLY) { | |
607 | dev_warn(&pdev->dev, | |
608 | "chan %d: wrong open delay, truncated to 0x%lX\n", | |
609 | chan, STEPCONFIG_MAX_OPENDLY); | |
610 | adc_dev->open_delay[i] = STEPCONFIG_MAX_OPENDLY; | |
611 | } | |
612 | ||
613 | if (adc_dev->sample_delay[i] > STEPCONFIG_MAX_SAMPLE) { | |
614 | dev_warn(&pdev->dev, | |
615 | "chan %d: wrong sample delay, truncated to 0x%lX\n", | |
616 | chan, STEPCONFIG_MAX_SAMPLE); | |
617 | adc_dev->sample_delay[i] = STEPCONFIG_MAX_SAMPLE; | |
618 | } | |
619 | } | |
620 | ||
dee1f550 V |
621 | return 0; |
622 | } | |
623 | ||
fc52692c | 624 | static int tiadc_probe(struct platform_device *pdev) |
5e53a69b PR |
625 | { |
626 | struct iio_dev *indio_dev; | |
627 | struct tiadc_device *adc_dev; | |
6f39ac4e | 628 | struct device_node *node = pdev->dev.of_node; |
5e53a69b PR |
629 | int err; |
630 | ||
0ead4fb2 SAS |
631 | if (!node) { |
632 | dev_err(&pdev->dev, "Could not find valid DT data.\n"); | |
5e53a69b PR |
633 | return -EINVAL; |
634 | } | |
635 | ||
5ba5b437 | 636 | indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev)); |
9cac0a02 | 637 | if (!indio_dev) { |
5e53a69b | 638 | dev_err(&pdev->dev, "failed to allocate iio device\n"); |
a0648130 | 639 | return -ENOMEM; |
5e53a69b PR |
640 | } |
641 | adc_dev = iio_priv(indio_dev); | |
642 | ||
6f39ac4e | 643 | adc_dev->mfd_tscadc = ti_tscadc_dev_get(pdev); |
dee1f550 | 644 | tiadc_parse_dt(pdev, adc_dev); |
5e53a69b | 645 | |
5e53a69b PR |
646 | indio_dev->name = dev_name(&pdev->dev); |
647 | indio_dev->modes = INDIO_DIRECT_MODE; | |
648 | indio_dev->info = &tiadc_info; | |
649 | ||
ca9a5638 ZL |
650 | tiadc_step_config(indio_dev); |
651 | tiadc_writel(adc_dev, REG_FIFO1THR, FIFO1_THRESHOLD); | |
90c43ec6 | 652 | mutex_init(&adc_dev->fifo1_lock); |
5e53a69b | 653 | |
6ff0199a | 654 | err = tiadc_channel_init(&pdev->dev, indio_dev, adc_dev->channels); |
5e53a69b | 655 | if (err < 0) |
a0648130 | 656 | return err; |
5e53a69b | 657 | |
3c530805 | 658 | err = tiadc_iio_buffered_hardware_setup(&pdev->dev, indio_dev, |
9cac0a02 MR |
659 | &tiadc_worker_h, |
660 | &tiadc_irq_h, | |
661 | adc_dev->mfd_tscadc->irq, | |
662 | IRQF_SHARED, | |
663 | &tiadc_buffer_setup_ops); | |
5e53a69b | 664 | if (err) |
16e8f8fe | 665 | return err; |
5e53a69b | 666 | |
ca9a5638 ZL |
667 | err = iio_device_register(indio_dev); |
668 | if (err) | |
16e8f8fe | 669 | return err; |
ca9a5638 | 670 | |
5e53a69b PR |
671 | platform_set_drvdata(pdev, indio_dev); |
672 | ||
f438b9da M |
673 | err = tiadc_request_dma(pdev, adc_dev); |
674 | if (err && err == -EPROBE_DEFER) | |
675 | goto err_dma; | |
676 | ||
5e53a69b PR |
677 | return 0; |
678 | ||
f438b9da M |
679 | err_dma: |
680 | iio_device_unregister(indio_dev); | |
16e8f8fe | 681 | |
5e53a69b PR |
682 | return err; |
683 | } | |
684 | ||
fc52692c | 685 | static int tiadc_remove(struct platform_device *pdev) |
5e53a69b PR |
686 | { |
687 | struct iio_dev *indio_dev = platform_get_drvdata(pdev); | |
abeccee4 | 688 | struct tiadc_device *adc_dev = iio_priv(indio_dev); |
f438b9da | 689 | struct tiadc_dma *dma = &adc_dev->dma; |
abeccee4 | 690 | u32 step_en; |
5e53a69b | 691 | |
f438b9da M |
692 | if (dma->chan) { |
693 | dma_free_coherent(dma->chan->device->dev, DMA_BUFFER_SIZE, | |
694 | dma->buf, dma->addr); | |
695 | dma_release_channel(dma->chan); | |
696 | } | |
5e53a69b | 697 | iio_device_unregister(indio_dev); |
5e53a69b | 698 | |
abeccee4 PR |
699 | step_en = get_adc_step_mask(adc_dev); |
700 | am335x_tsc_se_clr(adc_dev->mfd_tscadc, step_en); | |
701 | ||
5e53a69b PR |
702 | return 0; |
703 | } | |
704 | ||
0fda2c65 | 705 | static int tiadc_suspend(struct device *dev) |
5e53a69b PR |
706 | { |
707 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
708 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
5e53a69b PR |
709 | unsigned int idle; |
710 | ||
9eea8326 | 711 | idle = tiadc_readl(adc_dev, REG_CTRL); |
c3e36b5d | 712 | idle &= ~(CNTRLREG_SSENB); |
9cac0a02 | 713 | tiadc_writel(adc_dev, REG_CTRL, idle | CNTRLREG_POWERDOWN); |
5e53a69b PR |
714 | |
715 | return 0; | |
716 | } | |
717 | ||
0fda2c65 | 718 | static int tiadc_resume(struct device *dev) |
5e53a69b PR |
719 | { |
720 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
721 | struct tiadc_device *adc_dev = iio_priv(indio_dev); | |
722 | unsigned int restore; | |
723 | ||
724 | /* Make sure ADC is powered up */ | |
725 | restore = tiadc_readl(adc_dev, REG_CTRL); | |
9cac0a02 | 726 | restore &= ~CNTRLREG_POWERDOWN; |
5e53a69b PR |
727 | tiadc_writel(adc_dev, REG_CTRL, restore); |
728 | ||
ca9a5638 | 729 | tiadc_step_config(indio_dev); |
7ca6740c | 730 | am335x_tsc_se_set_cache(adc_dev->mfd_tscadc, |
9cac0a02 | 731 | adc_dev->buffer_en_ch_steps); |
5e53a69b PR |
732 | return 0; |
733 | } | |
734 | ||
0fda2c65 | 735 | static DEFINE_SIMPLE_DEV_PM_OPS(tiadc_pm_ops, tiadc_suspend, tiadc_resume); |
5e53a69b | 736 | |
6f39ac4e PR |
737 | static const struct of_device_id ti_adc_dt_ids[] = { |
738 | { .compatible = "ti,am3359-adc", }, | |
e7c8a5fe | 739 | { .compatible = "ti,am4372-adc", }, |
6f39ac4e PR |
740 | { } |
741 | }; | |
742 | MODULE_DEVICE_TABLE(of, ti_adc_dt_ids); | |
743 | ||
5e53a69b PR |
744 | static struct platform_driver tiadc_driver = { |
745 | .driver = { | |
9f99928f | 746 | .name = "TI-am335x-adc", |
0fda2c65 | 747 | .pm = pm_sleep_ptr(&tiadc_pm_ops), |
de06b344 | 748 | .of_match_table = ti_adc_dt_ids, |
5e53a69b PR |
749 | }, |
750 | .probe = tiadc_probe, | |
fc52692c | 751 | .remove = tiadc_remove, |
5e53a69b | 752 | }; |
5e53a69b PR |
753 | module_platform_driver(tiadc_driver); |
754 | ||
755 | MODULE_DESCRIPTION("TI ADC controller driver"); | |
756 | MODULE_AUTHOR("Rachna Patil <rachna@ti.com>"); | |
757 | MODULE_LICENSE("GPL"); |