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Merge tag 'io_uring-6.3-2023-04-14' of git://git.kernel.dk/linux
[linux-block.git] / drivers / iio / adc / sc27xx_adc.c
CommitLineData
5df362a6
FL		 1// SPDX-License-Identifier: GPL-2.0
2// Copyright (C) 2018 Spreadtrum Communications Inc.
3
4#include <linux/hwspinlock.h>
5#include <linux/iio/iio.h>
5df362a6 6#include <linux/module.h>
8433aa35 7#include <linux/mutex.h>
8ba0dbfd 8#include <linux/nvmem-consumer.h>
5df362a6
FL		 9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12#include <linux/regmap.h>
fff4a7a8 13#include <linux/regulator/consumer.h>
8ba0dbfd 14#include <linux/slab.h>
5df362a6
FL		 15
16/* PMIC global registers definition */
0ac507bb 17#define SC2730_MODULE_EN 0x1808
e4171388 18#define SC2731_MODULE_EN 0xc08
5df362a6 19#define SC27XX_MODULE_ADC_EN BIT(5)
fff4a7a8 20#define SC2721_ARM_CLK_EN 0xc0c
0ac507bb 21#define SC2730_ARM_CLK_EN 0x180c
e4171388 22#define SC2731_ARM_CLK_EN 0xc10
5df362a6
FL		 23#define SC27XX_CLK_ADC_EN BIT(5)
24#define SC27XX_CLK_ADC_CLK_EN BIT(6)
25
26/* ADC controller registers definition */
27#define SC27XX_ADC_CTL 0x0
28#define SC27XX_ADC_CH_CFG 0x4
29#define SC27XX_ADC_DATA 0x4c
30#define SC27XX_ADC_INT_EN 0x50
31#define SC27XX_ADC_INT_CLR 0x54
32#define SC27XX_ADC_INT_STS 0x58
33#define SC27XX_ADC_INT_RAW 0x5c
34
35/* Bits and mask definition for SC27XX_ADC_CTL register */
36#define SC27XX_ADC_EN BIT(0)
37#define SC27XX_ADC_CHN_RUN BIT(1)
38#define SC27XX_ADC_12BIT_MODE BIT(2)
39#define SC27XX_ADC_RUN_NUM_MASK GENMASK(7, 4)
40#define SC27XX_ADC_RUN_NUM_SHIFT 4
41
42/* Bits and mask definition for SC27XX_ADC_CH_CFG register */
43#define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0)
ad930a75 44#define SC27XX_ADC_SCALE_MASK GENMASK(10, 9)
fff4a7a8 45#define SC2721_ADC_SCALE_MASK BIT(5)
ad930a75 46#define SC27XX_ADC_SCALE_SHIFT 9
fff4a7a8 47#define SC2721_ADC_SCALE_SHIFT 5
5df362a6
FL		 48
49/* Bits definitions for SC27XX_ADC_INT_EN registers */
50#define SC27XX_ADC_IRQ_EN BIT(0)
51
52/* Bits definitions for SC27XX_ADC_INT_CLR registers */
53#define SC27XX_ADC_IRQ_CLR BIT(0)
54
8de877d2
FL		 55/* Bits definitions for SC27XX_ADC_INT_RAW registers */
56#define SC27XX_ADC_IRQ_RAW BIT(0)
57
5df362a6
FL		 58/* Mask definition for SC27XX_ADC_DATA register */
59#define SC27XX_ADC_DATA_MASK GENMASK(11, 0)
60
61/* Timeout (ms) for the trylock of hardware spinlocks */
62#define SC27XX_ADC_HWLOCK_TIMEOUT 5000
63
8de877d2
FL		 64/* Timeout (us) for ADC data conversion according to ADC datasheet */
65#define SC27XX_ADC_RDY_TIMEOUT 1000000
66#define SC27XX_ADC_POLL_RAW_STATUS 500
750ac07e 67
5df362a6
FL		 68/* Maximum ADC channel number */
69#define SC27XX_ADC_CHANNEL_MAX 32
70
71/* ADC voltage ratio definition */
72#define SC27XX_VOLT_RATIO(n, d) \
73 (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d))
74#define SC27XX_RATIO_NUMERATOR_OFFSET 16
75#define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0)
76
fff4a7a8
CG		 77/* ADC specific channel reference voltage 3.5V */
78#define SC27XX_ADC_REFVOL_VDD35 3500000
79
80/* ADC default channel reference voltage is 2.8V */
81#define SC27XX_ADC_REFVOL_VDD28 2800000
82
5df362a6
FL		 83struct sc27xx_adc_data {
84 struct device *dev;
fff4a7a8 85 struct regulator *volref;
5df362a6 86 struct regmap *regmap;
8433aa35
NS		 87 /* lock to protect against multiple access to the device */
88 struct mutex lock;
5df362a6
FL		 89 /*
90 * One hardware spinlock to synchronize between the multiple
91 * subsystems which will access the unique ADC controller.
92 */
93 struct hwspinlock *hwlock;
5df362a6
FL		 94 int channel_scale[SC27XX_ADC_CHANNEL_MAX];
95 u32 base;
5df362a6 96 int irq;
e4171388
CG		 97 const struct sc27xx_adc_variant_data *var_data;
98};
99
100/*
101 * Since different PMICs of SC27xx series can have different
102 * address and ratio, we should save ratio config and base
103 * in the device data structure.
104 */
105struct sc27xx_adc_variant_data {
106 u32 module_en;
107 u32 clk_en;
108 u32 scale_shift;
109 u32 scale_mask;
110 const struct sc27xx_adc_linear_graph *bscale_cal;
111 const struct sc27xx_adc_linear_graph *sscale_cal;
112 void (*init_scale)(struct sc27xx_adc_data *data);
113 int (*get_ratio)(int channel, int scale);
fff4a7a8 114 bool set_volref;
5df362a6
FL		 115};
116
117struct sc27xx_adc_linear_graph {
118 int volt0;
119 int adc0;
120 int volt1;
121 int adc1;
122};
123
124/*
125 * According to the datasheet, we can convert one ADC value to one voltage value
126 * through 2 points in the linear graph. If the voltage is less than 1.2v, we
127 * should use the small-scale graph, and if more than 1.2v, we should use the
128 * big-scale graph.
129 */
8ba0dbfd 130static struct sc27xx_adc_linear_graph big_scale_graph = {
5df362a6
FL		 131 4200, 3310,
132 3600, 2832,
133};
134
8ba0dbfd 135static struct sc27xx_adc_linear_graph small_scale_graph = {
5df362a6
FL		 136 1000, 3413,
137 100, 341,
138};
139
5a7a184b
CG		 140static const struct sc27xx_adc_linear_graph sc2731_big_scale_graph_calib = {
141 4200, 850,
142 3600, 728,
8ba0dbfd
BW		 143};
144
5a7a184b
CG		 145static const struct sc27xx_adc_linear_graph sc2731_small_scale_graph_calib = {
146 1000, 838,
147 100, 84,
8ba0dbfd
BW		 148};
149
fff4a7a8
CG		 150static const struct sc27xx_adc_linear_graph big_scale_graph_calib = {
151 4200, 856,
152 3600, 733,
153};
154
155static const struct sc27xx_adc_linear_graph small_scale_graph_calib = {
156 1000, 833,
157 100, 80,
158};
159
8ba0dbfd
BW		 160static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc)
161{
162 return ((calib_data & 0xff) + calib_adc - 128) * 4;
163}
164
aac053d0
CG		 165/* get the adc nvmem cell calibration data */
166static int adc_nvmem_cell_calib_data(struct sc27xx_adc_data *data, const char *cell_name)
167{
168 struct nvmem_cell *cell;
169 void *buf;
170 u32 origin_calib_data = 0;
171 size_t len;
172
173 if (!data)
174 return -EINVAL;
175
176 cell = nvmem_cell_get(data->dev, cell_name);
177 if (IS_ERR(cell))
178 return PTR_ERR(cell);
179
180 buf = nvmem_cell_read(cell, &len);
181 if (IS_ERR(buf)) {
182 nvmem_cell_put(cell);
183 return PTR_ERR(buf);
184 }
185
186 memcpy(&origin_calib_data, buf, min(len, sizeof(u32)));
187
188 kfree(buf);
189 nvmem_cell_put(cell);
190 return origin_calib_data;
191}
192
8ba0dbfd
BW		 193static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
194 bool big_scale)
195{
196 const struct sc27xx_adc_linear_graph *calib_graph;
197 struct sc27xx_adc_linear_graph *graph;
8ba0dbfd
BW		 198 const char *cell_name;
199 u32 calib_data = 0;
8ba0dbfd
BW		 200
201 if (big_scale) {
e4171388 202 calib_graph = data->var_data->bscale_cal;
8ba0dbfd
BW		 203 graph = &big_scale_graph;
204 cell_name = "big_scale_calib";
205 } else {
e4171388 206 calib_graph = data->var_data->sscale_cal;
8ba0dbfd
BW		 207 graph = &small_scale_graph;
208 cell_name = "small_scale_calib";
209 }
210
aac053d0 211 calib_data = adc_nvmem_cell_calib_data(data, cell_name);
8ba0dbfd
BW		 212
213 /* Only need to calibrate the adc values in the linear graph. */
214 graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0);
215 graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8,
216 calib_graph->adc1);
217
8ba0dbfd
BW		 218 return 0;
219}
220
fff4a7a8
CG		 221static int sc2720_adc_get_ratio(int channel, int scale)
222{
223 switch (channel) {
224 case 14:
225 switch (scale) {
226 case 0:
227 return SC27XX_VOLT_RATIO(68, 900);
228 case 1:
229 return SC27XX_VOLT_RATIO(68, 1760);
230 case 2:
231 return SC27XX_VOLT_RATIO(68, 2327);
232 case 3:
233 return SC27XX_VOLT_RATIO(68, 3654);
234 default:
235 return SC27XX_VOLT_RATIO(1, 1);
236 }
237 case 16:
238 switch (scale) {
239 case 0:
240 return SC27XX_VOLT_RATIO(48, 100);
241 case 1:
242 return SC27XX_VOLT_RATIO(480, 1955);
243 case 2:
244 return SC27XX_VOLT_RATIO(480, 2586);
245 case 3:
246 return SC27XX_VOLT_RATIO(48, 406);
247 default:
248 return SC27XX_VOLT_RATIO(1, 1);
249 }
250 case 21:
251 case 22:
252 case 23:
253 switch (scale) {
254 case 0:
255 return SC27XX_VOLT_RATIO(3, 8);
256 case 1:
257 return SC27XX_VOLT_RATIO(375, 1955);
258 case 2:
259 return SC27XX_VOLT_RATIO(375, 2586);
260 case 3:
261 return SC27XX_VOLT_RATIO(300, 3248);
262 default:
263 return SC27XX_VOLT_RATIO(1, 1);
264 }
265 default:
266 switch (scale) {
267 case 0:
268 return SC27XX_VOLT_RATIO(1, 1);
269 case 1:
270 return SC27XX_VOLT_RATIO(1000, 1955);
271 case 2:
272 return SC27XX_VOLT_RATIO(1000, 2586);
273 case 3:
274 return SC27XX_VOLT_RATIO(100, 406);
275 default:
276 return SC27XX_VOLT_RATIO(1, 1);
277 }
278 }
279 return SC27XX_VOLT_RATIO(1, 1);
280}
281
282static int sc2721_adc_get_ratio(int channel, int scale)
283{
284 switch (channel) {
285 case 1:
286 case 2:
287 case 3:
288 case 4:
289 return scale ? SC27XX_VOLT_RATIO(400, 1025) :
290 SC27XX_VOLT_RATIO(1, 1);
291 case 5:
292 return SC27XX_VOLT_RATIO(7, 29);
293 case 7:
294 case 9:
295 return scale ? SC27XX_VOLT_RATIO(100, 125) :
296 SC27XX_VOLT_RATIO(1, 1);
297 case 14:
298 return SC27XX_VOLT_RATIO(68, 900);
299 case 16:
300 return SC27XX_VOLT_RATIO(48, 100);
301 case 19:
302 return SC27XX_VOLT_RATIO(1, 3);
303 default:
304 return SC27XX_VOLT_RATIO(1, 1);
305 }
306 return SC27XX_VOLT_RATIO(1, 1);
307}
308
0ac507bb
CG		 309static int sc2730_adc_get_ratio(int channel, int scale)
310{
311 switch (channel) {
312 case 14:
313 switch (scale) {
314 case 0:
315 return SC27XX_VOLT_RATIO(68, 900);
316 case 1:
317 return SC27XX_VOLT_RATIO(68, 1760);
318 case 2:
319 return SC27XX_VOLT_RATIO(68, 2327);
320 case 3:
321 return SC27XX_VOLT_RATIO(68, 3654);
322 default:
323 return SC27XX_VOLT_RATIO(1, 1);
324 }
325 case 15:
326 switch (scale) {
327 case 0:
328 return SC27XX_VOLT_RATIO(1, 3);
329 case 1:
330 return SC27XX_VOLT_RATIO(1000, 5865);
331 case 2:
332 return SC27XX_VOLT_RATIO(500, 3879);
333 case 3:
334 return SC27XX_VOLT_RATIO(500, 6090);
335 default:
336 return SC27XX_VOLT_RATIO(1, 1);
337 }
338 case 16:
339 switch (scale) {
340 case 0:
341 return SC27XX_VOLT_RATIO(48, 100);
342 case 1:
343 return SC27XX_VOLT_RATIO(480, 1955);
344 case 2:
345 return SC27XX_VOLT_RATIO(480, 2586);
346 case 3:
347 return SC27XX_VOLT_RATIO(48, 406);
348 default:
349 return SC27XX_VOLT_RATIO(1, 1);
350 }
351 case 21:
352 case 22:
353 case 23:
354 switch (scale) {
355 case 0:
356 return SC27XX_VOLT_RATIO(3, 8);
357 case 1:
358 return SC27XX_VOLT_RATIO(375, 1955);
359 case 2:
360 return SC27XX_VOLT_RATIO(375, 2586);
361 case 3:
362 return SC27XX_VOLT_RATIO(300, 3248);
363 default:
364 return SC27XX_VOLT_RATIO(1, 1);
365 }
366 default:
367 switch (scale) {
368 case 0:
369 return SC27XX_VOLT_RATIO(1, 1);
370 case 1:
371 return SC27XX_VOLT_RATIO(1000, 1955);
372 case 2:
373 return SC27XX_VOLT_RATIO(1000, 2586);
374 case 3:
375 return SC27XX_VOLT_RATIO(1000, 4060);
376 default:
377 return SC27XX_VOLT_RATIO(1, 1);
378 }
379 }
380 return SC27XX_VOLT_RATIO(1, 1);
381}
382
e4171388 383static int sc2731_adc_get_ratio(int channel, int scale)
5df362a6
FL		 384{
385 switch (channel) {
386 case 1:
387 case 2:
388 case 3:
389 case 4:
390 return scale ? SC27XX_VOLT_RATIO(400, 1025) :
391 SC27XX_VOLT_RATIO(1, 1);
392 case 5:
393 return SC27XX_VOLT_RATIO(7, 29);
394 case 6:
395 return SC27XX_VOLT_RATIO(375, 9000);
396 case 7:
397 case 8:
398 return scale ? SC27XX_VOLT_RATIO(100, 125) :
399 SC27XX_VOLT_RATIO(1, 1);
400 case 19:
401 return SC27XX_VOLT_RATIO(1, 3);
402 default:
403 return SC27XX_VOLT_RATIO(1, 1);
404 }
405 return SC27XX_VOLT_RATIO(1, 1);
406}
407
e4171388
CG		 408/*
409 * According to the datasheet set specific value on some channel.
410 */
fff4a7a8
CG		 411static void sc2720_adc_scale_init(struct sc27xx_adc_data *data)
412{
413 int i;
414
415 for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) {
416 switch (i) {
417 case 5:
418 data->channel_scale[i] = 3;
419 break;
420 case 7:
421 case 9:
422 data->channel_scale[i] = 2;
423 break;
424 case 13:
425 data->channel_scale[i] = 1;
426 break;
427 case 19:
428 case 30:
429 case 31:
430 data->channel_scale[i] = 3;
431 break;
432 default:
433 data->channel_scale[i] = 0;
434 break;
435 }
436 }
437}
438
0ac507bb
CG		 439static void sc2730_adc_scale_init(struct sc27xx_adc_data *data)
440{
441 int i;
442
443 for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) {
444 switch (i) {
445 case 5:
446 case 10:
447 case 19:
448 case 30:
449 case 31:
450 data->channel_scale[i] = 3;
451 break;
452 case 7:
453 case 9:
454 data->channel_scale[i] = 2;
455 break;
456 case 13:
457 data->channel_scale[i] = 1;
458 break;
459 default:
460 data->channel_scale[i] = 0;
461 break;
462 }
463 }
464}
465
e4171388
CG		 466static void sc2731_adc_scale_init(struct sc27xx_adc_data *data)
467{
468 int i;
469 /*
470 * In the current software design, SC2731 support 2 scales,
471 * channels 5 uses big scale, others use smale.
472 */
473 for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) {
474 switch (i) {
475 case 5:
476 data->channel_scale[i] = 1;
477 break;
478 default:
479 data->channel_scale[i] = 0;
480 break;
481 }
482 }
483}
484
5df362a6
FL		 485static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel,
486 int scale, int *val)
487{
fff4a7a8 488 int ret, ret_volref;
8de877d2 489 u32 tmp, value, status;
5df362a6
FL		 490
491 ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT);
492 if (ret) {
493 dev_err(data->dev, "timeout to get the hwspinlock\n");
494 return ret;
495 }
496
fff4a7a8
CG		 497 /*
498 * According to the sc2721 chip data sheet, the reference voltage of
499 * specific channel 30 and channel 31 in ADC module needs to be set from
500 * the default 2.8v to 3.5v.
501 */
502 if ((data->var_data->set_volref) && (channel == 30 || channel == 31)) {
503 ret = regulator_set_voltage(data->volref,
504 SC27XX_ADC_REFVOL_VDD35,
505 SC27XX_ADC_REFVOL_VDD35);
506 if (ret) {
507 dev_err(data->dev, "failed to set the volref 3.5v\n");
508 goto unlock_adc;
509 }
510 }
511
5df362a6
FL		 512 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
513 SC27XX_ADC_EN, SC27XX_ADC_EN);
514 if (ret)
fff4a7a8 515 goto regulator_restore;
5df362a6 516
8de877d2
FL		 517 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
518 SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR);
519 if (ret)
520 goto disable_adc;
521
5df362a6 522 /* Configure the channel id and scale */
e4171388 523 tmp = (scale << data->var_data->scale_shift) & data->var_data->scale_mask;
5df362a6
FL		 524 tmp |= channel & SC27XX_ADC_CHN_ID_MASK;
525 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG,
e4171388
CG		 526 SC27XX_ADC_CHN_ID_MASK |
527 data->var_data->scale_mask,
5df362a6
FL		 528 tmp);
529 if (ret)
530 goto disable_adc;
531
532 /* Select 12bit conversion mode, and only sample 1 time */
533 tmp = SC27XX_ADC_12BIT_MODE;
534 tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK;
535 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
536 SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE,
537 tmp);
538 if (ret)
539 goto disable_adc;
540
541 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
542 SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN);
543 if (ret)
544 goto disable_adc;
545
8de877d2
FL		 546 ret = regmap_read_poll_timeout(data->regmap,
547 data->base + SC27XX_ADC_INT_RAW,
548 status, (status & SC27XX_ADC_IRQ_RAW),
549 SC27XX_ADC_POLL_RAW_STATUS,
550 SC27XX_ADC_RDY_TIMEOUT);
551 if (ret) {
552 dev_err(data->dev, "read adc timeout, status = 0x%x\n", status);
553 goto disable_adc;
750ac07e 554 }
5df362a6 555
8de877d2
FL		 556 ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, &value);
557 if (ret)
558 goto disable_adc;
559
560 value &= SC27XX_ADC_DATA_MASK;
561
5df362a6
FL		 562disable_adc:
563 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
564 SC27XX_ADC_EN, 0);
fff4a7a8
CG		 565regulator_restore:
566 if ((data->var_data->set_volref) && (channel == 30 || channel == 31)) {
567 ret_volref = regulator_set_voltage(data->volref,
568 SC27XX_ADC_REFVOL_VDD28,
569 SC27XX_ADC_REFVOL_VDD28);
570 if (ret_volref) {
571 dev_err(data->dev, "failed to set the volref 2.8v,ret_volref = 0x%x\n",
572 ret_volref);
573 ret = ret || ret_volref;
574 }
575 }
5df362a6
FL		 576unlock_adc:
577 hwspin_unlock_raw(data->hwlock);
578
579 if (!ret)
8de877d2 580 *val = value;
5df362a6
FL		 581
582 return ret;
583}
584
5a3ec28a
AS		 585static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, int channel, int scale,
586 struct u32_fract *fract)
5df362a6 587{
e4171388 588 u32 ratio;
5df362a6 589
e4171388 590 ratio = data->var_data->get_ratio(channel, scale);
5a3ec28a
AS		 591 fract->numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET;
592 fract->denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK;
5df362a6
FL		 593}
594
aac053d0 595static int adc_to_volt(struct sc27xx_adc_linear_graph *graph,
5df362a6
FL		 596 int raw_adc)
597{
598 int tmp;
599
600 tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1);
601 tmp /= (graph->adc0 - graph->adc1);
602 tmp += graph->volt1;
603
aac053d0
CG		 604 return tmp;
605}
606
607static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph,
608 int raw_adc)
609{
610 int tmp;
611
612 tmp = adc_to_volt(graph, raw_adc);
613
5df362a6
FL		 614 return tmp < 0 ? 0 : tmp;
615}
616
617static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel,
618 int scale, int raw_adc)
619{
5a3ec28a 620 struct u32_fract fract;
5df362a6
FL		 621 u32 volt;
622
623 /*
624 * Convert ADC values to voltage values according to the linear graph,
625 * and channel 5 and channel 1 has been calibrated, so we can just
626 * return the voltage values calculated by the linear graph. But other
627 * channels need be calculated to the real voltage values with the
628 * voltage ratio.
629 */
630 switch (channel) {
631 case 5:
632 return sc27xx_adc_to_volt(&big_scale_graph, raw_adc);
633
634 case 1:
635 return sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
636
637 default:
638 volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
639 break;
640 }
641
5a3ec28a 642 sc27xx_adc_volt_ratio(data, channel, scale, &fract);
5df362a6 643
5a3ec28a 644 return DIV_ROUND_CLOSEST(volt * fract.denominator, fract.numerator);
5df362a6
FL		 645}
646
647static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data,
648 int channel, int scale, int *val)
649{
650 int ret, raw_adc;
651
652 ret = sc27xx_adc_read(data, channel, scale, &raw_adc);
653 if (ret)
654 return ret;
655
656 *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc);
657 return 0;
658}
659
660static int sc27xx_adc_read_raw(struct iio_dev *indio_dev,
661 struct iio_chan_spec const *chan,
662 int *val, int *val2, long mask)
663{
664 struct sc27xx_adc_data *data = iio_priv(indio_dev);
665 int scale = data->channel_scale[chan->channel];
666 int ret, tmp;
667
668 switch (mask) {
fd2f53eb 669 case IIO_CHAN_INFO_RAW:
8433aa35 670 mutex_lock(&data->lock);
fd2f53eb 671 ret = sc27xx_adc_read(data, chan->channel, scale, &tmp);
8433aa35 672 mutex_unlock(&data->lock);
fd2f53eb
BW		 673
674 if (ret)
675 return ret;
676
677 *val = tmp;
678 return IIO_VAL_INT;
679
5df362a6 680 case IIO_CHAN_INFO_PROCESSED:
8433aa35 681 mutex_lock(&data->lock);
5df362a6
FL		 682 ret = sc27xx_adc_read_processed(data, chan->channel, scale,
683 &tmp);
8433aa35 684 mutex_unlock(&data->lock);
5df362a6
FL		 685
686 if (ret)
687 return ret;
688
689 *val = tmp;
690 return IIO_VAL_INT;
691
692 case IIO_CHAN_INFO_SCALE:
693 *val = scale;
694 return IIO_VAL_INT;
695
696 default:
697 return -EINVAL;
698 }
699}
700
701static int sc27xx_adc_write_raw(struct iio_dev *indio_dev,
702 struct iio_chan_spec const *chan,
703 int val, int val2, long mask)
704{
705 struct sc27xx_adc_data *data = iio_priv(indio_dev);
706
707 switch (mask) {
708 case IIO_CHAN_INFO_SCALE:
709 data->channel_scale[chan->channel] = val;
710 return IIO_VAL_INT;
711
712 default:
713 return -EINVAL;
714 }
715}
716
717static const struct iio_info sc27xx_info = {
718 .read_raw = &sc27xx_adc_read_raw,
719 .write_raw = &sc27xx_adc_write_raw,
720};
721
fd2f53eb 722#define SC27XX_ADC_CHANNEL(index, mask) { \
5df362a6
FL		 723 .type = IIO_VOLTAGE, \
724 .channel = index, \
fd2f53eb 725 .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \
5df362a6
FL		 726 .datasheet_name = "CH##index", \
727 .indexed = 1, \
728}
729
730static const struct iio_chan_spec sc27xx_channels[] = {
fd2f53eb
BW		 731 SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)),
732 SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)),
733 SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)),
734 SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)),
735 SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)),
736 SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)),
737 SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)),
738 SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)),
739 SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)),
740 SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)),
741 SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)),
742 SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)),
743 SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)),
744 SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)),
745 SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)),
746 SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)),
747 SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)),
748 SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)),
749 SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)),
750 SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)),
751 SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)),
752 SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)),
753 SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)),
754 SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)),
755 SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)),
756 SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)),
757 SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)),
758 SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)),
759 SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)),
760 SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)),
761 SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)),
762 SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)),
5df362a6
FL		 763};
764
765static int sc27xx_adc_enable(struct sc27xx_adc_data *data)
766{
767 int ret;
768
e4171388 769 ret = regmap_update_bits(data->regmap, data->var_data->module_en,
5df362a6
FL		 770 SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN);
771 if (ret)
772 return ret;
773
774 /* Enable ADC work clock and controller clock */
e4171388 775 ret = regmap_update_bits(data->regmap, data->var_data->clk_en,
5df362a6
FL		 776 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN,
777 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
778 if (ret)
779 goto disable_adc;
780
8ba0dbfd
BW		 781 /* ADC channel scales' calibration from nvmem device */
782 ret = sc27xx_adc_scale_calibration(data, true);
783 if (ret)
784 goto disable_clk;
785
786 ret = sc27xx_adc_scale_calibration(data, false);
787 if (ret)
788 goto disable_clk;
789
5df362a6
FL		 790 return 0;
791
792disable_clk:
e4171388 793 regmap_update_bits(data->regmap, data->var_data->clk_en,
5df362a6
FL		 794 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
795disable_adc:
e4171388 796 regmap_update_bits(data->regmap, data->var_data->module_en,
5df362a6
FL		 797 SC27XX_MODULE_ADC_EN, 0);
798
799 return ret;
800}
801
802static void sc27xx_adc_disable(void *_data)
803{
804 struct sc27xx_adc_data *data = _data;
805
5df362a6 806 /* Disable ADC work clock and controller clock */
e4171388 807 regmap_update_bits(data->regmap, data->var_data->clk_en,
5df362a6
FL		 808 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
809
e4171388 810 regmap_update_bits(data->regmap, data->var_data->module_en,
5df362a6
FL		 811 SC27XX_MODULE_ADC_EN, 0);
812}
813
e4171388
CG		 814static const struct sc27xx_adc_variant_data sc2731_data = {
815 .module_en = SC2731_MODULE_EN,
816 .clk_en = SC2731_ARM_CLK_EN,
817 .scale_shift = SC27XX_ADC_SCALE_SHIFT,
818 .scale_mask = SC27XX_ADC_SCALE_MASK,
819 .bscale_cal = &sc2731_big_scale_graph_calib,
820 .sscale_cal = &sc2731_small_scale_graph_calib,
821 .init_scale = sc2731_adc_scale_init,
822 .get_ratio = sc2731_adc_get_ratio,
fff4a7a8
CG		 823 .set_volref = false,
824};
825
0ac507bb
CG		 826static const struct sc27xx_adc_variant_data sc2730_data = {
827 .module_en = SC2730_MODULE_EN,
828 .clk_en = SC2730_ARM_CLK_EN,
829 .scale_shift = SC27XX_ADC_SCALE_SHIFT,
830 .scale_mask = SC27XX_ADC_SCALE_MASK,
831 .bscale_cal = &big_scale_graph_calib,
832 .sscale_cal = &small_scale_graph_calib,
833 .init_scale = sc2730_adc_scale_init,
834 .get_ratio = sc2730_adc_get_ratio,
835 .set_volref = false,
836};
837
fff4a7a8
CG		 838static const struct sc27xx_adc_variant_data sc2721_data = {
839 .module_en = SC2731_MODULE_EN,
840 .clk_en = SC2721_ARM_CLK_EN,
841 .scale_shift = SC2721_ADC_SCALE_SHIFT,
842 .scale_mask = SC2721_ADC_SCALE_MASK,
843 .bscale_cal = &sc2731_big_scale_graph_calib,
844 .sscale_cal = &sc2731_small_scale_graph_calib,
845 .init_scale = sc2731_adc_scale_init,
846 .get_ratio = sc2721_adc_get_ratio,
847 .set_volref = true,
848};
849
850static const struct sc27xx_adc_variant_data sc2720_data = {
851 .module_en = SC2731_MODULE_EN,
852 .clk_en = SC2721_ARM_CLK_EN,
853 .scale_shift = SC27XX_ADC_SCALE_SHIFT,
854 .scale_mask = SC27XX_ADC_SCALE_MASK,
855 .bscale_cal = &big_scale_graph_calib,
856 .sscale_cal = &small_scale_graph_calib,
857 .init_scale = sc2720_adc_scale_init,
858 .get_ratio = sc2720_adc_get_ratio,
859 .set_volref = false,
e4171388
CG		 860};
861
5df362a6
FL		 862static int sc27xx_adc_probe(struct platform_device *pdev)
863{
a0b4ddda
FH		 864 struct device *dev = &pdev->dev;
865 struct device_node *np = dev->of_node;
5df362a6 866 struct sc27xx_adc_data *sc27xx_data;
e4171388 867 const struct sc27xx_adc_variant_data *pdata;
5df362a6
FL		 868 struct iio_dev *indio_dev;
869 int ret;
870
e4171388
CG		 871 pdata = of_device_get_match_data(dev);
872 if (!pdata) {
873 dev_err(dev, "No matching driver data found\n");
874 return -EINVAL;
875 }
876
a0b4ddda 877 indio_dev = devm_iio_device_alloc(dev, sizeof(*sc27xx_data));
5df362a6
FL		 878 if (!indio_dev)
879 return -ENOMEM;
880
881 sc27xx_data = iio_priv(indio_dev);
882
a0b4ddda 883 sc27xx_data->regmap = dev_get_regmap(dev->parent, NULL);
5df362a6 884 if (!sc27xx_data->regmap) {
a0b4ddda 885 dev_err(dev, "failed to get ADC regmap\n");
5df362a6
FL		 886 return -ENODEV;
887 }
888
889 ret = of_property_read_u32(np, "reg", &sc27xx_data->base);
890 if (ret) {
a0b4ddda 891 dev_err(dev, "failed to get ADC base address\n");
5df362a6
FL		 892 return ret;
893 }
894
895 sc27xx_data->irq = platform_get_irq(pdev, 0);
7c279229 896 if (sc27xx_data->irq < 0)
5df362a6 897 return sc27xx_data->irq;
5df362a6
FL		 898
899 ret = of_hwspin_lock_get_id(np, 0);
900 if (ret < 0) {
a0b4ddda 901 dev_err(dev, "failed to get hwspinlock id\n");
5df362a6
FL		 902 return ret;
903 }
904
420119fc 905 sc27xx_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
5df362a6 906 if (!sc27xx_data->hwlock) {
a0b4ddda 907 dev_err(dev, "failed to request hwspinlock\n");
5df362a6
FL		 908 return -ENXIO;
909 }
910
a0b4ddda 911 sc27xx_data->dev = dev;
fff4a7a8
CG		 912 if (pdata->set_volref) {
913 sc27xx_data->volref = devm_regulator_get(dev, "vref");
914 if (IS_ERR(sc27xx_data->volref)) {
915 ret = PTR_ERR(sc27xx_data->volref);
916 return dev_err_probe(dev, ret, "failed to get ADC volref\n");
917 }
918 }
919
e4171388
CG		 920 sc27xx_data->var_data = pdata;
921 sc27xx_data->var_data->init_scale(sc27xx_data);
5df362a6
FL		 922
923 ret = sc27xx_adc_enable(sc27xx_data);
924 if (ret) {
a0b4ddda 925 dev_err(dev, "failed to enable ADC module\n");
5df362a6
FL		 926 return ret;
927 }
928
46916ded 929 ret = devm_add_action_or_reset(dev, sc27xx_adc_disable, sc27xx_data);
5df362a6 930 if (ret) {
a0b4ddda 931 dev_err(dev, "failed to add ADC disable action\n");
5df362a6
FL		 932 return ret;
933 }
934
a0b4ddda 935 indio_dev->name = dev_name(dev);
5df362a6
FL		 936 indio_dev->modes = INDIO_DIRECT_MODE;
937 indio_dev->info = &sc27xx_info;
938 indio_dev->channels = sc27xx_channels;
939 indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels);
8433aa35
NS		 940
941 mutex_init(&sc27xx_data->lock);
942
a0b4ddda 943 ret = devm_iio_device_register(dev, indio_dev);
5df362a6 944 if (ret)
a0b4ddda 945 dev_err(dev, "could not register iio (ADC)");
5df362a6
FL		 946
947 return ret;
948}
949
950static const struct of_device_id sc27xx_adc_of_match[] = {
e4171388 951 { .compatible = "sprd,sc2731-adc", .data = &sc2731_data},
0ac507bb 952 { .compatible = "sprd,sc2730-adc", .data = &sc2730_data},
fff4a7a8
CG		 953 { .compatible = "sprd,sc2721-adc", .data = &sc2721_data},
954 { .compatible = "sprd,sc2720-adc", .data = &sc2720_data},
5df362a6
FL		 955 { }
956};
f5abfa40 957MODULE_DEVICE_TABLE(of, sc27xx_adc_of_match);
5df362a6
FL		 958
959static struct platform_driver sc27xx_adc_driver = {
960 .probe = sc27xx_adc_probe,
961 .driver = {
962 .name = "sc27xx-adc",
963 .of_match_table = sc27xx_adc_of_match,
964 },
965};
966
967module_platform_driver(sc27xx_adc_driver);
968
969MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
970MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver");
971MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)