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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
07914c84 | 2 | /* |
505abf99 | 3 | * mcp3422.c - driver for the Microchip mcp3421/2/3/4/5/6/7/8 chip family |
07914c84 AC |
4 | * |
5 | * Copyright (C) 2013, Angelo Compagnucci | |
6 | * Author: Angelo Compagnucci <angelo.compagnucci@gmail.com> | |
7 | * | |
8 | * Datasheet: http://ww1.microchip.com/downloads/en/devicedoc/22088b.pdf | |
2816ac64 | 9 | * http://ww1.microchip.com/downloads/en/DeviceDoc/22226a.pdf |
505abf99 | 10 | * http://ww1.microchip.com/downloads/en/DeviceDoc/22072b.pdf |
07914c84 AC |
11 | * |
12 | * This driver exports the value of analog input voltage to sysfs, the | |
13 | * voltage unit is nV. | |
07914c84 AC |
14 | */ |
15 | ||
16 | #include <linux/err.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/sysfs.h> | |
de36d817 | 21 | #include <linux/of.h> |
07914c84 AC |
22 | |
23 | #include <linux/iio/iio.h> | |
24 | #include <linux/iio/sysfs.h> | |
25 | ||
26 | /* Masks */ | |
27 | #define MCP3422_CHANNEL_MASK 0x60 | |
28 | #define MCP3422_PGA_MASK 0x03 | |
29 | #define MCP3422_SRATE_MASK 0x0C | |
30 | #define MCP3422_SRATE_240 0x0 | |
31 | #define MCP3422_SRATE_60 0x1 | |
32 | #define MCP3422_SRATE_15 0x2 | |
33 | #define MCP3422_SRATE_3 0x3 | |
34 | #define MCP3422_PGA_1 0 | |
35 | #define MCP3422_PGA_2 1 | |
36 | #define MCP3422_PGA_4 2 | |
37 | #define MCP3422_PGA_8 3 | |
38 | #define MCP3422_CONT_SAMPLING 0x10 | |
39 | ||
40 | #define MCP3422_CHANNEL(config) (((config) & MCP3422_CHANNEL_MASK) >> 5) | |
41 | #define MCP3422_PGA(config) ((config) & MCP3422_PGA_MASK) | |
42 | #define MCP3422_SAMPLE_RATE(config) (((config) & MCP3422_SRATE_MASK) >> 2) | |
43 | ||
44 | #define MCP3422_CHANNEL_VALUE(value) (((value) << 5) & MCP3422_CHANNEL_MASK) | |
45 | #define MCP3422_PGA_VALUE(value) ((value) & MCP3422_PGA_MASK) | |
46 | #define MCP3422_SAMPLE_RATE_VALUE(value) ((value << 2) & MCP3422_SRATE_MASK) | |
47 | ||
48 | #define MCP3422_CHAN(_index) \ | |
49 | { \ | |
50 | .type = IIO_VOLTAGE, \ | |
51 | .indexed = 1, \ | |
52 | .channel = _index, \ | |
53 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ | |
54 | | BIT(IIO_CHAN_INFO_SCALE), \ | |
55 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ | |
56 | } | |
57 | ||
07914c84 | 58 | static const int mcp3422_scales[4][4] = { |
9e128ced | 59 | { 1000000, 500000, 250000, 125000 }, |
038a8b34 SS |
60 | { 250000, 125000, 62500, 31250 }, |
61 | { 62500, 31250, 15625, 7812 }, | |
62 | { 15625, 7812, 3906, 1953 } }; | |
07914c84 AC |
63 | |
64 | /* Constant msleep times for data acquisitions */ | |
65 | static const int mcp3422_read_times[4] = { | |
66 | [MCP3422_SRATE_240] = 1000 / 240, | |
67 | [MCP3422_SRATE_60] = 1000 / 60, | |
68 | [MCP3422_SRATE_15] = 1000 / 15, | |
69 | [MCP3422_SRATE_3] = 1000 / 3 }; | |
70 | ||
71 | /* sample rates to integer conversion table */ | |
72 | static const int mcp3422_sample_rates[4] = { | |
73 | [MCP3422_SRATE_240] = 240, | |
74 | [MCP3422_SRATE_60] = 60, | |
75 | [MCP3422_SRATE_15] = 15, | |
76 | [MCP3422_SRATE_3] = 3 }; | |
77 | ||
78 | /* sample rates to sign extension table */ | |
79 | static const int mcp3422_sign_extend[4] = { | |
a5a3e431 PM |
80 | [MCP3422_SRATE_240] = 11, |
81 | [MCP3422_SRATE_60] = 13, | |
82 | [MCP3422_SRATE_15] = 15, | |
83 | [MCP3422_SRATE_3] = 17 }; | |
07914c84 AC |
84 | |
85 | /* Client data (each client gets its own) */ | |
86 | struct mcp3422 { | |
87 | struct i2c_client *i2c; | |
2816ac64 | 88 | u8 id; |
07914c84 AC |
89 | u8 config; |
90 | u8 pga[4]; | |
91 | struct mutex lock; | |
92 | }; | |
93 | ||
94 | static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig) | |
95 | { | |
96 | int ret; | |
97 | ||
98 | mutex_lock(&adc->lock); | |
99 | ||
100 | ret = i2c_master_send(adc->i2c, &newconfig, 1); | |
101 | if (ret > 0) { | |
102 | adc->config = newconfig; | |
103 | ret = 0; | |
104 | } | |
105 | ||
106 | mutex_unlock(&adc->lock); | |
107 | ||
108 | return ret; | |
109 | } | |
110 | ||
111 | static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config) | |
112 | { | |
113 | int ret = 0; | |
114 | u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config); | |
115 | u8 buf[4] = {0, 0, 0, 0}; | |
116 | u32 temp; | |
117 | ||
118 | if (sample_rate == MCP3422_SRATE_3) { | |
119 | ret = i2c_master_recv(adc->i2c, buf, 4); | |
120 | temp = buf[0] << 16 | buf[1] << 8 | buf[2]; | |
121 | *config = buf[3]; | |
122 | } else { | |
123 | ret = i2c_master_recv(adc->i2c, buf, 3); | |
124 | temp = buf[0] << 8 | buf[1]; | |
125 | *config = buf[2]; | |
126 | } | |
127 | ||
128 | *value = sign_extend32(temp, mcp3422_sign_extend[sample_rate]); | |
129 | ||
130 | return ret; | |
131 | } | |
132 | ||
133 | static int mcp3422_read_channel(struct mcp3422 *adc, | |
134 | struct iio_chan_spec const *channel, int *value) | |
135 | { | |
136 | int ret; | |
137 | u8 config; | |
138 | u8 req_channel = channel->channel; | |
139 | ||
140 | if (req_channel != MCP3422_CHANNEL(adc->config)) { | |
141 | config = adc->config; | |
142 | config &= ~MCP3422_CHANNEL_MASK; | |
143 | config |= MCP3422_CHANNEL_VALUE(req_channel); | |
144 | config &= ~MCP3422_PGA_MASK; | |
145 | config |= MCP3422_PGA_VALUE(adc->pga[req_channel]); | |
146 | ret = mcp3422_update_config(adc, config); | |
147 | if (ret < 0) | |
148 | return ret; | |
149 | msleep(mcp3422_read_times[MCP3422_SAMPLE_RATE(adc->config)]); | |
150 | } | |
151 | ||
152 | return mcp3422_read(adc, value, &config); | |
153 | } | |
154 | ||
155 | static int mcp3422_read_raw(struct iio_dev *iio, | |
156 | struct iio_chan_spec const *channel, int *val1, | |
157 | int *val2, long mask) | |
158 | { | |
159 | struct mcp3422 *adc = iio_priv(iio); | |
160 | int err; | |
161 | ||
162 | u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config); | |
163 | u8 pga = MCP3422_PGA(adc->config); | |
164 | ||
165 | switch (mask) { | |
166 | case IIO_CHAN_INFO_RAW: | |
167 | err = mcp3422_read_channel(adc, channel, val1); | |
168 | if (err < 0) | |
169 | return -EINVAL; | |
170 | return IIO_VAL_INT; | |
171 | ||
172 | case IIO_CHAN_INFO_SCALE: | |
173 | ||
174 | *val1 = 0; | |
175 | *val2 = mcp3422_scales[sample_rate][pga]; | |
176 | return IIO_VAL_INT_PLUS_NANO; | |
177 | ||
178 | case IIO_CHAN_INFO_SAMP_FREQ: | |
179 | *val1 = mcp3422_sample_rates[MCP3422_SAMPLE_RATE(adc->config)]; | |
180 | return IIO_VAL_INT; | |
181 | ||
182 | default: | |
183 | break; | |
184 | } | |
185 | ||
186 | return -EINVAL; | |
187 | } | |
188 | ||
189 | static int mcp3422_write_raw(struct iio_dev *iio, | |
190 | struct iio_chan_spec const *channel, int val1, | |
191 | int val2, long mask) | |
192 | { | |
193 | struct mcp3422 *adc = iio_priv(iio); | |
194 | u8 temp; | |
195 | u8 config = adc->config; | |
196 | u8 req_channel = channel->channel; | |
197 | u8 sample_rate = MCP3422_SAMPLE_RATE(config); | |
198 | u8 i; | |
199 | ||
200 | switch (mask) { | |
201 | case IIO_CHAN_INFO_SCALE: | |
202 | if (val1 != 0) | |
203 | return -EINVAL; | |
204 | ||
205 | for (i = 0; i < ARRAY_SIZE(mcp3422_scales[0]); i++) { | |
206 | if (val2 == mcp3422_scales[sample_rate][i]) { | |
207 | adc->pga[req_channel] = i; | |
208 | ||
209 | config &= ~MCP3422_CHANNEL_MASK; | |
210 | config |= MCP3422_CHANNEL_VALUE(req_channel); | |
211 | config &= ~MCP3422_PGA_MASK; | |
212 | config |= MCP3422_PGA_VALUE(adc->pga[req_channel]); | |
213 | ||
214 | return mcp3422_update_config(adc, config); | |
215 | } | |
216 | } | |
217 | return -EINVAL; | |
218 | ||
219 | case IIO_CHAN_INFO_SAMP_FREQ: | |
220 | switch (val1) { | |
221 | case 240: | |
222 | temp = MCP3422_SRATE_240; | |
223 | break; | |
224 | case 60: | |
225 | temp = MCP3422_SRATE_60; | |
226 | break; | |
227 | case 15: | |
228 | temp = MCP3422_SRATE_15; | |
229 | break; | |
230 | case 3: | |
2816ac64 AC |
231 | if (adc->id > 4) |
232 | return -EINVAL; | |
07914c84 AC |
233 | temp = MCP3422_SRATE_3; |
234 | break; | |
235 | default: | |
236 | return -EINVAL; | |
237 | } | |
238 | ||
239 | config &= ~MCP3422_CHANNEL_MASK; | |
240 | config |= MCP3422_CHANNEL_VALUE(req_channel); | |
241 | config &= ~MCP3422_SRATE_MASK; | |
242 | config |= MCP3422_SAMPLE_RATE_VALUE(temp); | |
243 | ||
244 | return mcp3422_update_config(adc, config); | |
245 | ||
246 | default: | |
247 | break; | |
248 | } | |
249 | ||
250 | return -EINVAL; | |
251 | } | |
252 | ||
253 | static int mcp3422_write_raw_get_fmt(struct iio_dev *indio_dev, | |
254 | struct iio_chan_spec const *chan, long mask) | |
255 | { | |
256 | switch (mask) { | |
257 | case IIO_CHAN_INFO_SCALE: | |
258 | return IIO_VAL_INT_PLUS_NANO; | |
259 | case IIO_CHAN_INFO_SAMP_FREQ: | |
260 | return IIO_VAL_INT_PLUS_MICRO; | |
261 | default: | |
262 | return -EINVAL; | |
263 | } | |
264 | } | |
265 | ||
2816ac64 AC |
266 | static ssize_t mcp3422_show_samp_freqs(struct device *dev, |
267 | struct device_attribute *attr, char *buf) | |
268 | { | |
269 | struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev)); | |
270 | ||
271 | if (adc->id > 4) | |
272 | return sprintf(buf, "240 60 15\n"); | |
273 | ||
274 | return sprintf(buf, "240 60 15 3\n"); | |
275 | } | |
276 | ||
07914c84 AC |
277 | static ssize_t mcp3422_show_scales(struct device *dev, |
278 | struct device_attribute *attr, char *buf) | |
279 | { | |
280 | struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev)); | |
281 | u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config); | |
282 | ||
283 | return sprintf(buf, "0.%09u 0.%09u 0.%09u 0.%09u\n", | |
284 | mcp3422_scales[sample_rate][0], | |
285 | mcp3422_scales[sample_rate][1], | |
286 | mcp3422_scales[sample_rate][2], | |
287 | mcp3422_scales[sample_rate][3]); | |
288 | } | |
289 | ||
2816ac64 AC |
290 | static IIO_DEVICE_ATTR(sampling_frequency_available, S_IRUGO, |
291 | mcp3422_show_samp_freqs, NULL, 0); | |
07914c84 AC |
292 | static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, |
293 | mcp3422_show_scales, NULL, 0); | |
294 | ||
295 | static struct attribute *mcp3422_attributes[] = { | |
2816ac64 | 296 | &iio_dev_attr_sampling_frequency_available.dev_attr.attr, |
07914c84 AC |
297 | &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, |
298 | NULL, | |
299 | }; | |
300 | ||
301 | static const struct attribute_group mcp3422_attribute_group = { | |
302 | .attrs = mcp3422_attributes, | |
303 | }; | |
304 | ||
78f16dbd SH |
305 | static const struct iio_chan_spec mcp3421_channels[] = { |
306 | MCP3422_CHAN(0), | |
307 | }; | |
308 | ||
07914c84 AC |
309 | static const struct iio_chan_spec mcp3422_channels[] = { |
310 | MCP3422_CHAN(0), | |
311 | MCP3422_CHAN(1), | |
312 | }; | |
313 | ||
314 | static const struct iio_chan_spec mcp3424_channels[] = { | |
315 | MCP3422_CHAN(0), | |
316 | MCP3422_CHAN(1), | |
317 | MCP3422_CHAN(2), | |
318 | MCP3422_CHAN(3), | |
319 | }; | |
320 | ||
321 | static const struct iio_info mcp3422_info = { | |
322 | .read_raw = mcp3422_read_raw, | |
323 | .write_raw = mcp3422_write_raw, | |
324 | .write_raw_get_fmt = mcp3422_write_raw_get_fmt, | |
325 | .attrs = &mcp3422_attribute_group, | |
07914c84 AC |
326 | }; |
327 | ||
328 | static int mcp3422_probe(struct i2c_client *client, | |
329 | const struct i2c_device_id *id) | |
330 | { | |
331 | struct iio_dev *indio_dev; | |
332 | struct mcp3422 *adc; | |
333 | int err; | |
334 | u8 config; | |
335 | ||
336 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) | |
f8d9d3b4 | 337 | return -EOPNOTSUPP; |
07914c84 AC |
338 | |
339 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*adc)); | |
340 | if (!indio_dev) | |
341 | return -ENOMEM; | |
342 | ||
343 | adc = iio_priv(indio_dev); | |
344 | adc->i2c = client; | |
2816ac64 | 345 | adc->id = (u8)(id->driver_data); |
07914c84 AC |
346 | |
347 | mutex_init(&adc->lock); | |
348 | ||
349 | indio_dev->dev.parent = &client->dev; | |
b541eaff | 350 | indio_dev->dev.of_node = client->dev.of_node; |
07914c84 AC |
351 | indio_dev->name = dev_name(&client->dev); |
352 | indio_dev->modes = INDIO_DIRECT_MODE; | |
353 | indio_dev->info = &mcp3422_info; | |
354 | ||
2816ac64 | 355 | switch (adc->id) { |
78f16dbd | 356 | case 1: |
505abf99 | 357 | case 5: |
78f16dbd SH |
358 | indio_dev->channels = mcp3421_channels; |
359 | indio_dev->num_channels = ARRAY_SIZE(mcp3421_channels); | |
360 | break; | |
07914c84 AC |
361 | case 2: |
362 | case 3: | |
2816ac64 AC |
363 | case 6: |
364 | case 7: | |
07914c84 AC |
365 | indio_dev->channels = mcp3422_channels; |
366 | indio_dev->num_channels = ARRAY_SIZE(mcp3422_channels); | |
367 | break; | |
368 | case 4: | |
2816ac64 | 369 | case 8: |
07914c84 AC |
370 | indio_dev->channels = mcp3424_channels; |
371 | indio_dev->num_channels = ARRAY_SIZE(mcp3424_channels); | |
372 | break; | |
373 | } | |
374 | ||
375 | /* meaningful default configuration */ | |
376 | config = (MCP3422_CONT_SAMPLING | |
e3169994 | 377 | | MCP3422_CHANNEL_VALUE(0) |
07914c84 AC |
378 | | MCP3422_PGA_VALUE(MCP3422_PGA_1) |
379 | | MCP3422_SAMPLE_RATE_VALUE(MCP3422_SRATE_240)); | |
6be72b90 AC |
380 | err = mcp3422_update_config(adc, config); |
381 | if (err < 0) | |
382 | return err; | |
07914c84 | 383 | |
2842d4cc | 384 | err = devm_iio_device_register(&client->dev, indio_dev); |
07914c84 AC |
385 | if (err < 0) |
386 | return err; | |
387 | ||
388 | i2c_set_clientdata(client, indio_dev); | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
07914c84 | 393 | static const struct i2c_device_id mcp3422_id[] = { |
78f16dbd | 394 | { "mcp3421", 1 }, |
07914c84 AC |
395 | { "mcp3422", 2 }, |
396 | { "mcp3423", 3 }, | |
397 | { "mcp3424", 4 }, | |
505abf99 | 398 | { "mcp3425", 5 }, |
2816ac64 AC |
399 | { "mcp3426", 6 }, |
400 | { "mcp3427", 7 }, | |
401 | { "mcp3428", 8 }, | |
07914c84 AC |
402 | { } |
403 | }; | |
404 | MODULE_DEVICE_TABLE(i2c, mcp3422_id); | |
405 | ||
406 | #ifdef CONFIG_OF | |
407 | static const struct of_device_id mcp3422_of_match[] = { | |
408 | { .compatible = "mcp3422" }, | |
409 | { } | |
410 | }; | |
411 | MODULE_DEVICE_TABLE(of, mcp3422_of_match); | |
412 | #endif | |
413 | ||
414 | static struct i2c_driver mcp3422_driver = { | |
415 | .driver = { | |
416 | .name = "mcp3422", | |
07914c84 AC |
417 | .of_match_table = of_match_ptr(mcp3422_of_match), |
418 | }, | |
419 | .probe = mcp3422_probe, | |
07914c84 AC |
420 | .id_table = mcp3422_id, |
421 | }; | |
422 | module_i2c_driver(mcp3422_driver); | |
423 | ||
424 | MODULE_AUTHOR("Angelo Compagnucci <angelo.compagnucci@gmail.com>"); | |
505abf99 | 425 | MODULE_DESCRIPTION("Microchip mcp3421/2/3/4/5/6/7/8 driver"); |
07914c84 | 426 | MODULE_LICENSE("GPL v2"); |