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f5ce4a7a OA |
1 | /* |
2 | * Copyright (C) 2013 Oskar Andero <oskar.andero@gmail.com> | |
b12206e9 SA |
3 | * Copyright (C) 2014 Rose Technology |
4 | * Allan Bendorff Jensen <abj@rosetechnology.dk> | |
5 | * Soren Andersen <san@rosetechnology.dk> | |
6 | * | |
7 | * Driver for following ADC chips from Microchip Technology's: | |
8 | * 10 Bit converter | |
9 | * MCP3001 | |
10 | * MCP3002 | |
11 | * MCP3004 | |
12 | * MCP3008 | |
13 | * ------------ | |
14 | * 12 bit converter | |
15 | * MCP3201 | |
16 | * MCP3202 | |
17 | * MCP3204 | |
18 | * MCP3208 | |
19 | * ------------ | |
f5ce4a7a | 20 | * |
f5ce4a7a | 21 | * Datasheet can be found here: |
b12206e9 SA |
22 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf mcp3001 |
23 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21294E.pdf mcp3002 | |
24 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21295d.pdf mcp3004/08 | |
25 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21290D.pdf mcp3201 | |
26 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf mcp3202 | |
27 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf mcp3204/08 | |
f686a36b | 28 | * http://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf mcp3301 |
f5ce4a7a OA |
29 | * |
30 | * This program is free software; you can redistribute it and/or modify | |
31 | * it under the terms of the GNU General Public License version 2 as | |
32 | * published by the Free Software Foundation. | |
33 | */ | |
34 | ||
35 | #include <linux/err.h> | |
b12206e9 | 36 | #include <linux/delay.h> |
f5ce4a7a OA |
37 | #include <linux/spi/spi.h> |
38 | #include <linux/module.h> | |
39 | #include <linux/iio/iio.h> | |
40 | #include <linux/regulator/consumer.h> | |
41 | ||
f5ce4a7a | 42 | enum { |
b12206e9 SA |
43 | mcp3001, |
44 | mcp3002, | |
45 | mcp3004, | |
46 | mcp3008, | |
47 | mcp3201, | |
48 | mcp3202, | |
f5ce4a7a OA |
49 | mcp3204, |
50 | mcp3208, | |
f686a36b | 51 | mcp3301, |
f5ce4a7a OA |
52 | }; |
53 | ||
b12206e9 SA |
54 | struct mcp320x_chip_info { |
55 | const struct iio_chan_spec *channels; | |
56 | unsigned int num_channels; | |
57 | unsigned int resolution; | |
58 | }; | |
59 | ||
f5ce4a7a OA |
60 | struct mcp320x { |
61 | struct spi_device *spi; | |
62 | struct spi_message msg; | |
63 | struct spi_transfer transfer[2]; | |
64 | ||
f5ce4a7a OA |
65 | struct regulator *reg; |
66 | struct mutex lock; | |
b12206e9 | 67 | const struct mcp320x_chip_info *chip_info; |
0e81bc99 MW |
68 | |
69 | u8 tx_buf ____cacheline_aligned; | |
70 | u8 rx_buf[2]; | |
f5ce4a7a OA |
71 | }; |
72 | ||
b12206e9 SA |
73 | static int mcp320x_channel_to_tx_data(int device_index, |
74 | const unsigned int channel, bool differential) | |
75 | { | |
76 | int start_bit = 1; | |
77 | ||
78 | switch (device_index) { | |
79 | case mcp3001: | |
80 | case mcp3201: | |
f686a36b | 81 | case mcp3301: |
b12206e9 SA |
82 | return 0; |
83 | case mcp3002: | |
84 | case mcp3202: | |
85 | return ((start_bit << 4) | (!differential << 3) | | |
86 | (channel << 2)); | |
87 | case mcp3004: | |
88 | case mcp3204: | |
89 | case mcp3008: | |
90 | case mcp3208: | |
91 | return ((start_bit << 6) | (!differential << 5) | | |
92 | (channel << 2)); | |
93 | default: | |
94 | return -EINVAL; | |
95 | } | |
96 | } | |
97 | ||
98 | static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel, | |
99 | bool differential, int device_index) | |
f5ce4a7a OA |
100 | { |
101 | int ret; | |
102 | ||
b12206e9 SA |
103 | adc->rx_buf[0] = 0; |
104 | adc->rx_buf[1] = 0; | |
105 | adc->tx_buf = mcp320x_channel_to_tx_data(device_index, | |
106 | channel, differential); | |
107 | ||
f686a36b | 108 | if (device_index != mcp3001 && device_index != mcp3201 && device_index != mcp3301) { |
b12206e9 SA |
109 | ret = spi_sync(adc->spi, &adc->msg); |
110 | if (ret < 0) | |
111 | return ret; | |
112 | } else { | |
113 | ret = spi_read(adc->spi, &adc->rx_buf, sizeof(adc->rx_buf)); | |
114 | if (ret < 0) | |
115 | return ret; | |
116 | } | |
f5ce4a7a | 117 | |
b12206e9 SA |
118 | switch (device_index) { |
119 | case mcp3001: | |
120 | return (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3); | |
121 | case mcp3002: | |
122 | case mcp3004: | |
123 | case mcp3008: | |
124 | return (adc->rx_buf[0] << 2 | adc->rx_buf[1] >> 6); | |
125 | case mcp3201: | |
126 | return (adc->rx_buf[0] << 7 | adc->rx_buf[1] >> 1); | |
127 | case mcp3202: | |
128 | case mcp3204: | |
129 | case mcp3208: | |
130 | return (adc->rx_buf[0] << 4 | adc->rx_buf[1] >> 4); | |
f686a36b AG |
131 | case mcp3301: |
132 | return sign_extend32((adc->rx_buf[0] & 0x1f) << 8 | adc->rx_buf[1], 12); | |
b12206e9 SA |
133 | default: |
134 | return -EINVAL; | |
135 | } | |
f5ce4a7a OA |
136 | } |
137 | ||
138 | static int mcp320x_read_raw(struct iio_dev *indio_dev, | |
139 | struct iio_chan_spec const *channel, int *val, | |
140 | int *val2, long mask) | |
141 | { | |
142 | struct mcp320x *adc = iio_priv(indio_dev); | |
143 | int ret = -EINVAL; | |
b12206e9 | 144 | int device_index = 0; |
f5ce4a7a OA |
145 | |
146 | mutex_lock(&adc->lock); | |
147 | ||
b12206e9 SA |
148 | device_index = spi_get_device_id(adc->spi)->driver_data; |
149 | ||
f5ce4a7a OA |
150 | switch (mask) { |
151 | case IIO_CHAN_INFO_RAW: | |
b12206e9 SA |
152 | ret = mcp320x_adc_conversion(adc, channel->address, |
153 | channel->differential, device_index); | |
154 | ||
f5ce4a7a OA |
155 | if (ret < 0) |
156 | goto out; | |
157 | ||
158 | *val = ret; | |
159 | ret = IIO_VAL_INT; | |
160 | break; | |
161 | ||
162 | case IIO_CHAN_INFO_SCALE: | |
f5ce4a7a OA |
163 | ret = regulator_get_voltage(adc->reg); |
164 | if (ret < 0) | |
165 | goto out; | |
166 | ||
b12206e9 | 167 | /* convert regulator output voltage to mV */ |
f5ce4a7a | 168 | *val = ret / 1000; |
b12206e9 | 169 | *val2 = adc->chip_info->resolution; |
f5ce4a7a OA |
170 | ret = IIO_VAL_FRACTIONAL_LOG2; |
171 | break; | |
f5ce4a7a OA |
172 | } |
173 | ||
174 | out: | |
175 | mutex_unlock(&adc->lock); | |
176 | ||
177 | return ret; | |
178 | } | |
179 | ||
180 | #define MCP320X_VOLTAGE_CHANNEL(num) \ | |
181 | { \ | |
182 | .type = IIO_VOLTAGE, \ | |
183 | .indexed = 1, \ | |
184 | .channel = (num), \ | |
185 | .address = (num), \ | |
186 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
187 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ | |
188 | } | |
189 | ||
4ea71e5c | 190 | #define MCP320X_VOLTAGE_CHANNEL_DIFF(chan1, chan2) \ |
f5ce4a7a OA |
191 | { \ |
192 | .type = IIO_VOLTAGE, \ | |
193 | .indexed = 1, \ | |
4ea71e5c AM |
194 | .channel = (chan1), \ |
195 | .channel2 = (chan2), \ | |
196 | .address = (chan1), \ | |
f5ce4a7a OA |
197 | .differential = 1, \ |
198 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
199 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \ | |
200 | } | |
201 | ||
b12206e9 | 202 | static const struct iio_chan_spec mcp3201_channels[] = { |
4ea71e5c | 203 | MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1), |
b12206e9 SA |
204 | }; |
205 | ||
206 | static const struct iio_chan_spec mcp3202_channels[] = { | |
207 | MCP320X_VOLTAGE_CHANNEL(0), | |
208 | MCP320X_VOLTAGE_CHANNEL(1), | |
4ea71e5c AM |
209 | MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1), |
210 | MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0), | |
b12206e9 SA |
211 | }; |
212 | ||
f5ce4a7a OA |
213 | static const struct iio_chan_spec mcp3204_channels[] = { |
214 | MCP320X_VOLTAGE_CHANNEL(0), | |
215 | MCP320X_VOLTAGE_CHANNEL(1), | |
216 | MCP320X_VOLTAGE_CHANNEL(2), | |
217 | MCP320X_VOLTAGE_CHANNEL(3), | |
4ea71e5c AM |
218 | MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1), |
219 | MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0), | |
220 | MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3), | |
221 | MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2), | |
f5ce4a7a OA |
222 | }; |
223 | ||
224 | static const struct iio_chan_spec mcp3208_channels[] = { | |
225 | MCP320X_VOLTAGE_CHANNEL(0), | |
226 | MCP320X_VOLTAGE_CHANNEL(1), | |
227 | MCP320X_VOLTAGE_CHANNEL(2), | |
228 | MCP320X_VOLTAGE_CHANNEL(3), | |
229 | MCP320X_VOLTAGE_CHANNEL(4), | |
230 | MCP320X_VOLTAGE_CHANNEL(5), | |
231 | MCP320X_VOLTAGE_CHANNEL(6), | |
232 | MCP320X_VOLTAGE_CHANNEL(7), | |
4ea71e5c AM |
233 | MCP320X_VOLTAGE_CHANNEL_DIFF(0, 1), |
234 | MCP320X_VOLTAGE_CHANNEL_DIFF(1, 0), | |
235 | MCP320X_VOLTAGE_CHANNEL_DIFF(2, 3), | |
236 | MCP320X_VOLTAGE_CHANNEL_DIFF(3, 2), | |
237 | MCP320X_VOLTAGE_CHANNEL_DIFF(4, 5), | |
238 | MCP320X_VOLTAGE_CHANNEL_DIFF(5, 4), | |
239 | MCP320X_VOLTAGE_CHANNEL_DIFF(6, 7), | |
240 | MCP320X_VOLTAGE_CHANNEL_DIFF(7, 6), | |
f5ce4a7a OA |
241 | }; |
242 | ||
243 | static const struct iio_info mcp320x_info = { | |
244 | .read_raw = mcp320x_read_raw, | |
245 | .driver_module = THIS_MODULE, | |
246 | }; | |
247 | ||
b12206e9 SA |
248 | static const struct mcp320x_chip_info mcp320x_chip_infos[] = { |
249 | [mcp3001] = { | |
250 | .channels = mcp3201_channels, | |
251 | .num_channels = ARRAY_SIZE(mcp3201_channels), | |
252 | .resolution = 10 | |
253 | }, | |
254 | [mcp3002] = { | |
255 | .channels = mcp3202_channels, | |
256 | .num_channels = ARRAY_SIZE(mcp3202_channels), | |
257 | .resolution = 10 | |
258 | }, | |
259 | [mcp3004] = { | |
260 | .channels = mcp3204_channels, | |
261 | .num_channels = ARRAY_SIZE(mcp3204_channels), | |
262 | .resolution = 10 | |
263 | }, | |
264 | [mcp3008] = { | |
265 | .channels = mcp3208_channels, | |
266 | .num_channels = ARRAY_SIZE(mcp3208_channels), | |
267 | .resolution = 10 | |
268 | }, | |
269 | [mcp3201] = { | |
270 | .channels = mcp3201_channels, | |
271 | .num_channels = ARRAY_SIZE(mcp3201_channels), | |
272 | .resolution = 12 | |
273 | }, | |
274 | [mcp3202] = { | |
275 | .channels = mcp3202_channels, | |
276 | .num_channels = ARRAY_SIZE(mcp3202_channels), | |
277 | .resolution = 12 | |
278 | }, | |
f5ce4a7a OA |
279 | [mcp3204] = { |
280 | .channels = mcp3204_channels, | |
b12206e9 SA |
281 | .num_channels = ARRAY_SIZE(mcp3204_channels), |
282 | .resolution = 12 | |
f5ce4a7a OA |
283 | }, |
284 | [mcp3208] = { | |
285 | .channels = mcp3208_channels, | |
b12206e9 SA |
286 | .num_channels = ARRAY_SIZE(mcp3208_channels), |
287 | .resolution = 12 | |
f5ce4a7a | 288 | }, |
f686a36b AG |
289 | [mcp3301] = { |
290 | .channels = mcp3201_channels, | |
291 | .num_channels = ARRAY_SIZE(mcp3201_channels), | |
292 | .resolution = 13 | |
293 | }, | |
f5ce4a7a OA |
294 | }; |
295 | ||
296 | static int mcp320x_probe(struct spi_device *spi) | |
297 | { | |
298 | struct iio_dev *indio_dev; | |
299 | struct mcp320x *adc; | |
b12206e9 | 300 | const struct mcp320x_chip_info *chip_info; |
f5ce4a7a OA |
301 | int ret; |
302 | ||
a726dea5 | 303 | indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); |
f5ce4a7a OA |
304 | if (!indio_dev) |
305 | return -ENOMEM; | |
306 | ||
307 | adc = iio_priv(indio_dev); | |
308 | adc->spi = spi; | |
309 | ||
310 | indio_dev->dev.parent = &spi->dev; | |
311 | indio_dev->name = spi_get_device_id(spi)->name; | |
312 | indio_dev->modes = INDIO_DIRECT_MODE; | |
313 | indio_dev->info = &mcp320x_info; | |
314 | ||
b12206e9 | 315 | chip_info = &mcp320x_chip_infos[spi_get_device_id(spi)->driver_data]; |
f5ce4a7a OA |
316 | indio_dev->channels = chip_info->channels; |
317 | indio_dev->num_channels = chip_info->num_channels; | |
318 | ||
41be6a0d MS |
319 | adc->chip_info = chip_info; |
320 | ||
f5ce4a7a OA |
321 | adc->transfer[0].tx_buf = &adc->tx_buf; |
322 | adc->transfer[0].len = sizeof(adc->tx_buf); | |
323 | adc->transfer[1].rx_buf = adc->rx_buf; | |
324 | adc->transfer[1].len = sizeof(adc->rx_buf); | |
325 | ||
326 | spi_message_init_with_transfers(&adc->msg, adc->transfer, | |
327 | ARRAY_SIZE(adc->transfer)); | |
328 | ||
a726dea5 SK |
329 | adc->reg = devm_regulator_get(&spi->dev, "vref"); |
330 | if (IS_ERR(adc->reg)) | |
331 | return PTR_ERR(adc->reg); | |
f5ce4a7a OA |
332 | |
333 | ret = regulator_enable(adc->reg); | |
334 | if (ret < 0) | |
a726dea5 | 335 | return ret; |
f5ce4a7a OA |
336 | |
337 | mutex_init(&adc->lock); | |
338 | ||
339 | ret = iio_device_register(indio_dev); | |
340 | if (ret < 0) | |
341 | goto reg_disable; | |
342 | ||
343 | return 0; | |
344 | ||
345 | reg_disable: | |
346 | regulator_disable(adc->reg); | |
f5ce4a7a OA |
347 | |
348 | return ret; | |
349 | } | |
350 | ||
351 | static int mcp320x_remove(struct spi_device *spi) | |
352 | { | |
353 | struct iio_dev *indio_dev = spi_get_drvdata(spi); | |
354 | struct mcp320x *adc = iio_priv(indio_dev); | |
355 | ||
356 | iio_device_unregister(indio_dev); | |
357 | regulator_disable(adc->reg); | |
f5ce4a7a OA |
358 | |
359 | return 0; | |
360 | } | |
361 | ||
b12206e9 SA |
362 | #if defined(CONFIG_OF) |
363 | static const struct of_device_id mcp320x_dt_ids[] = { | |
0d0e5384 | 364 | /* NOTE: The use of compatibles with no vendor prefix is deprecated. */ |
b12206e9 SA |
365 | { |
366 | .compatible = "mcp3001", | |
367 | .data = &mcp320x_chip_infos[mcp3001], | |
368 | }, { | |
369 | .compatible = "mcp3002", | |
370 | .data = &mcp320x_chip_infos[mcp3002], | |
371 | }, { | |
372 | .compatible = "mcp3004", | |
373 | .data = &mcp320x_chip_infos[mcp3004], | |
374 | }, { | |
375 | .compatible = "mcp3008", | |
376 | .data = &mcp320x_chip_infos[mcp3008], | |
377 | }, { | |
378 | .compatible = "mcp3201", | |
379 | .data = &mcp320x_chip_infos[mcp3201], | |
380 | }, { | |
381 | .compatible = "mcp3202", | |
382 | .data = &mcp320x_chip_infos[mcp3202], | |
383 | }, { | |
384 | .compatible = "mcp3204", | |
385 | .data = &mcp320x_chip_infos[mcp3204], | |
386 | }, { | |
387 | .compatible = "mcp3208", | |
388 | .data = &mcp320x_chip_infos[mcp3208], | |
f686a36b AG |
389 | }, { |
390 | .compatible = "mcp3301", | |
391 | .data = &mcp320x_chip_infos[mcp3301], | |
0d0e5384 JMC |
392 | }, { |
393 | .compatible = "microchip,mcp3001", | |
394 | .data = &mcp320x_chip_infos[mcp3001], | |
395 | }, { | |
396 | .compatible = "microchip,mcp3002", | |
397 | .data = &mcp320x_chip_infos[mcp3002], | |
398 | }, { | |
399 | .compatible = "microchip,mcp3004", | |
400 | .data = &mcp320x_chip_infos[mcp3004], | |
401 | }, { | |
402 | .compatible = "microchip,mcp3008", | |
403 | .data = &mcp320x_chip_infos[mcp3008], | |
404 | }, { | |
405 | .compatible = "microchip,mcp3201", | |
406 | .data = &mcp320x_chip_infos[mcp3201], | |
407 | }, { | |
408 | .compatible = "microchip,mcp3202", | |
409 | .data = &mcp320x_chip_infos[mcp3202], | |
410 | }, { | |
411 | .compatible = "microchip,mcp3204", | |
412 | .data = &mcp320x_chip_infos[mcp3204], | |
413 | }, { | |
414 | .compatible = "microchip,mcp3208", | |
415 | .data = &mcp320x_chip_infos[mcp3208], | |
416 | }, { | |
417 | .compatible = "microchip,mcp3301", | |
418 | .data = &mcp320x_chip_infos[mcp3301], | |
b12206e9 SA |
419 | }, { |
420 | } | |
421 | }; | |
422 | MODULE_DEVICE_TABLE(of, mcp320x_dt_ids); | |
423 | #endif | |
424 | ||
f5ce4a7a | 425 | static const struct spi_device_id mcp320x_id[] = { |
b12206e9 SA |
426 | { "mcp3001", mcp3001 }, |
427 | { "mcp3002", mcp3002 }, | |
428 | { "mcp3004", mcp3004 }, | |
429 | { "mcp3008", mcp3008 }, | |
430 | { "mcp3201", mcp3201 }, | |
431 | { "mcp3202", mcp3202 }, | |
f5ce4a7a OA |
432 | { "mcp3204", mcp3204 }, |
433 | { "mcp3208", mcp3208 }, | |
f686a36b | 434 | { "mcp3301", mcp3301 }, |
f5ce4a7a OA |
435 | { } |
436 | }; | |
437 | MODULE_DEVICE_TABLE(spi, mcp320x_id); | |
438 | ||
439 | static struct spi_driver mcp320x_driver = { | |
440 | .driver = { | |
441 | .name = "mcp320x", | |
ab6ff6c6 | 442 | .of_match_table = of_match_ptr(mcp320x_dt_ids), |
f5ce4a7a OA |
443 | }, |
444 | .probe = mcp320x_probe, | |
445 | .remove = mcp320x_remove, | |
446 | .id_table = mcp320x_id, | |
447 | }; | |
448 | module_spi_driver(mcp320x_driver); | |
449 | ||
450 | MODULE_AUTHOR("Oskar Andero <oskar.andero@gmail.com>"); | |
b12206e9 | 451 | MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08"); |
f5ce4a7a | 452 | MODULE_LICENSE("GPL v2"); |