Commit | Line | Data |
---|---|---|
1664f6a5 PM |
1 | /* |
2 | * Copyright (c) 2014-2015 Imagination Technologies Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License version 2 as published by | |
6 | * the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_device.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/regulator/consumer.h> | |
19 | #include <linux/slab.h> | |
20 | ||
21 | #include <linux/iio/buffer.h> | |
22 | #include <linux/iio/iio.h> | |
23 | #include <linux/iio/sysfs.h> | |
24 | #include <linux/iio/trigger.h> | |
25 | #include <linux/iio/trigger_consumer.h> | |
26 | #include <linux/iio/triggered_buffer.h> | |
27 | ||
28 | /* Registers */ | |
29 | #define CC10001_ADC_CONFIG 0x00 | |
30 | #define CC10001_ADC_START_CONV BIT(4) | |
31 | #define CC10001_ADC_MODE_SINGLE_CONV BIT(5) | |
32 | ||
33 | #define CC10001_ADC_DDATA_OUT 0x04 | |
34 | #define CC10001_ADC_EOC 0x08 | |
35 | #define CC10001_ADC_EOC_SET BIT(0) | |
36 | ||
37 | #define CC10001_ADC_CHSEL_SAMPLED 0x0c | |
713276ea NT |
38 | #define CC10001_ADC_POWER_DOWN 0x10 |
39 | #define CC10001_ADC_POWER_DOWN_SET BIT(0) | |
40 | ||
1664f6a5 PM |
41 | #define CC10001_ADC_DEBUG 0x14 |
42 | #define CC10001_ADC_DATA_COUNT 0x20 | |
43 | ||
44 | #define CC10001_ADC_DATA_MASK GENMASK(9, 0) | |
45 | #define CC10001_ADC_NUM_CHANNELS 8 | |
46 | #define CC10001_ADC_CH_MASK GENMASK(2, 0) | |
47 | ||
48 | #define CC10001_INVALID_SAMPLED 0xffff | |
49 | #define CC10001_MAX_POLL_COUNT 20 | |
50 | ||
51 | /* | |
52 | * As per device specification, wait six clock cycles after power-up to | |
53 | * activate START. Since adding two more clock cycles delay does not | |
54 | * impact the performance too much, we are adding two additional cycles delay | |
55 | * intentionally here. | |
56 | */ | |
57 | #define CC10001_WAIT_CYCLES 8 | |
58 | ||
59 | struct cc10001_adc_device { | |
60 | void __iomem *reg_base; | |
61 | struct clk *adc_clk; | |
62 | struct regulator *reg; | |
63 | u16 *buf; | |
64 | ||
ae354962 | 65 | bool shared; |
1664f6a5 | 66 | struct mutex lock; |
1664f6a5 PM |
67 | unsigned int start_delay_ns; |
68 | unsigned int eoc_delay_ns; | |
69 | }; | |
70 | ||
71 | static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev, | |
72 | u32 reg, u32 val) | |
73 | { | |
74 | writel(val, adc_dev->reg_base + reg); | |
75 | } | |
76 | ||
77 | static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev, | |
78 | u32 reg) | |
79 | { | |
80 | return readl(adc_dev->reg_base + reg); | |
81 | } | |
82 | ||
713276ea NT |
83 | static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev) |
84 | { | |
85 | cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0); | |
86 | ndelay(adc_dev->start_delay_ns); | |
87 | } | |
88 | ||
89 | static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev) | |
90 | { | |
91 | cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, | |
92 | CC10001_ADC_POWER_DOWN_SET); | |
93 | } | |
94 | ||
1664f6a5 PM |
95 | static void cc10001_adc_start(struct cc10001_adc_device *adc_dev, |
96 | unsigned int channel) | |
97 | { | |
98 | u32 val; | |
99 | ||
100 | /* Channel selection and mode of operation */ | |
101 | val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV; | |
102 | cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val); | |
103 | ||
f29b212e | 104 | udelay(1); |
1664f6a5 PM |
105 | val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG); |
106 | val = val | CC10001_ADC_START_CONV; | |
107 | cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val); | |
108 | } | |
109 | ||
110 | static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev, | |
111 | unsigned int channel, | |
112 | unsigned int delay) | |
113 | { | |
114 | struct cc10001_adc_device *adc_dev = iio_priv(indio_dev); | |
115 | unsigned int poll_count = 0; | |
116 | ||
117 | while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) & | |
118 | CC10001_ADC_EOC_SET)) { | |
119 | ||
120 | ndelay(delay); | |
121 | if (poll_count++ == CC10001_MAX_POLL_COUNT) | |
122 | return CC10001_INVALID_SAMPLED; | |
123 | } | |
124 | ||
125 | poll_count = 0; | |
126 | while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) & | |
127 | CC10001_ADC_CH_MASK) != channel) { | |
128 | ||
129 | ndelay(delay); | |
130 | if (poll_count++ == CC10001_MAX_POLL_COUNT) | |
131 | return CC10001_INVALID_SAMPLED; | |
132 | } | |
133 | ||
134 | /* Read the 10 bit output register */ | |
135 | return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) & | |
136 | CC10001_ADC_DATA_MASK; | |
137 | } | |
138 | ||
139 | static irqreturn_t cc10001_adc_trigger_h(int irq, void *p) | |
140 | { | |
141 | struct cc10001_adc_device *adc_dev; | |
142 | struct iio_poll_func *pf = p; | |
143 | struct iio_dev *indio_dev; | |
144 | unsigned int delay_ns; | |
145 | unsigned int channel; | |
13415a99 | 146 | unsigned int scan_idx; |
1664f6a5 PM |
147 | bool sample_invalid; |
148 | u16 *data; | |
149 | int i; | |
150 | ||
151 | indio_dev = pf->indio_dev; | |
152 | adc_dev = iio_priv(indio_dev); | |
153 | data = adc_dev->buf; | |
154 | ||
155 | mutex_lock(&adc_dev->lock); | |
156 | ||
ae354962 NT |
157 | if (!adc_dev->shared) |
158 | cc10001_adc_power_up(adc_dev); | |
1664f6a5 PM |
159 | |
160 | /* Calculate delay step for eoc and sampled data */ | |
161 | delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT; | |
162 | ||
163 | i = 0; | |
164 | sample_invalid = false; | |
13415a99 | 165 | for_each_set_bit(scan_idx, indio_dev->active_scan_mask, |
1664f6a5 PM |
166 | indio_dev->masklength) { |
167 | ||
13415a99 | 168 | channel = indio_dev->channels[scan_idx].channel; |
1664f6a5 PM |
169 | cc10001_adc_start(adc_dev, channel); |
170 | ||
171 | data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns); | |
172 | if (data[i] == CC10001_INVALID_SAMPLED) { | |
173 | dev_warn(&indio_dev->dev, | |
174 | "invalid sample on channel %d\n", channel); | |
175 | sample_invalid = true; | |
176 | goto done; | |
177 | } | |
178 | i++; | |
179 | } | |
180 | ||
181 | done: | |
ae354962 NT |
182 | if (!adc_dev->shared) |
183 | cc10001_adc_power_down(adc_dev); | |
1664f6a5 PM |
184 | |
185 | mutex_unlock(&adc_dev->lock); | |
186 | ||
187 | if (!sample_invalid) | |
188 | iio_push_to_buffers_with_timestamp(indio_dev, data, | |
bc2b7dab | 189 | iio_get_time_ns(indio_dev)); |
1664f6a5 PM |
190 | iio_trigger_notify_done(indio_dev->trig); |
191 | ||
192 | return IRQ_HANDLED; | |
193 | } | |
194 | ||
195 | static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev, | |
196 | struct iio_chan_spec const *chan) | |
197 | { | |
198 | struct cc10001_adc_device *adc_dev = iio_priv(indio_dev); | |
199 | unsigned int delay_ns; | |
200 | u16 val; | |
201 | ||
ae354962 NT |
202 | if (!adc_dev->shared) |
203 | cc10001_adc_power_up(adc_dev); | |
1664f6a5 PM |
204 | |
205 | /* Calculate delay step for eoc and sampled data */ | |
206 | delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT; | |
207 | ||
208 | cc10001_adc_start(adc_dev, chan->channel); | |
209 | ||
210 | val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns); | |
211 | ||
ae354962 NT |
212 | if (!adc_dev->shared) |
213 | cc10001_adc_power_down(adc_dev); | |
1664f6a5 PM |
214 | |
215 | return val; | |
216 | } | |
217 | ||
218 | static int cc10001_adc_read_raw(struct iio_dev *indio_dev, | |
219 | struct iio_chan_spec const *chan, | |
220 | int *val, int *val2, long mask) | |
221 | { | |
222 | struct cc10001_adc_device *adc_dev = iio_priv(indio_dev); | |
223 | int ret; | |
224 | ||
225 | switch (mask) { | |
226 | case IIO_CHAN_INFO_RAW: | |
227 | if (iio_buffer_enabled(indio_dev)) | |
228 | return -EBUSY; | |
229 | mutex_lock(&adc_dev->lock); | |
230 | *val = cc10001_adc_read_raw_voltage(indio_dev, chan); | |
231 | mutex_unlock(&adc_dev->lock); | |
232 | ||
233 | if (*val == CC10001_INVALID_SAMPLED) | |
234 | return -EIO; | |
235 | return IIO_VAL_INT; | |
236 | ||
237 | case IIO_CHAN_INFO_SCALE: | |
238 | ret = regulator_get_voltage(adc_dev->reg); | |
65a761bf | 239 | if (ret < 0) |
1664f6a5 PM |
240 | return ret; |
241 | ||
242 | *val = ret / 1000; | |
243 | *val2 = chan->scan_type.realbits; | |
244 | return IIO_VAL_FRACTIONAL_LOG2; | |
245 | ||
246 | default: | |
247 | return -EINVAL; | |
248 | } | |
249 | } | |
250 | ||
251 | static int cc10001_update_scan_mode(struct iio_dev *indio_dev, | |
252 | const unsigned long *scan_mask) | |
253 | { | |
254 | struct cc10001_adc_device *adc_dev = iio_priv(indio_dev); | |
255 | ||
256 | kfree(adc_dev->buf); | |
257 | adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL); | |
258 | if (!adc_dev->buf) | |
259 | return -ENOMEM; | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | static const struct iio_info cc10001_adc_info = { | |
265 | .driver_module = THIS_MODULE, | |
266 | .read_raw = &cc10001_adc_read_raw, | |
267 | .update_scan_mode = &cc10001_update_scan_mode, | |
268 | }; | |
269 | ||
13415a99 NT |
270 | static int cc10001_adc_channel_init(struct iio_dev *indio_dev, |
271 | unsigned long channel_map) | |
1664f6a5 | 272 | { |
1664f6a5 PM |
273 | struct iio_chan_spec *chan_array, *timestamp; |
274 | unsigned int bit, idx = 0; | |
275 | ||
13415a99 NT |
276 | indio_dev->num_channels = bitmap_weight(&channel_map, |
277 | CC10001_ADC_NUM_CHANNELS) + 1; | |
1664f6a5 | 278 | |
13415a99 | 279 | chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels, |
1664f6a5 PM |
280 | sizeof(struct iio_chan_spec), |
281 | GFP_KERNEL); | |
282 | if (!chan_array) | |
283 | return -ENOMEM; | |
284 | ||
13415a99 | 285 | for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) { |
1664f6a5 PM |
286 | struct iio_chan_spec *chan = &chan_array[idx]; |
287 | ||
288 | chan->type = IIO_VOLTAGE; | |
289 | chan->indexed = 1; | |
290 | chan->channel = bit; | |
291 | chan->scan_index = idx; | |
292 | chan->scan_type.sign = 'u'; | |
293 | chan->scan_type.realbits = 10; | |
294 | chan->scan_type.storagebits = 16; | |
295 | chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); | |
296 | chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); | |
297 | idx++; | |
298 | } | |
299 | ||
300 | timestamp = &chan_array[idx]; | |
301 | timestamp->type = IIO_TIMESTAMP; | |
302 | timestamp->channel = -1; | |
303 | timestamp->scan_index = idx; | |
304 | timestamp->scan_type.sign = 's'; | |
305 | timestamp->scan_type.realbits = 64; | |
306 | timestamp->scan_type.storagebits = 64; | |
307 | ||
308 | indio_dev->channels = chan_array; | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | static int cc10001_adc_probe(struct platform_device *pdev) | |
314 | { | |
315 | struct device_node *node = pdev->dev.of_node; | |
316 | struct cc10001_adc_device *adc_dev; | |
317 | unsigned long adc_clk_rate; | |
318 | struct resource *res; | |
319 | struct iio_dev *indio_dev; | |
13415a99 | 320 | unsigned long channel_map; |
1664f6a5 PM |
321 | int ret; |
322 | ||
323 | indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev)); | |
324 | if (indio_dev == NULL) | |
325 | return -ENOMEM; | |
326 | ||
327 | adc_dev = iio_priv(indio_dev); | |
328 | ||
13415a99 | 329 | channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0); |
ae354962 NT |
330 | if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) { |
331 | adc_dev->shared = true; | |
13415a99 | 332 | channel_map &= ~ret; |
ae354962 | 333 | } |
1664f6a5 PM |
334 | |
335 | adc_dev->reg = devm_regulator_get(&pdev->dev, "vref"); | |
336 | if (IS_ERR(adc_dev->reg)) | |
337 | return PTR_ERR(adc_dev->reg); | |
338 | ||
339 | ret = regulator_enable(adc_dev->reg); | |
340 | if (ret) | |
341 | return ret; | |
342 | ||
343 | indio_dev->dev.parent = &pdev->dev; | |
344 | indio_dev->name = dev_name(&pdev->dev); | |
345 | indio_dev->info = &cc10001_adc_info; | |
346 | indio_dev->modes = INDIO_DIRECT_MODE; | |
347 | ||
348 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
349 | adc_dev->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
350 | if (IS_ERR(adc_dev->reg_base)) { | |
351 | ret = PTR_ERR(adc_dev->reg_base); | |
352 | goto err_disable_reg; | |
353 | } | |
354 | ||
355 | adc_dev->adc_clk = devm_clk_get(&pdev->dev, "adc"); | |
356 | if (IS_ERR(adc_dev->adc_clk)) { | |
357 | dev_err(&pdev->dev, "failed to get the clock\n"); | |
358 | ret = PTR_ERR(adc_dev->adc_clk); | |
359 | goto err_disable_reg; | |
360 | } | |
361 | ||
362 | ret = clk_prepare_enable(adc_dev->adc_clk); | |
363 | if (ret) { | |
364 | dev_err(&pdev->dev, "failed to enable the clock\n"); | |
365 | goto err_disable_reg; | |
366 | } | |
367 | ||
368 | adc_clk_rate = clk_get_rate(adc_dev->adc_clk); | |
369 | if (!adc_clk_rate) { | |
370 | ret = -EINVAL; | |
371 | dev_err(&pdev->dev, "null clock rate!\n"); | |
372 | goto err_disable_clk; | |
373 | } | |
374 | ||
375 | adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate; | |
376 | adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES; | |
377 | ||
ae354962 NT |
378 | /* |
379 | * There is only one register to power-up/power-down the AUX ADC. | |
380 | * If the ADC is shared among multiple CPUs, always power it up here. | |
381 | * If the ADC is used only by the MIPS, power-up/power-down at runtime. | |
382 | */ | |
383 | if (adc_dev->shared) | |
384 | cc10001_adc_power_up(adc_dev); | |
385 | ||
1664f6a5 | 386 | /* Setup the ADC channels available on the device */ |
13415a99 | 387 | ret = cc10001_adc_channel_init(indio_dev, channel_map); |
1664f6a5 PM |
388 | if (ret < 0) |
389 | goto err_disable_clk; | |
390 | ||
391 | mutex_init(&adc_dev->lock); | |
392 | ||
393 | ret = iio_triggered_buffer_setup(indio_dev, NULL, | |
394 | &cc10001_adc_trigger_h, NULL); | |
395 | if (ret < 0) | |
396 | goto err_disable_clk; | |
397 | ||
398 | ret = iio_device_register(indio_dev); | |
399 | if (ret < 0) | |
400 | goto err_cleanup_buffer; | |
401 | ||
402 | platform_set_drvdata(pdev, indio_dev); | |
403 | ||
404 | return 0; | |
405 | ||
406 | err_cleanup_buffer: | |
407 | iio_triggered_buffer_cleanup(indio_dev); | |
408 | err_disable_clk: | |
409 | clk_disable_unprepare(adc_dev->adc_clk); | |
410 | err_disable_reg: | |
411 | regulator_disable(adc_dev->reg); | |
412 | return ret; | |
413 | } | |
414 | ||
415 | static int cc10001_adc_remove(struct platform_device *pdev) | |
416 | { | |
417 | struct iio_dev *indio_dev = platform_get_drvdata(pdev); | |
418 | struct cc10001_adc_device *adc_dev = iio_priv(indio_dev); | |
419 | ||
ae354962 | 420 | cc10001_adc_power_down(adc_dev); |
1664f6a5 PM |
421 | iio_device_unregister(indio_dev); |
422 | iio_triggered_buffer_cleanup(indio_dev); | |
423 | clk_disable_unprepare(adc_dev->adc_clk); | |
424 | regulator_disable(adc_dev->reg); | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
429 | static const struct of_device_id cc10001_adc_dt_ids[] = { | |
430 | { .compatible = "cosmic,10001-adc", }, | |
431 | { } | |
432 | }; | |
433 | MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids); | |
434 | ||
435 | static struct platform_driver cc10001_adc_driver = { | |
436 | .driver = { | |
437 | .name = "cc10001-adc", | |
438 | .of_match_table = cc10001_adc_dt_ids, | |
439 | }, | |
440 | .probe = cc10001_adc_probe, | |
441 | .remove = cc10001_adc_remove, | |
442 | }; | |
443 | module_platform_driver(cc10001_adc_driver); | |
444 | ||
445 | MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>"); | |
446 | MODULE_DESCRIPTION("Cosmic Circuits ADC driver"); | |
447 | MODULE_LICENSE("GPL v2"); |