[linux-2.6-block.git] / drivers / iio / adc / cc10001_adc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014-2015 Imagination Technologies Ltd.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>

#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

/* Registers */
#define CC10001_ADC_CONFIG		0x00
#define CC10001_ADC_START_CONV		BIT(4)
#define CC10001_ADC_MODE_SINGLE_CONV	BIT(5)

#define CC10001_ADC_DDATA_OUT		0x04
#define CC10001_ADC_EOC			0x08
#define CC10001_ADC_EOC_SET		BIT(0)

#define CC10001_ADC_CHSEL_SAMPLED	0x0c
#define CC10001_ADC_POWER_DOWN		0x10
#define CC10001_ADC_POWER_DOWN_SET	BIT(0)

#define CC10001_ADC_DEBUG		0x14
#define CC10001_ADC_DATA_COUNT		0x20

#define CC10001_ADC_DATA_MASK		GENMASK(9, 0)
#define CC10001_ADC_NUM_CHANNELS	8
#define CC10001_ADC_CH_MASK		GENMASK(2, 0)

#define CC10001_INVALID_SAMPLED		0xffff
#define CC10001_MAX_POLL_COUNT		20

/*
 * As per device specification, wait six clock cycles after power-up to
 * activate START. Since adding two more clock cycles delay does not
 * impact the performance too much, we are adding two additional cycles delay
 * intentionally here.
 */
#define	CC10001_WAIT_CYCLES		8

struct cc10001_adc_device {
	void __iomem *reg_base;
	struct clk *adc_clk;
	struct regulator *reg;
	u16 *buf;

	bool shared;
	struct mutex lock;
	unsigned int start_delay_ns;
	unsigned int eoc_delay_ns;
};

static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
					 u32 reg, u32 val)
{
	writel(val, adc_dev->reg_base + reg);
}

static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
				       u32 reg)
{
	return readl(adc_dev->reg_base + reg);
}

static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev)
{
	cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0);
	ndelay(adc_dev->start_delay_ns);
}

static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev)
{
	cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN,
			      CC10001_ADC_POWER_DOWN_SET);
}

static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
			      unsigned int channel)
{
	u32 val;

	/* Channel selection and mode of operation */
	val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV;
	cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);

	udelay(1);
	val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
	val = val | CC10001_ADC_START_CONV;
	cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
}

static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
				 unsigned int channel,
				 unsigned int delay)
{
	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
	unsigned int poll_count = 0;

	while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
			CC10001_ADC_EOC_SET)) {

		ndelay(delay);
		if (poll_count++ == CC10001_MAX_POLL_COUNT)
			return CC10001_INVALID_SAMPLED;
	}

	poll_count = 0;
	while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
			CC10001_ADC_CH_MASK) != channel) {

		ndelay(delay);
		if (poll_count++ == CC10001_MAX_POLL_COUNT)
			return CC10001_INVALID_SAMPLED;
	}

	/* Read the 10 bit output register */
	return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
			       CC10001_ADC_DATA_MASK;
}

static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
{
	struct cc10001_adc_device *adc_dev;
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev;
	unsigned int delay_ns;
	unsigned int channel;
	unsigned int scan_idx;
	bool sample_invalid;
	u16 *data;
	int i;

	indio_dev = pf->indio_dev;
	adc_dev = iio_priv(indio_dev);
	data = adc_dev->buf;

	mutex_lock(&adc_dev->lock);

	if (!adc_dev->shared)
		cc10001_adc_power_up(adc_dev);

	/* Calculate delay step for eoc and sampled data */
	delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;

	i = 0;
	sample_invalid = false;
	for_each_set_bit(scan_idx, indio_dev->active_scan_mask,
				  indio_dev->masklength) {

		channel = indio_dev->channels[scan_idx].channel;
		cc10001_adc_start(adc_dev, channel);

		data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
		if (data[i] == CC10001_INVALID_SAMPLED) {
			dev_warn(&indio_dev->dev,
				 "invalid sample on channel %d\n", channel);
			sample_invalid = true;
			goto done;
		}
		i++;
	}

done:
	if (!adc_dev->shared)
		cc10001_adc_power_down(adc_dev);

	mutex_unlock(&adc_dev->lock);

	if (!sample_invalid)
		iio_push_to_buffers_with_timestamp(indio_dev, data,
						   iio_get_time_ns(indio_dev));
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
					struct iio_chan_spec const *chan)
{
	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
	unsigned int delay_ns;
	u16 val;

	if (!adc_dev->shared)
		cc10001_adc_power_up(adc_dev);

	/* Calculate delay step for eoc and sampled data */
	delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;

	cc10001_adc_start(adc_dev, chan->channel);

	val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);

	if (!adc_dev->shared)
		cc10001_adc_power_down(adc_dev);

	return val;
}

static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
				 struct iio_chan_spec const *chan,
				 int *val, int *val2, long mask)
{
	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
	int ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
		if (iio_buffer_enabled(indio_dev))
			return -EBUSY;
		mutex_lock(&adc_dev->lock);
		*val = cc10001_adc_read_raw_voltage(indio_dev, chan);
		mutex_unlock(&adc_dev->lock);

		if (*val == CC10001_INVALID_SAMPLED)
			return -EIO;
		return IIO_VAL_INT;

	case IIO_CHAN_INFO_SCALE:
		ret = regulator_get_voltage(adc_dev->reg);
		if (ret < 0)
			return ret;

		*val = ret / 1000;
		*val2 = chan->scan_type.realbits;
		return IIO_VAL_FRACTIONAL_LOG2;

	default:
		return -EINVAL;
	}
}

static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
				    const unsigned long *scan_mask)
{
	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);

	kfree(adc_dev->buf);
	adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
	if (!adc_dev->buf)
		return -ENOMEM;

	return 0;
}

static const struct iio_info cc10001_adc_info = {
	.read_raw = &cc10001_adc_read_raw,
	.update_scan_mode = &cc10001_update_scan_mode,
};

static int cc10001_adc_channel_init(struct iio_dev *indio_dev,
				    unsigned long channel_map)
{
	struct iio_chan_spec *chan_array, *timestamp;
	unsigned int bit, idx = 0;

	indio_dev->num_channels = bitmap_weight(&channel_map,
						CC10001_ADC_NUM_CHANNELS) + 1;

	chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels,
				  sizeof(struct iio_chan_spec),
				  GFP_KERNEL);
	if (!chan_array)
		return -ENOMEM;

	for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) {
		struct iio_chan_spec *chan = &chan_array[idx];

		chan->type = IIO_VOLTAGE;
		chan->indexed = 1;
		chan->channel = bit;
		chan->scan_index = idx;
		chan->scan_type.sign = 'u';
		chan->scan_type.realbits = 10;
		chan->scan_type.storagebits = 16;
		chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
		chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
		idx++;
	}

	timestamp = &chan_array[idx];
	timestamp->type = IIO_TIMESTAMP;
	timestamp->channel = -1;
	timestamp->scan_index = idx;
	timestamp->scan_type.sign = 's';
	timestamp->scan_type.realbits = 64;
	timestamp->scan_type.storagebits = 64;

	indio_dev->channels = chan_array;

	return 0;
}

static int cc10001_adc_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct cc10001_adc_device *adc_dev;
	unsigned long adc_clk_rate;
	struct iio_dev *indio_dev;
	unsigned long channel_map;
	int ret;

	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
	if (indio_dev == NULL)
		return -ENOMEM;

	adc_dev = iio_priv(indio_dev);

	channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
	if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) {
		adc_dev->shared = true;
		channel_map &= ~ret;
	}

	adc_dev->reg = devm_regulator_get(&pdev->dev, "vref");
	if (IS_ERR(adc_dev->reg))
		return PTR_ERR(adc_dev->reg);

	ret = regulator_enable(adc_dev->reg);
	if (ret)
		return ret;

	indio_dev->name = dev_name(&pdev->dev);
	indio_dev->info = &cc10001_adc_info;
	indio_dev->modes = INDIO_DIRECT_MODE;

	adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(adc_dev->reg_base)) {
		ret = PTR_ERR(adc_dev->reg_base);
		goto err_disable_reg;
	}

	adc_dev->adc_clk = devm_clk_get(&pdev->dev, "adc");
	if (IS_ERR(adc_dev->adc_clk)) {
		dev_err(&pdev->dev, "failed to get the clock\n");
		ret = PTR_ERR(adc_dev->adc_clk);
		goto err_disable_reg;
	}

	ret = clk_prepare_enable(adc_dev->adc_clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable the clock\n");
		goto err_disable_reg;
	}

	adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
	if (!adc_clk_rate) {
		ret = -EINVAL;
		dev_err(&pdev->dev, "null clock rate!\n");
		goto err_disable_clk;
	}

	adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
	adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;

	/*
	 * There is only one register to power-up/power-down the AUX ADC.
	 * If the ADC is shared among multiple CPUs, always power it up here.
	 * If the ADC is used only by the MIPS, power-up/power-down at runtime.
	 */
	if (adc_dev->shared)
		cc10001_adc_power_up(adc_dev);

	/* Setup the ADC channels available on the device */
	ret = cc10001_adc_channel_init(indio_dev, channel_map);
	if (ret < 0)
		goto err_disable_clk;

	mutex_init(&adc_dev->lock);

	ret = iio_triggered_buffer_setup(indio_dev, NULL,
					 &cc10001_adc_trigger_h, NULL);
	if (ret < 0)
		goto err_disable_clk;

	ret = iio_device_register(indio_dev);
	if (ret < 0)
		goto err_cleanup_buffer;

	platform_set_drvdata(pdev, indio_dev);

	return 0;

err_cleanup_buffer:
	iio_triggered_buffer_cleanup(indio_dev);
err_disable_clk:
	clk_disable_unprepare(adc_dev->adc_clk);
err_disable_reg:
	regulator_disable(adc_dev->reg);
	return ret;
}

static int cc10001_adc_remove(struct platform_device *pdev)
{
	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);

	cc10001_adc_power_down(adc_dev);
	iio_device_unregister(indio_dev);
	iio_triggered_buffer_cleanup(indio_dev);
	clk_disable_unprepare(adc_dev->adc_clk);
	regulator_disable(adc_dev->reg);

	return 0;
}

static const struct of_device_id cc10001_adc_dt_ids[] = {
	{ .compatible = "cosmic,10001-adc", },
	{ }
};
MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);

static struct platform_driver cc10001_adc_driver = {
	.driver = {
		.name   = "cc10001-adc",
		.of_match_table = cc10001_adc_dt_ids,
	},
	.probe	= cc10001_adc_probe,
	.remove	= cc10001_adc_remove,
};
module_platform_driver(cc10001_adc_driver);

MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1664f6a5 PM	2	/*
1664f6a5 PM	3	* Copyright (c) 2014-2015 Imagination Technologies Ltd.
1664f6a5 PM	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/delay.h>
	8	#include <linux/err.h>
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/of.h>
	12	#include <linux/of_device.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/regulator/consumer.h>
	15	#include <linux/slab.h>
	16
	17	#include <linux/iio/buffer.h>
	18	#include <linux/iio/iio.h>
	19	#include <linux/iio/sysfs.h>
	20	#include <linux/iio/trigger.h>
	21	#include <linux/iio/trigger_consumer.h>
	22	#include <linux/iio/triggered_buffer.h>
	23
	24	/* Registers */
	25	#define CC10001_ADC_CONFIG 0x00
	26	#define CC10001_ADC_START_CONV BIT(4)
	27	#define CC10001_ADC_MODE_SINGLE_CONV BIT(5)
	28
	29	#define CC10001_ADC_DDATA_OUT 0x04
	30	#define CC10001_ADC_EOC 0x08
	31	#define CC10001_ADC_EOC_SET BIT(0)
	32
	33	#define CC10001_ADC_CHSEL_SAMPLED 0x0c
713276ea NT	34	#define CC10001_ADC_POWER_DOWN 0x10
	35	#define CC10001_ADC_POWER_DOWN_SET BIT(0)
	36
1664f6a5 PM	37	#define CC10001_ADC_DEBUG 0x14
	38	#define CC10001_ADC_DATA_COUNT 0x20
	39
	40	#define CC10001_ADC_DATA_MASK GENMASK(9, 0)
	41	#define CC10001_ADC_NUM_CHANNELS 8
	42	#define CC10001_ADC_CH_MASK GENMASK(2, 0)
	43
	44	#define CC10001_INVALID_SAMPLED 0xffff
	45	#define CC10001_MAX_POLL_COUNT 20
	46
	47	/*
	48	* As per device specification, wait six clock cycles after power-up to
	49	* activate START. Since adding two more clock cycles delay does not
	50	* impact the performance too much, we are adding two additional cycles delay
	51	* intentionally here.
	52	*/
	53	#define CC10001_WAIT_CYCLES 8
	54
	55	struct cc10001_adc_device {
	56	void __iomem *reg_base;
	57	struct clk *adc_clk;
	58	struct regulator *reg;
	59	u16 *buf;
	60
ae354962	61	bool shared;
1664f6a5	62	struct mutex lock;
1664f6a5 PM	63	unsigned int start_delay_ns;
	64	unsigned int eoc_delay_ns;
	65	};
	66
	67	static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
	68	u32 reg, u32 val)
	69	{
	70	writel(val, adc_dev->reg_base + reg);
	71	}
	72
	73	static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
	74	u32 reg)
	75	{
	76	return readl(adc_dev->reg_base + reg);
	77	}
	78
713276ea NT	79	static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev)
	80	{
	81	cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0);
	82	ndelay(adc_dev->start_delay_ns);
	83	}
	84
	85	static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev)
	86	{
	87	cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN,
	88	CC10001_ADC_POWER_DOWN_SET);
	89	}
	90
1664f6a5 PM	91	static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
	92	unsigned int channel)
	93	{
	94	u32 val;
	95
	96	/* Channel selection and mode of operation */
	97	val = (channel & CC10001_ADC_CH_MASK) \| CC10001_ADC_MODE_SINGLE_CONV;
	98	cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
	99
f29b212e	100	udelay(1);
1664f6a5 PM	101	val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
	102	val = val \| CC10001_ADC_START_CONV;
	103	cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
	104	}
	105
	106	static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
	107	unsigned int channel,
	108	unsigned int delay)
	109	{
	110	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
	111	unsigned int poll_count = 0;
	112
	113	while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
	114	CC10001_ADC_EOC_SET)) {
	115
	116	ndelay(delay);
	117	if (poll_count++ == CC10001_MAX_POLL_COUNT)
	118	return CC10001_INVALID_SAMPLED;
	119	}
	120
	121	poll_count = 0;
	122	while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
	123	CC10001_ADC_CH_MASK) != channel) {
	124
	125	ndelay(delay);
	126	if (poll_count++ == CC10001_MAX_POLL_COUNT)
	127	return CC10001_INVALID_SAMPLED;
	128	}
	129
	130	/* Read the 10 bit output register */
	131	return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
	132	CC10001_ADC_DATA_MASK;
	133	}
	134
	135	static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
	136	{
	137	struct cc10001_adc_device *adc_dev;
	138	struct iio_poll_func *pf = p;
	139	struct iio_dev *indio_dev;
	140	unsigned int delay_ns;
	141	unsigned int channel;
13415a99	142	unsigned int scan_idx;
1664f6a5 PM	143	bool sample_invalid;
	144	u16 *data;
	145	int i;
	146
	147	indio_dev = pf->indio_dev;
	148	adc_dev = iio_priv(indio_dev);
	149	data = adc_dev->buf;
	150
	151	mutex_lock(&adc_dev->lock);
	152
ae354962 NT	153	if (!adc_dev->shared)
ae354962 NT	154	cc10001_adc_power_up(adc_dev);
1664f6a5 PM	155
	156	/* Calculate delay step for eoc and sampled data */
	157	delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
	158
	159	i = 0;
	160	sample_invalid = false;
13415a99	161	for_each_set_bit(scan_idx, indio_dev->active_scan_mask,
1664f6a5 PM	162	indio_dev->masklength) {
1664f6a5 PM	163
13415a99	164	channel = indio_dev->channels[scan_idx].channel;
1664f6a5 PM	165	cc10001_adc_start(adc_dev, channel);
	166
	167	data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
	168	if (data[i] == CC10001_INVALID_SAMPLED) {
	169	dev_warn(&indio_dev->dev,
	170	"invalid sample on channel %d\n", channel);
	171	sample_invalid = true;
	172	goto done;
	173	}
	174	i++;
	175	}
	176
	177	done:
ae354962 NT	178	if (!adc_dev->shared)
ae354962 NT	179	cc10001_adc_power_down(adc_dev);
1664f6a5 PM	180
	181	mutex_unlock(&adc_dev->lock);
	182
	183	if (!sample_invalid)
	184	iio_push_to_buffers_with_timestamp(indio_dev, data,
bc2b7dab	185	iio_get_time_ns(indio_dev));
1664f6a5 PM	186	iio_trigger_notify_done(indio_dev->trig);
	187
	188	return IRQ_HANDLED;
	189	}
	190
	191	static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
	192	struct iio_chan_spec const *chan)
	193	{
	194	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
	195	unsigned int delay_ns;
	196	u16 val;
	197
ae354962 NT	198	if (!adc_dev->shared)
ae354962 NT	199	cc10001_adc_power_up(adc_dev);
1664f6a5 PM	200
	201	/* Calculate delay step for eoc and sampled data */
	202	delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
	203
	204	cc10001_adc_start(adc_dev, chan->channel);
	205
	206	val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);
	207
ae354962 NT	208	if (!adc_dev->shared)
ae354962 NT	209	cc10001_adc_power_down(adc_dev);
1664f6a5 PM	210
	211	return val;
	212	}
	213
	214	static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
	215	struct iio_chan_spec const *chan,
	216	int val, int val2, long mask)
	217	{
	218	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
	219	int ret;
	220
	221	switch (mask) {
	222	case IIO_CHAN_INFO_RAW:
	223	if (iio_buffer_enabled(indio_dev))
	224	return -EBUSY;
	225	mutex_lock(&adc_dev->lock);
	226	*val = cc10001_adc_read_raw_voltage(indio_dev, chan);
	227	mutex_unlock(&adc_dev->lock);
	228
	229	if (*val == CC10001_INVALID_SAMPLED)
	230	return -EIO;
	231	return IIO_VAL_INT;
	232
	233	case IIO_CHAN_INFO_SCALE:
	234	ret = regulator_get_voltage(adc_dev->reg);
65a761bf	235	if (ret < 0)
1664f6a5 PM	236	return ret;
	237
	238	*val = ret / 1000;
	239	*val2 = chan->scan_type.realbits;
	240	return IIO_VAL_FRACTIONAL_LOG2;
	241
	242	default:
	243	return -EINVAL;
	244	}
	245	}
	246
	247	static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
	248	const unsigned long *scan_mask)
	249	{
	250	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
	251
	252	kfree(adc_dev->buf);
	253	adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
	254	if (!adc_dev->buf)
	255	return -ENOMEM;
	256
	257	return 0;
	258	}
	259
	260	static const struct iio_info cc10001_adc_info = {
1664f6a5 PM	261	.read_raw = &cc10001_adc_read_raw,
	262	.update_scan_mode = &cc10001_update_scan_mode,
	263	};
	264
13415a99 NT	265	static int cc10001_adc_channel_init(struct iio_dev *indio_dev,
13415a99 NT	266	unsigned long channel_map)
1664f6a5	267	{
1664f6a5 PM	268	struct iio_chan_spec chan_array, timestamp;
	269	unsigned int bit, idx = 0;
	270
13415a99 NT	271	indio_dev->num_channels = bitmap_weight(&channel_map,
13415a99 NT	272	CC10001_ADC_NUM_CHANNELS) + 1;
1664f6a5	273
13415a99	274	chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels,
1664f6a5 PM	275	sizeof(struct iio_chan_spec),
	276	GFP_KERNEL);
	277	if (!chan_array)
	278	return -ENOMEM;
	279
13415a99	280	for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) {
1664f6a5 PM	281	struct iio_chan_spec *chan = &chan_array[idx];
	282
	283	chan->type = IIO_VOLTAGE;
	284	chan->indexed = 1;
	285	chan->channel = bit;
	286	chan->scan_index = idx;
	287	chan->scan_type.sign = 'u';
	288	chan->scan_type.realbits = 10;
	289	chan->scan_type.storagebits = 16;
	290	chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
	291	chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
	292	idx++;
	293	}
	294
	295	timestamp = &chan_array[idx];
	296	timestamp->type = IIO_TIMESTAMP;
	297	timestamp->channel = -1;
	298	timestamp->scan_index = idx;
	299	timestamp->scan_type.sign = 's';
	300	timestamp->scan_type.realbits = 64;
	301	timestamp->scan_type.storagebits = 64;
	302
	303	indio_dev->channels = chan_array;
	304
	305	return 0;
	306	}
	307
	308	static int cc10001_adc_probe(struct platform_device *pdev)
	309	{
	310	struct device_node *node = pdev->dev.of_node;
	311	struct cc10001_adc_device *adc_dev;
	312	unsigned long adc_clk_rate;
1664f6a5	313	struct iio_dev *indio_dev;
13415a99	314	unsigned long channel_map;
1664f6a5 PM	315	int ret;
	316
	317	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
	318	if (indio_dev == NULL)
	319	return -ENOMEM;
	320
	321	adc_dev = iio_priv(indio_dev);
	322
13415a99	323	channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
ae354962 NT	324	if (!of_property_read_u32(node, "adc-reserved-channels", &ret)) {
ae354962 NT	325	adc_dev->shared = true;
13415a99	326	channel_map &= ~ret;
ae354962	327	}
1664f6a5 PM	328
	329	adc_dev->reg = devm_regulator_get(&pdev->dev, "vref");
	330	if (IS_ERR(adc_dev->reg))
	331	return PTR_ERR(adc_dev->reg);
	332
	333	ret = regulator_enable(adc_dev->reg);
	334	if (ret)
	335	return ret;
	336
1664f6a5 PM	337	indio_dev->name = dev_name(&pdev->dev);
	338	indio_dev->info = &cc10001_adc_info;
	339	indio_dev->modes = INDIO_DIRECT_MODE;
	340
46e55d06	341	adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0);
1664f6a5 PM	342	if (IS_ERR(adc_dev->reg_base)) {
	343	ret = PTR_ERR(adc_dev->reg_base);
	344	goto err_disable_reg;
	345	}
	346
	347	adc_dev->adc_clk = devm_clk_get(&pdev->dev, "adc");
	348	if (IS_ERR(adc_dev->adc_clk)) {
	349	dev_err(&pdev->dev, "failed to get the clock\n");
	350	ret = PTR_ERR(adc_dev->adc_clk);
	351	goto err_disable_reg;
	352	}
	353
	354	ret = clk_prepare_enable(adc_dev->adc_clk);
	355	if (ret) {
	356	dev_err(&pdev->dev, "failed to enable the clock\n");
	357	goto err_disable_reg;
	358	}
	359
	360	adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
	361	if (!adc_clk_rate) {
	362	ret = -EINVAL;
	363	dev_err(&pdev->dev, "null clock rate!\n");
	364	goto err_disable_clk;
	365	}
	366
	367	adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
	368	adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;
	369
ae354962 NT	370	/*
	371	* There is only one register to power-up/power-down the AUX ADC.
	372	* If the ADC is shared among multiple CPUs, always power it up here.
	373	* If the ADC is used only by the MIPS, power-up/power-down at runtime.
	374	*/
	375	if (adc_dev->shared)
	376	cc10001_adc_power_up(adc_dev);
	377
1664f6a5	378	/* Setup the ADC channels available on the device */
13415a99	379	ret = cc10001_adc_channel_init(indio_dev, channel_map);
1664f6a5 PM	380	if (ret < 0)
	381	goto err_disable_clk;
	382
	383	mutex_init(&adc_dev->lock);
	384
	385	ret = iio_triggered_buffer_setup(indio_dev, NULL,
	386	&cc10001_adc_trigger_h, NULL);
	387	if (ret < 0)
	388	goto err_disable_clk;
	389
	390	ret = iio_device_register(indio_dev);
	391	if (ret < 0)
	392	goto err_cleanup_buffer;
	393
	394	platform_set_drvdata(pdev, indio_dev);
	395
	396	return 0;
	397
	398	err_cleanup_buffer:
	399	iio_triggered_buffer_cleanup(indio_dev);
	400	err_disable_clk:
	401	clk_disable_unprepare(adc_dev->adc_clk);
	402	err_disable_reg:
	403	regulator_disable(adc_dev->reg);
	404	return ret;
	405	}
	406
	407	static int cc10001_adc_remove(struct platform_device *pdev)
	408	{
	409	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
	410	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
	411
ae354962	412	cc10001_adc_power_down(adc_dev);
1664f6a5 PM	413	iio_device_unregister(indio_dev);
	414	iio_triggered_buffer_cleanup(indio_dev);
	415	clk_disable_unprepare(adc_dev->adc_clk);
	416	regulator_disable(adc_dev->reg);
	417
	418	return 0;
	419	}
	420
	421	static const struct of_device_id cc10001_adc_dt_ids[] = {
	422	{ .compatible = "cosmic,10001-adc", },
	423	{ }
	424	};
	425	MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);
	426
	427	static struct platform_driver cc10001_adc_driver = {
	428	.driver = {
	429	.name = "cc10001-adc",
	430	.of_match_table = cc10001_adc_dt_ids,
	431	},
	432	.probe = cc10001_adc_probe,
	433	.remove = cc10001_adc_remove,
	434	};
	435	module_platform_driver(cc10001_adc_driver);
	436
	437	MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
	438	MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
	439	MODULE_LICENSE("GPL v2");