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[linux-2.6-block.git] / drivers / iio / adc / at91_adc.c
CommitLineData
0e589d5f
MR		 1/*
2 * Driver for the ADC present in the Atmel AT91 evaluation boards.
3 *
4 * Copyright 2011 Free Electrons
5 *
6 * Licensed under the GPLv2 or later.
7 */
8
9#include <linux/bitmap.h>
10#include <linux/bitops.h>
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/io.h>
c8b11de0 14#include <linux/input.h>
0e589d5f
MR		 15#include <linux/interrupt.h>
16#include <linux/jiffies.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
e364185f
MR		 19#include <linux/of.h>
20#include <linux/of_device.h>
0e589d5f
MR		 21#include <linux/platform_device.h>
22#include <linux/sched.h>
23#include <linux/slab.h>
24#include <linux/wait.h>
25
26#include <linux/platform_data/at91_adc.h>
27
28#include <linux/iio/iio.h>
29#include <linux/iio/buffer.h>
0e589d5f
MR		 30#include <linux/iio/trigger.h>
31#include <linux/iio/trigger_consumer.h>
90032e4e 32#include <linux/iio/triggered_buffer.h>
0e589d5f 33
bee20c4b
AB		 34/* Registers */
35#define AT91_ADC_CR 0x00 /* Control Register */
36#define AT91_ADC_SWRST (1 << 0) /* Software Reset */
37#define AT91_ADC_START (1 << 1) /* Start Conversion */
38
39#define AT91_ADC_MR 0x04 /* Mode Register */
40#define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
41#define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
42#define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
43#define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
44#define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
45#define AT91_ADC_TRGSEL_TC0 (0 << 1)
46#define AT91_ADC_TRGSEL_TC1 (1 << 1)
47#define AT91_ADC_TRGSEL_TC2 (2 << 1)
48#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
49#define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
50#define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
51#define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
52#define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
53#define AT91_ADC_PRESCAL_9G45 (0xff << 8)
54#define AT91_ADC_PRESCAL_(x) ((x) << 8)
55#define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
56#define AT91_ADC_STARTUP_9G45 (0x7f << 16)
57#define AT91_ADC_STARTUP_9X5 (0xf << 16)
58#define AT91_ADC_STARTUP_(x) ((x) << 16)
59#define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
60#define AT91_ADC_SHTIM_(x) ((x) << 24)
61#define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
62#define AT91_ADC_PENDBC_(x) ((x) << 28)
63
64#define AT91_ADC_TSR 0x0C
65#define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
66#define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
67
68#define AT91_ADC_CHER 0x10 /* Channel Enable Register */
69#define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
70#define AT91_ADC_CHSR 0x18 /* Channel Status Register */
71#define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
72
73#define AT91_ADC_SR 0x1C /* Status Register */
74#define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
75#define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
76#define AT91_ADC_DRDY (1 << 16) /* Data Ready */
77#define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
78#define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
79#define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
80
81#define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
82#define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
83
84#define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
85#define AT91_ADC_LDATA (0x3ff)
86
87#define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
88#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
89#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
90#define AT91RL_ADC_IER_PEN (1 << 20)
91#define AT91RL_ADC_IER_NOPEN (1 << 21)
92#define AT91_ADC_IER_PEN (1 << 29)
93#define AT91_ADC_IER_NOPEN (1 << 30)
94#define AT91_ADC_IER_XRDY (1 << 20)
95#define AT91_ADC_IER_YRDY (1 << 21)
96#define AT91_ADC_IER_PRDY (1 << 22)
97#define AT91_ADC_ISR_PENS (1 << 31)
98
99#define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
100#define AT91_ADC_DATA (0x3ff)
101
102#define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
103
104#define AT91_ADC_ACR 0x94 /* Analog Control Register */
105#define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
106
107#define AT91_ADC_TSMR 0xB0
108#define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
109#define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
110#define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
111#define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
112#define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
113#define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
114#define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
115#define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
116#define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
117#define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
118#define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
119#define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
120#define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
121
122#define AT91_ADC_TSXPOSR 0xB4
123#define AT91_ADC_TSYPOSR 0xB8
124#define AT91_ADC_TSPRESSR 0xBC
125
126#define AT91_ADC_TRGR_9260 AT91_ADC_MR
127#define AT91_ADC_TRGR_9G45 0x08
128#define AT91_ADC_TRGR_9X5 0xC0
129
130/* Trigger Register bit field */
131#define AT91_ADC_TRGR_TRGPER (0xffff << 16)
132#define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
133#define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
134#define AT91_ADC_TRGR_NONE (0 << 0)
135#define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
0e589d5f
MR		 136
137#define AT91_ADC_CHAN(st, ch) \
138 (st->registers->channel_base + (ch * 4))
139#define at91_adc_readl(st, reg) \
140 (readl_relaxed(st->reg_base + reg))
141#define at91_adc_writel(st, reg, val) \
142 (writel_relaxed(val, st->reg_base + reg))
143
c8b11de0
JW		 144#define DRIVER_NAME "at91_adc"
145#define MAX_POS_BITS 12
146
147#define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
148#define TOUCH_PEN_DETECT_DEBOUNCE_US 200
149
84882b06
AB		 150#define MAX_RLPOS_BITS 10
151#define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
152#define TOUCH_SHTIM 0xa
153
2de0c019
AB		 154/**
155 * struct at91_adc_reg_desc - Various informations relative to registers
156 * @channel_base: Base offset for the channel data registers
157 * @drdy_mask: Mask of the DRDY field in the relevant registers
158 (Interruptions registers mostly)
159 * @status_register: Offset of the Interrupt Status Register
160 * @trigger_register: Offset of the Trigger setup register
161 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
162 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
163 */
164struct at91_adc_reg_desc {
165 u8 channel_base;
166 u32 drdy_mask;
167 u8 status_register;
168 u8 trigger_register;
169 u32 mr_prescal_mask;
170 u32 mr_startup_mask;
171};
172
e1811f97 173struct at91_adc_caps {
c8b11de0
JW		 174 bool has_ts; /* Support touch screen */
175 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
176 /*
177 * Numbers of sampling data will be averaged. Can be 0~3.
178 * Hardware can average (2 ^ ts_filter_average) sample data.
179 */
180 u8 ts_filter_average;
181 /* Pen Detection input pull-up resistor, can be 0~3 */
182 u8 ts_pen_detect_sensitivity;
183
c4601666
JW		 184 /* startup time calculate function */
185 u32 (*calc_startup_ticks)(u8 startup_time, u32 adc_clk_khz);
186
2b6d598b 187 u8 num_channels;
e1811f97
JW		 188 struct at91_adc_reg_desc registers;
189};
190
0e589d5f
MR		 191struct at91_adc_state {
192 struct clk *adc_clk;
193 u16 *buffer;
194 unsigned long channels_mask;
195 struct clk *clk;
196 bool done;
197 int irq;
0e589d5f
MR		 198 u16 last_value;
199 struct mutex lock;
200 u8 num_channels;
201 void __iomem *reg_base;
202 struct at91_adc_reg_desc *registers;
203 u8 startup_time;
beca9e76 204 u8 sample_hold_time;
e748783c 205 bool sleep_mode;
0e589d5f
MR		 206 struct iio_trigger **trig;
207 struct at91_adc_trigger *trigger_list;
208 u32 trigger_number;
209 bool use_external;
210 u32 vref_mv;
47be16b6
LD		 211 u32 res; /* resolution used for convertions */
212 bool low_res; /* the resolution corresponds to the lowest one */
0e589d5f 213 wait_queue_head_t wq_data_avail;
e1811f97 214 struct at91_adc_caps *caps;
c8b11de0
JW		 215
216 /*
217 * Following ADC channels are shared by touchscreen:
218 *
219 * CH0 -- Touch screen XP/UL
220 * CH1 -- Touch screen XM/UR
221 * CH2 -- Touch screen YP/LL
222 * CH3 -- Touch screen YM/Sense
223 * CH4 -- Touch screen LR(5-wire only)
224 *
225 * The bitfields below represents the reserved channel in the
226 * touchscreen mode.
227 */
228#define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
229#define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
230 enum atmel_adc_ts_type touchscreen_type;
231 struct input_dev *ts_input;
232
233 u16 ts_sample_period_val;
234 u32 ts_pressure_threshold;
84882b06
AB		 235 u16 ts_pendbc;
236
237 bool ts_bufferedmeasure;
238 u32 ts_prev_absx;
239 u32 ts_prev_absy;
0e589d5f
MR		 240};
241
242static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
243{
244 struct iio_poll_func *pf = p;
245 struct iio_dev *idev = pf->indio_dev;
246 struct at91_adc_state *st = iio_priv(idev);
0e589d5f
MR		 247 int i, j = 0;
248
249 for (i = 0; i < idev->masklength; i++) {
250 if (!test_bit(i, idev->active_scan_mask))
251 continue;
252 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i));
253 j++;
254 }
255
e79cece0 256 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
0e589d5f
MR		 257
258 iio_trigger_notify_done(idev->trig);
0e589d5f
MR		 259
260 /* Needed to ACK the DRDY interruption */
261 at91_adc_readl(st, AT91_ADC_LCDR);
262
263 enable_irq(st->irq);
264
265 return IRQ_HANDLED;
266}
267
c8b11de0
JW		 268/* Handler for classic adc channel eoc trigger */
269void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
0e589d5f 270{
0e589d5f 271 struct at91_adc_state *st = iio_priv(idev);
0e589d5f
MR		 272
273 if (iio_buffer_enabled(idev)) {
274 disable_irq_nosync(irq);
0e589d5f
MR		 275 iio_trigger_poll(idev->trig, iio_get_time_ns());
276 } else {
277 st->last_value = at91_adc_readl(st, AT91_ADC_LCDR);
278 st->done = true;
279 wake_up_interruptible(&st->wq_data_avail);
280 }
c8b11de0
JW		 281}
282
283static int at91_ts_sample(struct at91_adc_state *st)
284{
285 unsigned int xscale, yscale, reg, z1, z2;
286 unsigned int x, y, pres, xpos, ypos;
287 unsigned int rxp = 1;
288 unsigned int factor = 1000;
289 struct iio_dev *idev = iio_priv_to_dev(st);
290
291 unsigned int xyz_mask_bits = st->res;
292 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
293
294 /* calculate position */
295 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
296 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
297 xpos = reg & xyz_mask;
298 x = (xpos << MAX_POS_BITS) - xpos;
299 xscale = (reg >> 16) & xyz_mask;
300 if (xscale == 0) {
301 dev_err(&idev->dev, "Error: xscale == 0!\n");
302 return -1;
303 }
304 x /= xscale;
305
306 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
307 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
308 ypos = reg & xyz_mask;
309 y = (ypos << MAX_POS_BITS) - ypos;
310 yscale = (reg >> 16) & xyz_mask;
311 if (yscale == 0) {
312 dev_err(&idev->dev, "Error: yscale == 0!\n");
313 return -1;
314 }
315 y /= yscale;
316
317 /* calculate the pressure */
318 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
319 z1 = reg & xyz_mask;
320 z2 = (reg >> 16) & xyz_mask;
321
322 if (z1 != 0)
323 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
324 / factor;
325 else
326 pres = st->ts_pressure_threshold; /* no pen contacted */
327
328 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
329 xpos, xscale, ypos, yscale, z1, z2, pres);
330
331 if (pres < st->ts_pressure_threshold) {
332 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
333 x, y, pres / factor);
334 input_report_abs(st->ts_input, ABS_X, x);
335 input_report_abs(st->ts_input, ABS_Y, y);
336 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
337 input_report_key(st->ts_input, BTN_TOUCH, 1);
338 input_sync(st->ts_input);
339 } else {
340 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
341 }
342
343 return 0;
344}
345
84882b06
AB		 346static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
347{
348 struct iio_dev *idev = private;
349 struct at91_adc_state *st = iio_priv(idev);
350 u32 status = at91_adc_readl(st, st->registers->status_register);
351 unsigned int reg;
352
353 status &= at91_adc_readl(st, AT91_ADC_IMR);
354 if (status & st->registers->drdy_mask)
355 handle_adc_eoc_trigger(irq, idev);
356
357 if (status & AT91RL_ADC_IER_PEN) {
358 /* Disabling pen debounce is required to get a NOPEN irq */
359 reg = at91_adc_readl(st, AT91_ADC_MR);
360 reg &= ~AT91_ADC_PENDBC;
361 at91_adc_writel(st, AT91_ADC_MR, reg);
362
363 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
364 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
365 | AT91_ADC_EOC(3));
366 /* Set up period trigger for sampling */
367 at91_adc_writel(st, st->registers->trigger_register,
368 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
369 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
370 } else if (status & AT91RL_ADC_IER_NOPEN) {
371 reg = at91_adc_readl(st, AT91_ADC_MR);
372 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
373 at91_adc_writel(st, AT91_ADC_MR, reg);
374 at91_adc_writel(st, st->registers->trigger_register,
375 AT91_ADC_TRGR_NONE);
376
377 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
378 | AT91_ADC_EOC(3));
379 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
380 st->ts_bufferedmeasure = false;
381 input_report_key(st->ts_input, BTN_TOUCH, 0);
382 input_sync(st->ts_input);
383 } else if (status & AT91_ADC_EOC(3)) {
384 /* Conversion finished */
385 if (st->ts_bufferedmeasure) {
386 /*
387 * Last measurement is always discarded, since it can
388 * be erroneous.
389 * Always report previous measurement
390 */
391 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
392 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
393 input_report_key(st->ts_input, BTN_TOUCH, 1);
394 input_sync(st->ts_input);
395 } else
396 st->ts_bufferedmeasure = true;
397
398 /* Now make new measurement */
399 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
400 << MAX_RLPOS_BITS;
401 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
402
403 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
404 << MAX_RLPOS_BITS;
405 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
406 }
407
408 return IRQ_HANDLED;
409}
410
411static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
c8b11de0
JW		 412{
413 struct iio_dev *idev = private;
414 struct at91_adc_state *st = iio_priv(idev);
415 u32 status = at91_adc_readl(st, st->registers->status_register);
416 const uint32_t ts_data_irq_mask =
417 AT91_ADC_IER_XRDY |
418 AT91_ADC_IER_YRDY |
419 AT91_ADC_IER_PRDY;
420
421 if (status & st->registers->drdy_mask)
422 handle_adc_eoc_trigger(irq, idev);
423
424 if (status & AT91_ADC_IER_PEN) {
425 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
426 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
427 ts_data_irq_mask);
428 /* Set up period trigger for sampling */
429 at91_adc_writel(st, st->registers->trigger_register,
430 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
431 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
432 } else if (status & AT91_ADC_IER_NOPEN) {
433 at91_adc_writel(st, st->registers->trigger_register, 0);
434 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
435 ts_data_irq_mask);
436 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
437
438 input_report_key(st->ts_input, BTN_TOUCH, 0);
439 input_sync(st->ts_input);
440 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
441 /* Now all touchscreen data is ready */
442
443 if (status & AT91_ADC_ISR_PENS) {
444 /* validate data by pen contact */
445 at91_ts_sample(st);
446 } else {
447 /* triggered by event that is no pen contact, just read
448 * them to clean the interrupt and discard all.
449 */
450 at91_adc_readl(st, AT91_ADC_TSXPOSR);
451 at91_adc_readl(st, AT91_ADC_TSYPOSR);
452 at91_adc_readl(st, AT91_ADC_TSPRESSR);
453 }
454 }
0e589d5f
MR		 455
456 return IRQ_HANDLED;
457}
458
459static int at91_adc_channel_init(struct iio_dev *idev)
460{
461 struct at91_adc_state *st = iio_priv(idev);
462 struct iio_chan_spec *chan_array, *timestamp;
463 int bit, idx = 0;
c8b11de0
JW		 464 unsigned long rsvd_mask = 0;
465
466 /* If touchscreen is enable, then reserve the adc channels */
467 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
468 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
469 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
470 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
471
472 /* set up the channel mask to reserve touchscreen channels */
473 st->channels_mask &= ~rsvd_mask;
0e589d5f
MR		 474
475 idev->num_channels = bitmap_weight(&st->channels_mask,
476 st->num_channels) + 1;
477
6b3aa313
AL		 478 chan_array = devm_kzalloc(&idev->dev,
479 ((idev->num_channels + 1) *
480 sizeof(struct iio_chan_spec)),
481 GFP_KERNEL);
0e589d5f
MR		 482
483 if (!chan_array)
484 return -ENOMEM;
485
486 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
487 struct iio_chan_spec *chan = chan_array + idx;
488
489 chan->type = IIO_VOLTAGE;
490 chan->indexed = 1;
491 chan->channel = bit;
492 chan->scan_index = idx;
493 chan->scan_type.sign = 'u';
47be16b6 494 chan->scan_type.realbits = st->res;
0e589d5f 495 chan->scan_type.storagebits = 16;
01bdab66
JC		 496 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
497 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
0e589d5f
MR		 498 idx++;
499 }
500 timestamp = chan_array + idx;
501
502 timestamp->type = IIO_TIMESTAMP;
503 timestamp->channel = -1;
504 timestamp->scan_index = idx;
505 timestamp->scan_type.sign = 's';
506 timestamp->scan_type.realbits = 64;
507 timestamp->scan_type.storagebits = 64;
508
509 idev->channels = chan_array;
510 return idev->num_channels;
511}
512
4f3bcd87 513static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
0e589d5f
MR		 514 struct at91_adc_trigger *triggers,
515 const char *trigger_name)
516{
517 struct at91_adc_state *st = iio_priv(idev);
0e589d5f
MR		 518 int i;
519
520 for (i = 0; i < st->trigger_number; i++) {
521 char *name = kasprintf(GFP_KERNEL,
522 "%s-dev%d-%s",
523 idev->name,
524 idev->id,
525 triggers[i].name);
526 if (!name)
527 return -ENOMEM;
528
529 if (strcmp(trigger_name, name) == 0) {
0e589d5f 530 kfree(name);
4f3bcd87
DC		 531 if (triggers[i].value == 0)
532 return -EINVAL;
533 return triggers[i].value;
0e589d5f
MR		 534 }
535
536 kfree(name);
537 }
538
4f3bcd87 539 return -EINVAL;
0e589d5f
MR		 540}
541
542static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
543{
1e9663c6 544 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
0e589d5f
MR		 545 struct at91_adc_state *st = iio_priv(idev);
546 struct iio_buffer *buffer = idev->buffer;
547 struct at91_adc_reg_desc *reg = st->registers;
548 u32 status = at91_adc_readl(st, reg->trigger_register);
4f3bcd87 549 int value;
0e589d5f
MR		 550 u8 bit;
551
552 value = at91_adc_get_trigger_value_by_name(idev,
553 st->trigger_list,
554 idev->trig->name);
4f3bcd87
DC		 555 if (value < 0)
556 return value;
0e589d5f
MR		 557
558 if (state) {
559 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
560 if (st->buffer == NULL)
561 return -ENOMEM;
562
563 at91_adc_writel(st, reg->trigger_register,
564 status | value);
565
566 for_each_set_bit(bit, buffer->scan_mask,
567 st->num_channels) {
568 struct iio_chan_spec const *chan = idev->channels + bit;
569 at91_adc_writel(st, AT91_ADC_CHER,
570 AT91_ADC_CH(chan->channel));
571 }
572
573 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
574
575 } else {
576 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
577
578 at91_adc_writel(st, reg->trigger_register,
579 status & ~value);
580
581 for_each_set_bit(bit, buffer->scan_mask,
582 st->num_channels) {
583 struct iio_chan_spec const *chan = idev->channels + bit;
584 at91_adc_writel(st, AT91_ADC_CHDR,
585 AT91_ADC_CH(chan->channel));
586 }
587 kfree(st->buffer);
588 }
589
590 return 0;
591}
592
593static const struct iio_trigger_ops at91_adc_trigger_ops = {
594 .owner = THIS_MODULE,
595 .set_trigger_state = &at91_adc_configure_trigger,
596};
597
598static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
599 struct at91_adc_trigger *trigger)
600{
601 struct iio_trigger *trig;
602 int ret;
603
604 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
605 idev->id, trigger->name);
606 if (trig == NULL)
607 return NULL;
608
609 trig->dev.parent = idev->dev.parent;
1e9663c6 610 iio_trigger_set_drvdata(trig, idev);
0e589d5f
MR		 611 trig->ops = &at91_adc_trigger_ops;
612
613 ret = iio_trigger_register(trig);
614 if (ret)
615 return NULL;
616
617 return trig;
618}
619
620static int at91_adc_trigger_init(struct iio_dev *idev)
621{
622 struct at91_adc_state *st = iio_priv(idev);
623 int i, ret;
624
6b3aa313 625 st->trig = devm_kzalloc(&idev->dev,
42877236 626 st->trigger_number * sizeof(*st->trig),
6b3aa313 627 GFP_KERNEL);
0e589d5f
MR		 628
629 if (st->trig == NULL) {
630 ret = -ENOMEM;
631 goto error_ret;
632 }
633
634 for (i = 0; i < st->trigger_number; i++) {
635 if (st->trigger_list[i].is_external && !(st->use_external))
636 continue;
637
638 st->trig[i] = at91_adc_allocate_trigger(idev,
639 st->trigger_list + i);
640 if (st->trig[i] == NULL) {
641 dev_err(&idev->dev,
642 "Could not allocate trigger %d\n", i);
643 ret = -ENOMEM;
644 goto error_trigger;
645 }
646 }
647
648 return 0;
649
650error_trigger:
651 for (i--; i >= 0; i--) {
652 iio_trigger_unregister(st->trig[i]);
653 iio_trigger_free(st->trig[i]);
654 }
655error_ret:
656 return ret;
657}
658
659static void at91_adc_trigger_remove(struct iio_dev *idev)
660{
661 struct at91_adc_state *st = iio_priv(idev);
662 int i;
663
664 for (i = 0; i < st->trigger_number; i++) {
665 iio_trigger_unregister(st->trig[i]);
666 iio_trigger_free(st->trig[i]);
667 }
668}
669
0e589d5f
MR		 670static int at91_adc_buffer_init(struct iio_dev *idev)
671{
90032e4e
LPC		 672 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
673 &at91_adc_trigger_handler, NULL);
0e589d5f
MR		 674}
675
676static void at91_adc_buffer_remove(struct iio_dev *idev)
677{
90032e4e 678 iio_triggered_buffer_cleanup(idev);
0e589d5f
MR		 679}
680
681static int at91_adc_read_raw(struct iio_dev *idev,
682 struct iio_chan_spec const *chan,
683 int *val, int *val2, long mask)
684{
685 struct at91_adc_state *st = iio_priv(idev);
686 int ret;
687
688 switch (mask) {
689 case IIO_CHAN_INFO_RAW:
690 mutex_lock(&st->lock);
691
692 at91_adc_writel(st, AT91_ADC_CHER,
693 AT91_ADC_CH(chan->channel));
694 at91_adc_writel(st, AT91_ADC_IER, st->registers->drdy_mask);
695 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
696
697 ret = wait_event_interruptible_timeout(st->wq_data_avail,
698 st->done,
699 msecs_to_jiffies(1000));
700 if (ret == 0)
90e6dc7c
LPC		 701 ret = -ETIMEDOUT;
702 if (ret < 0) {
703 mutex_unlock(&st->lock);
0e589d5f 704 return ret;
90e6dc7c 705 }
0e589d5f
MR		 706
707 *val = st->last_value;
708
709 at91_adc_writel(st, AT91_ADC_CHDR,
710 AT91_ADC_CH(chan->channel));
711 at91_adc_writel(st, AT91_ADC_IDR, st->registers->drdy_mask);
712
713 st->last_value = 0;
714 st->done = false;
715 mutex_unlock(&st->lock);
716 return IIO_VAL_INT;
717
718 case IIO_CHAN_INFO_SCALE:
c45e561e
LPC		 719 *val = st->vref_mv;
720 *val2 = chan->scan_type.realbits;
721 return IIO_VAL_FRACTIONAL_LOG2;
0e589d5f
MR		 722 default:
723 break;
724 }
725 return -EINVAL;
726}
727
47be16b6
LD		 728static int at91_adc_of_get_resolution(struct at91_adc_state *st,
729 struct platform_device *pdev)
730{
731 struct iio_dev *idev = iio_priv_to_dev(st);
732 struct device_node *np = pdev->dev.of_node;
733 int count, i, ret = 0;
734 char *res_name, *s;
735 u32 *resolutions;
736
737 count = of_property_count_strings(np, "atmel,adc-res-names");
738 if (count < 2) {
739 dev_err(&idev->dev, "You must specified at least two resolution names for "
740 "adc-res-names property in the DT\n");
741 return count;
742 }
743
744 resolutions = kmalloc(count * sizeof(*resolutions), GFP_KERNEL);
745 if (!resolutions)
746 return -ENOMEM;
747
748 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
749 dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
750 ret = -ENODEV;
751 goto ret;
752 }
753
754 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
755 res_name = "highres";
756
757 for (i = 0; i < count; i++) {
758 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
759 continue;
760
761 if (strcmp(res_name, s))
762 continue;
763
764 st->res = resolutions[i];
765 if (!strcmp(res_name, "lowres"))
766 st->low_res = true;
767 else
768 st->low_res = false;
769
770 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
771 goto ret;
772 }
773
774 dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
775
776ret:
777 kfree(resolutions);
778 return ret;
779}
780
c4601666
JW		 781static u32 calc_startup_ticks_9260(u8 startup_time, u32 adc_clk_khz)
782{
783 /*
784 * Number of ticks needed to cover the startup time of the ADC
785 * as defined in the electrical characteristics of the board,
786 * divided by 8. The formula thus is :
787 * Startup Time = (ticks + 1) * 8 / ADC Clock
788 */
789 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
790}
791
792static u32 calc_startup_ticks_9x5(u8 startup_time, u32 adc_clk_khz)
793{
794 /*
795 * For sama5d3x and at91sam9x5, the formula changes to:
796 * Startup Time = <lookup_table_value> / ADC Clock
797 */
798 const int startup_lookup[] = {
799 0 , 8 , 16 , 24 ,
800 64 , 80 , 96 , 112,
801 512, 576, 640, 704,
802 768, 832, 896, 960
803 };
804 int i, size = ARRAY_SIZE(startup_lookup);
805 unsigned int ticks;
806
807 ticks = startup_time * adc_clk_khz / 1000;
808 for (i = 0; i < size; i++)
809 if (ticks < startup_lookup[i])
810 break;
811
812 ticks = i;
813 if (ticks == size)
814 /* Reach the end of lookup table */
815 ticks = size - 1;
816
817 return ticks;
818}
819
e1811f97
JW		 820static const struct of_device_id at91_adc_dt_ids[];
821
c8b11de0
JW		 822static int at91_adc_probe_dt_ts(struct device_node *node,
823 struct at91_adc_state *st, struct device *dev)
824{
825 int ret;
826 u32 prop;
827
828 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
829 if (ret) {
830 dev_info(dev, "ADC Touch screen is disabled.\n");
831 return 0;
832 }
833
834 switch (prop) {
835 case 4:
836 case 5:
837 st->touchscreen_type = prop;
838 break;
839 default:
840 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
841 return -EINVAL;
842 }
843
84882b06
AB		 844 if (!st->caps->has_tsmr)
845 return 0;
c8b11de0
JW		 846 prop = 0;
847 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
848 st->ts_pressure_threshold = prop;
849 if (st->ts_pressure_threshold) {
850 return 0;
851 } else {
852 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
853 return -EINVAL;
854 }
855}
856
e364185f
MR		 857static int at91_adc_probe_dt(struct at91_adc_state *st,
858 struct platform_device *pdev)
859{
860 struct iio_dev *idev = iio_priv_to_dev(st);
861 struct device_node *node = pdev->dev.of_node;
862 struct device_node *trig_node;
863 int i = 0, ret;
864 u32 prop;
865
866 if (!node)
867 return -EINVAL;
868
e1811f97
JW		 869 st->caps = (struct at91_adc_caps *)
870 of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
871
e364185f
MR		 872 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
873
874 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
875 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
876 ret = -EINVAL;
877 goto error_ret;
878 }
879 st->channels_mask = prop;
880
e748783c
JCPV		 881 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
882
e364185f
MR		 883 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
884 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
885 ret = -EINVAL;
886 goto error_ret;
887 }
888 st->startup_time = prop;
889
beca9e76
JCPV		 890 prop = 0;
891 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
892 st->sample_hold_time = prop;
e364185f
MR		 893
894 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
895 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
896 ret = -EINVAL;
897 goto error_ret;
898 }
899 st->vref_mv = prop;
900
47be16b6
LD		 901 ret = at91_adc_of_get_resolution(st, pdev);
902 if (ret)
903 goto error_ret;
904
e1811f97 905 st->registers = &st->caps->registers;
2b6d598b 906 st->num_channels = st->caps->num_channels;
e364185f 907 st->trigger_number = of_get_child_count(node);
6b3aa313
AL		 908 st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
909 sizeof(struct at91_adc_trigger),
910 GFP_KERNEL);
e364185f
MR		 911 if (!st->trigger_list) {
912 dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
913 ret = -ENOMEM;
914 goto error_ret;
915 }
916
917 for_each_child_of_node(node, trig_node) {
918 struct at91_adc_trigger *trig = st->trigger_list + i;
919 const char *name;
920
921 if (of_property_read_string(trig_node, "trigger-name", &name)) {
922 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
923 ret = -EINVAL;
924 goto error_ret;
925 }
926 trig->name = name;
927
928 if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
929 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
930 ret = -EINVAL;
931 goto error_ret;
932 }
933 trig->value = prop;
934 trig->is_external = of_property_read_bool(trig_node, "trigger-external");
935 i++;
936 }
937
c8b11de0
JW		 938 /* Check if touchscreen is supported. */
939 if (st->caps->has_ts)
940 return at91_adc_probe_dt_ts(node, st, &idev->dev);
941 else
942 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
943
e364185f
MR		 944 return 0;
945
946error_ret:
947 return ret;
948}
949
0e589d5f
MR		 950static int at91_adc_probe_pdata(struct at91_adc_state *st,
951 struct platform_device *pdev)
952{
953 struct at91_adc_data *pdata = pdev->dev.platform_data;
954
955 if (!pdata)
956 return -EINVAL;
957
467a44b0
AB		 958 st->caps = (struct at91_adc_caps *)
959 platform_get_device_id(pdev)->driver_data;
960
0e589d5f
MR		 961 st->use_external = pdata->use_external_triggers;
962 st->vref_mv = pdata->vref;
963 st->channels_mask = pdata->channels_used;
467a44b0 964 st->num_channels = st->caps->num_channels;
0e589d5f
MR		 965 st->startup_time = pdata->startup_time;
966 st->trigger_number = pdata->trigger_number;
967 st->trigger_list = pdata->trigger_list;
467a44b0 968 st->registers = &st->caps->registers;
84882b06 969 st->touchscreen_type = pdata->touchscreen_type;
0e589d5f
MR		 970
971 return 0;
972}
973
974static const struct iio_info at91_adc_info = {
975 .driver_module = THIS_MODULE,
976 .read_raw = &at91_adc_read_raw,
977};
978
c8b11de0
JW		 979/* Touchscreen related functions */
980static int atmel_ts_open(struct input_dev *dev)
981{
982 struct at91_adc_state *st = input_get_drvdata(dev);
983
84882b06
AB		 984 if (st->caps->has_tsmr)
985 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
986 else
987 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
c8b11de0
JW		 988 return 0;
989}
990
991static void atmel_ts_close(struct input_dev *dev)
992{
993 struct at91_adc_state *st = input_get_drvdata(dev);
994
84882b06
AB		 995 if (st->caps->has_tsmr)
996 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
997 else
998 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
c8b11de0
JW		 999}
1000
1001static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
1002{
84882b06 1003 u32 reg = 0;
c8b11de0
JW		 1004 int i = 0;
1005
c8b11de0
JW		 1006 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
1007 * pen detect noise.
1008 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
1009 */
84882b06
AB		 1010 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1011 1000, 1);
c8b11de0 1012
84882b06 1013 while (st->ts_pendbc >> ++i)
c8b11de0 1014 ; /* Empty! Find the shift offset */
84882b06
AB		 1015 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1016 st->ts_pendbc = i;
c8b11de0 1017 else
84882b06 1018 st->ts_pendbc = i - 1;
c8b11de0 1019
84882b06
AB		 1020 if (!st->caps->has_tsmr) {
1021 reg = at91_adc_readl(st, AT91_ADC_MR);
1022 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1023
1024 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1025 at91_adc_writel(st, AT91_ADC_MR, reg);
1026
1027 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1028 at91_adc_writel(st, AT91_ADC_TSR, reg);
1029
1030 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1031 adc_clk_khz / 1000) - 1, 1);
1032
1033 return 0;
c8b11de0
JW		 1034 }
1035
84882b06
AB		 1036 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1037 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1038 else
1039 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1040
1041 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1042 & AT91_ADC_TSMR_TSAV;
1043 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1044 reg |= AT91_ADC_TSMR_NOTSDMA;
1045 reg |= AT91_ADC_TSMR_PENDET_ENA;
1046 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
1047
1048 at91_adc_writel(st, AT91_ADC_TSMR, reg);
1049
c8b11de0
JW		 1050 /* Change adc internal resistor value for better pen detection,
1051 * default value is 100 kOhm.
1052 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
1053 * option only available on ES2 and higher
1054 */
1055 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1056 & AT91_ADC_ACR_PENDETSENS);
1057
84882b06 1058 /* Sample Period Time = (TRGPER + 1) / ADCClock */
c8b11de0
JW		 1059 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1060 adc_clk_khz / 1000) - 1, 1);
1061
1062 return 0;
1063}
1064
1065static int at91_ts_register(struct at91_adc_state *st,
1066 struct platform_device *pdev)
1067{
1068 struct input_dev *input;
1069 struct iio_dev *idev = iio_priv_to_dev(st);
1070 int ret;
1071
1072 input = input_allocate_device();
1073 if (!input) {
1074 dev_err(&idev->dev, "Failed to allocate TS device!\n");
1075 return -ENOMEM;
1076 }
1077
1078 input->name = DRIVER_NAME;
1079 input->id.bustype = BUS_HOST;
1080 input->dev.parent = &pdev->dev;
1081 input->open = atmel_ts_open;
1082 input->close = atmel_ts_close;
1083
1084 __set_bit(EV_ABS, input->evbit);
1085 __set_bit(EV_KEY, input->evbit);
1086 __set_bit(BTN_TOUCH, input->keybit);
84882b06
AB		 1087 if (st->caps->has_tsmr) {
1088 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1089 0, 0);
1090 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1091 0, 0);
1092 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1093 } else {
1094 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1095 dev_err(&pdev->dev,
1096 "This touchscreen controller only support 4 wires\n");
1097 ret = -EINVAL;
1098 goto err;
1099 }
1100
1101 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1102 0, 0);
1103 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1104 0, 0);
1105 }
c8b11de0
JW		 1106
1107 st->ts_input = input;
1108 input_set_drvdata(input, st);
1109
1110 ret = input_register_device(input);
1111 if (ret)
84882b06
AB		 1112 goto err;
1113
1114 return ret;
c8b11de0 1115
84882b06
AB		 1116err:
1117 input_free_device(st->ts_input);
c8b11de0
JW		 1118 return ret;
1119}
1120
1121static void at91_ts_unregister(struct at91_adc_state *st)
1122{
1123 input_unregister_device(st->ts_input);
1124}
1125
fc52692c 1126static int at91_adc_probe(struct platform_device *pdev)
0e589d5f 1127{
db10e201 1128 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
0e589d5f
MR		 1129 int ret;
1130 struct iio_dev *idev;
1131 struct at91_adc_state *st;
1132 struct resource *res;
e748783c 1133 u32 reg;
0e589d5f 1134
f8837532
SK		 1135 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1136 if (!idev)
1137 return -ENOMEM;
0e589d5f
MR		 1138
1139 st = iio_priv(idev);
1140
e364185f
MR		 1141 if (pdev->dev.of_node)
1142 ret = at91_adc_probe_dt(st, pdev);
1143 else
1144 ret = at91_adc_probe_pdata(st, pdev);
1145
0e589d5f
MR		 1146 if (ret) {
1147 dev_err(&pdev->dev, "No platform data available.\n");
f8837532 1148 return -EINVAL;
0e589d5f
MR		 1149 }
1150
0e589d5f
MR		 1151 platform_set_drvdata(pdev, idev);
1152
1153 idev->dev.parent = &pdev->dev;
1154 idev->name = dev_name(&pdev->dev);
1155 idev->modes = INDIO_DIRECT_MODE;
1156 idev->info = &at91_adc_info;
1157
1158 st->irq = platform_get_irq(pdev, 0);
1159 if (st->irq < 0) {
1160 dev_err(&pdev->dev, "No IRQ ID is designated\n");
f8837532 1161 return -ENODEV;
0e589d5f
MR		 1162 }
1163
390d75c1 1164 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0e589d5f 1165
5fd98466
TR		 1166 st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1167 if (IS_ERR(st->reg_base)) {
f8837532 1168 return PTR_ERR(st->reg_base);
0e589d5f
MR		 1169 }
1170
1171 /*
1172 * Disable all IRQs before setting up the handler
1173 */
1174 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1175 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
84882b06
AB		 1176
1177 if (st->caps->has_tsmr)
1178 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1179 pdev->dev.driver->name, idev);
1180 else
1181 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1182 pdev->dev.driver->name, idev);
0e589d5f
MR		 1183 if (ret) {
1184 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
f8837532 1185 return ret;
0e589d5f
MR		 1186 }
1187
390d75c1 1188 st->clk = devm_clk_get(&pdev->dev, "adc_clk");
0e589d5f
MR		 1189 if (IS_ERR(st->clk)) {
1190 dev_err(&pdev->dev, "Failed to get the clock.\n");
1191 ret = PTR_ERR(st->clk);
1192 goto error_free_irq;
1193 }
1194
00062a9c 1195 ret = clk_prepare_enable(st->clk);
0e589d5f 1196 if (ret) {
00062a9c
JL		 1197 dev_err(&pdev->dev,
1198 "Could not prepare or enable the clock.\n");
390d75c1 1199 goto error_free_irq;
0e589d5f
MR		 1200 }
1201
390d75c1 1202 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
0e589d5f
MR		 1203 if (IS_ERR(st->adc_clk)) {
1204 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
f755bbbf 1205 ret = PTR_ERR(st->adc_clk);
0e589d5f
MR		 1206 goto error_disable_clk;
1207 }
1208
00062a9c 1209 ret = clk_prepare_enable(st->adc_clk);
0e589d5f 1210 if (ret) {
00062a9c
JL		 1211 dev_err(&pdev->dev,
1212 "Could not prepare or enable the ADC clock.\n");
390d75c1 1213 goto error_disable_clk;
0e589d5f
MR		 1214 }
1215
0e589d5f
MR		 1216 /*
1217 * Prescaler rate computation using the formula from the Atmel's
1218 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1219 * specified by the electrical characteristics of the board.
1220 */
1221 mstrclk = clk_get_rate(st->clk);
1222 adc_clk = clk_get_rate(st->adc_clk);
db10e201 1223 adc_clk_khz = adc_clk / 1000;
c8b11de0
JW		 1224
1225 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1226 mstrclk, adc_clk);
1227
0e589d5f
MR		 1228 prsc = (mstrclk / (2 * adc_clk)) - 1;
1229
1230 if (!st->startup_time) {
1231 dev_err(&pdev->dev, "No startup time available.\n");
1232 ret = -EINVAL;
1233 goto error_disable_adc_clk;
1234 }
c4601666 1235 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
0e589d5f 1236
beca9e76
JCPV		 1237 /*
1238 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1239 * the best converted final value between two channels selection
1240 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1241 */
8f32b6ba
AB		 1242 if (st->sample_hold_time > 0)
1243 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1244 - 1, 1);
1245 else
1246 shtim = 0;
beca9e76 1247
9120c0be
JW		 1248 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1249 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
47be16b6 1250 if (st->low_res)
e748783c
JCPV		 1251 reg |= AT91_ADC_LOWRES;
1252 if (st->sleep_mode)
1253 reg |= AT91_ADC_SLEEP;
beca9e76 1254 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
e748783c 1255 at91_adc_writel(st, AT91_ADC_MR, reg);
0e589d5f
MR		 1256
1257 /* Setup the ADC channels available on the board */
1258 ret = at91_adc_channel_init(idev);
1259 if (ret < 0) {
1260 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1261 goto error_disable_adc_clk;
1262 }
1263
1264 init_waitqueue_head(&st->wq_data_avail);
1265 mutex_init(&st->lock);
1266
c8b11de0
JW		 1267 /*
1268 * Since touch screen will set trigger register as period trigger. So
1269 * when touch screen is enabled, then we have to disable hardware
1270 * trigger for classic adc.
1271 */
1272 if (!st->touchscreen_type) {
1273 ret = at91_adc_buffer_init(idev);
1274 if (ret < 0) {
1275 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1276 goto error_disable_adc_clk;
1277 }
0e589d5f 1278
c8b11de0
JW		 1279 ret = at91_adc_trigger_init(idev);
1280 if (ret < 0) {
1281 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1282 at91_adc_buffer_remove(idev);
1283 goto error_disable_adc_clk;
1284 }
1285 } else {
c8b11de0
JW		 1286 ret = at91_ts_register(st, pdev);
1287 if (ret)
1288 goto error_disable_adc_clk;
1289
1290 at91_ts_hw_init(st, adc_clk_khz);
0e589d5f
MR		 1291 }
1292
1293 ret = iio_device_register(idev);
1294 if (ret < 0) {
1295 dev_err(&pdev->dev, "Couldn't register the device.\n");
c8b11de0 1296 goto error_iio_device_register;
0e589d5f
MR		 1297 }
1298
1299 return 0;
1300
c8b11de0
JW		 1301error_iio_device_register:
1302 if (!st->touchscreen_type) {
1303 at91_adc_trigger_remove(idev);
1304 at91_adc_buffer_remove(idev);
1305 } else {
1306 at91_ts_unregister(st);
1307 }
0e589d5f 1308error_disable_adc_clk:
00062a9c 1309 clk_disable_unprepare(st->adc_clk);
0e589d5f 1310error_disable_clk:
00062a9c 1311 clk_disable_unprepare(st->clk);
0e589d5f
MR		 1312error_free_irq:
1313 free_irq(st->irq, idev);
0e589d5f
MR		 1314 return ret;
1315}
1316
fc52692c 1317static int at91_adc_remove(struct platform_device *pdev)
0e589d5f
MR		 1318{
1319 struct iio_dev *idev = platform_get_drvdata(pdev);
0e589d5f
MR		 1320 struct at91_adc_state *st = iio_priv(idev);
1321
1322 iio_device_unregister(idev);
c8b11de0
JW		 1323 if (!st->touchscreen_type) {
1324 at91_adc_trigger_remove(idev);
1325 at91_adc_buffer_remove(idev);
1326 } else {
1327 at91_ts_unregister(st);
1328 }
0e589d5f 1329 clk_disable_unprepare(st->adc_clk);
00062a9c 1330 clk_disable_unprepare(st->clk);
0e589d5f 1331 free_irq(st->irq, idev);
0e589d5f
MR		 1332
1333 return 0;
1334}
1335
e1811f97 1336static struct at91_adc_caps at91sam9260_caps = {
c4601666 1337 .calc_startup_ticks = calc_startup_ticks_9260,
2b6d598b 1338 .num_channels = 4,
e1811f97
JW		 1339 .registers = {
1340 .channel_base = AT91_ADC_CHR(0),
1341 .drdy_mask = AT91_ADC_DRDY,
1342 .status_register = AT91_ADC_SR,
1343 .trigger_register = AT91_ADC_TRGR_9260,
9120c0be
JW		 1344 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1345 .mr_startup_mask = AT91_ADC_STARTUP_9260,
e1811f97
JW		 1346 },
1347};
1348
65b1fdba
AB		 1349static struct at91_adc_caps at91sam9rl_caps = {
1350 .has_ts = true,
1351 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1352 .num_channels = 6,
1353 .registers = {
1354 .channel_base = AT91_ADC_CHR(0),
1355 .drdy_mask = AT91_ADC_DRDY,
1356 .status_register = AT91_ADC_SR,
1357 .trigger_register = AT91_ADC_TRGR_9G45,
1358 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1359 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1360 },
1361};
1362
e1811f97 1363static struct at91_adc_caps at91sam9g45_caps = {
c8b11de0 1364 .has_ts = true,
c4601666 1365 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
2b6d598b 1366 .num_channels = 8,
e1811f97
JW		 1367 .registers = {
1368 .channel_base = AT91_ADC_CHR(0),
1369 .drdy_mask = AT91_ADC_DRDY,
1370 .status_register = AT91_ADC_SR,
1371 .trigger_register = AT91_ADC_TRGR_9G45,
9120c0be
JW		 1372 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1373 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
e1811f97
JW		 1374 },
1375};
1376
1377static struct at91_adc_caps at91sam9x5_caps = {
c8b11de0
JW		 1378 .has_ts = true,
1379 .has_tsmr = true,
1380 .ts_filter_average = 3,
1381 .ts_pen_detect_sensitivity = 2,
c4601666 1382 .calc_startup_ticks = calc_startup_ticks_9x5,
2b6d598b 1383 .num_channels = 12,
e1811f97
JW		 1384 .registers = {
1385 .channel_base = AT91_ADC_CDR0_9X5,
1386 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1387 .status_register = AT91_ADC_SR_9X5,
1388 .trigger_register = AT91_ADC_TRGR_9X5,
9120c0be
JW		 1389 /* prescal mask is same as 9G45 */
1390 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1391 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
e1811f97
JW		 1392 },
1393};
1394
e364185f 1395static const struct of_device_id at91_adc_dt_ids[] = {
e1811f97 1396 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
65b1fdba 1397 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
e1811f97
JW		 1398 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1399 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
e364185f
MR		 1400 {},
1401};
1402MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
467a44b0
AB		 1403
1404static const struct platform_device_id at91_adc_ids[] = {
1405 {
1406 .name = "at91sam9260-adc",
1407 .driver_data = (unsigned long)&at91sam9260_caps,
65b1fdba
AB		 1408 }, {
1409 .name = "at91sam9rl-adc",
1410 .driver_data = (unsigned long)&at91sam9rl_caps,
467a44b0
AB		 1411 }, {
1412 .name = "at91sam9g45-adc",
1413 .driver_data = (unsigned long)&at91sam9g45_caps,
1414 }, {
1415 .name = "at91sam9x5-adc",
1416 .driver_data = (unsigned long)&at91sam9x5_caps,
1417 }, {
1418 /* terminator */
1419 }
1420};
1421MODULE_DEVICE_TABLE(platform, at91_adc_ids);
e364185f 1422
0e589d5f
MR		 1423static struct platform_driver at91_adc_driver = {
1424 .probe = at91_adc_probe,
fc52692c 1425 .remove = at91_adc_remove,
467a44b0 1426 .id_table = at91_adc_ids,
0e589d5f 1427 .driver = {
c8b11de0 1428 .name = DRIVER_NAME,
e364185f 1429 .of_match_table = of_match_ptr(at91_adc_dt_ids),
0e589d5f
MR		 1430 },
1431};
1432
1433module_platform_driver(at91_adc_driver);
1434
1435MODULE_LICENSE("GPL");
1436MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1437MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
Linux 6.x block layer and io_uring tree(s)