Commit | Line | Data |
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0e589d5f MR |
1 | /* |
2 | * Driver for the ADC present in the Atmel AT91 evaluation boards. | |
3 | * | |
4 | * Copyright 2011 Free Electrons | |
5 | * | |
6 | * Licensed under the GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/bitmap.h> | |
10 | #include <linux/bitops.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/jiffies.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
e364185f MR |
18 | #include <linux/of.h> |
19 | #include <linux/of_device.h> | |
0e589d5f MR |
20 | #include <linux/platform_device.h> |
21 | #include <linux/sched.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/wait.h> | |
24 | ||
25 | #include <linux/platform_data/at91_adc.h> | |
26 | ||
27 | #include <linux/iio/iio.h> | |
28 | #include <linux/iio/buffer.h> | |
0e589d5f MR |
29 | #include <linux/iio/trigger.h> |
30 | #include <linux/iio/trigger_consumer.h> | |
90032e4e | 31 | #include <linux/iio/triggered_buffer.h> |
0e589d5f MR |
32 | |
33 | #include <mach/at91_adc.h> | |
34 | ||
35 | #define AT91_ADC_CHAN(st, ch) \ | |
36 | (st->registers->channel_base + (ch * 4)) | |
37 | #define at91_adc_readl(st, reg) \ | |
38 | (readl_relaxed(st->reg_base + reg)) | |
39 | #define at91_adc_writel(st, reg, val) \ | |
40 | (writel_relaxed(val, st->reg_base + reg)) | |
41 | ||
42 | struct at91_adc_state { | |
43 | struct clk *adc_clk; | |
44 | u16 *buffer; | |
45 | unsigned long channels_mask; | |
46 | struct clk *clk; | |
47 | bool done; | |
48 | int irq; | |
0e589d5f MR |
49 | u16 last_value; |
50 | struct mutex lock; | |
51 | u8 num_channels; | |
52 | void __iomem *reg_base; | |
53 | struct at91_adc_reg_desc *registers; | |
54 | u8 startup_time; | |
beca9e76 | 55 | u8 sample_hold_time; |
e748783c | 56 | bool sleep_mode; |
0e589d5f MR |
57 | struct iio_trigger **trig; |
58 | struct at91_adc_trigger *trigger_list; | |
59 | u32 trigger_number; | |
60 | bool use_external; | |
61 | u32 vref_mv; | |
47be16b6 LD |
62 | u32 res; /* resolution used for convertions */ |
63 | bool low_res; /* the resolution corresponds to the lowest one */ | |
0e589d5f MR |
64 | wait_queue_head_t wq_data_avail; |
65 | }; | |
66 | ||
67 | static irqreturn_t at91_adc_trigger_handler(int irq, void *p) | |
68 | { | |
69 | struct iio_poll_func *pf = p; | |
70 | struct iio_dev *idev = pf->indio_dev; | |
71 | struct at91_adc_state *st = iio_priv(idev); | |
0e589d5f MR |
72 | int i, j = 0; |
73 | ||
74 | for (i = 0; i < idev->masklength; i++) { | |
75 | if (!test_bit(i, idev->active_scan_mask)) | |
76 | continue; | |
77 | st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i)); | |
78 | j++; | |
79 | } | |
80 | ||
81 | if (idev->scan_timestamp) { | |
82 | s64 *timestamp = (s64 *)((u8 *)st->buffer + | |
83 | ALIGN(j, sizeof(s64))); | |
84 | *timestamp = pf->timestamp; | |
85 | } | |
86 | ||
11679767 | 87 | iio_push_to_buffers(idev, (u8 *)st->buffer); |
0e589d5f MR |
88 | |
89 | iio_trigger_notify_done(idev->trig); | |
0e589d5f MR |
90 | |
91 | /* Needed to ACK the DRDY interruption */ | |
92 | at91_adc_readl(st, AT91_ADC_LCDR); | |
93 | ||
94 | enable_irq(st->irq); | |
95 | ||
96 | return IRQ_HANDLED; | |
97 | } | |
98 | ||
99 | static irqreturn_t at91_adc_eoc_trigger(int irq, void *private) | |
100 | { | |
101 | struct iio_dev *idev = private; | |
102 | struct at91_adc_state *st = iio_priv(idev); | |
103 | u32 status = at91_adc_readl(st, st->registers->status_register); | |
104 | ||
105 | if (!(status & st->registers->drdy_mask)) | |
106 | return IRQ_HANDLED; | |
107 | ||
108 | if (iio_buffer_enabled(idev)) { | |
109 | disable_irq_nosync(irq); | |
0e589d5f MR |
110 | iio_trigger_poll(idev->trig, iio_get_time_ns()); |
111 | } else { | |
112 | st->last_value = at91_adc_readl(st, AT91_ADC_LCDR); | |
113 | st->done = true; | |
114 | wake_up_interruptible(&st->wq_data_avail); | |
115 | } | |
116 | ||
117 | return IRQ_HANDLED; | |
118 | } | |
119 | ||
120 | static int at91_adc_channel_init(struct iio_dev *idev) | |
121 | { | |
122 | struct at91_adc_state *st = iio_priv(idev); | |
123 | struct iio_chan_spec *chan_array, *timestamp; | |
124 | int bit, idx = 0; | |
125 | ||
126 | idev->num_channels = bitmap_weight(&st->channels_mask, | |
127 | st->num_channels) + 1; | |
128 | ||
6b3aa313 AL |
129 | chan_array = devm_kzalloc(&idev->dev, |
130 | ((idev->num_channels + 1) * | |
131 | sizeof(struct iio_chan_spec)), | |
132 | GFP_KERNEL); | |
0e589d5f MR |
133 | |
134 | if (!chan_array) | |
135 | return -ENOMEM; | |
136 | ||
137 | for_each_set_bit(bit, &st->channels_mask, st->num_channels) { | |
138 | struct iio_chan_spec *chan = chan_array + idx; | |
139 | ||
140 | chan->type = IIO_VOLTAGE; | |
141 | chan->indexed = 1; | |
142 | chan->channel = bit; | |
143 | chan->scan_index = idx; | |
144 | chan->scan_type.sign = 'u'; | |
47be16b6 | 145 | chan->scan_type.realbits = st->res; |
0e589d5f | 146 | chan->scan_type.storagebits = 16; |
01bdab66 JC |
147 | chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); |
148 | chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); | |
0e589d5f MR |
149 | idx++; |
150 | } | |
151 | timestamp = chan_array + idx; | |
152 | ||
153 | timestamp->type = IIO_TIMESTAMP; | |
154 | timestamp->channel = -1; | |
155 | timestamp->scan_index = idx; | |
156 | timestamp->scan_type.sign = 's'; | |
157 | timestamp->scan_type.realbits = 64; | |
158 | timestamp->scan_type.storagebits = 64; | |
159 | ||
160 | idev->channels = chan_array; | |
161 | return idev->num_channels; | |
162 | } | |
163 | ||
164 | static u8 at91_adc_get_trigger_value_by_name(struct iio_dev *idev, | |
165 | struct at91_adc_trigger *triggers, | |
166 | const char *trigger_name) | |
167 | { | |
168 | struct at91_adc_state *st = iio_priv(idev); | |
169 | u8 value = 0; | |
170 | int i; | |
171 | ||
172 | for (i = 0; i < st->trigger_number; i++) { | |
173 | char *name = kasprintf(GFP_KERNEL, | |
174 | "%s-dev%d-%s", | |
175 | idev->name, | |
176 | idev->id, | |
177 | triggers[i].name); | |
178 | if (!name) | |
179 | return -ENOMEM; | |
180 | ||
181 | if (strcmp(trigger_name, name) == 0) { | |
182 | value = triggers[i].value; | |
183 | kfree(name); | |
184 | break; | |
185 | } | |
186 | ||
187 | kfree(name); | |
188 | } | |
189 | ||
190 | return value; | |
191 | } | |
192 | ||
193 | static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) | |
194 | { | |
1e9663c6 | 195 | struct iio_dev *idev = iio_trigger_get_drvdata(trig); |
0e589d5f MR |
196 | struct at91_adc_state *st = iio_priv(idev); |
197 | struct iio_buffer *buffer = idev->buffer; | |
198 | struct at91_adc_reg_desc *reg = st->registers; | |
199 | u32 status = at91_adc_readl(st, reg->trigger_register); | |
200 | u8 value; | |
201 | u8 bit; | |
202 | ||
203 | value = at91_adc_get_trigger_value_by_name(idev, | |
204 | st->trigger_list, | |
205 | idev->trig->name); | |
206 | if (value == 0) | |
207 | return -EINVAL; | |
208 | ||
209 | if (state) { | |
210 | st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); | |
211 | if (st->buffer == NULL) | |
212 | return -ENOMEM; | |
213 | ||
214 | at91_adc_writel(st, reg->trigger_register, | |
215 | status | value); | |
216 | ||
217 | for_each_set_bit(bit, buffer->scan_mask, | |
218 | st->num_channels) { | |
219 | struct iio_chan_spec const *chan = idev->channels + bit; | |
220 | at91_adc_writel(st, AT91_ADC_CHER, | |
221 | AT91_ADC_CH(chan->channel)); | |
222 | } | |
223 | ||
224 | at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); | |
225 | ||
226 | } else { | |
227 | at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); | |
228 | ||
229 | at91_adc_writel(st, reg->trigger_register, | |
230 | status & ~value); | |
231 | ||
232 | for_each_set_bit(bit, buffer->scan_mask, | |
233 | st->num_channels) { | |
234 | struct iio_chan_spec const *chan = idev->channels + bit; | |
235 | at91_adc_writel(st, AT91_ADC_CHDR, | |
236 | AT91_ADC_CH(chan->channel)); | |
237 | } | |
238 | kfree(st->buffer); | |
239 | } | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
244 | static const struct iio_trigger_ops at91_adc_trigger_ops = { | |
245 | .owner = THIS_MODULE, | |
246 | .set_trigger_state = &at91_adc_configure_trigger, | |
247 | }; | |
248 | ||
249 | static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, | |
250 | struct at91_adc_trigger *trigger) | |
251 | { | |
252 | struct iio_trigger *trig; | |
253 | int ret; | |
254 | ||
255 | trig = iio_trigger_alloc("%s-dev%d-%s", idev->name, | |
256 | idev->id, trigger->name); | |
257 | if (trig == NULL) | |
258 | return NULL; | |
259 | ||
260 | trig->dev.parent = idev->dev.parent; | |
1e9663c6 | 261 | iio_trigger_set_drvdata(trig, idev); |
0e589d5f MR |
262 | trig->ops = &at91_adc_trigger_ops; |
263 | ||
264 | ret = iio_trigger_register(trig); | |
265 | if (ret) | |
266 | return NULL; | |
267 | ||
268 | return trig; | |
269 | } | |
270 | ||
271 | static int at91_adc_trigger_init(struct iio_dev *idev) | |
272 | { | |
273 | struct at91_adc_state *st = iio_priv(idev); | |
274 | int i, ret; | |
275 | ||
6b3aa313 AL |
276 | st->trig = devm_kzalloc(&idev->dev, |
277 | st->trigger_number * sizeof(st->trig), | |
278 | GFP_KERNEL); | |
0e589d5f MR |
279 | |
280 | if (st->trig == NULL) { | |
281 | ret = -ENOMEM; | |
282 | goto error_ret; | |
283 | } | |
284 | ||
285 | for (i = 0; i < st->trigger_number; i++) { | |
286 | if (st->trigger_list[i].is_external && !(st->use_external)) | |
287 | continue; | |
288 | ||
289 | st->trig[i] = at91_adc_allocate_trigger(idev, | |
290 | st->trigger_list + i); | |
291 | if (st->trig[i] == NULL) { | |
292 | dev_err(&idev->dev, | |
293 | "Could not allocate trigger %d\n", i); | |
294 | ret = -ENOMEM; | |
295 | goto error_trigger; | |
296 | } | |
297 | } | |
298 | ||
299 | return 0; | |
300 | ||
301 | error_trigger: | |
302 | for (i--; i >= 0; i--) { | |
303 | iio_trigger_unregister(st->trig[i]); | |
304 | iio_trigger_free(st->trig[i]); | |
305 | } | |
306 | error_ret: | |
307 | return ret; | |
308 | } | |
309 | ||
310 | static void at91_adc_trigger_remove(struct iio_dev *idev) | |
311 | { | |
312 | struct at91_adc_state *st = iio_priv(idev); | |
313 | int i; | |
314 | ||
315 | for (i = 0; i < st->trigger_number; i++) { | |
316 | iio_trigger_unregister(st->trig[i]); | |
317 | iio_trigger_free(st->trig[i]); | |
318 | } | |
319 | } | |
320 | ||
0e589d5f MR |
321 | static int at91_adc_buffer_init(struct iio_dev *idev) |
322 | { | |
90032e4e LPC |
323 | return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, |
324 | &at91_adc_trigger_handler, NULL); | |
0e589d5f MR |
325 | } |
326 | ||
327 | static void at91_adc_buffer_remove(struct iio_dev *idev) | |
328 | { | |
90032e4e | 329 | iio_triggered_buffer_cleanup(idev); |
0e589d5f MR |
330 | } |
331 | ||
332 | static int at91_adc_read_raw(struct iio_dev *idev, | |
333 | struct iio_chan_spec const *chan, | |
334 | int *val, int *val2, long mask) | |
335 | { | |
336 | struct at91_adc_state *st = iio_priv(idev); | |
337 | int ret; | |
338 | ||
339 | switch (mask) { | |
340 | case IIO_CHAN_INFO_RAW: | |
341 | mutex_lock(&st->lock); | |
342 | ||
343 | at91_adc_writel(st, AT91_ADC_CHER, | |
344 | AT91_ADC_CH(chan->channel)); | |
345 | at91_adc_writel(st, AT91_ADC_IER, st->registers->drdy_mask); | |
346 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); | |
347 | ||
348 | ret = wait_event_interruptible_timeout(st->wq_data_avail, | |
349 | st->done, | |
350 | msecs_to_jiffies(1000)); | |
351 | if (ret == 0) | |
90e6dc7c LPC |
352 | ret = -ETIMEDOUT; |
353 | if (ret < 0) { | |
354 | mutex_unlock(&st->lock); | |
0e589d5f | 355 | return ret; |
90e6dc7c | 356 | } |
0e589d5f MR |
357 | |
358 | *val = st->last_value; | |
359 | ||
360 | at91_adc_writel(st, AT91_ADC_CHDR, | |
361 | AT91_ADC_CH(chan->channel)); | |
362 | at91_adc_writel(st, AT91_ADC_IDR, st->registers->drdy_mask); | |
363 | ||
364 | st->last_value = 0; | |
365 | st->done = false; | |
366 | mutex_unlock(&st->lock); | |
367 | return IIO_VAL_INT; | |
368 | ||
369 | case IIO_CHAN_INFO_SCALE: | |
370 | *val = (st->vref_mv * 1000) >> chan->scan_type.realbits; | |
371 | *val2 = 0; | |
372 | return IIO_VAL_INT_PLUS_MICRO; | |
373 | default: | |
374 | break; | |
375 | } | |
376 | return -EINVAL; | |
377 | } | |
378 | ||
47be16b6 LD |
379 | static int at91_adc_of_get_resolution(struct at91_adc_state *st, |
380 | struct platform_device *pdev) | |
381 | { | |
382 | struct iio_dev *idev = iio_priv_to_dev(st); | |
383 | struct device_node *np = pdev->dev.of_node; | |
384 | int count, i, ret = 0; | |
385 | char *res_name, *s; | |
386 | u32 *resolutions; | |
387 | ||
388 | count = of_property_count_strings(np, "atmel,adc-res-names"); | |
389 | if (count < 2) { | |
390 | dev_err(&idev->dev, "You must specified at least two resolution names for " | |
391 | "adc-res-names property in the DT\n"); | |
392 | return count; | |
393 | } | |
394 | ||
395 | resolutions = kmalloc(count * sizeof(*resolutions), GFP_KERNEL); | |
396 | if (!resolutions) | |
397 | return -ENOMEM; | |
398 | ||
399 | if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) { | |
400 | dev_err(&idev->dev, "Missing adc-res property in the DT.\n"); | |
401 | ret = -ENODEV; | |
402 | goto ret; | |
403 | } | |
404 | ||
405 | if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name)) | |
406 | res_name = "highres"; | |
407 | ||
408 | for (i = 0; i < count; i++) { | |
409 | if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s)) | |
410 | continue; | |
411 | ||
412 | if (strcmp(res_name, s)) | |
413 | continue; | |
414 | ||
415 | st->res = resolutions[i]; | |
416 | if (!strcmp(res_name, "lowres")) | |
417 | st->low_res = true; | |
418 | else | |
419 | st->low_res = false; | |
420 | ||
421 | dev_info(&idev->dev, "Resolution used: %u bits\n", st->res); | |
422 | goto ret; | |
423 | } | |
424 | ||
425 | dev_err(&idev->dev, "There is no resolution for %s\n", res_name); | |
426 | ||
427 | ret: | |
428 | kfree(resolutions); | |
429 | return ret; | |
430 | } | |
431 | ||
e364185f MR |
432 | static int at91_adc_probe_dt(struct at91_adc_state *st, |
433 | struct platform_device *pdev) | |
434 | { | |
435 | struct iio_dev *idev = iio_priv_to_dev(st); | |
436 | struct device_node *node = pdev->dev.of_node; | |
437 | struct device_node *trig_node; | |
438 | int i = 0, ret; | |
439 | u32 prop; | |
440 | ||
441 | if (!node) | |
442 | return -EINVAL; | |
443 | ||
444 | st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); | |
445 | ||
446 | if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { | |
447 | dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); | |
448 | ret = -EINVAL; | |
449 | goto error_ret; | |
450 | } | |
451 | st->channels_mask = prop; | |
452 | ||
453 | if (of_property_read_u32(node, "atmel,adc-num-channels", &prop)) { | |
454 | dev_err(&idev->dev, "Missing adc-num-channels property in the DT.\n"); | |
455 | ret = -EINVAL; | |
456 | goto error_ret; | |
457 | } | |
458 | st->num_channels = prop; | |
459 | ||
e748783c JCPV |
460 | st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); |
461 | ||
e364185f MR |
462 | if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { |
463 | dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); | |
464 | ret = -EINVAL; | |
465 | goto error_ret; | |
466 | } | |
467 | st->startup_time = prop; | |
468 | ||
beca9e76 JCPV |
469 | prop = 0; |
470 | of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop); | |
471 | st->sample_hold_time = prop; | |
e364185f MR |
472 | |
473 | if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { | |
474 | dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); | |
475 | ret = -EINVAL; | |
476 | goto error_ret; | |
477 | } | |
478 | st->vref_mv = prop; | |
479 | ||
47be16b6 LD |
480 | ret = at91_adc_of_get_resolution(st, pdev); |
481 | if (ret) | |
482 | goto error_ret; | |
483 | ||
e364185f MR |
484 | st->registers = devm_kzalloc(&idev->dev, |
485 | sizeof(struct at91_adc_reg_desc), | |
486 | GFP_KERNEL); | |
487 | if (!st->registers) { | |
488 | dev_err(&idev->dev, "Could not allocate register memory.\n"); | |
489 | ret = -ENOMEM; | |
490 | goto error_ret; | |
491 | } | |
492 | ||
493 | if (of_property_read_u32(node, "atmel,adc-channel-base", &prop)) { | |
494 | dev_err(&idev->dev, "Missing adc-channel-base property in the DT.\n"); | |
495 | ret = -EINVAL; | |
496 | goto error_ret; | |
497 | } | |
498 | st->registers->channel_base = prop; | |
499 | ||
500 | if (of_property_read_u32(node, "atmel,adc-drdy-mask", &prop)) { | |
501 | dev_err(&idev->dev, "Missing adc-drdy-mask property in the DT.\n"); | |
502 | ret = -EINVAL; | |
503 | goto error_ret; | |
504 | } | |
505 | st->registers->drdy_mask = prop; | |
506 | ||
507 | if (of_property_read_u32(node, "atmel,adc-status-register", &prop)) { | |
508 | dev_err(&idev->dev, "Missing adc-status-register property in the DT.\n"); | |
509 | ret = -EINVAL; | |
510 | goto error_ret; | |
511 | } | |
512 | st->registers->status_register = prop; | |
513 | ||
514 | if (of_property_read_u32(node, "atmel,adc-trigger-register", &prop)) { | |
515 | dev_err(&idev->dev, "Missing adc-trigger-register property in the DT.\n"); | |
516 | ret = -EINVAL; | |
517 | goto error_ret; | |
518 | } | |
519 | st->registers->trigger_register = prop; | |
520 | ||
521 | st->trigger_number = of_get_child_count(node); | |
6b3aa313 AL |
522 | st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number * |
523 | sizeof(struct at91_adc_trigger), | |
524 | GFP_KERNEL); | |
e364185f MR |
525 | if (!st->trigger_list) { |
526 | dev_err(&idev->dev, "Could not allocate trigger list memory.\n"); | |
527 | ret = -ENOMEM; | |
528 | goto error_ret; | |
529 | } | |
530 | ||
531 | for_each_child_of_node(node, trig_node) { | |
532 | struct at91_adc_trigger *trig = st->trigger_list + i; | |
533 | const char *name; | |
534 | ||
535 | if (of_property_read_string(trig_node, "trigger-name", &name)) { | |
536 | dev_err(&idev->dev, "Missing trigger-name property in the DT.\n"); | |
537 | ret = -EINVAL; | |
538 | goto error_ret; | |
539 | } | |
540 | trig->name = name; | |
541 | ||
542 | if (of_property_read_u32(trig_node, "trigger-value", &prop)) { | |
543 | dev_err(&idev->dev, "Missing trigger-value property in the DT.\n"); | |
544 | ret = -EINVAL; | |
545 | goto error_ret; | |
546 | } | |
547 | trig->value = prop; | |
548 | trig->is_external = of_property_read_bool(trig_node, "trigger-external"); | |
549 | i++; | |
550 | } | |
551 | ||
552 | return 0; | |
553 | ||
554 | error_ret: | |
555 | return ret; | |
556 | } | |
557 | ||
0e589d5f MR |
558 | static int at91_adc_probe_pdata(struct at91_adc_state *st, |
559 | struct platform_device *pdev) | |
560 | { | |
561 | struct at91_adc_data *pdata = pdev->dev.platform_data; | |
562 | ||
563 | if (!pdata) | |
564 | return -EINVAL; | |
565 | ||
566 | st->use_external = pdata->use_external_triggers; | |
567 | st->vref_mv = pdata->vref; | |
568 | st->channels_mask = pdata->channels_used; | |
569 | st->num_channels = pdata->num_channels; | |
570 | st->startup_time = pdata->startup_time; | |
571 | st->trigger_number = pdata->trigger_number; | |
572 | st->trigger_list = pdata->trigger_list; | |
573 | st->registers = pdata->registers; | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static const struct iio_info at91_adc_info = { | |
579 | .driver_module = THIS_MODULE, | |
580 | .read_raw = &at91_adc_read_raw, | |
581 | }; | |
582 | ||
fc52692c | 583 | static int at91_adc_probe(struct platform_device *pdev) |
0e589d5f | 584 | { |
beca9e76 | 585 | unsigned int prsc, mstrclk, ticks, adc_clk, shtim; |
0e589d5f MR |
586 | int ret; |
587 | struct iio_dev *idev; | |
588 | struct at91_adc_state *st; | |
589 | struct resource *res; | |
e748783c | 590 | u32 reg; |
0e589d5f MR |
591 | |
592 | idev = iio_device_alloc(sizeof(struct at91_adc_state)); | |
593 | if (idev == NULL) { | |
594 | ret = -ENOMEM; | |
595 | goto error_ret; | |
596 | } | |
597 | ||
598 | st = iio_priv(idev); | |
599 | ||
e364185f MR |
600 | if (pdev->dev.of_node) |
601 | ret = at91_adc_probe_dt(st, pdev); | |
602 | else | |
603 | ret = at91_adc_probe_pdata(st, pdev); | |
604 | ||
0e589d5f MR |
605 | if (ret) { |
606 | dev_err(&pdev->dev, "No platform data available.\n"); | |
607 | ret = -EINVAL; | |
608 | goto error_free_device; | |
609 | } | |
610 | ||
0e589d5f MR |
611 | platform_set_drvdata(pdev, idev); |
612 | ||
613 | idev->dev.parent = &pdev->dev; | |
614 | idev->name = dev_name(&pdev->dev); | |
615 | idev->modes = INDIO_DIRECT_MODE; | |
616 | idev->info = &at91_adc_info; | |
617 | ||
618 | st->irq = platform_get_irq(pdev, 0); | |
619 | if (st->irq < 0) { | |
620 | dev_err(&pdev->dev, "No IRQ ID is designated\n"); | |
621 | ret = -ENODEV; | |
622 | goto error_free_device; | |
623 | } | |
624 | ||
390d75c1 | 625 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
0e589d5f | 626 | |
5fd98466 TR |
627 | st->reg_base = devm_ioremap_resource(&pdev->dev, res); |
628 | if (IS_ERR(st->reg_base)) { | |
629 | ret = PTR_ERR(st->reg_base); | |
390d75c1 | 630 | goto error_free_device; |
0e589d5f MR |
631 | } |
632 | ||
633 | /* | |
634 | * Disable all IRQs before setting up the handler | |
635 | */ | |
636 | at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); | |
637 | at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); | |
638 | ret = request_irq(st->irq, | |
639 | at91_adc_eoc_trigger, | |
640 | 0, | |
641 | pdev->dev.driver->name, | |
642 | idev); | |
643 | if (ret) { | |
644 | dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); | |
390d75c1 | 645 | goto error_free_device; |
0e589d5f MR |
646 | } |
647 | ||
390d75c1 | 648 | st->clk = devm_clk_get(&pdev->dev, "adc_clk"); |
0e589d5f MR |
649 | if (IS_ERR(st->clk)) { |
650 | dev_err(&pdev->dev, "Failed to get the clock.\n"); | |
651 | ret = PTR_ERR(st->clk); | |
652 | goto error_free_irq; | |
653 | } | |
654 | ||
00062a9c | 655 | ret = clk_prepare_enable(st->clk); |
0e589d5f | 656 | if (ret) { |
00062a9c JL |
657 | dev_err(&pdev->dev, |
658 | "Could not prepare or enable the clock.\n"); | |
390d75c1 | 659 | goto error_free_irq; |
0e589d5f MR |
660 | } |
661 | ||
390d75c1 | 662 | st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); |
0e589d5f MR |
663 | if (IS_ERR(st->adc_clk)) { |
664 | dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); | |
f755bbbf | 665 | ret = PTR_ERR(st->adc_clk); |
0e589d5f MR |
666 | goto error_disable_clk; |
667 | } | |
668 | ||
00062a9c | 669 | ret = clk_prepare_enable(st->adc_clk); |
0e589d5f | 670 | if (ret) { |
00062a9c JL |
671 | dev_err(&pdev->dev, |
672 | "Could not prepare or enable the ADC clock.\n"); | |
390d75c1 | 673 | goto error_disable_clk; |
0e589d5f MR |
674 | } |
675 | ||
0e589d5f MR |
676 | /* |
677 | * Prescaler rate computation using the formula from the Atmel's | |
678 | * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being | |
679 | * specified by the electrical characteristics of the board. | |
680 | */ | |
681 | mstrclk = clk_get_rate(st->clk); | |
682 | adc_clk = clk_get_rate(st->adc_clk); | |
683 | prsc = (mstrclk / (2 * adc_clk)) - 1; | |
684 | ||
685 | if (!st->startup_time) { | |
686 | dev_err(&pdev->dev, "No startup time available.\n"); | |
687 | ret = -EINVAL; | |
688 | goto error_disable_adc_clk; | |
689 | } | |
690 | ||
691 | /* | |
692 | * Number of ticks needed to cover the startup time of the ADC as | |
693 | * defined in the electrical characteristics of the board, divided by 8. | |
694 | * The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock | |
695 | */ | |
696 | ticks = round_up((st->startup_time * adc_clk / | |
697 | 1000000) - 1, 8) / 8; | |
beca9e76 JCPV |
698 | /* |
699 | * a minimal Sample and Hold Time is necessary for the ADC to guarantee | |
700 | * the best converted final value between two channels selection | |
701 | * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock | |
702 | */ | |
703 | shtim = round_up((st->sample_hold_time * adc_clk / | |
704 | 1000000) - 1, 1); | |
705 | ||
e748783c JCPV |
706 | reg = AT91_ADC_PRESCAL_(prsc) & AT91_ADC_PRESCAL; |
707 | reg |= AT91_ADC_STARTUP_(ticks) & AT91_ADC_STARTUP; | |
47be16b6 | 708 | if (st->low_res) |
e748783c JCPV |
709 | reg |= AT91_ADC_LOWRES; |
710 | if (st->sleep_mode) | |
711 | reg |= AT91_ADC_SLEEP; | |
beca9e76 | 712 | reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; |
e748783c | 713 | at91_adc_writel(st, AT91_ADC_MR, reg); |
0e589d5f MR |
714 | |
715 | /* Setup the ADC channels available on the board */ | |
716 | ret = at91_adc_channel_init(idev); | |
717 | if (ret < 0) { | |
718 | dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); | |
719 | goto error_disable_adc_clk; | |
720 | } | |
721 | ||
722 | init_waitqueue_head(&st->wq_data_avail); | |
723 | mutex_init(&st->lock); | |
724 | ||
725 | ret = at91_adc_buffer_init(idev); | |
726 | if (ret < 0) { | |
727 | dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); | |
728 | goto error_disable_adc_clk; | |
729 | } | |
730 | ||
731 | ret = at91_adc_trigger_init(idev); | |
732 | if (ret < 0) { | |
733 | dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); | |
734 | goto error_unregister_buffer; | |
735 | } | |
736 | ||
737 | ret = iio_device_register(idev); | |
738 | if (ret < 0) { | |
739 | dev_err(&pdev->dev, "Couldn't register the device.\n"); | |
740 | goto error_remove_triggers; | |
741 | } | |
742 | ||
743 | return 0; | |
744 | ||
745 | error_remove_triggers: | |
746 | at91_adc_trigger_remove(idev); | |
747 | error_unregister_buffer: | |
748 | at91_adc_buffer_remove(idev); | |
749 | error_disable_adc_clk: | |
00062a9c | 750 | clk_disable_unprepare(st->adc_clk); |
0e589d5f | 751 | error_disable_clk: |
00062a9c | 752 | clk_disable_unprepare(st->clk); |
0e589d5f MR |
753 | error_free_irq: |
754 | free_irq(st->irq, idev); | |
0e589d5f MR |
755 | error_free_device: |
756 | iio_device_free(idev); | |
757 | error_ret: | |
758 | return ret; | |
759 | } | |
760 | ||
fc52692c | 761 | static int at91_adc_remove(struct platform_device *pdev) |
0e589d5f MR |
762 | { |
763 | struct iio_dev *idev = platform_get_drvdata(pdev); | |
0e589d5f MR |
764 | struct at91_adc_state *st = iio_priv(idev); |
765 | ||
766 | iio_device_unregister(idev); | |
767 | at91_adc_trigger_remove(idev); | |
768 | at91_adc_buffer_remove(idev); | |
769 | clk_disable_unprepare(st->adc_clk); | |
00062a9c | 770 | clk_disable_unprepare(st->clk); |
0e589d5f | 771 | free_irq(st->irq, idev); |
0e589d5f MR |
772 | iio_device_free(idev); |
773 | ||
774 | return 0; | |
775 | } | |
776 | ||
00738ff6 | 777 | #ifdef CONFIG_OF |
e364185f MR |
778 | static const struct of_device_id at91_adc_dt_ids[] = { |
779 | { .compatible = "atmel,at91sam9260-adc" }, | |
780 | {}, | |
781 | }; | |
782 | MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); | |
00738ff6 | 783 | #endif |
e364185f | 784 | |
0e589d5f MR |
785 | static struct platform_driver at91_adc_driver = { |
786 | .probe = at91_adc_probe, | |
fc52692c | 787 | .remove = at91_adc_remove, |
0e589d5f MR |
788 | .driver = { |
789 | .name = "at91_adc", | |
e364185f | 790 | .of_match_table = of_match_ptr(at91_adc_dt_ids), |
0e589d5f MR |
791 | }, |
792 | }; | |
793 | ||
794 | module_platform_driver(at91_adc_driver); | |
795 | ||
796 | MODULE_LICENSE("GPL"); | |
797 | MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); | |
798 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); |