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Merge tag 'bcachefs-2024-10-05' of git://evilpiepirate.org/bcachefs
[linux-block.git] / drivers / iio / adc / ad9467.c
CommitLineData
ad679712
MH		 1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Analog Devices AD9467 SPI ADC driver
4 *
5 * Copyright 2012-2020 Analog Devices Inc.
6 */
05c4081f
NS		 7
8#include <linux/bitmap.h>
9#include <linux/bitops.h>
73772019 10#include <linux/cleanup.h>
05c4081f 11#include <linux/debugfs.h>
ad679712 12#include <linux/module.h>
73772019 13#include <linux/mutex.h>
ad679712
MH		 14#include <linux/device.h>
15#include <linux/kernel.h>
16#include <linux/slab.h>
17#include <linux/spi/spi.h>
d6b133a6 18#include <linux/seq_file.h>
ad679712
MH		 19#include <linux/err.h>
20#include <linux/delay.h>
21#include <linux/gpio/consumer.h>
1240c94c 22#include <linux/of.h>
ad679712
MH		 23
24
bb42191f 25#include <linux/iio/backend.h>
ad679712
MH		 26#include <linux/iio/iio.h>
27#include <linux/iio/sysfs.h>
28
29#include <linux/clk.h>
30
ad679712
MH		 31/*
32 * ADI High-Speed ADC common spi interface registers
33 * See Application-Note AN-877:
34 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
35 */
36
37#define AN877_ADC_REG_CHIP_PORT_CONF 0x00
38#define AN877_ADC_REG_CHIP_ID 0x01
39#define AN877_ADC_REG_CHIP_GRADE 0x02
40#define AN877_ADC_REG_CHAN_INDEX 0x05
41#define AN877_ADC_REG_TRANSFER 0xFF
42#define AN877_ADC_REG_MODES 0x08
43#define AN877_ADC_REG_TEST_IO 0x0D
44#define AN877_ADC_REG_ADC_INPUT 0x0F
45#define AN877_ADC_REG_OFFSET 0x10
46#define AN877_ADC_REG_OUTPUT_MODE 0x14
47#define AN877_ADC_REG_OUTPUT_ADJUST 0x15
48#define AN877_ADC_REG_OUTPUT_PHASE 0x16
49#define AN877_ADC_REG_OUTPUT_DELAY 0x17
50#define AN877_ADC_REG_VREF 0x18
51#define AN877_ADC_REG_ANALOG_INPUT 0x2C
52
53/* AN877_ADC_REG_TEST_IO */
54#define AN877_ADC_TESTMODE_OFF 0x0
55#define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1
56#define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2
57#define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3
58#define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4
59#define AN877_ADC_TESTMODE_PN23_SEQ 0x5
60#define AN877_ADC_TESTMODE_PN9_SEQ 0x6
61#define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7
62#define AN877_ADC_TESTMODE_USER 0x8
63#define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9
64#define AN877_ADC_TESTMODE_SYNC 0xA
65#define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB
66#define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC
67#define AN877_ADC_TESTMODE_RAMP 0xF
68
69/* AN877_ADC_REG_TRANSFER */
70#define AN877_ADC_TRANSFER_SYNC 0x1
71
72/* AN877_ADC_REG_OUTPUT_MODE */
73#define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0
74#define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1
75#define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2
76
77/* AN877_ADC_REG_OUTPUT_PHASE */
78#define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20
79#define AN877_ADC_INVERT_DCO_CLK 0x80
80
81/* AN877_ADC_REG_OUTPUT_DELAY */
82#define AN877_ADC_DCO_DELAY_ENABLE 0x80
83
eb61343d
MH		 84/*
85 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC
86 */
87
88#define CHIPID_AD9265 0x64
89#define AD9265_DEF_OUTPUT_MODE 0x40
90#define AD9265_REG_VREF_MASK 0xC0
91
4606d0f4
MH		 92/*
93 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC
94 */
95
96#define CHIPID_AD9434 0x6A
97#define AD9434_DEF_OUTPUT_MODE 0x00
98#define AD9434_REG_VREF_MASK 0xC0
99
ad679712
MH		 100/*
101 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
102 */
103
104#define CHIPID_AD9467 0x50
105#define AD9467_DEF_OUTPUT_MODE 0x08
106#define AD9467_REG_VREF_MASK 0x0F
107
43ebc481
NS		 108/*
109 * Analog Devices AD9643 14-Bit, 170/210/250 MSPS ADC
110 */
111
112#define CHIPID_AD9643 0x82
113#define AD9643_REG_VREF_MASK 0x1F
114
115/*
116 * Analog Devices AD9652 16-bit 310 MSPS ADC
117 */
118
119#define CHIPID_AD9652 0xC1
120#define AD9652_REG_VREF_MASK 0xC0
121
122/*
123 * Analog Devices AD9649 14-bit 20/40/65/80 MSPS ADC
124 */
125
126#define CHIPID_AD9649 0x6F
127#define AD9649_TEST_POINTS 8
128
05c4081f 129#define AD9647_MAX_TEST_POINTS 32
bdc87f98
NS		 130#define AD9467_CAN_INVERT(st) \
131 (!(st)->info->has_dco || (st)->info->has_dco_invert)
05c4081f 132
337dbb6e 133struct ad9467_chip_info {
fefbc4a5
NS		 134 const char *name;
135 unsigned int id;
136 const struct iio_chan_spec *channels;
137 unsigned int num_channels;
138 const unsigned int (*scale_table)[2];
139 int num_scales;
d6b133a6
NS		 140 unsigned long test_mask;
141 unsigned int test_mask_len;
fefbc4a5
NS		 142 unsigned long max_rate;
143 unsigned int default_output_mode;
144 unsigned int vref_mask;
145 unsigned int num_lanes;
bdc87f98
NS		 146 unsigned int dco_en;
147 unsigned int test_points;
05c4081f 148 /* data clock output */
fefbc4a5 149 bool has_dco;
bdc87f98 150 bool has_dco_invert;
337dbb6e
AA		 151};
152
d6b133a6
NS		 153struct ad9467_chan_test_mode {
154 struct ad9467_state *st;
155 unsigned int idx;
156 u8 mode;
157};
158
ad679712 159struct ad9467_state {
fefbc4a5
NS		 160 const struct ad9467_chip_info *info;
161 struct iio_backend *back;
162 struct spi_device *spi;
163 struct clk *clk;
d6b133a6
NS		 164 /* used for debugfs */
165 struct ad9467_chan_test_mode *chan_test;
fefbc4a5
NS		 166 unsigned int output_mode;
167 unsigned int (*scales)[2];
05c4081f
NS		 168 /*
169 * Times 2 because we may also invert the signal polarity and run the
170 * calibration again. For some reference on the test points (ad9265) see:
171 * https://www.analog.com/media/en/technical-documentation/data-sheets/ad9265.pdf
172 * at page 38 for the dco output delay. On devices as ad9467, the
173 * calibration is done at the backend level. For the ADI axi-adc:
174 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
175 * at the io delay control section.
176 */
177 DECLARE_BITMAP(calib_map, AD9647_MAX_TEST_POINTS * 2);
bdc87f98
NS		 178 /* number of bits of the map */
179 unsigned int calib_map_size;
fefbc4a5 180 struct gpio_desc *pwrdown_gpio;
73772019 181 /* ensure consistent state obtained on multiple related accesses */
fefbc4a5
NS		 182 struct mutex lock;
183 u8 buf[3] __aligned(IIO_DMA_MINALIGN);
ad679712
MH		 184};
185
7a8e7f13 186static int ad9467_spi_read(struct ad9467_state *st, unsigned int reg)
ad679712
MH		 187{
188 unsigned char tbuf[2], rbuf[1];
189 int ret;
190
191 tbuf[0] = 0x80 | (reg >> 8);
192 tbuf[1] = reg & 0xFF;
193
7a8e7f13 194 ret = spi_write_then_read(st->spi,
ad679712
MH		 195 tbuf, ARRAY_SIZE(tbuf),
196 rbuf, ARRAY_SIZE(rbuf));
197
198 if (ret < 0)
199 return ret;
200
201 return rbuf[0];
202}
203
7a8e7f13 204static int ad9467_spi_write(struct ad9467_state *st, unsigned int reg,
ad679712
MH		 205 unsigned int val)
206{
7a8e7f13
NS		 207 st->buf[0] = reg >> 8;
208 st->buf[1] = reg & 0xFF;
209 st->buf[2] = val;
ad679712 210
7a8e7f13 211 return spi_write(st->spi, st->buf, ARRAY_SIZE(st->buf));
ad679712
MH		 212}
213
bb42191f 214static int ad9467_reg_access(struct iio_dev *indio_dev, unsigned int reg,
ad679712
MH		 215 unsigned int writeval, unsigned int *readval)
216{
bb42191f 217 struct ad9467_state *st = iio_priv(indio_dev);
ad679712
MH		 218 int ret;
219
8bdfa4a2 220 if (!readval) {
73772019 221 guard(mutex)(&st->lock);
7a8e7f13 222 ret = ad9467_spi_write(st, reg, writeval);
e072e149
NS		 223 if (ret)
224 return ret;
7a8e7f13 225 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
e072e149 226 AN877_ADC_TRANSFER_SYNC);
ad679712
MH		 227 }
228
7a8e7f13 229 ret = ad9467_spi_read(st, reg);
ad679712
MH		 230 if (ret < 0)
231 return ret;
232 *readval = ret;
233
234 return 0;
235}
236
eb61343d
MH		 237static const unsigned int ad9265_scale_table[][2] = {
238 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
239};
240
4606d0f4
MH		 241static const unsigned int ad9434_scale_table[][2] = {
242 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00},
243 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05},
244 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A},
245 {1200, 0x0B}, {1180, 0x0C},
246};
247
ad679712
MH		 248static const unsigned int ad9467_scale_table[][2] = {
249 {2000, 0}, {2100, 6}, {2200, 7},
250 {2300, 8}, {2400, 9}, {2500, 10},
251};
252
43ebc481
NS		 253static const unsigned int ad9643_scale_table[][2] = {
254 {2087, 0x0F}, {2065, 0x0E}, {2042, 0x0D}, {2020, 0x0C}, {1997, 0x0B},
255 {1975, 0x0A}, {1952, 0x09}, {1930, 0x08}, {1907, 0x07}, {1885, 0x06},
256 {1862, 0x05}, {1840, 0x04}, {1817, 0x03}, {1795, 0x02}, {1772, 0x01},
257 {1750, 0x00}, {1727, 0x1F}, {1704, 0x1E}, {1681, 0x1D}, {1658, 0x1C},
258 {1635, 0x1B}, {1612, 0x1A}, {1589, 0x19}, {1567, 0x18}, {1544, 0x17},
259 {1521, 0x16}, {1498, 0x15}, {1475, 0x14}, {1452, 0x13}, {1429, 0x12},
260 {1406, 0x11}, {1383, 0x10},
261};
262
263static const unsigned int ad9649_scale_table[][2] = {
264 {2000, 0},
265};
266
267static const unsigned int ad9652_scale_table[][2] = {
268 {1250, 0}, {1125, 1}, {1200, 2}, {1250, 3}, {1000, 5},
269};
270
bb42191f 271static void __ad9467_get_scale(struct ad9467_state *st, int index,
ad679712
MH		 272 unsigned int *val, unsigned int *val2)
273{
bb42191f 274 const struct ad9467_chip_info *info = st->info;
ad679712
MH		 275 const struct iio_chan_spec *chan = &info->channels[0];
276 unsigned int tmp;
277
278 tmp = (info->scale_table[index][0] * 1000000ULL) >>
279 chan->scan_type.realbits;
280 *val = tmp / 1000000;
281 *val2 = tmp % 1000000;
282}
283
b92f94f7 284#define AD9467_CHAN(_chan, avai_mask, _si, _bits, _sign) \
ad679712
MH		 285{ \
286 .type = IIO_VOLTAGE, \
287 .indexed = 1, \
288 .channel = _chan, \
289 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
290 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
b92f94f7 291 .info_mask_shared_by_type_available = avai_mask, \
ad679712
MH		 292 .scan_index = _si, \
293 .scan_type = { \
294 .sign = _sign, \
295 .realbits = _bits, \
296 .storagebits = 16, \
297 }, \
298}
299
4606d0f4 300static const struct iio_chan_spec ad9434_channels[] = {
b92f94f7 301 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 12, 's'),
4606d0f4
MH		 302};
303
ad679712 304static const struct iio_chan_spec ad9467_channels[] = {
b92f94f7 305 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 16, 's'),
ad679712
MH		 306};
307
43ebc481
NS		 308static const struct iio_chan_spec ad9643_channels[] = {
309 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 14, 's'),
310 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE), 1, 14, 's'),
311};
312
313static const struct iio_chan_spec ad9649_channels[] = {
314 AD9467_CHAN(0, 0, 0, 14, 's'),
315};
316
317static const struct iio_chan_spec ad9652_channels[] = {
318 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 16, 's'),
319 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE), 1, 16, 's'),
320};
321
d6b133a6
NS		 322static const char * const ad9467_test_modes[] = {
323 [AN877_ADC_TESTMODE_OFF] = "off",
324 [AN877_ADC_TESTMODE_MIDSCALE_SHORT] = "midscale_short",
325 [AN877_ADC_TESTMODE_POS_FULLSCALE] = "pos_fullscale",
326 [AN877_ADC_TESTMODE_NEG_FULLSCALE] = "neg_fullscale",
327 [AN877_ADC_TESTMODE_ALT_CHECKERBOARD] = "checkerboard",
328 [AN877_ADC_TESTMODE_PN23_SEQ] = "prbs23",
329 [AN877_ADC_TESTMODE_PN9_SEQ] = "prbs9",
330 [AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE] = "one_zero_toggle",
331 [AN877_ADC_TESTMODE_USER] = "user",
332 [AN877_ADC_TESTMODE_BIT_TOGGLE] = "bit_toggle",
333 [AN877_ADC_TESTMODE_SYNC] = "sync",
334 [AN877_ADC_TESTMODE_ONE_BIT_HIGH] = "one_bit_high",
335 [AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY] = "mixed_bit_frequency",
336 [AN877_ADC_TESTMODE_RAMP] = "ramp",
337};
338
6dd3fa9f 339static const struct ad9467_chip_info ad9467_chip_tbl = {
bb42191f
NS		 340 .name = "ad9467",
341 .id = CHIPID_AD9467,
342 .max_rate = 250000000UL,
343 .scale_table = ad9467_scale_table,
344 .num_scales = ARRAY_SIZE(ad9467_scale_table),
345 .channels = ad9467_channels,
346 .num_channels = ARRAY_SIZE(ad9467_channels),
bdc87f98 347 .test_points = AD9647_MAX_TEST_POINTS,
d6b133a6
NS		 348 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE,
349 AN877_ADC_TESTMODE_OFF),
350 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1,
6dd3fa9f
NS		 351 .default_output_mode = AD9467_DEF_OUTPUT_MODE,
352 .vref_mask = AD9467_REG_VREF_MASK,
05c4081f 353 .num_lanes = 8,
6dd3fa9f
NS		 354};
355
356static const struct ad9467_chip_info ad9434_chip_tbl = {
bb42191f
NS		 357 .name = "ad9434",
358 .id = CHIPID_AD9434,
359 .max_rate = 500000000UL,
360 .scale_table = ad9434_scale_table,
361 .num_scales = ARRAY_SIZE(ad9434_scale_table),
362 .channels = ad9434_channels,
363 .num_channels = ARRAY_SIZE(ad9434_channels),
bdc87f98 364 .test_points = AD9647_MAX_TEST_POINTS,
d6b133a6
NS		 365 .test_mask = GENMASK(AN877_ADC_TESTMODE_USER, AN877_ADC_TESTMODE_OFF),
366 .test_mask_len = AN877_ADC_TESTMODE_USER + 1,
6dd3fa9f
NS		 367 .default_output_mode = AD9434_DEF_OUTPUT_MODE,
368 .vref_mask = AD9434_REG_VREF_MASK,
05c4081f 369 .num_lanes = 6,
6dd3fa9f
NS		 370};
371
372static const struct ad9467_chip_info ad9265_chip_tbl = {
bb42191f
NS		 373 .name = "ad9265",
374 .id = CHIPID_AD9265,
375 .max_rate = 125000000UL,
376 .scale_table = ad9265_scale_table,
377 .num_scales = ARRAY_SIZE(ad9265_scale_table),
378 .channels = ad9467_channels,
379 .num_channels = ARRAY_SIZE(ad9467_channels),
bdc87f98 380 .test_points = AD9647_MAX_TEST_POINTS,
d6b133a6
NS		 381 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE,
382 AN877_ADC_TESTMODE_OFF),
383 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1,
6dd3fa9f
NS		 384 .default_output_mode = AD9265_DEF_OUTPUT_MODE,
385 .vref_mask = AD9265_REG_VREF_MASK,
05c4081f 386 .has_dco = true,
bdc87f98 387 .has_dco_invert = true,
ad679712
MH		 388};
389
43ebc481
NS		 390static const struct ad9467_chip_info ad9643_chip_tbl = {
391 .name = "ad9643",
392 .id = CHIPID_AD9643,
393 .max_rate = 250000000UL,
394 .scale_table = ad9643_scale_table,
395 .num_scales = ARRAY_SIZE(ad9643_scale_table),
396 .channels = ad9643_channels,
397 .num_channels = ARRAY_SIZE(ad9643_channels),
398 .test_points = AD9647_MAX_TEST_POINTS,
d6b133a6
NS		 399 .test_mask = BIT(AN877_ADC_TESTMODE_RAMP) |
400 GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, AN877_ADC_TESTMODE_OFF),
401 .test_mask_len = AN877_ADC_TESTMODE_RAMP + 1,
43ebc481
NS		 402 .vref_mask = AD9643_REG_VREF_MASK,
403 .has_dco = true,
404 .has_dco_invert = true,
405 .dco_en = AN877_ADC_DCO_DELAY_ENABLE,
406};
407
408static const struct ad9467_chip_info ad9649_chip_tbl = {
409 .name = "ad9649",
410 .id = CHIPID_AD9649,
411 .max_rate = 80000000UL,
412 .scale_table = ad9649_scale_table,
413 .num_scales = ARRAY_SIZE(ad9649_scale_table),
414 .channels = ad9649_channels,
415 .num_channels = ARRAY_SIZE(ad9649_channels),
416 .test_points = AD9649_TEST_POINTS,
d6b133a6
NS		 417 .test_mask = GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY,
418 AN877_ADC_TESTMODE_OFF),
419 .test_mask_len = AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY + 1,
43ebc481
NS		 420 .has_dco = true,
421 .has_dco_invert = true,
422 .dco_en = AN877_ADC_DCO_DELAY_ENABLE,
423};
424
425static const struct ad9467_chip_info ad9652_chip_tbl = {
426 .name = "ad9652",
427 .id = CHIPID_AD9652,
428 .max_rate = 310000000UL,
429 .scale_table = ad9652_scale_table,
430 .num_scales = ARRAY_SIZE(ad9652_scale_table),
431 .channels = ad9652_channels,
432 .num_channels = ARRAY_SIZE(ad9652_channels),
433 .test_points = AD9647_MAX_TEST_POINTS,
d6b133a6
NS		 434 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE,
435 AN877_ADC_TESTMODE_OFF),
436 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1,
43ebc481
NS		 437 .vref_mask = AD9652_REG_VREF_MASK,
438 .has_dco = true,
439};
440
bb42191f 441static int ad9467_get_scale(struct ad9467_state *st, int *val, int *val2)
ad679712 442{
bb42191f 443 const struct ad9467_chip_info *info = st->info;
b92f94f7
NS		 444 unsigned int vref_val;
445 unsigned int i = 0;
e072e149 446 int ret;
ad679712 447
b92f94f7
NS		 448 /* nothing to read if we only have one possible scale */
449 if (info->num_scales == 1)
450 goto out_get_scale;
451
7a8e7f13 452 ret = ad9467_spi_read(st, AN877_ADC_REG_VREF);
e072e149
NS		 453 if (ret < 0)
454 return ret;
ad679712 455
bb42191f 456 vref_val = ret & info->vref_mask;
ad679712
MH		 457
458 for (i = 0; i < info->num_scales; i++) {
459 if (vref_val == info->scale_table[i][1])
460 break;
461 }
462
463 if (i == info->num_scales)
464 return -ERANGE;
465
b92f94f7 466out_get_scale:
bb42191f 467 __ad9467_get_scale(st, i, val, val2);
ad679712
MH		 468
469 return IIO_VAL_INT_PLUS_MICRO;
470}
471
bb42191f 472static int ad9467_set_scale(struct ad9467_state *st, int val, int val2)
ad679712 473{
bb42191f 474 const struct ad9467_chip_info *info = st->info;
ad679712
MH		 475 unsigned int scale_val[2];
476 unsigned int i;
e072e149 477 int ret;
ad679712
MH		 478
479 if (val != 0)
480 return -EINVAL;
b92f94f7
NS		 481 if (info->num_scales == 1)
482 return -EOPNOTSUPP;
ad679712
MH		 483
484 for (i = 0; i < info->num_scales; i++) {
bb42191f 485 __ad9467_get_scale(st, i, &scale_val[0], &scale_val[1]);
ad679712
MH		 486 if (scale_val[0] != val || scale_val[1] != val2)
487 continue;
488
73772019 489 guard(mutex)(&st->lock);
7a8e7f13 490 ret = ad9467_spi_write(st, AN877_ADC_REG_VREF,
e072e149
NS		 491 info->scale_table[i][1]);
492 if (ret < 0)
493 return ret;
494
7a8e7f13 495 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
e072e149 496 AN877_ADC_TRANSFER_SYNC);
ad679712
MH		 497 }
498
499 return -EINVAL;
500}
501
7a8e7f13 502static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode)
05c4081f
NS		 503{
504 int ret;
505
7a8e7f13 506 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_MODE, mode);
05c4081f
NS		 507 if (ret < 0)
508 return ret;
509
7a8e7f13 510 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
05c4081f
NS		 511 AN877_ADC_TRANSFER_SYNC);
512}
513
7394a155
NS		 514static int ad9467_testmode_set(struct ad9467_state *st, unsigned int chan,
515 unsigned int test_mode)
516{
517 int ret;
518
519 if (st->info->num_channels > 1) {
520 /* so that the test mode is only applied to one channel */
521 ret = ad9467_spi_write(st, AN877_ADC_REG_CHAN_INDEX, BIT(chan));
522 if (ret)
523 return ret;
524 }
525
526 ret = ad9467_spi_write(st, AN877_ADC_REG_TEST_IO, test_mode);
527 if (ret)
528 return ret;
529
530 if (st->info->num_channels > 1) {
531 /* go to default state where all channels get write commands */
532 ret = ad9467_spi_write(st, AN877_ADC_REG_CHAN_INDEX,
533 GENMASK(st->info->num_channels - 1, 0));
534 if (ret)
535 return ret;
536 }
537
538 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
539 AN877_ADC_TRANSFER_SYNC);
540}
541
5b30937b
NS		 542static int ad9467_backend_testmode_on(struct ad9467_state *st,
543 unsigned int chan,
544 enum iio_backend_test_pattern pattern)
05c4081f
NS		 545{
546 struct iio_backend_data_fmt data = {
547 .enable = false,
548 };
5b30937b
NS		 549 int ret;
550
551 ret = iio_backend_data_format_set(st->back, chan, &data);
552 if (ret)
553 return ret;
554
555 ret = iio_backend_test_pattern_set(st->back, chan, pattern);
556 if (ret)
557 return ret;
558
559 return iio_backend_chan_enable(st->back, chan);
560}
561
562static int ad9467_backend_testmode_off(struct ad9467_state *st,
563 unsigned int chan)
564{
565 struct iio_backend_data_fmt data = {
566 .enable = true,
567 .sign_extend = true,
568 };
569 int ret;
570
571 ret = iio_backend_chan_disable(st->back, chan);
572 if (ret)
573 return ret;
574
575 ret = iio_backend_test_pattern_set(st->back, chan,
576 IIO_BACKEND_NO_TEST_PATTERN);
577 if (ret)
578 return ret;
579
580 return iio_backend_data_format_set(st->back, chan, &data);
581}
582
583static int ad9647_calibrate_prepare(struct ad9467_state *st)
584{
05c4081f
NS		 585 unsigned int c;
586 int ret;
587
7a8e7f13 588 ret = ad9467_outputmode_set(st, st->info->default_output_mode);
05c4081f
NS		 589 if (ret)
590 return ret;
591
592 for (c = 0; c < st->info->num_channels; c++) {
7394a155
NS		 593 ret = ad9467_testmode_set(st, c, AN877_ADC_TESTMODE_PN9_SEQ);
594 if (ret)
595 return ret;
596
5b30937b
NS		 597 ret = ad9467_backend_testmode_on(st, c,
598 IIO_BACKEND_ADI_PRBS_9A);
7394a155
NS		 599 if (ret)
600 return ret;
601 }
05c4081f 602
7394a155 603 return 0;
05c4081f
NS		 604}
605
7a8e7f13 606static int ad9647_calibrate_polarity_set(struct ad9467_state *st,
05c4081f
NS		 607 bool invert)
608{
609 enum iio_backend_sample_trigger trigger;
610
611 if (st->info->has_dco) {
612 unsigned int phase = AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN;
613
614 if (invert)
615 phase |= AN877_ADC_INVERT_DCO_CLK;
616
7a8e7f13 617 return ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_PHASE,
05c4081f
NS		 618 phase);
619 }
620
621 if (invert)
622 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING;
623 else
624 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING;
625
626 return iio_backend_data_sample_trigger(st->back, trigger);
627}
628
629/*
630 * The idea is pretty simple. Find the max number of successful points in a row
631 * and get the one in the middle.
632 */
633static unsigned int ad9467_find_optimal_point(const unsigned long *calib_map,
634 unsigned int start,
635 unsigned int nbits,
636 unsigned int *val)
637{
638 unsigned int bit = start, end, start_cnt, cnt = 0;
639
640 for_each_clear_bitrange_from(bit, end, calib_map, nbits + start) {
641 if (end - bit > cnt) {
642 cnt = end - bit;
643 start_cnt = bit;
644 }
645 }
646
647 if (cnt)
648 *val = start_cnt + cnt / 2;
649
650 return cnt;
651}
652
7a8e7f13 653static int ad9467_calibrate_apply(struct ad9467_state *st, unsigned int val)
05c4081f
NS		 654{
655 unsigned int lane;
656 int ret;
657
658 if (st->info->has_dco) {
7a8e7f13 659 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_DELAY,
bdc87f98 660 val | st->info->dco_en);
05c4081f
NS		 661 if (ret)
662 return ret;
663
7a8e7f13 664 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER,
05c4081f
NS		 665 AN877_ADC_TRANSFER_SYNC);
666 }
667
668 for (lane = 0; lane < st->info->num_lanes; lane++) {
669 ret = iio_backend_iodelay_set(st->back, lane, val);
670 if (ret)
671 return ret;
672 }
673
674 return 0;
675}
676
7a8e7f13 677static int ad9647_calibrate_stop(struct ad9467_state *st)
05c4081f 678{
05c4081f
NS		 679 unsigned int c, mode;
680 int ret;
681
7394a155 682 for (c = 0; c < st->info->num_channels; c++) {
5b30937b 683 ret = ad9467_backend_testmode_off(st, c);
05c4081f
NS		 684 if (ret)
685 return ret;
7394a155
NS		 686
687 ret = ad9467_testmode_set(st, c, AN877_ADC_TESTMODE_OFF);
688 if (ret)
689 return ret;
05c4081f
NS		 690 }
691
692 mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
7394a155 693 return ad9467_outputmode_set(st, mode);
05c4081f
NS		 694}
695
696static int ad9467_calibrate(struct ad9467_state *st)
697{
7394a155 698 unsigned int point, val, inv_val, cnt, inv_cnt = 0, c;
05c4081f
NS		 699 /*
700 * Half of the bitmap is for the inverted signal. The number of test
701 * points is the same though...
702 */
bdc87f98 703 unsigned int test_points = st->info->test_points;
05c4081f
NS		 704 unsigned long sample_rate = clk_get_rate(st->clk);
705 struct device *dev = &st->spi->dev;
706 bool invert = false, stat;
707 int ret;
708
709 /* all points invalid */
bdc87f98 710 bitmap_fill(st->calib_map, st->calib_map_size);
05c4081f
NS		 711
712 ret = ad9647_calibrate_prepare(st);
713 if (ret)
714 return ret;
715retune:
716 ret = ad9647_calibrate_polarity_set(st, invert);
717 if (ret)
718 return ret;
719
bdc87f98 720 for (point = 0; point < st->info->test_points; point++) {
05c4081f
NS		 721 ret = ad9467_calibrate_apply(st, point);
722 if (ret)
723 return ret;
724
7394a155
NS		 725 for (c = 0; c < st->info->num_channels; c++) {
726 ret = iio_backend_chan_status(st->back, c, &stat);
727 if (ret)
728 return ret;
729
730 /*
731 * A point is considered valid if all channels report no
732 * error. If one reports an error, then we consider the
733 * point as invalid and we can break the loop right away.
734 */
735 if (stat) {
736 dev_dbg(dev, "Invalid point(%u, inv:%u) for CH:%u\n",
737 point, invert, c);
738 break;
739 }
740
741 if (c == st->info->num_channels - 1)
742 __clear_bit(point + invert * test_points,
743 st->calib_map);
744 }
05c4081f
NS		 745 }
746
747 if (!invert) {
748 cnt = ad9467_find_optimal_point(st->calib_map, 0, test_points,
749 &val);
750 /*
751 * We're happy if we find, at least, three good test points in
752 * a row.
753 */
754 if (cnt < 3) {
bdc87f98
NS		 755 if (AD9467_CAN_INVERT(st)) {
756 invert = true;
757 goto retune;
758 }
759
760 if (!cnt)
761 return -EIO;
05c4081f
NS		 762 }
763 } else {
764 inv_cnt = ad9467_find_optimal_point(st->calib_map, test_points,
765 test_points, &inv_val);
766 if (!inv_cnt && !cnt)
767 return -EIO;
768 }
769
770 if (inv_cnt < cnt) {
771 ret = ad9647_calibrate_polarity_set(st, false);
772 if (ret)
773 return ret;
774 } else {
775 /*
776 * polarity inverted is the last test to run. Hence, there's no
777 * need to re-do any configuration. We just need to "normalize"
778 * the selected value.
779 */
780 val = inv_val - test_points;
781 }
782
783 if (st->info->has_dco)
784 dev_dbg(dev, "%sDCO 0x%X CLK %lu Hz\n", inv_cnt >= cnt ? "INVERT " : "",
785 val, sample_rate);
786 else
787 dev_dbg(dev, "%sIDELAY 0x%x\n", inv_cnt >= cnt ? "INVERT " : "",
788 val);
789
790 ret = ad9467_calibrate_apply(st, val);
791 if (ret)
792 return ret;
793
794 /* finally apply the optimal value */
795 return ad9647_calibrate_stop(st);
796}
797
bb42191f 798static int ad9467_read_raw(struct iio_dev *indio_dev,
ad679712
MH		 799 struct iio_chan_spec const *chan,
800 int *val, int *val2, long m)
801{
bb42191f 802 struct ad9467_state *st = iio_priv(indio_dev);
ad679712
MH		 803
804 switch (m) {
805 case IIO_CHAN_INFO_SCALE:
bb42191f 806 return ad9467_get_scale(st, val, val2);
ad679712
MH		 807 case IIO_CHAN_INFO_SAMP_FREQ:
808 *val = clk_get_rate(st->clk);
809
810 return IIO_VAL_INT;
811 default:
812 return -EINVAL;
813 }
814}
815
bb42191f 816static int ad9467_write_raw(struct iio_dev *indio_dev,
ad679712
MH		 817 struct iio_chan_spec const *chan,
818 int val, int val2, long mask)
819{
bb42191f
NS		 820 struct ad9467_state *st = iio_priv(indio_dev);
821 const struct ad9467_chip_info *info = st->info;
05c4081f 822 unsigned long sample_rate;
ad679712 823 long r_clk;
05c4081f 824 int ret;
ad679712
MH		 825
826 switch (mask) {
827 case IIO_CHAN_INFO_SCALE:
bb42191f 828 return ad9467_set_scale(st, val, val2);
ad679712
MH		 829 case IIO_CHAN_INFO_SAMP_FREQ:
830 r_clk = clk_round_rate(st->clk, val);
831 if (r_clk < 0 || r_clk > info->max_rate) {
832 dev_warn(&st->spi->dev,
833 "Error setting ADC sample rate %ld", r_clk);
834 return -EINVAL;
835 }
836
05c4081f
NS		 837 sample_rate = clk_get_rate(st->clk);
838 /*
839 * clk_set_rate() would also do this but since we would still
840 * need it for avoiding an unnecessary calibration, do it now.
841 */
842 if (sample_rate == r_clk)
843 return 0;
844
845 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
846 ret = clk_set_rate(st->clk, r_clk);
847 if (ret)
848 return ret;
849
850 guard(mutex)(&st->lock);
851 ret = ad9467_calibrate(st);
852 }
853 return ret;
ad679712
MH		 854 default:
855 return -EINVAL;
856 }
857}
858
bb42191f 859static int ad9467_read_avail(struct iio_dev *indio_dev,
b73f08bb
NS		 860 struct iio_chan_spec const *chan,
861 const int **vals, int *type, int *length,
862 long mask)
863{
bb42191f
NS		 864 struct ad9467_state *st = iio_priv(indio_dev);
865 const struct ad9467_chip_info *info = st->info;
b73f08bb
NS		 866
867 switch (mask) {
868 case IIO_CHAN_INFO_SCALE:
869 *vals = (const int *)st->scales;
870 *type = IIO_VAL_INT_PLUS_MICRO;
871 /* Values are stored in a 2D matrix */
872 *length = info->num_scales * 2;
873 return IIO_AVAIL_LIST;
874 default:
875 return -EINVAL;
876 }
877}
878
bb42191f
NS		 879static int ad9467_update_scan_mode(struct iio_dev *indio_dev,
880 const unsigned long *scan_mask)
881{
882 struct ad9467_state *st = iio_priv(indio_dev);
883 unsigned int c;
884 int ret;
885
886 for (c = 0; c < st->info->num_channels; c++) {
887 if (test_bit(c, scan_mask))
888 ret = iio_backend_chan_enable(st->back, c);
889 else
890 ret = iio_backend_chan_disable(st->back, c);
891 if (ret)
892 return ret;
893 }
894
895 return 0;
896}
897
b92f94f7 898static struct iio_info ad9467_info = {
bb42191f
NS		 899 .read_raw = ad9467_read_raw,
900 .write_raw = ad9467_write_raw,
901 .update_scan_mode = ad9467_update_scan_mode,
902 .debugfs_reg_access = ad9467_reg_access,
903 .read_avail = ad9467_read_avail,
904};
905
bb42191f 906static int ad9467_scale_fill(struct ad9467_state *st)
b73f08bb 907{
bb42191f 908 const struct ad9467_chip_info *info = st->info;
b73f08bb
NS		 909 unsigned int i, val1, val2;
910
911 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales,
912 sizeof(*st->scales), GFP_KERNEL);
913 if (!st->scales)
914 return -ENOMEM;
915
916 for (i = 0; i < info->num_scales; i++) {
bb42191f 917 __ad9467_get_scale(st, i, &val1, &val2);
b73f08bb
NS		 918 st->scales[i][0] = val1;
919 st->scales[i][1] = val2;
920 }
921
922 return 0;
923}
924
76f02853
NS		 925static int ad9467_reset(struct device *dev)
926{
927 struct gpio_desc *gpio;
928
929 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
930 if (IS_ERR_OR_NULL(gpio))
931 return PTR_ERR_OR_ZERO(gpio);
932
933 fsleep(1);
934 gpiod_set_value_cansleep(gpio, 0);
935 fsleep(10 * USEC_PER_MSEC);
936
937 return 0;
938}
939
bb42191f
NS		 940static int ad9467_iio_backend_get(struct ad9467_state *st)
941{
942 struct device *dev = &st->spi->dev;
943 struct device_node *__back;
944
945 st->back = devm_iio_backend_get(dev, NULL);
946 if (!IS_ERR(st->back))
947 return 0;
948 /* If not found, don't error out as we might have legacy DT property */
949 if (PTR_ERR(st->back) != -ENOENT)
950 return PTR_ERR(st->back);
951
952 /*
953 * if we don't get the backend using the normal API's, use the legacy
954 * 'adi,adc-dev' property. So we get all nodes with that property, and
955 * look for the one pointing at us. Then we directly lookup that fwnode
956 * on the backend list of registered devices. This is done so we don't
957 * make io-backends mandatory which would break DT ABI.
958 */
959 for_each_node_with_property(__back, "adi,adc-dev") {
960 struct device_node *__me;
961
962 __me = of_parse_phandle(__back, "adi,adc-dev", 0);
963 if (!__me)
964 continue;
965
966 if (!device_match_of_node(dev, __me)) {
967 of_node_put(__me);
968 continue;
969 }
970
971 of_node_put(__me);
972 st->back = __devm_iio_backend_get_from_fwnode_lookup(dev,
973 of_fwnode_handle(__back));
974 of_node_put(__back);
975 return PTR_ERR_OR_ZERO(st->back);
976 }
977
978 return -ENODEV;
979}
980
d6b133a6
NS		 981static int ad9467_test_mode_available_show(struct seq_file *s, void *ignored)
982{
983 struct ad9467_state *st = s->private;
984 unsigned int bit;
985
986 for_each_set_bit(bit, &st->info->test_mask, st->info->test_mask_len)
987 seq_printf(s, "%s\n", ad9467_test_modes[bit]);
988
989 return 0;
990}
991DEFINE_SHOW_ATTRIBUTE(ad9467_test_mode_available);
992
993static ssize_t ad9467_chan_test_mode_read(struct file *file,
994 char __user *userbuf, size_t count,
995 loff_t *ppos)
996{
997 struct ad9467_chan_test_mode *chan = file->private_data;
998 struct ad9467_state *st = chan->st;
999 char buf[128] = {0};
1000 size_t len;
1001 int ret;
1002
1003 if (chan->mode == AN877_ADC_TESTMODE_PN9_SEQ ||
1004 chan->mode == AN877_ADC_TESTMODE_PN23_SEQ) {
1005 len = scnprintf(buf, sizeof(buf), "Running \"%s\" Test:\n\t",
1006 ad9467_test_modes[chan->mode]);
1007
1008 ret = iio_backend_debugfs_print_chan_status(st->back, chan->idx,
1009 buf + len,
1010 sizeof(buf) - len);
1011 if (ret < 0)
1012 return ret;
1013 len += ret;
1014 } else if (chan->mode == AN877_ADC_TESTMODE_OFF) {
1015 len = scnprintf(buf, sizeof(buf), "No test Running...\n");
1016 } else {
1017 len = scnprintf(buf, sizeof(buf), "Running \"%s\" Test on CH:%u\n",
1018 ad9467_test_modes[chan->mode], chan->idx);
1019 }
1020
1021 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
1022}
1023
1024static ssize_t ad9467_chan_test_mode_write(struct file *file,
1025 const char __user *userbuf,
1026 size_t count, loff_t *ppos)
1027{
1028 struct ad9467_chan_test_mode *chan = file->private_data;
1029 struct ad9467_state *st = chan->st;
1030 char test_mode[32] = {0};
1031 unsigned int mode;
1032 int ret;
1033
1034 ret = simple_write_to_buffer(test_mode, sizeof(test_mode) - 1, ppos,
1035 userbuf, count);
1036 if (ret < 0)
1037 return ret;
1038
1039 for_each_set_bit(mode, &st->info->test_mask, st->info->test_mask_len) {
1040 if (sysfs_streq(test_mode, ad9467_test_modes[mode]))
1041 break;
1042 }
1043
1044 if (mode == st->info->test_mask_len)
1045 return -EINVAL;
1046
1047 guard(mutex)(&st->lock);
1048
1049 if (mode == AN877_ADC_TESTMODE_OFF) {
1050 unsigned int out_mode;
1051
1052 if (chan->mode == AN877_ADC_TESTMODE_PN9_SEQ ||
1053 chan->mode == AN877_ADC_TESTMODE_PN23_SEQ) {
1054 ret = ad9467_backend_testmode_off(st, chan->idx);
1055 if (ret)
1056 return ret;
1057 }
1058
1059 ret = ad9467_testmode_set(st, chan->idx, mode);
1060 if (ret)
1061 return ret;
1062
1063 out_mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
1064 ret = ad9467_outputmode_set(st, out_mode);
1065 if (ret)
1066 return ret;
1067 } else {
1068 ret = ad9467_outputmode_set(st, st->info->default_output_mode);
1069 if (ret)
1070 return ret;
1071
1072 ret = ad9467_testmode_set(st, chan->idx, mode);
1073 if (ret)
1074 return ret;
1075
1076 /* some patterns have a backend matching monitoring block */
1077 if (mode == AN877_ADC_TESTMODE_PN9_SEQ) {
1078 ret = ad9467_backend_testmode_on(st, chan->idx,
1079 IIO_BACKEND_ADI_PRBS_9A);
1080 if (ret)
1081 return ret;
1082 } else if (mode == AN877_ADC_TESTMODE_PN23_SEQ) {
1083 ret = ad9467_backend_testmode_on(st, chan->idx,
1084 IIO_BACKEND_ADI_PRBS_23A);
1085 if (ret)
1086 return ret;
1087 }
1088 }
1089
1090 chan->mode = mode;
1091
1092 return count;
1093}
1094
1095static const struct file_operations ad9467_chan_test_mode_fops = {
1096 .open = simple_open,
1097 .read = ad9467_chan_test_mode_read,
1098 .write = ad9467_chan_test_mode_write,
1099 .llseek = default_llseek,
1100 .owner = THIS_MODULE,
1101};
1102
05c4081f
NS		 1103static ssize_t ad9467_dump_calib_table(struct file *file,
1104 char __user *userbuf,
1105 size_t count, loff_t *ppos)
1106{
1107 struct ad9467_state *st = file->private_data;
bdc87f98 1108 unsigned int bit;
05c4081f
NS		 1109 /* +2 for the newline and +1 for the string termination */
1110 unsigned char map[AD9647_MAX_TEST_POINTS * 2 + 3];
1111 ssize_t len = 0;
1112
1113 guard(mutex)(&st->lock);
1114 if (*ppos)
1115 goto out_read;
1116
bdc87f98
NS		 1117 for (bit = 0; bit < st->calib_map_size; bit++) {
1118 if (AD9467_CAN_INVERT(st) && bit == st->calib_map_size / 2)
05c4081f
NS		 1119 len += scnprintf(map + len, sizeof(map) - len, "\n");
1120
1121 len += scnprintf(map + len, sizeof(map) - len, "%c",
1122 test_bit(bit, st->calib_map) ? 'x' : 'o');
1123 }
1124
1125 len += scnprintf(map + len, sizeof(map) - len, "\n");
1126out_read:
1127 return simple_read_from_buffer(userbuf, count, ppos, map, len);
1128}
1129
1130static const struct file_operations ad9467_calib_table_fops = {
1131 .open = simple_open,
1132 .read = ad9467_dump_calib_table,
1133 .llseek = default_llseek,
1134 .owner = THIS_MODULE,
1135};
1136
1137static void ad9467_debugfs_init(struct iio_dev *indio_dev)
1138{
1139 struct dentry *d = iio_get_debugfs_dentry(indio_dev);
1140 struct ad9467_state *st = iio_priv(indio_dev);
d6b133a6
NS		 1141 char attr_name[32];
1142 unsigned int chan;
05c4081f
NS		 1143
1144 if (!IS_ENABLED(CONFIG_DEBUG_FS))
1145 return;
1146
d6b133a6
NS		 1147 st->chan_test = devm_kcalloc(&st->spi->dev, st->info->num_channels,
1148 sizeof(*st->chan_test), GFP_KERNEL);
1149 if (!st->chan_test)
1150 return;
1151
05c4081f
NS		 1152 debugfs_create_file("calibration_table_dump", 0400, d, st,
1153 &ad9467_calib_table_fops);
d6b133a6
NS		 1154
1155 for (chan = 0; chan < st->info->num_channels; chan++) {
1156 snprintf(attr_name, sizeof(attr_name), "in_voltage%u_test_mode",
1157 chan);
1158 st->chan_test[chan].idx = chan;
1159 st->chan_test[chan].st = st;
1160 debugfs_create_file(attr_name, 0600, d, &st->chan_test[chan],
1161 &ad9467_chan_test_mode_fops);
1162 }
1163
1164 debugfs_create_file("in_voltage_test_mode_available", 0400, d, st,
1165 &ad9467_test_mode_available_fops);
1166
1167 iio_backend_debugfs_add(st->back, indio_dev);
05c4081f
NS		 1168}
1169
ad679712
MH		 1170static int ad9467_probe(struct spi_device *spi)
1171{
bb42191f 1172 struct iio_dev *indio_dev;
ad679712
MH		 1173 struct ad9467_state *st;
1174 unsigned int id;
1175 int ret;
1176
bb42191f
NS		 1177 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1178 if (!indio_dev)
1179 return -ENOMEM;
ad679712 1180
bb42191f 1181 st = iio_priv(indio_dev);
ad679712
MH		 1182 st->spi = spi;
1183
bb42191f
NS		 1184 st->info = spi_get_device_match_data(spi);
1185 if (!st->info)
1186 return -ENODEV;
1187
bdc87f98
NS		 1188 st->calib_map_size = st->info->test_points;
1189 if (AD9467_CAN_INVERT(st))
1190 st->calib_map_size *= 2;
1191
cdd07b3a 1192 st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk");
ad679712
MH		 1193 if (IS_ERR(st->clk))
1194 return PTR_ERR(st->clk);
1195
ad679712
MH		 1196 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
1197 GPIOD_OUT_LOW);
1198 if (IS_ERR(st->pwrdown_gpio))
1199 return PTR_ERR(st->pwrdown_gpio);
1200
76f02853
NS		 1201 ret = ad9467_reset(&spi->dev);
1202 if (ret)
1203 return ret;
ad679712 1204
bb42191f 1205 ret = ad9467_scale_fill(st);
b73f08bb
NS		 1206 if (ret)
1207 return ret;
1208
7a8e7f13 1209 id = ad9467_spi_read(st, AN877_ADC_REG_CHIP_ID);
bb42191f 1210 if (id != st->info->id) {
6026af6a 1211 dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n",
bb42191f 1212 id, st->info->id);
ad679712
MH		 1213 return -ENODEV;
1214 }
1215
b92f94f7
NS		 1216 if (st->info->num_scales > 1)
1217 ad9467_info.read_avail = ad9467_read_avail;
bb42191f
NS		 1218 indio_dev->name = st->info->name;
1219 indio_dev->channels = st->info->channels;
1220 indio_dev->num_channels = st->info->num_channels;
1221 indio_dev->info = &ad9467_info;
ad679712 1222
bb42191f
NS		 1223 ret = ad9467_iio_backend_get(st);
1224 if (ret)
1225 return ret;
337dbb6e 1226
bb42191f
NS		 1227 ret = devm_iio_backend_request_buffer(&spi->dev, st->back, indio_dev);
1228 if (ret)
1229 return ret;
1230
1231 ret = devm_iio_backend_enable(&spi->dev, st->back);
1232 if (ret)
1233 return ret;
1234
05c4081f
NS		 1235 ret = ad9467_calibrate(st);
1236 if (ret)
1237 return ret;
1238
1239 ret = devm_iio_device_register(&spi->dev, indio_dev);
bb42191f
NS		 1240 if (ret)
1241 return ret;
1242
05c4081f
NS		 1243 ad9467_debugfs_init(indio_dev);
1244
1245 return 0;
ad679712
MH		 1246}
1247
1248static const struct of_device_id ad9467_of_match[] = {
6dd3fa9f
NS		 1249 { .compatible = "adi,ad9265", .data = &ad9265_chip_tbl, },
1250 { .compatible = "adi,ad9434", .data = &ad9434_chip_tbl, },
1251 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl, },
43ebc481
NS		 1252 { .compatible = "adi,ad9643", .data = &ad9643_chip_tbl, },
1253 { .compatible = "adi,ad9649", .data = &ad9649_chip_tbl, },
1254 { .compatible = "adi,ad9652", .data = &ad9652_chip_tbl, },
09e3bdfe 1255 { }
ad679712
MH		 1256};
1257MODULE_DEVICE_TABLE(of, ad9467_of_match);
1258
28302652 1259static const struct spi_device_id ad9467_ids[] = {
6dd3fa9f
NS		 1260 { "ad9265", (kernel_ulong_t)&ad9265_chip_tbl },
1261 { "ad9434", (kernel_ulong_t)&ad9434_chip_tbl },
1262 { "ad9467", (kernel_ulong_t)&ad9467_chip_tbl },
43ebc481
NS		 1263 { "ad9643", (kernel_ulong_t)&ad9643_chip_tbl },
1264 { "ad9649", (kernel_ulong_t)&ad9649_chip_tbl, },
1265 { "ad9652", (kernel_ulong_t)&ad9652_chip_tbl, },
09e3bdfe 1266 { }
28302652
WY		 1267};
1268MODULE_DEVICE_TABLE(spi, ad9467_ids);
1269
ad679712
MH		 1270static struct spi_driver ad9467_driver = {
1271 .driver = {
1272 .name = "ad9467",
1273 .of_match_table = ad9467_of_match,
1274 },
1275 .probe = ad9467_probe,
28302652 1276 .id_table = ad9467_ids,
ad679712
MH		 1277};
1278module_spi_driver(ad9467_driver);
1279
1280MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1281MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver");
1282MODULE_LICENSE("GPL v2");
bb42191f 1283MODULE_IMPORT_NS(IIO_BACKEND);
Linux 6.x block layer and io_uring tree(s)