[linux-block.git] / drivers / iio / adc / ad7923.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * AD7904/AD7914/AD7923/AD7924/AD7908/AD7918/AD7928 SPI ADC driver
 *
 * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
 * Copyright 2012 CS Systemes d'Information
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/property.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/interrupt.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#define AD7923_WRITE_CR		BIT(11)		/* write control register */
#define AD7923_RANGE		BIT(1)		/* range to REFin */
#define AD7923_CODING		BIT(0)		/* coding is straight binary */
#define AD7923_PM_MODE_AS	(1)		/* auto shutdown */
#define AD7923_PM_MODE_FS	(2)		/* full shutdown */
#define AD7923_PM_MODE_OPS	(3)		/* normal operation */
#define AD7923_SEQUENCE_OFF	(0)		/* no sequence fonction */
#define AD7923_SEQUENCE_PROTECT	(2)		/* no interrupt write cycle */
#define AD7923_SEQUENCE_ON	(3)		/* continuous sequence */


#define AD7923_PM_MODE_WRITE(mode)	((mode) << 4)	 /* write mode */
#define AD7923_CHANNEL_WRITE(channel)	((channel) << 6) /* write channel */
#define AD7923_SEQUENCE_WRITE(sequence)	((((sequence) & 1) << 3) \
					+ (((sequence) & 2) << 9))
						/* write sequence fonction */
/* left shift for CR : bit 11 transmit in first */
#define AD7923_SHIFT_REGISTER	4

/* val = value, dec = left shift, bits = number of bits of the mask */
#define EXTRACT(val, dec, bits)		(((val) >> (dec)) & ((1 << (bits)) - 1))

struct ad7923_state {
	struct spi_device		*spi;
	struct spi_transfer		ring_xfer[5];
	struct spi_transfer		scan_single_xfer[2];
	struct spi_message		ring_msg;
	struct spi_message		scan_single_msg;

	struct regulator		*reg;

	unsigned int			settings;

	/*
	 * DMA (thus cache coherency maintenance) may require the
	 * transfer buffers to live in their own cache lines.
	 * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp
	 * Length = 8 channels + 4 extra for 8 byte timestamp
	 */
	__be16				rx_buf[12] __aligned(IIO_DMA_MINALIGN);
	__be16				tx_buf[4];
};

struct ad7923_chip_info {
	const struct iio_chan_spec *channels;
	unsigned int num_channels;
};

enum ad7923_id {
	AD7904,
	AD7914,
	AD7924,
	AD7908,
	AD7918,
	AD7928
};

#define AD7923_V_CHAN(index, bits)					\
	{								\
		.type = IIO_VOLTAGE,					\
		.indexed = 1,						\
		.channel = index,					\
		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
		.address = index,					\
		.scan_index = index,					\
		.scan_type = {						\
			.sign = 'u',					\
			.realbits = (bits),				\
			.storagebits = 16,				\
			.shift = 12 - (bits),				\
			.endianness = IIO_BE,				\
		},							\
	}

#define DECLARE_AD7923_CHANNELS(name, bits) \
const struct iio_chan_spec name ## _channels[] = { \
	AD7923_V_CHAN(0, bits), \
	AD7923_V_CHAN(1, bits), \
	AD7923_V_CHAN(2, bits), \
	AD7923_V_CHAN(3, bits), \
	IIO_CHAN_SOFT_TIMESTAMP(4), \
}

#define DECLARE_AD7908_CHANNELS(name, bits) \
const struct iio_chan_spec name ## _channels[] = { \
	AD7923_V_CHAN(0, bits), \
	AD7923_V_CHAN(1, bits), \
	AD7923_V_CHAN(2, bits), \
	AD7923_V_CHAN(3, bits), \
	AD7923_V_CHAN(4, bits), \
	AD7923_V_CHAN(5, bits), \
	AD7923_V_CHAN(6, bits), \
	AD7923_V_CHAN(7, bits), \
	IIO_CHAN_SOFT_TIMESTAMP(8), \
}

static DECLARE_AD7923_CHANNELS(ad7904, 8);
static DECLARE_AD7923_CHANNELS(ad7914, 10);
static DECLARE_AD7923_CHANNELS(ad7924, 12);
static DECLARE_AD7908_CHANNELS(ad7908, 8);
static DECLARE_AD7908_CHANNELS(ad7918, 10);
static DECLARE_AD7908_CHANNELS(ad7928, 12);

static const struct ad7923_chip_info ad7923_chip_info[] = {
	[AD7904] = {
		.channels = ad7904_channels,
		.num_channels = ARRAY_SIZE(ad7904_channels),
	},
	[AD7914] = {
		.channels = ad7914_channels,
		.num_channels = ARRAY_SIZE(ad7914_channels),
	},
	[AD7924] = {
		.channels = ad7924_channels,
		.num_channels = ARRAY_SIZE(ad7924_channels),
	},
	[AD7908] = {
		.channels = ad7908_channels,
		.num_channels = ARRAY_SIZE(ad7908_channels),
	},
	[AD7918] = {
		.channels = ad7918_channels,
		.num_channels = ARRAY_SIZE(ad7918_channels),
	},
	[AD7928] = {
		.channels = ad7928_channels,
		.num_channels = ARRAY_SIZE(ad7928_channels),
	},
};

/*
 * ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask
 */
static int ad7923_update_scan_mode(struct iio_dev *indio_dev,
				   const unsigned long *active_scan_mask)
{
	struct ad7923_state *st = iio_priv(indio_dev);
	int i, cmd, len;

	len = 0;
	/*
	 * For this driver the last channel is always the software timestamp so
	 * skip that one.
	 */
	for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) {
		cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) |
			AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
			st->settings;
		cmd <<= AD7923_SHIFT_REGISTER;
		st->tx_buf[len++] = cpu_to_be16(cmd);
	}
	/* build spi ring message */
	st->ring_xfer[0].tx_buf = &st->tx_buf[0];
	st->ring_xfer[0].len = len;
	st->ring_xfer[0].cs_change = 1;

	spi_message_init(&st->ring_msg);
	spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);

	for (i = 0; i < len; i++) {
		st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i];
		st->ring_xfer[i + 1].len = 2;
		st->ring_xfer[i + 1].cs_change = 1;
		spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg);
	}
	/* make sure last transfer cs_change is not set */
	st->ring_xfer[i + 1].cs_change = 0;

	return 0;
}

static irqreturn_t ad7923_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct ad7923_state *st = iio_priv(indio_dev);
	int b_sent;

	b_sent = spi_sync(st->spi, &st->ring_msg);
	if (b_sent)
		goto done;

	iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
					   iio_get_time_ns(indio_dev));

done:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static int ad7923_scan_direct(struct ad7923_state *st, unsigned int ch)
{
	int ret, cmd;

	cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) |
		AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
		st->settings;
	cmd <<= AD7923_SHIFT_REGISTER;
	st->tx_buf[0] = cpu_to_be16(cmd);

	ret = spi_sync(st->spi, &st->scan_single_msg);
	if (ret)
		return ret;

	return be16_to_cpu(st->rx_buf[0]);
}

static int ad7923_get_range(struct ad7923_state *st)
{
	int vref;

	vref = regulator_get_voltage(st->reg);
	if (vref < 0)
		return vref;

	vref /= 1000;

	if (!(st->settings & AD7923_RANGE))
		vref *= 2;

	return vref;
}

static int ad7923_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	int ret;
	struct ad7923_state *st = iio_priv(indio_dev);

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		ret = iio_device_claim_direct_mode(indio_dev);
		if (ret)
			return ret;
		ret = ad7923_scan_direct(st, chan->address);
		iio_device_release_direct_mode(indio_dev);

		if (ret < 0)
			return ret;

		if (chan->address == EXTRACT(ret, 12, 4))
			*val = EXTRACT(ret, chan->scan_type.shift,
				       chan->scan_type.realbits);
		else
			return -EIO;

		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		ret = ad7923_get_range(st);
		if (ret < 0)
			return ret;
		*val = ret;
		*val2 = chan->scan_type.realbits;
		return IIO_VAL_FRACTIONAL_LOG2;
	}
	return -EINVAL;
}

static const struct iio_info ad7923_info = {
	.read_raw = &ad7923_read_raw,
	.update_scan_mode = ad7923_update_scan_mode,
};

static void ad7923_regulator_disable(void *data)
{
	struct ad7923_state *st = data;

	regulator_disable(st->reg);
}

static int ad7923_probe(struct spi_device *spi)
{
	u32 ad7923_range = AD7923_RANGE;
	struct ad7923_state *st;
	struct iio_dev *indio_dev;
	const struct ad7923_chip_info *info;
	int ret;

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (!indio_dev)
		return -ENOMEM;

	st = iio_priv(indio_dev);

	if (device_property_read_bool(&spi->dev, "adi,range-double"))
		ad7923_range = 0;

	st->spi = spi;
	st->settings = AD7923_CODING | ad7923_range |
			AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS);

	info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data];

	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = info->channels;
	indio_dev->num_channels = info->num_channels;
	indio_dev->info = &ad7923_info;

	/* Setup default message */

	st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
	st->scan_single_xfer[0].len = 2;
	st->scan_single_xfer[0].cs_change = 1;
	st->scan_single_xfer[1].rx_buf = &st->rx_buf[0];
	st->scan_single_xfer[1].len = 2;

	spi_message_init(&st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
	spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);

	st->reg = devm_regulator_get(&spi->dev, "refin");
	if (IS_ERR(st->reg))
		return PTR_ERR(st->reg);

	ret = regulator_enable(st->reg);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(&spi->dev, ad7923_regulator_disable, st);
	if (ret)
		return ret;

	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
					      &ad7923_trigger_handler, NULL);
	if (ret)
		return ret;

	return devm_iio_device_register(&spi->dev, indio_dev);
}

static const struct spi_device_id ad7923_id[] = {
	{"ad7904", AD7904},
	{"ad7914", AD7914},
	{"ad7923", AD7924},
	{"ad7924", AD7924},
	{"ad7908", AD7908},
	{"ad7918", AD7918},
	{"ad7928", AD7928},
	{}
};
MODULE_DEVICE_TABLE(spi, ad7923_id);

static const struct of_device_id ad7923_of_match[] = {
	{ .compatible = "adi,ad7904", },
	{ .compatible = "adi,ad7914", },
	{ .compatible = "adi,ad7923", },
	{ .compatible = "adi,ad7924", },
	{ .compatible = "adi,ad7908", },
	{ .compatible = "adi,ad7918", },
	{ .compatible = "adi,ad7928", },
	{ },
};
MODULE_DEVICE_TABLE(of, ad7923_of_match);

static struct spi_driver ad7923_driver = {
	.driver = {
		.name	= "ad7923",
		.of_match_table = ad7923_of_match,
	},
	.probe		= ad7923_probe,
	.id_table	= ad7923_id,
};
module_spi_driver(ad7923_driver);

MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>");
MODULE_DESCRIPTION("Analog Devices AD7923 and similar ADC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
fda8d26e	1	// SPDX-License-Identifier: GPL-2.0-only
0eac259d	2	/*
851644a6	3	* AD7904/AD7914/AD7923/AD7924/AD7908/AD7918/AD7928 SPI ADC driver
0eac259d CL	4	*
	5	* Copyright 2011 Analog Devices Inc (from AD7923 Driver)
	6	* Copyright 2012 CS Systemes d'Information
0eac259d CL	7	*/
	8
	9	#include <linux/device.h>
	10	#include <linux/kernel.h>
096d2dac	11	#include <linux/property.h>
0eac259d CL	12	#include <linux/slab.h>
	13	#include <linux/sysfs.h>
	14	#include <linux/spi/spi.h>
ecf6ca25	15	#include <linux/regulator/consumer.h>
0eac259d CL	16	#include <linux/err.h>
	17	#include <linux/delay.h>
	18	#include <linux/module.h>
	19	#include <linux/interrupt.h>
	20
	21	#include <linux/iio/iio.h>
	22	#include <linux/iio/sysfs.h>
	23	#include <linux/iio/buffer.h>
	24	#include <linux/iio/trigger_consumer.h>
	25	#include <linux/iio/triggered_buffer.h>
	26
c1fc8bb0 BF	27	#define AD7923_WRITE_CR BIT(11) /* write control register */
	28	#define AD7923_RANGE BIT(1) /* range to REFin */
	29	#define AD7923_CODING BIT(0) /* coding is straight binary */
0eac259d CL	30	#define AD7923_PM_MODE_AS (1) /* auto shutdown */
	31	#define AD7923_PM_MODE_FS (2) /* full shutdown */
	32	#define AD7923_PM_MODE_OPS (3) /* normal operation */
0eac259d CL	33	#define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */
	34	#define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */
	35	#define AD7923_SEQUENCE_ON (3) /* continuous sequence */
	36
0eac259d	37
385c301c BF	38	#define AD7923_PM_MODE_WRITE(mode) ((mode) << 4) /* write mode */
	39	#define AD7923_CHANNEL_WRITE(channel) ((channel) << 6) /* write channel */
	40	#define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \
	41	+ (((sequence) & 2) << 9))
0eac259d CL	42	/* write sequence fonction */
	43	/* left shift for CR : bit 11 transmit in first */
	44	#define AD7923_SHIFT_REGISTER 4
	45
	46	/* val = value, dec = left shift, bits = number of bits of the mask */
385c301c	47	#define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1))
0eac259d CL	48
	49	struct ad7923_state {
	50	struct spi_device *spi;
	51	struct spi_transfer ring_xfer[5];
	52	struct spi_transfer scan_single_xfer[2];
	53	struct spi_message ring_msg;
	54	struct spi_message scan_single_msg;
ecf6ca25 LPC	55
	56	struct regulator *reg;
	57
	58	unsigned int settings;
	59
0eac259d	60	/*
908af45d	61	* DMA (thus cache coherency maintenance) may require the
0eac259d	62	* transfer buffers to live in their own cache lines.
01fcf129 JC	63	* Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp
01fcf129 JC	64	* Length = 8 channels + 4 extra for 8 byte timestamp
0eac259d	65	*/
908af45d	66	__be16 rx_buf[12] __aligned(IIO_DMA_MINALIGN);
0eac259d CL	67	__be16 tx_buf[4];
	68	};
	69
f2f7a449 LPC	70	struct ad7923_chip_info {
	71	const struct iio_chan_spec *channels;
	72	unsigned int num_channels;
	73	};
	74
	75	enum ad7923_id {
	76	AD7904,
	77	AD7914,
	78	AD7924,
851644a6 DJ	79	AD7908,
	80	AD7918,
	81	AD7928
f2f7a449 LPC	82	};
	83
	84	#define AD7923_V_CHAN(index, bits) \
0eac259d CL	85	{ \
	86	.type = IIO_VOLTAGE, \
	87	.indexed = 1, \
	88	.channel = index, \
7657719f JC	89	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
7657719f JC	90	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
0eac259d CL	91	.address = index, \
	92	.scan_index = index, \
	93	.scan_type = { \
	94	.sign = 'u', \
f2f7a449	95	.realbits = (bits), \
0eac259d	96	.storagebits = 16, \
f4f43f01	97	.shift = 12 - (bits), \
0eac259d CL	98	.endianness = IIO_BE, \
	99	}, \
	100	}
	101
f2f7a449 LPC	102	#define DECLARE_AD7923_CHANNELS(name, bits) \
	103	const struct iio_chan_spec name ## _channels[] = { \
	104	AD7923_V_CHAN(0, bits), \
	105	AD7923_V_CHAN(1, bits), \
	106	AD7923_V_CHAN(2, bits), \
	107	AD7923_V_CHAN(3, bits), \
	108	IIO_CHAN_SOFT_TIMESTAMP(4), \
	109	}
	110
851644a6 DJ	111	#define DECLARE_AD7908_CHANNELS(name, bits) \
	112	const struct iio_chan_spec name ## _channels[] = { \
	113	AD7923_V_CHAN(0, bits), \
	114	AD7923_V_CHAN(1, bits), \
	115	AD7923_V_CHAN(2, bits), \
	116	AD7923_V_CHAN(3, bits), \
	117	AD7923_V_CHAN(4, bits), \
	118	AD7923_V_CHAN(5, bits), \
	119	AD7923_V_CHAN(6, bits), \
	120	AD7923_V_CHAN(7, bits), \
	121	IIO_CHAN_SOFT_TIMESTAMP(8), \
	122	}
	123
f2f7a449 LPC	124	static DECLARE_AD7923_CHANNELS(ad7904, 8);
	125	static DECLARE_AD7923_CHANNELS(ad7914, 10);
	126	static DECLARE_AD7923_CHANNELS(ad7924, 12);
851644a6 DJ	127	static DECLARE_AD7908_CHANNELS(ad7908, 8);
	128	static DECLARE_AD7908_CHANNELS(ad7918, 10);
	129	static DECLARE_AD7908_CHANNELS(ad7928, 12);
f2f7a449 LPC	130
	131	static const struct ad7923_chip_info ad7923_chip_info[] = {
	132	[AD7904] = {
	133	.channels = ad7904_channels,
	134	.num_channels = ARRAY_SIZE(ad7904_channels),
	135	},
	136	[AD7914] = {
	137	.channels = ad7914_channels,
	138	.num_channels = ARRAY_SIZE(ad7914_channels),
	139	},
	140	[AD7924] = {
	141	.channels = ad7924_channels,
	142	.num_channels = ARRAY_SIZE(ad7924_channels),
	143	},
851644a6 DJ	144	[AD7908] = {
	145	.channels = ad7908_channels,
	146	.num_channels = ARRAY_SIZE(ad7908_channels),
	147	},
	148	[AD7918] = {
	149	.channels = ad7918_channels,
	150	.num_channels = ARRAY_SIZE(ad7918_channels),
	151	},
	152	[AD7928] = {
	153	.channels = ad7928_channels,
	154	.num_channels = ARRAY_SIZE(ad7928_channels),
	155	},
0eac259d CL	156	};
0eac259d CL	157
700b60e1	158	/*
0eac259d	159	* ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask
700b60e1	160	*/
0eac259d	161	static int ad7923_update_scan_mode(struct iio_dev *indio_dev,
66deb5c1	162	const unsigned long *active_scan_mask)
0eac259d CL	163	{
	164	struct ad7923_state *st = iio_priv(indio_dev);
	165	int i, cmd, len;
	166
	167	len = 0;
851644a6 DJ	168	/*
	169	* For this driver the last channel is always the software timestamp so
	170	* skip that one.
	171	*/
	172	for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) {
ecf6ca25	173	cmd = AD7923_WRITE_CR \| AD7923_CHANNEL_WRITE(i) \|
0eac259d	174	AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) \|
ecf6ca25	175	st->settings;
0eac259d CL	176	cmd <<= AD7923_SHIFT_REGISTER;
	177	st->tx_buf[len++] = cpu_to_be16(cmd);
	178	}
	179	/* build spi ring message */
	180	st->ring_xfer[0].tx_buf = &st->tx_buf[0];
	181	st->ring_xfer[0].len = len;
	182	st->ring_xfer[0].cs_change = 1;
	183
	184	spi_message_init(&st->ring_msg);
	185	spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
	186
	187	for (i = 0; i < len; i++) {
	188	st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i];
	189	st->ring_xfer[i + 1].len = 2;
	190	st->ring_xfer[i + 1].cs_change = 1;
	191	spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg);
	192	}
	193	/* make sure last transfer cs_change is not set */
	194	st->ring_xfer[i + 1].cs_change = 0;
	195
	196	return 0;
	197	}
	198
0eac259d CL	199	static irqreturn_t ad7923_trigger_handler(int irq, void *p)
	200	{
	201	struct iio_poll_func *pf = p;
	202	struct iio_dev *indio_dev = pf->indio_dev;
	203	struct ad7923_state *st = iio_priv(indio_dev);
0eac259d CL	204	int b_sent;
	205
	206	b_sent = spi_sync(st->spi, &st->ring_msg);
	207	if (b_sent)
	208	goto done;
	209
9f4fa4f7	210	iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
66deb5c1	211	iio_get_time_ns(indio_dev));
0eac259d CL	212
	213	done:
	214	iio_trigger_notify_done(indio_dev->trig);
	215
	216	return IRQ_HANDLED;
	217	}
	218
c87de1ba	219	static int ad7923_scan_direct(struct ad7923_state *st, unsigned int ch)
0eac259d CL	220	{
	221	int ret, cmd;
	222
ecf6ca25 LPC	223	cmd = AD7923_WRITE_CR \| AD7923_CHANNEL_WRITE(ch) \|
	224	AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) \|
	225	st->settings;
0eac259d CL	226	cmd <<= AD7923_SHIFT_REGISTER;
	227	st->tx_buf[0] = cpu_to_be16(cmd);
	228
	229	ret = spi_sync(st->spi, &st->scan_single_msg);
	230	if (ret)
	231	return ret;
	232
	233	return be16_to_cpu(st->rx_buf[0]);
	234	}
	235
ecf6ca25 LPC	236	static int ad7923_get_range(struct ad7923_state *st)
	237	{
	238	int vref;
	239
	240	vref = regulator_get_voltage(st->reg);
	241	if (vref < 0)
	242	return vref;
	243
	244	vref /= 1000;
	245
	246	if (!(st->settings & AD7923_RANGE))
	247	vref *= 2;
	248
	249	return vref;
	250	}
	251
0eac259d CL	252	static int ad7923_read_raw(struct iio_dev *indio_dev,
	253	struct iio_chan_spec const *chan,
	254	int *val,
	255	int *val2,
	256	long m)
	257	{
	258	int ret;
	259	struct ad7923_state *st = iio_priv(indio_dev);
	260
	261	switch (m) {
	262	case IIO_CHAN_INFO_RAW:
9f57e068 AS	263	ret = iio_device_claim_direct_mode(indio_dev);
	264	if (ret)
	265	return ret;
	266	ret = ad7923_scan_direct(st, chan->address);
	267	iio_device_release_direct_mode(indio_dev);
0eac259d CL	268
	269	if (ret < 0)
	270	return ret;
	271
	272	if (chan->address == EXTRACT(ret, 12, 4))
f4f43f01 NS	273	*val = EXTRACT(ret, chan->scan_type.shift,
f4f43f01 NS	274	chan->scan_type.realbits);
135f0646 LPC	275	else
135f0646 LPC	276	return -EIO;
0eac259d CL	277
0eac259d CL	278	return IIO_VAL_INT;
ecf6ca25 LPC	279	case IIO_CHAN_INFO_SCALE:
	280	ret = ad7923_get_range(st);
	281	if (ret < 0)
	282	return ret;
	283	*val = ret;
	284	*val2 = chan->scan_type.realbits;
	285	return IIO_VAL_FRACTIONAL_LOG2;
0eac259d CL	286	}
	287	return -EINVAL;
	288	}
	289
	290	static const struct iio_info ad7923_info = {
	291	.read_raw = &ad7923_read_raw,
	292	.update_scan_mode = ad7923_update_scan_mode,
0eac259d CL	293	};
0eac259d CL	294
44fc4de9 LS	295	static void ad7923_regulator_disable(void *data)
	296	{
	297	struct ad7923_state *st = data;
	298
	299	regulator_disable(st->reg);
	300	}
	301
0eac259d CL	302	static int ad7923_probe(struct spi_device *spi)
0eac259d CL	303	{
096d2dac	304	u32 ad7923_range = AD7923_RANGE;
0eac259d	305	struct ad7923_state *st;
e59576d4	306	struct iio_dev *indio_dev;
f2f7a449	307	const struct ad7923_chip_info *info;
0eac259d CL	308	int ret;
0eac259d CL	309
e59576d4	310	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
0a39ac29	311	if (!indio_dev)
0eac259d CL	312	return -ENOMEM;
	313
	314	st = iio_priv(indio_dev);
	315
096d2dac NS	316	if (device_property_read_bool(&spi->dev, "adi,range-double"))
	317	ad7923_range = 0;
	318
0eac259d	319	st->spi = spi;
096d2dac	320	st->settings = AD7923_CODING \| ad7923_range \|
ecf6ca25	321	AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS);
0eac259d	322
f2f7a449 LPC	323	info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data];
f2f7a449 LPC	324
0eac259d	325	indio_dev->name = spi_get_device_id(spi)->name;
0eac259d	326	indio_dev->modes = INDIO_DIRECT_MODE;
f2f7a449 LPC	327	indio_dev->channels = info->channels;
f2f7a449 LPC	328	indio_dev->num_channels = info->num_channels;
0eac259d CL	329	indio_dev->info = &ad7923_info;
	330
	331	/* Setup default message */
	332
	333	st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
	334	st->scan_single_xfer[0].len = 2;
	335	st->scan_single_xfer[0].cs_change = 1;
	336	st->scan_single_xfer[1].rx_buf = &st->rx_buf[0];
	337	st->scan_single_xfer[1].len = 2;
	338
	339	spi_message_init(&st->scan_single_msg);
	340	spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
	341	spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
	342
e59576d4 SK	343	st->reg = devm_regulator_get(&spi->dev, "refin");
	344	if (IS_ERR(st->reg))
	345	return PTR_ERR(st->reg);
	346
ecf6ca25 LPC	347	ret = regulator_enable(st->reg);
ecf6ca25 LPC	348	if (ret)
e59576d4	349	return ret;
ecf6ca25	350
44fc4de9 LS	351	ret = devm_add_action_or_reset(&spi->dev, ad7923_regulator_disable, st);
	352	if (ret)
	353	return ret;
	354
075dff33 LS	355	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
075dff33 LS	356	&ad7923_trigger_handler, NULL);
0eac259d	357	if (ret)
44fc4de9	358	return ret;
0eac259d	359
3e55bb6f	360	return devm_iio_device_register(&spi->dev, indio_dev);
0eac259d CL	361	}
	362
	363	static const struct spi_device_id ad7923_id[] = {
f2f7a449 LPC	364	{"ad7904", AD7904},
	365	{"ad7914", AD7914},
	366	{"ad7923", AD7924},
	367	{"ad7924", AD7924},
851644a6 DJ	368	{"ad7908", AD7908},
	369	{"ad7918", AD7918},
	370	{"ad7928", AD7928},
0eac259d CL	371	{}
	372	};
	373	MODULE_DEVICE_TABLE(spi, ad7923_id);
	374
233e7de4 DJ	375	static const struct of_device_id ad7923_of_match[] = {
	376	{ .compatible = "adi,ad7904", },
	377	{ .compatible = "adi,ad7914", },
	378	{ .compatible = "adi,ad7923", },
	379	{ .compatible = "adi,ad7924", },
851644a6 DJ	380	{ .compatible = "adi,ad7908", },
	381	{ .compatible = "adi,ad7918", },
	382	{ .compatible = "adi,ad7928", },
233e7de4 DJ	383	{ },
	384	};
	385	MODULE_DEVICE_TABLE(of, ad7923_of_match);
	386
0eac259d CL	387	static struct spi_driver ad7923_driver = {
	388	.driver = {
	389	.name = "ad7923",
233e7de4	390	.of_match_table = ad7923_of_match,
0eac259d CL	391	},
0eac259d CL	392	.probe = ad7923_probe,
0eac259d CL	393	.id_table = ad7923_id,
	394	};
	395	module_spi_driver(ad7923_driver);
	396
9920ed25	397	MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
0eac259d	398	MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>");
851644a6	399	MODULE_DESCRIPTION("Analog Devices AD7923 and similar ADC");
0eac259d	400	MODULE_LICENSE("GPL v2");