[linux-block.git] / drivers / iio / adc / ad7887.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * AD7887 SPI ADC driver
 *
 * Copyright 2010-2011 Analog Devices Inc.
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>

#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#include <linux/platform_data/ad7887.h>

#define AD7887_REF_DIS		BIT(5)	/* on-chip reference disable */
#define AD7887_DUAL		BIT(4)	/* dual-channel mode */
#define AD7887_CH_AIN1		BIT(3)	/* convert on channel 1, DUAL=1 */
#define AD7887_CH_AIN0		0	/* convert on channel 0, DUAL=0,1 */
#define AD7887_PM_MODE1		0	/* CS based shutdown */
#define AD7887_PM_MODE2		1	/* full on */
#define AD7887_PM_MODE3		2	/* auto shutdown after conversion */
#define AD7887_PM_MODE4		3	/* standby mode */

enum ad7887_channels {
	AD7887_CH0,
	AD7887_CH0_CH1,
	AD7887_CH1,
};

/**
 * struct ad7887_chip_info - chip specifc information
 * @int_vref_mv:	the internal reference voltage
 * @channels:		channels specification
 * @num_channels:	number of channels
 * @dual_channels:	channels specification in dual mode
 * @num_dual_channels:	number of channels in dual mode
 */
struct ad7887_chip_info {
	u16				int_vref_mv;
	const struct iio_chan_spec	*channels;
	unsigned int			num_channels;
	const struct iio_chan_spec	*dual_channels;
	unsigned int			num_dual_channels;
};

struct ad7887_state {
	struct spi_device		*spi;
	const struct ad7887_chip_info	*chip_info;
	struct regulator		*reg;
	struct spi_transfer		xfer[4];
	struct spi_message		msg[3];
	struct spi_message		*ring_msg;
	unsigned char			tx_cmd_buf[4];

	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 * Buffer needs to be large enough to hold two 16 bit samples and a
	 * 64 bit aligned 64 bit timestamp.
	 */
	unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)]
		____cacheline_aligned;
};

enum ad7887_supported_device_ids {
	ID_AD7887
};

static int ad7887_ring_preenable(struct iio_dev *indio_dev)
{
	struct ad7887_state *st = iio_priv(indio_dev);

	/* We know this is a single long so can 'cheat' */
	switch (*indio_dev->active_scan_mask) {
	case (1 << 0):
		st->ring_msg = &st->msg[AD7887_CH0];
		break;
	case (1 << 1):
		st->ring_msg = &st->msg[AD7887_CH1];
		/* Dummy read: push CH1 setting down to hardware */
		spi_sync(st->spi, st->ring_msg);
		break;
	case ((1 << 1) | (1 << 0)):
		st->ring_msg = &st->msg[AD7887_CH0_CH1];
		break;
	}

	return 0;
}

static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
{
	struct ad7887_state *st = iio_priv(indio_dev);

	/* dummy read: restore default CH0 settin */
	return spi_sync(st->spi, &st->msg[AD7887_CH0]);
}

/**
 * ad7887_trigger_handler() bh of trigger launched polling to ring buffer
 *
 * Currently there is no option in this driver to disable the saving of
 * timestamps within the ring.
 **/
static irqreturn_t ad7887_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct ad7887_state *st = iio_priv(indio_dev);
	int b_sent;

	b_sent = spi_sync(st->spi, st->ring_msg);
	if (b_sent)
		goto done;

	iio_push_to_buffers_with_timestamp(indio_dev, st->data,
		iio_get_time_ns(indio_dev));
done:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
	.preenable = &ad7887_ring_preenable,
	.postenable = &iio_triggered_buffer_postenable,
	.predisable = &iio_triggered_buffer_predisable,
	.postdisable = &ad7887_ring_postdisable,
};

static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
{
	int ret = spi_sync(st->spi, &st->msg[ch]);
	if (ret)
		return ret;

	return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1];
}

static int ad7887_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	int ret;
	struct ad7887_state *st = iio_priv(indio_dev);

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		ret = iio_device_claim_direct_mode(indio_dev);
		if (ret)
			return ret;
		ret = ad7887_scan_direct(st, chan->address);
		iio_device_release_direct_mode(indio_dev);

		if (ret < 0)
			return ret;
		*val = ret >> chan->scan_type.shift;
		*val &= GENMASK(chan->scan_type.realbits - 1, 0);
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		if (st->reg) {
			*val = regulator_get_voltage(st->reg);
			if (*val < 0)
				return *val;
			*val /= 1000;
		} else {
			*val = st->chip_info->int_vref_mv;
		}

		*val2 = chan->scan_type.realbits;

		return IIO_VAL_FRACTIONAL_LOG2;
	}
	return -EINVAL;
}

#define AD7887_CHANNEL(x) { \
	.type = IIO_VOLTAGE, \
	.indexed = 1, \
	.channel = (x), \
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
	.address = (x), \
	.scan_index = (x), \
	.scan_type = { \
		.sign = 'u', \
		.realbits = 12, \
		.storagebits = 16, \
		.shift = 0, \
		.endianness = IIO_BE, \
	}, \
}

static const struct iio_chan_spec ad7887_channels[] = {
	AD7887_CHANNEL(0),
	IIO_CHAN_SOFT_TIMESTAMP(1),
};

static const struct iio_chan_spec ad7887_dual_channels[] = {
	AD7887_CHANNEL(0),
	AD7887_CHANNEL(1),
	IIO_CHAN_SOFT_TIMESTAMP(2),
};

static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
	/*
	 * More devices added in future
	 */
	[ID_AD7887] = {
		.channels = ad7887_channels,
		.num_channels = ARRAY_SIZE(ad7887_channels),
		.dual_channels = ad7887_dual_channels,
		.num_dual_channels = ARRAY_SIZE(ad7887_dual_channels),
		.int_vref_mv = 2500,
	},
};

static const struct iio_info ad7887_info = {
	.read_raw = &ad7887_read_raw,
};

static int ad7887_probe(struct spi_device *spi)
{
	struct ad7887_platform_data *pdata = spi->dev.platform_data;
	struct ad7887_state *st;
	struct iio_dev *indio_dev;
	uint8_t mode;
	int ret;

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (indio_dev == NULL)
		return -ENOMEM;

	st = iio_priv(indio_dev);

	if (!pdata || !pdata->use_onchip_ref) {
		st->reg = devm_regulator_get(&spi->dev, "vref");
		if (IS_ERR(st->reg))
			return PTR_ERR(st->reg);

		ret = regulator_enable(st->reg);
		if (ret)
			return ret;
	}

	st->chip_info =
		&ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];

	spi_set_drvdata(spi, indio_dev);
	st->spi = spi;

	/* Estabilish that the iio_dev is a child of the spi device */
	indio_dev->dev.parent = &spi->dev;
	indio_dev->dev.of_node = spi->dev.of_node;
	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->info = &ad7887_info;
	indio_dev->modes = INDIO_DIRECT_MODE;

	/* Setup default message */

	mode = AD7887_PM_MODE4;
	if (!pdata || !pdata->use_onchip_ref)
		mode |= AD7887_REF_DIS;
	if (pdata && pdata->en_dual)
		mode |= AD7887_DUAL;

	st->tx_cmd_buf[0] = AD7887_CH_AIN0 | mode;

	st->xfer[0].rx_buf = &st->data[0];
	st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
	st->xfer[0].len = 2;

	spi_message_init(&st->msg[AD7887_CH0]);
	spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);

	if (pdata && pdata->en_dual) {
		st->tx_cmd_buf[2] = AD7887_CH_AIN1 | mode;

		st->xfer[1].rx_buf = &st->data[0];
		st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
		st->xfer[1].len = 2;

		st->xfer[2].rx_buf = &st->data[2];
		st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
		st->xfer[2].len = 2;

		spi_message_init(&st->msg[AD7887_CH0_CH1]);
		spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
		spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);

		st->xfer[3].rx_buf = &st->data[2];
		st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
		st->xfer[3].len = 2;

		spi_message_init(&st->msg[AD7887_CH1]);
		spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);

		indio_dev->channels = st->chip_info->dual_channels;
		indio_dev->num_channels = st->chip_info->num_dual_channels;
	} else {
		indio_dev->channels = st->chip_info->channels;
		indio_dev->num_channels = st->chip_info->num_channels;
	}

	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
			&ad7887_trigger_handler, &ad7887_ring_setup_ops);
	if (ret)
		goto error_disable_reg;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_unregister_ring;

	return 0;
error_unregister_ring:
	iio_triggered_buffer_cleanup(indio_dev);
error_disable_reg:
	if (st->reg)
		regulator_disable(st->reg);

	return ret;
}

static int ad7887_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad7887_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	iio_triggered_buffer_cleanup(indio_dev);
	if (st->reg)
		regulator_disable(st->reg);

	return 0;
}

static const struct spi_device_id ad7887_id[] = {
	{"ad7887", ID_AD7887},
	{}
};
MODULE_DEVICE_TABLE(spi, ad7887_id);

static struct spi_driver ad7887_driver = {
	.driver = {
		.name	= "ad7887",
	},
	.probe		= ad7887_probe,
	.remove		= ad7887_remove,
	.id_table	= ad7887_id,
};
module_spi_driver(ad7887_driver);

MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
fda8d26e	1	// SPDX-License-Identifier: GPL-2.0-only
2b4756aa MH	2	/*
	3	* AD7887 SPI ADC driver
	4	*
596d0609	5	* Copyright 2010-2011 Analog Devices Inc.
2b4756aa MH	6	*/
2b4756aa MH	7
2b4756aa MH	8	#include <linux/device.h>
	9	#include <linux/kernel.h>
	10	#include <linux/slab.h>
	11	#include <linux/sysfs.h>
2b4756aa MH	12	#include <linux/spi/spi.h>
	13	#include <linux/regulator/consumer.h>
	14	#include <linux/err.h>
99c97852	15	#include <linux/module.h>
65dd3d3d	16	#include <linux/interrupt.h>
09a1737e	17	#include <linux/bitops.h>
2b4756aa	18
06458e27 JC	19	#include <linux/iio/iio.h>
	20	#include <linux/iio/sysfs.h>
	21	#include <linux/iio/buffer.h>
cdf38709	22
65dd3d3d LPC	23	#include <linux/iio/trigger_consumer.h>
65dd3d3d LPC	24	#include <linux/iio/triggered_buffer.h>
2b4756aa	25
4eb3ccf1	26	#include <linux/platform_data/ad7887.h>
2b4756aa	27
09a1737e PM	28	#define AD7887_REF_DIS BIT(5) /* on-chip reference disable */
	29	#define AD7887_DUAL BIT(4) /* dual-channel mode */
	30	#define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */
	31	#define AD7887_CH_AIN0 0 /* convert on channel 0, DUAL=0,1 */
	32	#define AD7887_PM_MODE1 0 /* CS based shutdown */
	33	#define AD7887_PM_MODE2 1 /* full on */
	34	#define AD7887_PM_MODE3 2 /* auto shutdown after conversion */
	35	#define AD7887_PM_MODE4 3 /* standby mode */
65dd3d3d LPC	36
	37	enum ad7887_channels {
	38	AD7887_CH0,
	39	AD7887_CH0_CH1,
	40	AD7887_CH1,
	41	};
	42
65dd3d3d LPC	43	/**
	44	* struct ad7887_chip_info - chip specifc information
	45	* @int_vref_mv: the internal reference voltage
b0ec7a44 BB	46	* @channels: channels specification
	47	* @num_channels: number of channels
	48	* @dual_channels: channels specification in dual mode
	49	* @num_dual_channels: number of channels in dual mode
65dd3d3d LPC	50	*/
	51	struct ad7887_chip_info {
	52	u16 int_vref_mv;
b0ec7a44 BB	53	const struct iio_chan_spec *channels;
	54	unsigned int num_channels;
	55	const struct iio_chan_spec *dual_channels;
	56	unsigned int num_dual_channels;
65dd3d3d LPC	57	};
	58
	59	struct ad7887_state {
	60	struct spi_device *spi;
	61	const struct ad7887_chip_info *chip_info;
	62	struct regulator *reg;
	63	struct spi_transfer xfer[4];
	64	struct spi_message msg[3];
	65	struct spi_message *ring_msg;
fce7c3ea	66	unsigned char tx_cmd_buf[4];
65dd3d3d LPC	67
	68	/*
	69	* DMA (thus cache coherency maintenance) requires the
	70	* transfer buffers to live in their own cache lines.
	71	* Buffer needs to be large enough to hold two 16 bit samples and a
	72	* 64 bit aligned 64 bit timestamp.
	73	*/
	74	unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)]
	75	____cacheline_aligned;
	76	};
	77
	78	enum ad7887_supported_device_ids {
	79	ID_AD7887
	80	};
	81
	82	static int ad7887_ring_preenable(struct iio_dev *indio_dev)
	83	{
	84	struct ad7887_state *st = iio_priv(indio_dev);
65dd3d3d LPC	85
	86	/* We know this is a single long so can 'cheat' */
	87	switch (*indio_dev->active_scan_mask) {
	88	case (1 << 0):
	89	st->ring_msg = &st->msg[AD7887_CH0];
	90	break;
	91	case (1 << 1):
	92	st->ring_msg = &st->msg[AD7887_CH1];
	93	/* Dummy read: push CH1 setting down to hardware */
	94	spi_sync(st->spi, st->ring_msg);
	95	break;
	96	case ((1 << 1) \| (1 << 0)):
	97	st->ring_msg = &st->msg[AD7887_CH0_CH1];
	98	break;
	99	}
	100
	101	return 0;
	102	}
	103
	104	static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
	105	{
	106	struct ad7887_state *st = iio_priv(indio_dev);
	107
	108	/* dummy read: restore default CH0 settin */
	109	return spi_sync(st->spi, &st->msg[AD7887_CH0]);
	110	}
	111
	112	/**
	113	* ad7887_trigger_handler() bh of trigger launched polling to ring buffer
	114	*
	115	* Currently there is no option in this driver to disable the saving of
	116	* timestamps within the ring.
	117	**/
	118	static irqreturn_t ad7887_trigger_handler(int irq, void *p)
	119	{
	120	struct iio_poll_func *pf = p;
	121	struct iio_dev *indio_dev = pf->indio_dev;
	122	struct ad7887_state *st = iio_priv(indio_dev);
65dd3d3d LPC	123	int b_sent;
	124
	125	b_sent = spi_sync(st->spi, st->ring_msg);
	126	if (b_sent)
	127	goto done;
	128
5afd602b	129	iio_push_to_buffers_with_timestamp(indio_dev, st->data,
bc2b7dab	130	iio_get_time_ns(indio_dev));
65dd3d3d LPC	131	done:
	132	iio_trigger_notify_done(indio_dev->trig);
	133
	134	return IRQ_HANDLED;
	135	}
	136
	137	static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
	138	.preenable = &ad7887_ring_preenable,
	139	.postenable = &iio_triggered_buffer_postenable,
	140	.predisable = &iio_triggered_buffer_predisable,
	141	.postdisable = &ad7887_ring_postdisable,
	142	};
	143
2b4756aa MH	144	static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
	145	{
	146	int ret = spi_sync(st->spi, &st->msg[ch]);
	147	if (ret)
	148	return ret;
	149
	150	return (st->data[(ch * 2)] << 8) \| st->data[(ch * 2) + 1];
	151	}
	152
84f79ecb	153	static int ad7887_read_raw(struct iio_dev *indio_dev,
596d0609 MH	154	struct iio_chan_spec const *chan,
	155	int *val,
	156	int *val2,
	157	long m)
2b4756aa	158	{
2b4756aa	159	int ret;
84f79ecb	160	struct ad7887_state *st = iio_priv(indio_dev);
2b4756aa	161
596d0609	162	switch (m) {
b11f98ff	163	case IIO_CHAN_INFO_RAW:
6fea8a42 AS	164	ret = iio_device_claim_direct_mode(indio_dev);
	165	if (ret)
	166	return ret;
	167	ret = ad7887_scan_direct(st, chan->address);
	168	iio_device_release_direct_mode(indio_dev);
596d0609 MH	169
	170	if (ret < 0)
	171	return ret;
98efb70a	172	*val = ret >> chan->scan_type.shift;
09a1737e	173	*val &= GENMASK(chan->scan_type.realbits - 1, 0);
596d0609	174	return IIO_VAL_INT;
c8a9f805	175	case IIO_CHAN_INFO_SCALE:
bf5d2613 LPC	176	if (st->reg) {
	177	*val = regulator_get_voltage(st->reg);
	178	if (*val < 0)
	179	return *val;
	180	*val /= 1000;
	181	} else {
	182	*val = st->chip_info->int_vref_mv;
	183	}
	184
98efb70a	185	*val2 = chan->scan_type.realbits;
bf5d2613 LPC	186
bf5d2613 LPC	187	return IIO_VAL_FRACTIONAL_LOG2;
596d0609 MH	188	}
596d0609 MH	189	return -EINVAL;
2b4756aa MH	190	}
2b4756aa MH	191
b0ec7a44 BB	192	#define AD7887_CHANNEL(x) { \
	193	.type = IIO_VOLTAGE, \
	194	.indexed = 1, \
	195	.channel = (x), \
	196	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
	197	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
	198	.address = (x), \
	199	.scan_index = (x), \
	200	.scan_type = { \
	201	.sign = 'u', \
	202	.realbits = 12, \
	203	.storagebits = 16, \
	204	.shift = 0, \
	205	.endianness = IIO_BE, \
	206	}, \
	207	}
	208
	209	static const struct iio_chan_spec ad7887_channels[] = {
	210	AD7887_CHANNEL(0),
	211	IIO_CHAN_SOFT_TIMESTAMP(1),
	212	};
	213
	214	static const struct iio_chan_spec ad7887_dual_channels[] = {
	215	AD7887_CHANNEL(0),
	216	AD7887_CHANNEL(1),
	217	IIO_CHAN_SOFT_TIMESTAMP(2),
	218	};
2b4756aa MH	219
	220	static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
	221	/*
	222	* More devices added in future
	223	*/
	224	[ID_AD7887] = {
b0ec7a44 BB	225	.channels = ad7887_channels,
	226	.num_channels = ARRAY_SIZE(ad7887_channels),
	227	.dual_channels = ad7887_dual_channels,
	228	.num_dual_channels = ARRAY_SIZE(ad7887_dual_channels),
2b4756aa MH	229	.int_vref_mv = 2500,
	230	},
	231	};
	232
6fe8135f JC	233	static const struct iio_info ad7887_info = {
6fe8135f JC	234	.read_raw = &ad7887_read_raw,
6fe8135f JC	235	};
6fe8135f JC	236
fc52692c	237	static int ad7887_probe(struct spi_device *spi)
2b4756aa MH	238	{
	239	struct ad7887_platform_data *pdata = spi->dev.platform_data;
	240	struct ad7887_state *st;
82429e0d	241	struct iio_dev *indio_dev;
fce7c3ea	242	uint8_t mode;
bf5d2613	243	int ret;
2b4756aa	244
82429e0d	245	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
f39e086a MH	246	if (indio_dev == NULL)
	247	return -ENOMEM;
	248
	249	st = iio_priv(indio_dev);
2b4756aa	250
bf5d2613	251	if (!pdata \|\| !pdata->use_onchip_ref) {
82429e0d SK	252	st->reg = devm_regulator_get(&spi->dev, "vref");
	253	if (IS_ERR(st->reg))
	254	return PTR_ERR(st->reg);
bf5d2613	255
2b4756aa MH	256	ret = regulator_enable(st->reg);
2b4756aa MH	257	if (ret)
82429e0d	258	return ret;
2b4756aa MH	259	}
	260
	261	st->chip_info =
	262	&ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];
	263
f39e086a	264	spi_set_drvdata(spi, indio_dev);
2b4756aa MH	265	st->spi = spi;
2b4756aa MH	266
2b4756aa	267	/* Estabilish that the iio_dev is a child of the spi device */
f39e086a	268	indio_dev->dev.parent = &spi->dev;
b541eaff	269	indio_dev->dev.of_node = spi->dev.of_node;
f39e086a	270	indio_dev->name = spi_get_device_id(spi)->name;
6fe8135f	271	indio_dev->info = &ad7887_info;
f39e086a	272	indio_dev->modes = INDIO_DIRECT_MODE;
2b4756aa MH	273
	274	/* Setup default message */
	275
fce7c3ea LPC	276	mode = AD7887_PM_MODE4;
	277	if (!pdata \|\| !pdata->use_onchip_ref)
	278	mode \|= AD7887_REF_DIS;
	279	if (pdata && pdata->en_dual)
	280	mode \|= AD7887_DUAL;
	281
	282	st->tx_cmd_buf[0] = AD7887_CH_AIN0 \| mode;
2b4756aa MH	283
	284	st->xfer[0].rx_buf = &st->data[0];
	285	st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
	286	st->xfer[0].len = 2;
	287
	288	spi_message_init(&st->msg[AD7887_CH0]);
	289	spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);
	290
	291	if (pdata && pdata->en_dual) {
fce7c3ea	292	st->tx_cmd_buf[2] = AD7887_CH_AIN1 \| mode;
2b4756aa MH	293
	294	st->xfer[1].rx_buf = &st->data[0];
	295	st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
	296	st->xfer[1].len = 2;
	297
	298	st->xfer[2].rx_buf = &st->data[2];
fce7c3ea	299	st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
2b4756aa MH	300	st->xfer[2].len = 2;
	301
	302	spi_message_init(&st->msg[AD7887_CH0_CH1]);
	303	spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
	304	spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);
	305
fce7c3ea LPC	306	st->xfer[3].rx_buf = &st->data[2];
fce7c3ea LPC	307	st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
2b4756aa MH	308	st->xfer[3].len = 2;
	309
	310	spi_message_init(&st->msg[AD7887_CH1]);
	311	spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
	312
b0ec7a44 BB	313	indio_dev->channels = st->chip_info->dual_channels;
b0ec7a44 BB	314	indio_dev->num_channels = st->chip_info->num_dual_channels;
2b4756aa	315	} else {
b0ec7a44 BB	316	indio_dev->channels = st->chip_info->channels;
b0ec7a44 BB	317	indio_dev->num_channels = st->chip_info->num_channels;
596d0609	318	}
2b4756aa	319
65dd3d3d LPC	320	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
65dd3d3d LPC	321	&ad7887_trigger_handler, &ad7887_ring_setup_ops);
2b4756aa	322	if (ret)
f39e086a	323	goto error_disable_reg;
2b4756aa	324
26d25ae3 JC	325	ret = iio_device_register(indio_dev);
	326	if (ret)
	327	goto error_unregister_ring;
	328
	329	return 0;
	330	error_unregister_ring:
65dd3d3d	331	iio_triggered_buffer_cleanup(indio_dev);
2b4756aa	332	error_disable_reg:
bf5d2613	333	if (st->reg)
2b4756aa	334	regulator_disable(st->reg);
f39e086a	335
2b4756aa MH	336	return ret;
	337	}
	338
fc52692c	339	static int ad7887_remove(struct spi_device *spi)
2b4756aa	340	{
f39e086a MH	341	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	342	struct ad7887_state *st = iio_priv(indio_dev);
	343
d2fffd6c	344	iio_device_unregister(indio_dev);
65dd3d3d	345	iio_triggered_buffer_cleanup(indio_dev);
82429e0d	346	if (st->reg)
2b4756aa	347	regulator_disable(st->reg);
f39e086a	348
2b4756aa MH	349	return 0;
	350	}
	351
	352	static const struct spi_device_id ad7887_id[] = {
	353	{"ad7887", ID_AD7887},
	354	{}
	355	};
55e4390c	356	MODULE_DEVICE_TABLE(spi, ad7887_id);
2b4756aa MH	357
	358	static struct spi_driver ad7887_driver = {
	359	.driver = {
	360	.name = "ad7887",
2b4756aa MH	361	},
2b4756aa MH	362	.probe = ad7887_probe,
fc52692c	363	.remove = ad7887_remove,
2b4756aa MH	364	.id_table = ad7887_id,
2b4756aa MH	365	};
ae6ae6fe	366	module_spi_driver(ad7887_driver);
2b4756aa	367
9920ed25	368	MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
2b4756aa MH	369	MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
2b4756aa MH	370	MODULE_LICENSE("GPL v2");