[linux-2.6-block.git] / drivers / iio / adc / ad7476.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver
 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
 *
 * Copyright 2010 Analog Devices Inc.
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/delay.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

struct ad7476_state;

struct ad7476_chip_info {
	unsigned int			int_vref_uv;
	struct iio_chan_spec		channel[2];
	/* channels used when convst gpio is defined */
	struct iio_chan_spec		convst_channel[2];
	void (*reset)(struct ad7476_state *);
	bool				has_vref;
	bool				has_vdrive;
};

struct ad7476_state {
	struct spi_device		*spi;
	const struct ad7476_chip_info	*chip_info;
	struct regulator		*ref_reg;
	struct gpio_desc		*convst_gpio;
	struct spi_transfer		xfer;
	struct spi_message		msg;
	/*
	 * DMA (thus cache coherency maintenance) requires the
	 * transfer buffers to live in their own cache lines.
	 * Make the buffer large enough for one 16 bit sample and one 64 bit
	 * aligned 64 bit timestamp.
	 */
	unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)]
			____cacheline_aligned;
};

enum ad7476_supported_device_ids {
	ID_AD7091,
	ID_AD7091R,
	ID_AD7273,
	ID_AD7274,
	ID_AD7276,
	ID_AD7277,
	ID_AD7278,
	ID_AD7466,
	ID_AD7467,
	ID_AD7468,
	ID_AD7475,
	ID_AD7495,
	ID_AD7940,
	ID_ADC081S,
	ID_ADC101S,
	ID_ADC121S,
	ID_ADS7866,
	ID_ADS7867,
	ID_ADS7868,
	ID_LTC2314_14,
};

static void ad7091_convst(struct ad7476_state *st)
{
	if (!st->convst_gpio)
		return;

	gpiod_set_value(st->convst_gpio, 0);
	udelay(1); /* CONVST pulse width: 10 ns min */
	gpiod_set_value(st->convst_gpio, 1);
	udelay(1); /* Conversion time: 650 ns max */
}

static irqreturn_t ad7476_trigger_handler(int irq, void  *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct ad7476_state *st = iio_priv(indio_dev);
	int b_sent;

	ad7091_convst(st);

	b_sent = spi_sync(st->spi, &st->msg);
	if (b_sent < 0)
		goto done;

	iio_push_to_buffers_with_timestamp(indio_dev, st->data,
		iio_get_time_ns(indio_dev));
done:
	iio_trigger_notify_done(indio_dev->trig);

	return IRQ_HANDLED;
}

static void ad7091_reset(struct ad7476_state *st)
{
	/* Any transfers with 8 scl cycles will reset the device */
	spi_read(st->spi, st->data, 1);
}

static int ad7476_scan_direct(struct ad7476_state *st)
{
	int ret;

	ad7091_convst(st);

	ret = spi_sync(st->spi, &st->msg);
	if (ret)
		return ret;

	return be16_to_cpup((__be16 *)st->data);
}

static int ad7476_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	int ret;
	struct ad7476_state *st = iio_priv(indio_dev);
	int scale_uv;

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		ret = iio_device_claim_direct_mode(indio_dev);
		if (ret)
			return ret;
		ret = ad7476_scan_direct(st);
		iio_device_release_direct_mode(indio_dev);

		if (ret < 0)
			return ret;
		*val = (ret >> st->chip_info->channel[0].scan_type.shift) &
			GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		if (st->ref_reg) {
			scale_uv = regulator_get_voltage(st->ref_reg);
			if (scale_uv < 0)
				return scale_uv;
		} else {
			scale_uv = st->chip_info->int_vref_uv;
		}
		*val = scale_uv / 1000;
		*val2 = chan->scan_type.realbits;
		return IIO_VAL_FRACTIONAL_LOG2;
	}
	return -EINVAL;
}

#define _AD7476_CHAN(bits, _shift, _info_mask_sep)		\
	{							\
	.type = IIO_VOLTAGE,					\
	.indexed = 1,						\
	.info_mask_separate = _info_mask_sep,			\
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
	.scan_type = {						\
		.sign = 'u',					\
		.realbits = (bits),				\
		.storagebits = 16,				\
		.shift = (_shift),				\
		.endianness = IIO_BE,				\
	},							\
}

#define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
		BIT(IIO_CHAN_INFO_RAW))
#define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \
		BIT(IIO_CHAN_INFO_RAW))
#define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \
		BIT(IIO_CHAN_INFO_RAW))
#define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0)
#define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \
		BIT(IIO_CHAN_INFO_RAW))
#define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
		BIT(IIO_CHAN_INFO_RAW))

static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
	[ID_AD7091] = {
		.channel[0] = AD7091R_CHAN(12),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
		.convst_channel[0] = AD7091R_CONVST_CHAN(12),
		.convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
		.reset = ad7091_reset,
	},
	[ID_AD7091R] = {
		.channel[0] = AD7091R_CHAN(12),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
		.convst_channel[0] = AD7091R_CONVST_CHAN(12),
		.convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
		.int_vref_uv = 2500000,
		.has_vref = true,
		.reset = ad7091_reset,
	},
	[ID_AD7273] = {
		.channel[0] = AD7940_CHAN(10),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
		.has_vref = true,
	},
	[ID_AD7274] = {
		.channel[0] = AD7940_CHAN(12),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
		.has_vref = true,
	},
	[ID_AD7276] = {
		.channel[0] = AD7940_CHAN(12),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_AD7277] = {
		.channel[0] = AD7940_CHAN(10),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_AD7278] = {
		.channel[0] = AD7940_CHAN(8),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_AD7466] = {
		.channel[0] = AD7476_CHAN(12),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_AD7467] = {
		.channel[0] = AD7476_CHAN(10),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_AD7468] = {
		.channel[0] = AD7476_CHAN(8),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_AD7475] = {
		.channel[0] = AD7476_CHAN(12),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
		.has_vref = true,
		.has_vdrive = true,
	},
	[ID_AD7495] = {
		.channel[0] = AD7476_CHAN(12),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
		.int_vref_uv = 2500000,
		.has_vdrive = true,
	},
	[ID_AD7940] = {
		.channel[0] = AD7940_CHAN(14),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_ADC081S] = {
		.channel[0] = ADC081S_CHAN(8),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_ADC101S] = {
		.channel[0] = ADC081S_CHAN(10),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_ADC121S] = {
		.channel[0] = ADC081S_CHAN(12),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_ADS7866] = {
		.channel[0] = ADS786X_CHAN(12),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_ADS7867] = {
		.channel[0] = ADS786X_CHAN(10),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_ADS7868] = {
		.channel[0] = ADS786X_CHAN(8),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	},
	[ID_LTC2314_14] = {
		.channel[0] = AD7940_CHAN(14),
		.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
		.has_vref = true,
	},
};

static const struct iio_info ad7476_info = {
	.read_raw = &ad7476_read_raw,
};

static void ad7476_reg_disable(void *data)
{
	struct regulator *reg = data;

	regulator_disable(reg);
}

static int ad7476_probe(struct spi_device *spi)
{
	struct ad7476_state *st;
	struct iio_dev *indio_dev;
	struct regulator *reg;
	int ret;

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (!indio_dev)
		return -ENOMEM;

	st = iio_priv(indio_dev);
	st->chip_info =
		&ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data];

	reg = devm_regulator_get(&spi->dev, "vcc");
	if (IS_ERR(reg))
		return PTR_ERR(reg);

	ret = regulator_enable(reg);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, reg);
	if (ret)
		return ret;

	/* Either vcc or vref (below) as appropriate */
	if (!st->chip_info->int_vref_uv)
		st->ref_reg = reg;

	if (st->chip_info->has_vref) {

		/* If a device has an internal reference vref is optional */
		if (st->chip_info->int_vref_uv) {
			reg = devm_regulator_get_optional(&spi->dev, "vref");
			if (IS_ERR(reg) && (PTR_ERR(reg) != -ENODEV))
				return PTR_ERR(reg);
		} else {
			reg = devm_regulator_get(&spi->dev, "vref");
			if (IS_ERR(reg))
				return PTR_ERR(reg);
		}

		if (!IS_ERR(reg)) {
			ret = regulator_enable(reg);
			if (ret)
				return ret;

			ret = devm_add_action_or_reset(&spi->dev,
						       ad7476_reg_disable,
						       reg);
			if (ret)
				return ret;
			st->ref_reg = reg;
		} else {
			/*
			 * Can only get here if device supports both internal
			 * and external reference, but the regulator connected
			 * to the external reference is not connected.
			 * Set the reference regulator pointer to NULL to
			 * indicate this.
			 */
			st->ref_reg = NULL;
		}
	}

	if (st->chip_info->has_vdrive) {
		reg = devm_regulator_get(&spi->dev, "vdrive");
		if (IS_ERR(reg))
			return PTR_ERR(reg);

		ret = regulator_enable(reg);
		if (ret)
			return ret;

		ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable,
					       reg);
		if (ret)
			return ret;
	}

	st->convst_gpio = devm_gpiod_get_optional(&spi->dev,
						  "adi,conversion-start",
						  GPIOD_OUT_LOW);
	if (IS_ERR(st->convst_gpio))
		return PTR_ERR(st->convst_gpio);

	st->spi = spi;

	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = st->chip_info->channel;
	indio_dev->num_channels = 2;
	indio_dev->info = &ad7476_info;

	if (st->convst_gpio)
		indio_dev->channels = st->chip_info->convst_channel;
	/* Setup default message */

	st->xfer.rx_buf = &st->data;
	st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;

	spi_message_init(&st->msg);
	spi_message_add_tail(&st->xfer, &st->msg);

	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
					      &ad7476_trigger_handler, NULL);
	if (ret)
		return ret;

	if (st->chip_info->reset)
		st->chip_info->reset(st);

	return devm_iio_device_register(&spi->dev, indio_dev);
}

static const struct spi_device_id ad7476_id[] = {
	{"ad7091", ID_AD7091},
	{"ad7091r", ID_AD7091R},
	{"ad7273", ID_AD7273},
	{"ad7274", ID_AD7274},
	{"ad7276", ID_AD7276},
	{"ad7277", ID_AD7277},
	{"ad7278", ID_AD7278},
	{"ad7466", ID_AD7466},
	{"ad7467", ID_AD7467},
	{"ad7468", ID_AD7468},
	{"ad7475", ID_AD7475},
	{"ad7476", ID_AD7466},
	{"ad7476a", ID_AD7466},
	{"ad7477", ID_AD7467},
	{"ad7477a", ID_AD7467},
	{"ad7478", ID_AD7468},
	{"ad7478a", ID_AD7468},
	{"ad7495", ID_AD7495},
	{"ad7910", ID_AD7467},
	{"ad7920", ID_AD7466},
	{"ad7940", ID_AD7940},
	{"adc081s", ID_ADC081S},
	{"adc101s", ID_ADC101S},
	{"adc121s", ID_ADC121S},
	{"ads7866", ID_ADS7866},
	{"ads7867", ID_ADS7867},
	{"ads7868", ID_ADS7868},
	{"ltc2314-14", ID_LTC2314_14},
	{}
};
MODULE_DEVICE_TABLE(spi, ad7476_id);

static struct spi_driver ad7476_driver = {
	.driver = {
		.name	= "ad7476",
	},
	.probe		= ad7476_probe,
	.id_table	= ad7476_id,
};
module_spi_driver(ad7476_driver);

MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
54033f19	1	// SPDX-License-Identifier: GPL-2.0
349282d8	2	/*
4d2b6d8c MS	3	* Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver
4d2b6d8c MS	4	* TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
349282d8 MH	5	*
349282d8 MH	6	* Copyright 2010 Analog Devices Inc.
349282d8 MH	7	*/
349282d8 MH	8
349282d8 MH	9	#include <linux/device.h>
	10	#include <linux/kernel.h>
	11	#include <linux/slab.h>
	12	#include <linux/sysfs.h>
349282d8 MH	13	#include <linux/spi/spi.h>
349282d8 MH	14	#include <linux/regulator/consumer.h>
af37e470	15	#include <linux/gpio/consumer.h>
349282d8	16	#include <linux/err.h>
99c97852	17	#include <linux/module.h>
bc74fb81	18	#include <linux/bitops.h>
af37e470	19	#include <linux/delay.h>
349282d8	20
06458e27 JC	21	#include <linux/iio/iio.h>
	22	#include <linux/iio/sysfs.h>
	23	#include <linux/iio/buffer.h>
7a28fe3c LPC	24	#include <linux/iio/trigger_consumer.h>
7a28fe3c LPC	25	#include <linux/iio/triggered_buffer.h>
349282d8	26
87c5b10f LPC	27	struct ad7476_state;
87c5b10f LPC	28
7a28fe3c LPC	29	struct ad7476_chip_info {
	30	unsigned int int_vref_uv;
	31	struct iio_chan_spec channel[2];
3a6af93d DB	32	/* channels used when convst gpio is defined */
3a6af93d DB	33	struct iio_chan_spec convst_channel[2];
87c5b10f	34	void (reset)(struct ad7476_state );
7bf50a96 JC	35	bool has_vref;
7bf50a96 JC	36	bool has_vdrive;
7a28fe3c LPC	37	};
	38
	39	struct ad7476_state {
	40	struct spi_device *spi;
	41	const struct ad7476_chip_info *chip_info;
7bf50a96	42	struct regulator *ref_reg;
af37e470	43	struct gpio_desc *convst_gpio;
7a28fe3c LPC	44	struct spi_transfer xfer;
	45	struct spi_message msg;
	46	/*
	47	* DMA (thus cache coherency maintenance) requires the
	48	* transfer buffers to live in their own cache lines.
	49	* Make the buffer large enough for one 16 bit sample and one 64 bit
	50	* aligned 64 bit timestamp.
	51	*/
	52	unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)]
	53	____cacheline_aligned;
	54	};
	55
	56	enum ad7476_supported_device_ids {
7bf50a96	57	ID_AD7091,
87c5b10f	58	ID_AD7091R,
7bf50a96 JC	59	ID_AD7273,
7bf50a96 JC	60	ID_AD7274,
c26cc89e LPC	61	ID_AD7276,
	62	ID_AD7277,
	63	ID_AD7278,
7a28fe3c LPC	64	ID_AD7466,
	65	ID_AD7467,
	66	ID_AD7468,
7bf50a96	67	ID_AD7475,
4c337de8 LPC	68	ID_AD7495,
4c337de8 LPC	69	ID_AD7940,
4d2b6d8c MS	70	ID_ADC081S,
	71	ID_ADC101S,
	72	ID_ADC121S,
77c5a7f5 RRD	73	ID_ADS7866,
	74	ID_ADS7867,
	75	ID_ADS7868,
28e37a92	76	ID_LTC2314_14,
7a28fe3c LPC	77	};
7a28fe3c LPC	78
af37e470 DB	79	static void ad7091_convst(struct ad7476_state *st)
	80	{
	81	if (!st->convst_gpio)
	82	return;
	83
	84	gpiod_set_value(st->convst_gpio, 0);
	85	udelay(1); /* CONVST pulse width: 10 ns min */
	86	gpiod_set_value(st->convst_gpio, 1);
	87	udelay(1); /* Conversion time: 650 ns max */
	88	}
	89
7a28fe3c LPC	90	static irqreturn_t ad7476_trigger_handler(int irq, void *p)
	91	{
	92	struct iio_poll_func *pf = p;
	93	struct iio_dev *indio_dev = pf->indio_dev;
	94	struct ad7476_state *st = iio_priv(indio_dev);
7a28fe3c LPC	95	int b_sent;
7a28fe3c LPC	96
af37e470 DB	97	ad7091_convst(st);
af37e470 DB	98
7a28fe3c LPC	99	b_sent = spi_sync(st->spi, &st->msg);
	100	if (b_sent < 0)
	101	goto done;
	102
b05583a7	103	iio_push_to_buffers_with_timestamp(indio_dev, st->data,
bc2b7dab	104	iio_get_time_ns(indio_dev));
7a28fe3c LPC	105	done:
	106	iio_trigger_notify_done(indio_dev->trig);
	107
	108	return IRQ_HANDLED;
	109	}
349282d8	110
87c5b10f LPC	111	static void ad7091_reset(struct ad7476_state *st)
	112	{
	113	/* Any transfers with 8 scl cycles will reset the device */
	114	spi_read(st->spi, st->data, 1);
	115	}
	116
349282d8 MH	117	static int ad7476_scan_direct(struct ad7476_state *st)
349282d8 MH	118	{
349282d8 MH	119	int ret;
349282d8 MH	120
3a6af93d DB	121	ad7091_convst(st);
3a6af93d DB	122
668413e9	123	ret = spi_sync(st->spi, &st->msg);
349282d8 MH	124	if (ret)
	125	return ret;
	126
610a407c	127	return be16_to_cpup((__be16 *)st->data);
349282d8 MH	128	}
349282d8 MH	129
84f79ecb	130	static int ad7476_read_raw(struct iio_dev *indio_dev,
c5e0819e JC	131	struct iio_chan_spec const *chan,
	132	int *val,
	133	int *val2,
	134	long m)
349282d8	135	{
349282d8	136	int ret;
84f79ecb	137	struct ad7476_state *st = iio_priv(indio_dev);
cb093e44	138	int scale_uv;
c5e0819e JC	139
c5e0819e JC	140	switch (m) {
b11f98ff	141	case IIO_CHAN_INFO_RAW:
a52f238e AS	142	ret = iio_device_claim_direct_mode(indio_dev);
	143	if (ret)
	144	return ret;
	145	ret = ad7476_scan_direct(st);
	146	iio_device_release_direct_mode(indio_dev);
c5e0819e JC	147
	148	if (ret < 0)
	149	return ret;
	150	*val = (ret >> st->chip_info->channel[0].scan_type.shift) &
bc74fb81	151	GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
c5e0819e	152	return IIO_VAL_INT;
c8a9f805	153	case IIO_CHAN_INFO_SCALE:
7bf50a96 JC	154	if (st->ref_reg) {
7bf50a96 JC	155	scale_uv = regulator_get_voltage(st->ref_reg);
cb093e44 LPC	156	if (scale_uv < 0)
	157	return scale_uv;
	158	} else {
	159	scale_uv = st->chip_info->int_vref_uv;
	160	}
d88c89db LPC	161	*val = scale_uv / 1000;
	162	*val2 = chan->scan_type.realbits;
	163	return IIO_VAL_FRACTIONAL_LOG2;
c5e0819e JC	164	}
c5e0819e JC	165	return -EINVAL;
349282d8	166	}
349282d8	167
8c1033f7	168	#define _AD7476_CHAN(bits, _shift, _info_mask_sep) \
85871cd8 JC	169	{ \
	170	.type = IIO_VOLTAGE, \
	171	.indexed = 1, \
8c1033f7 JC	172	.info_mask_separate = _info_mask_sep, \
8c1033f7 JC	173	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
85871cd8 JC	174	.scan_type = { \
85871cd8 JC	175	.sign = 'u', \
4c337de8	176	.realbits = (bits), \
85871cd8	177	.storagebits = 16, \
4c337de8 LPC	178	.shift = (_shift), \
4c337de8 LPC	179	.endianness = IIO_BE, \
85871cd8 JC	180	}, \
	181	}
	182
4d2b6d8c MS	183	#define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
4d2b6d8c MS	184	BIT(IIO_CHAN_INFO_RAW))
87c5b10f	185	#define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \
8c1033f7	186	BIT(IIO_CHAN_INFO_RAW))
87c5b10f	187	#define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \
8c1033f7	188	BIT(IIO_CHAN_INFO_RAW))
87c5b10f	189	#define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0)
3a6af93d DB	190	#define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \
3a6af93d DB	191	BIT(IIO_CHAN_INFO_RAW))
77c5a7f5 RRD	192	#define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
77c5a7f5 RRD	193	BIT(IIO_CHAN_INFO_RAW))
4c337de8	194
349282d8	195	static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
7bf50a96 JC	196	[ID_AD7091] = {
	197	.channel[0] = AD7091R_CHAN(12),
	198	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	199	.convst_channel[0] = AD7091R_CONVST_CHAN(12),
	200	.convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	201	.reset = ad7091_reset,
	202	},
87c5b10f LPC	203	[ID_AD7091R] = {
	204	.channel[0] = AD7091R_CHAN(12),
	205	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
3a6af93d DB	206	.convst_channel[0] = AD7091R_CONVST_CHAN(12),
3a6af93d DB	207	.convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
7bf50a96 JC	208	.int_vref_uv = 2500000,
7bf50a96 JC	209	.has_vref = true,
87c5b10f LPC	210	.reset = ad7091_reset,
87c5b10f LPC	211	},
7bf50a96 JC	212	[ID_AD7273] = {
	213	.channel[0] = AD7940_CHAN(10),
	214	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	215	.has_vref = true,
	216	},
	217	[ID_AD7274] = {
	218	.channel[0] = AD7940_CHAN(12),
	219	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	220	.has_vref = true,
	221	},
c26cc89e LPC	222	[ID_AD7276] = {
	223	.channel[0] = AD7940_CHAN(12),
	224	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	225	},
	226	[ID_AD7277] = {
	227	.channel[0] = AD7940_CHAN(10),
	228	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	229	},
	230	[ID_AD7278] = {
	231	.channel[0] = AD7940_CHAN(8),
	232	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	233	},
349282d8	234	[ID_AD7466] = {
85871cd8	235	.channel[0] = AD7476_CHAN(12),
c5e0819e	236	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
349282d8 MH	237	},
349282d8 MH	238	[ID_AD7467] = {
85871cd8	239	.channel[0] = AD7476_CHAN(10),
c5e0819e	240	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
349282d8 MH	241	},
349282d8 MH	242	[ID_AD7468] = {
85871cd8	243	.channel[0] = AD7476_CHAN(8),
c5e0819e	244	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
349282d8	245	},
7bf50a96 JC	246	[ID_AD7475] = {
	247	.channel[0] = AD7476_CHAN(12),
	248	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	249	.has_vref = true,
	250	.has_vdrive = true,
	251	},
349282d8	252	[ID_AD7495] = {
85871cd8	253	.channel[0] = AD7476_CHAN(12),
c5e0819e	254	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
cb093e44	255	.int_vref_uv = 2500000,
7bf50a96	256	.has_vdrive = true,
349282d8	257	},
4c337de8 LPC	258	[ID_AD7940] = {
	259	.channel[0] = AD7940_CHAN(14),
	260	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	261	},
4d2b6d8c MS	262	[ID_ADC081S] = {
	263	.channel[0] = ADC081S_CHAN(8),
	264	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	265	},
	266	[ID_ADC101S] = {
	267	.channel[0] = ADC081S_CHAN(10),
	268	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	269	},
	270	[ID_ADC121S] = {
	271	.channel[0] = ADC081S_CHAN(12),
	272	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	273	},
77c5a7f5 RRD	274	[ID_ADS7866] = {
	275	.channel[0] = ADS786X_CHAN(12),
	276	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	277	},
	278	[ID_ADS7867] = {
	279	.channel[0] = ADS786X_CHAN(10),
	280	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	281	},
	282	[ID_ADS7868] = {
	283	.channel[0] = ADS786X_CHAN(8),
	284	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
	285	},
28e37a92 DB	286	[ID_LTC2314_14] = {
	287	.channel[0] = AD7940_CHAN(14),
	288	.channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
7bf50a96	289	.has_vref = true,
28e37a92	290	},
349282d8 MH	291	};
349282d8 MH	292
6fe8135f	293	static const struct iio_info ad7476_info = {
6fe8135f JC	294	.read_raw = &ad7476_read_raw,
	295	};
	296
4bb2b8f9 BB	297	static void ad7476_reg_disable(void *data)
4bb2b8f9 BB	298	{
7bf50a96	299	struct regulator *reg = data;
4bb2b8f9	300
7bf50a96	301	regulator_disable(reg);
4bb2b8f9 BB	302	}
4bb2b8f9 BB	303
fc52692c	304	static int ad7476_probe(struct spi_device *spi)
349282d8	305	{
349282d8	306	struct ad7476_state *st;
67688105	307	struct iio_dev *indio_dev;
7bf50a96	308	struct regulator *reg;
cb093e44	309	int ret;
349282d8	310
4ea454d2 SK	311	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	312	if (!indio_dev)
	313	return -ENOMEM;
	314
67688105	315	st = iio_priv(indio_dev);
349282d8 MH	316	st->chip_info =
	317	&ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data];
	318
7bf50a96 JC	319	reg = devm_regulator_get(&spi->dev, "vcc");
	320	if (IS_ERR(reg))
	321	return PTR_ERR(reg);
cb093e44	322
7bf50a96	323	ret = regulator_enable(reg);
cb093e44	324	if (ret)
4ea454d2	325	return ret;
349282d8	326
7bf50a96	327	ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, reg);
4bb2b8f9 BB	328	if (ret)
	329	return ret;
	330
7bf50a96 JC	331	/* Either vcc or vref (below) as appropriate */
	332	if (!st->chip_info->int_vref_uv)
	333	st->ref_reg = reg;
	334
	335	if (st->chip_info->has_vref) {
	336
	337	/* If a device has an internal reference vref is optional */
	338	if (st->chip_info->int_vref_uv) {
	339	reg = devm_regulator_get_optional(&spi->dev, "vref");
	340	if (IS_ERR(reg) && (PTR_ERR(reg) != -ENODEV))
	341	return PTR_ERR(reg);
	342	} else {
	343	reg = devm_regulator_get(&spi->dev, "vref");
	344	if (IS_ERR(reg))
	345	return PTR_ERR(reg);
	346	}
	347
	348	if (!IS_ERR(reg)) {
	349	ret = regulator_enable(reg);
	350	if (ret)
	351	return ret;
	352
	353	ret = devm_add_action_or_reset(&spi->dev,
	354	ad7476_reg_disable,
	355	reg);
	356	if (ret)
	357	return ret;
	358	st->ref_reg = reg;
	359	} else {
	360	/*
	361	* Can only get here if device supports both internal
	362	* and external reference, but the regulator connected
	363	* to the external reference is not connected.
	364	* Set the reference regulator pointer to NULL to
	365	* indicate this.
	366	*/
	367	st->ref_reg = NULL;
	368	}
	369	}
	370
	371	if (st->chip_info->has_vdrive) {
	372	reg = devm_regulator_get(&spi->dev, "vdrive");
	373	if (IS_ERR(reg))
	374	return PTR_ERR(reg);
	375
	376	ret = regulator_enable(reg);
	377	if (ret)
	378	return ret;
	379
	380	ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable,
	381	reg);
	382	if (ret)
	383	return ret;
	384	}
	385
af37e470 DB	386	st->convst_gpio = devm_gpiod_get_optional(&spi->dev,
	387	"adi,conversion-start",
	388	GPIOD_OUT_LOW);
	389	if (IS_ERR(st->convst_gpio))
	390	return PTR_ERR(st->convst_gpio);
	391
349282d8 MH	392	st->spi = spi;
349282d8 MH	393
67688105 JC	394	indio_dev->name = spi_get_device_id(spi)->name;
	395	indio_dev->modes = INDIO_DIRECT_MODE;
	396	indio_dev->channels = st->chip_info->channel;
	397	indio_dev->num_channels = 2;
	398	indio_dev->info = &ad7476_info;
3a6af93d	399
a66904b2	400	if (st->convst_gpio)
3a6af93d	401	indio_dev->channels = st->chip_info->convst_channel;
349282d8 MH	402	/* Setup default message */
	403
	404	st->xfer.rx_buf = &st->data;
c5e0819e	405	st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;
349282d8 MH	406
	407	spi_message_init(&st->msg);
	408	spi_message_add_tail(&st->xfer, &st->msg);
	409
6baee4bd JC	410	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
6baee4bd JC	411	&ad7476_trigger_handler, NULL);
349282d8	412	if (ret)
6baee4bd	413	return ret;
349282d8	414
87c5b10f LPC	415	if (st->chip_info->reset)
	416	st->chip_info->reset(st);
	417
6baee4bd	418	return devm_iio_device_register(&spi->dev, indio_dev);
349282d8 MH	419	}
349282d8 MH	420
349282d8	421	static const struct spi_device_id ad7476_id[] = {
7bf50a96	422	{"ad7091", ID_AD7091},
87c5b10f	423	{"ad7091r", ID_AD7091R},
7bf50a96 JC	424	{"ad7273", ID_AD7273},
7bf50a96 JC	425	{"ad7274", ID_AD7274},
c26cc89e LPC	426	{"ad7276", ID_AD7276},
	427	{"ad7277", ID_AD7277},
	428	{"ad7278", ID_AD7278},
349282d8 MH	429	{"ad7466", ID_AD7466},
	430	{"ad7467", ID_AD7467},
	431	{"ad7468", ID_AD7468},
7bf50a96	432	{"ad7475", ID_AD7475},
fcc7800b LPC	433	{"ad7476", ID_AD7466},
	434	{"ad7476a", ID_AD7466},
	435	{"ad7477", ID_AD7467},
	436	{"ad7477a", ID_AD7467},
	437	{"ad7478", ID_AD7468},
	438	{"ad7478a", ID_AD7468},
349282d8	439	{"ad7495", ID_AD7495},
ac5332b1 LPC	440	{"ad7910", ID_AD7467},
ac5332b1 LPC	441	{"ad7920", ID_AD7466},
4c337de8	442	{"ad7940", ID_AD7940},
4d2b6d8c MS	443	{"adc081s", ID_ADC081S},
	444	{"adc101s", ID_ADC101S},
	445	{"adc121s", ID_ADC121S},
77c5a7f5 RRD	446	{"ads7866", ID_ADS7866},
	447	{"ads7867", ID_ADS7867},
	448	{"ads7868", ID_ADS7868},
28e37a92	449	{"ltc2314-14", ID_LTC2314_14},
349282d8 MH	450	{}
349282d8 MH	451	};
55e4390c	452	MODULE_DEVICE_TABLE(spi, ad7476_id);
349282d8 MH	453
	454	static struct spi_driver ad7476_driver = {
	455	.driver = {
	456	.name = "ad7476",
349282d8 MH	457	},
349282d8 MH	458	.probe = ad7476_probe,
349282d8 MH	459	.id_table = ad7476_id,
349282d8 MH	460	};
ae6ae6fe	461	module_spi_driver(ad7476_driver);
349282d8	462
9920ed25	463	MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
ac5332b1	464	MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs");
349282d8	465	MODULE_LICENSE("GPL v2");