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07063bbf LW |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
4 | * | |
5 | * Author: Arun R Murthy <arun.murthy@stericsson.com> | |
6 | * Author: Daniel Willerud <daniel.willerud@stericsson.com> | |
7 | * Author: Johan Palsson <johan.palsson@stericsson.com> | |
8 | * Author: M'boumba Cedric Madianga | |
9 | * Author: Linus Walleij <linus.walleij@linaro.org> | |
10 | * | |
11 | * AB8500 General Purpose ADC driver. The AB8500 uses reference voltages: | |
12 | * VinVADC, and VADC relative to GND to do its job. It monitors main and backup | |
13 | * battery voltages, AC (mains) voltage, USB cable voltage, as well as voltages | |
14 | * representing the temperature of the chip die and battery, accessory | |
15 | * detection by resistance measurements using relative voltages and GSM burst | |
16 | * information. | |
17 | * | |
18 | * Some of the voltages are measured on external pins on the IC, such as | |
19 | * battery temperature or "ADC aux" 1 and 2. Other voltages are internal rails | |
20 | * from other parts of the ASIC such as main charger voltage, main and battery | |
21 | * backup voltage or USB VBUS voltage. For this reason drivers for other | |
22 | * parts of the system are required to obtain handles to the ADC to do work | |
23 | * for them and the IIO driver provides arbitration among these consumers. | |
24 | */ | |
25 | #include <linux/init.h> | |
26 | #include <linux/bits.h> | |
27 | #include <linux/iio/iio.h> | |
28 | #include <linux/iio/sysfs.h> | |
29 | #include <linux/device.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/pm_runtime.h> | |
34 | #include <linux/platform_device.h> | |
35 | #include <linux/completion.h> | |
36 | #include <linux/regulator/consumer.h> | |
37 | #include <linux/random.h> | |
38 | #include <linux/err.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/mfd/abx500.h> | |
41 | #include <linux/mfd/abx500/ab8500.h> | |
42 | ||
43 | /* GPADC register offsets and bit definitions */ | |
44 | ||
45 | #define AB8500_GPADC_CTRL1_REG 0x00 | |
46 | /* GPADC control register 1 bits */ | |
47 | #define AB8500_GPADC_CTRL1_DISABLE 0x00 | |
48 | #define AB8500_GPADC_CTRL1_ENABLE BIT(0) | |
49 | #define AB8500_GPADC_CTRL1_TRIG_ENA BIT(1) | |
50 | #define AB8500_GPADC_CTRL1_START_SW_CONV BIT(2) | |
51 | #define AB8500_GPADC_CTRL1_BTEMP_PULL_UP BIT(3) | |
52 | /* 0 = use rising edge, 1 = use falling edge */ | |
53 | #define AB8500_GPADC_CTRL1_TRIG_EDGE BIT(4) | |
54 | /* 0 = use VTVOUT, 1 = use VRTC as pull-up supply for battery temp NTC */ | |
55 | #define AB8500_GPADC_CTRL1_PUPSUPSEL BIT(5) | |
56 | #define AB8500_GPADC_CTRL1_BUF_ENA BIT(6) | |
57 | #define AB8500_GPADC_CTRL1_ICHAR_ENA BIT(7) | |
58 | ||
59 | #define AB8500_GPADC_CTRL2_REG 0x01 | |
60 | #define AB8500_GPADC_CTRL3_REG 0x02 | |
61 | /* | |
62 | * GPADC control register 2 and 3 bits | |
63 | * the bit layout is the same for SW and HW conversion set-up | |
64 | */ | |
65 | #define AB8500_GPADC_CTRL2_AVG_1 0x00 | |
66 | #define AB8500_GPADC_CTRL2_AVG_4 BIT(5) | |
67 | #define AB8500_GPADC_CTRL2_AVG_8 BIT(6) | |
68 | #define AB8500_GPADC_CTRL2_AVG_16 (BIT(5) | BIT(6)) | |
69 | ||
70 | enum ab8500_gpadc_channel { | |
71 | AB8500_GPADC_CHAN_UNUSED = 0x00, | |
72 | AB8500_GPADC_CHAN_BAT_CTRL = 0x01, | |
73 | AB8500_GPADC_CHAN_BAT_TEMP = 0x02, | |
74 | /* This is not used on AB8505 */ | |
75 | AB8500_GPADC_CHAN_MAIN_CHARGER = 0x03, | |
76 | AB8500_GPADC_CHAN_ACC_DET_1 = 0x04, | |
77 | AB8500_GPADC_CHAN_ACC_DET_2 = 0x05, | |
78 | AB8500_GPADC_CHAN_ADC_AUX_1 = 0x06, | |
79 | AB8500_GPADC_CHAN_ADC_AUX_2 = 0x07, | |
80 | AB8500_GPADC_CHAN_VBAT_A = 0x08, | |
81 | AB8500_GPADC_CHAN_VBUS = 0x09, | |
82 | AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT = 0x0a, | |
83 | AB8500_GPADC_CHAN_USB_CHARGER_CURRENT = 0x0b, | |
84 | AB8500_GPADC_CHAN_BACKUP_BAT = 0x0c, | |
85 | /* Only on AB8505 */ | |
86 | AB8505_GPADC_CHAN_DIE_TEMP = 0x0d, | |
87 | AB8500_GPADC_CHAN_ID = 0x0e, | |
88 | AB8500_GPADC_CHAN_INTERNAL_TEST_1 = 0x0f, | |
89 | AB8500_GPADC_CHAN_INTERNAL_TEST_2 = 0x10, | |
90 | AB8500_GPADC_CHAN_INTERNAL_TEST_3 = 0x11, | |
91 | /* FIXME: Applicable to all ASIC variants? */ | |
92 | AB8500_GPADC_CHAN_XTAL_TEMP = 0x12, | |
93 | AB8500_GPADC_CHAN_VBAT_TRUE_MEAS = 0x13, | |
94 | /* FIXME: Doesn't seem to work with pure AB8500 */ | |
95 | AB8500_GPADC_CHAN_BAT_CTRL_AND_IBAT = 0x1c, | |
96 | AB8500_GPADC_CHAN_VBAT_MEAS_AND_IBAT = 0x1d, | |
97 | AB8500_GPADC_CHAN_VBAT_TRUE_MEAS_AND_IBAT = 0x1e, | |
98 | AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT = 0x1f, | |
99 | /* | |
100 | * Virtual channel used only for ibat conversion to ampere. | |
101 | * Battery current conversion (ibat) cannot be requested as a | |
102 | * single conversion but it is always requested in combination | |
103 | * with other input requests. | |
104 | */ | |
105 | AB8500_GPADC_CHAN_IBAT_VIRTUAL = 0xFF, | |
106 | }; | |
107 | ||
108 | #define AB8500_GPADC_AUTO_TIMER_REG 0x03 | |
109 | ||
110 | #define AB8500_GPADC_STAT_REG 0x04 | |
111 | #define AB8500_GPADC_STAT_BUSY BIT(0) | |
112 | ||
113 | #define AB8500_GPADC_MANDATAL_REG 0x05 | |
114 | #define AB8500_GPADC_MANDATAH_REG 0x06 | |
115 | #define AB8500_GPADC_AUTODATAL_REG 0x07 | |
116 | #define AB8500_GPADC_AUTODATAH_REG 0x08 | |
117 | #define AB8500_GPADC_MUX_CTRL_REG 0x09 | |
118 | #define AB8540_GPADC_MANDATA2L_REG 0x09 | |
119 | #define AB8540_GPADC_MANDATA2H_REG 0x0A | |
120 | #define AB8540_GPADC_APEAAX_REG 0x10 | |
121 | #define AB8540_GPADC_APEAAT_REG 0x11 | |
122 | #define AB8540_GPADC_APEAAM_REG 0x12 | |
123 | #define AB8540_GPADC_APEAAH_REG 0x13 | |
124 | #define AB8540_GPADC_APEAAL_REG 0x14 | |
125 | ||
126 | /* | |
127 | * OTP register offsets | |
128 | * Bank : 0x15 | |
129 | */ | |
130 | #define AB8500_GPADC_CAL_1 0x0F | |
131 | #define AB8500_GPADC_CAL_2 0x10 | |
132 | #define AB8500_GPADC_CAL_3 0x11 | |
133 | #define AB8500_GPADC_CAL_4 0x12 | |
134 | #define AB8500_GPADC_CAL_5 0x13 | |
135 | #define AB8500_GPADC_CAL_6 0x14 | |
136 | #define AB8500_GPADC_CAL_7 0x15 | |
137 | /* New calibration for 8540 */ | |
138 | #define AB8540_GPADC_OTP4_REG_7 0x38 | |
139 | #define AB8540_GPADC_OTP4_REG_6 0x39 | |
140 | #define AB8540_GPADC_OTP4_REG_5 0x3A | |
141 | ||
142 | #define AB8540_GPADC_DIS_ZERO 0x00 | |
143 | #define AB8540_GPADC_EN_VBIAS_XTAL_TEMP 0x02 | |
144 | ||
145 | /* GPADC constants from AB8500 spec, UM0836 */ | |
146 | #define AB8500_ADC_RESOLUTION 1024 | |
147 | #define AB8500_ADC_CH_BTEMP_MIN 0 | |
148 | #define AB8500_ADC_CH_BTEMP_MAX 1350 | |
149 | #define AB8500_ADC_CH_DIETEMP_MIN 0 | |
150 | #define AB8500_ADC_CH_DIETEMP_MAX 1350 | |
151 | #define AB8500_ADC_CH_CHG_V_MIN 0 | |
152 | #define AB8500_ADC_CH_CHG_V_MAX 20030 | |
153 | #define AB8500_ADC_CH_ACCDET2_MIN 0 | |
154 | #define AB8500_ADC_CH_ACCDET2_MAX 2500 | |
155 | #define AB8500_ADC_CH_VBAT_MIN 2300 | |
156 | #define AB8500_ADC_CH_VBAT_MAX 4800 | |
157 | #define AB8500_ADC_CH_CHG_I_MIN 0 | |
158 | #define AB8500_ADC_CH_CHG_I_MAX 1500 | |
159 | #define AB8500_ADC_CH_BKBAT_MIN 0 | |
160 | #define AB8500_ADC_CH_BKBAT_MAX 3200 | |
161 | ||
162 | /* GPADC constants from AB8540 spec */ | |
163 | #define AB8500_ADC_CH_IBAT_MIN (-6000) /* mA range measured by ADC for ibat */ | |
164 | #define AB8500_ADC_CH_IBAT_MAX 6000 | |
165 | #define AB8500_ADC_CH_IBAT_MIN_V (-60) /* mV range measured by ADC for ibat */ | |
166 | #define AB8500_ADC_CH_IBAT_MAX_V 60 | |
167 | #define AB8500_GPADC_IBAT_VDROP_L (-56) /* mV */ | |
168 | #define AB8500_GPADC_IBAT_VDROP_H 56 | |
169 | ||
170 | /* This is used to not lose precision when dividing to get gain and offset */ | |
171 | #define AB8500_GPADC_CALIB_SCALE 1000 | |
172 | /* | |
173 | * Number of bits shift used to not lose precision | |
174 | * when dividing to get ibat gain. | |
175 | */ | |
176 | #define AB8500_GPADC_CALIB_SHIFT_IBAT 20 | |
177 | ||
178 | /* Time in ms before disabling regulator */ | |
179 | #define AB8500_GPADC_AUTOSUSPEND_DELAY 1 | |
180 | ||
181 | #define AB8500_GPADC_CONVERSION_TIME 500 /* ms */ | |
182 | ||
183 | enum ab8500_cal_channels { | |
184 | AB8500_CAL_VMAIN = 0, | |
185 | AB8500_CAL_BTEMP, | |
186 | AB8500_CAL_VBAT, | |
187 | AB8500_CAL_IBAT, | |
188 | AB8500_CAL_NR, | |
189 | }; | |
190 | ||
191 | /** | |
192 | * struct ab8500_adc_cal_data - Table for storing gain and offset for the | |
193 | * calibrated ADC channels | |
194 | * @gain: Gain of the ADC channel | |
195 | * @offset: Offset of the ADC channel | |
196 | * @otp_calib_hi: Calibration from OTP | |
197 | * @otp_calib_lo: Calibration from OTP | |
198 | */ | |
199 | struct ab8500_adc_cal_data { | |
200 | s64 gain; | |
201 | s64 offset; | |
202 | u16 otp_calib_hi; | |
203 | u16 otp_calib_lo; | |
204 | }; | |
205 | ||
206 | /** | |
207 | * struct ab8500_gpadc_chan_info - per-channel GPADC info | |
208 | * @name: name of the channel | |
209 | * @id: the internal AB8500 ID number for the channel | |
210 | * @hardware_control: indicate that we want to use hardware ADC control | |
211 | * on this channel, the default is software ADC control. Hardware control | |
212 | * is normally only used to test the battery voltage during GSM bursts | |
213 | * and needs a hardware trigger on the GPADCTrig pin of the ASIC. | |
214 | * @falling_edge: indicate that we want to trigger on falling edge | |
215 | * rather than rising edge, rising edge is the default | |
216 | * @avg_sample: how many samples to average: must be 1, 4, 8 or 16. | |
217 | * @trig_timer: how long to wait for the trigger, in 32kHz periods: | |
218 | * 0 .. 255 periods | |
219 | */ | |
220 | struct ab8500_gpadc_chan_info { | |
221 | const char *name; | |
222 | u8 id; | |
223 | bool hardware_control; | |
224 | bool falling_edge; | |
225 | u8 avg_sample; | |
226 | u8 trig_timer; | |
227 | }; | |
228 | ||
229 | /** | |
230 | * struct ab8500_gpadc - AB8500 GPADC device information | |
231 | * @dev: pointer to the containing device | |
232 | * @ab8500: pointer to the parent AB8500 device | |
233 | * @chans: internal per-channel information container | |
234 | * @nchans: number of channels | |
235 | * @complete: pointer to the completion that indicates | |
236 | * the completion of an gpadc conversion cycle | |
237 | * @vddadc: pointer to the regulator supplying VDDADC | |
238 | * @irq_sw: interrupt number that is used by gpadc for software ADC conversion | |
239 | * @irq_hw: interrupt number that is used by gpadc for hardware ADC conversion | |
240 | * @cal_data: array of ADC calibration data structs | |
241 | */ | |
242 | struct ab8500_gpadc { | |
243 | struct device *dev; | |
244 | struct ab8500 *ab8500; | |
245 | struct ab8500_gpadc_chan_info *chans; | |
246 | unsigned int nchans; | |
247 | struct completion complete; | |
248 | struct regulator *vddadc; | |
249 | int irq_sw; | |
250 | int irq_hw; | |
251 | struct ab8500_adc_cal_data cal_data[AB8500_CAL_NR]; | |
252 | }; | |
253 | ||
254 | static struct ab8500_gpadc_chan_info * | |
255 | ab8500_gpadc_get_channel(struct ab8500_gpadc *gpadc, u8 chan) | |
256 | { | |
257 | struct ab8500_gpadc_chan_info *ch; | |
258 | int i; | |
259 | ||
260 | for (i = 0; i < gpadc->nchans; i++) { | |
261 | ch = &gpadc->chans[i]; | |
262 | if (ch->id == chan) | |
263 | break; | |
264 | } | |
265 | if (i == gpadc->nchans) | |
266 | return NULL; | |
267 | ||
268 | return ch; | |
269 | } | |
270 | ||
271 | /** | |
272 | * ab8500_gpadc_ad_to_voltage() - Convert a raw ADC value to a voltage | |
273 | * @gpadc: GPADC instance | |
274 | * @ch: the sampled channel this raw value is coming from | |
275 | * @ad_value: the raw value | |
276 | */ | |
277 | static int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc, | |
278 | enum ab8500_gpadc_channel ch, | |
279 | int ad_value) | |
280 | { | |
281 | int res; | |
282 | ||
283 | switch (ch) { | |
284 | case AB8500_GPADC_CHAN_MAIN_CHARGER: | |
285 | /* No calibration data available: just interpolate */ | |
286 | if (!gpadc->cal_data[AB8500_CAL_VMAIN].gain) { | |
287 | res = AB8500_ADC_CH_CHG_V_MIN + (AB8500_ADC_CH_CHG_V_MAX - | |
288 | AB8500_ADC_CH_CHG_V_MIN) * ad_value / | |
289 | AB8500_ADC_RESOLUTION; | |
290 | break; | |
291 | } | |
292 | /* Here we can use calibration */ | |
293 | res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_VMAIN].gain + | |
294 | gpadc->cal_data[AB8500_CAL_VMAIN].offset) / AB8500_GPADC_CALIB_SCALE; | |
295 | break; | |
296 | ||
297 | case AB8500_GPADC_CHAN_BAT_CTRL: | |
298 | case AB8500_GPADC_CHAN_BAT_TEMP: | |
299 | case AB8500_GPADC_CHAN_ACC_DET_1: | |
300 | case AB8500_GPADC_CHAN_ADC_AUX_1: | |
301 | case AB8500_GPADC_CHAN_ADC_AUX_2: | |
302 | case AB8500_GPADC_CHAN_XTAL_TEMP: | |
303 | /* No calibration data available: just interpolate */ | |
304 | if (!gpadc->cal_data[AB8500_CAL_BTEMP].gain) { | |
305 | res = AB8500_ADC_CH_BTEMP_MIN + (AB8500_ADC_CH_BTEMP_MAX - | |
306 | AB8500_ADC_CH_BTEMP_MIN) * ad_value / | |
307 | AB8500_ADC_RESOLUTION; | |
308 | break; | |
309 | } | |
310 | /* Here we can use calibration */ | |
311 | res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_BTEMP].gain + | |
312 | gpadc->cal_data[AB8500_CAL_BTEMP].offset) / AB8500_GPADC_CALIB_SCALE; | |
313 | break; | |
314 | ||
315 | case AB8500_GPADC_CHAN_VBAT_A: | |
316 | case AB8500_GPADC_CHAN_VBAT_TRUE_MEAS: | |
317 | /* No calibration data available: just interpolate */ | |
318 | if (!gpadc->cal_data[AB8500_CAL_VBAT].gain) { | |
319 | res = AB8500_ADC_CH_VBAT_MIN + (AB8500_ADC_CH_VBAT_MAX - | |
320 | AB8500_ADC_CH_VBAT_MIN) * ad_value / | |
321 | AB8500_ADC_RESOLUTION; | |
322 | break; | |
323 | } | |
324 | /* Here we can use calibration */ | |
325 | res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_VBAT].gain + | |
326 | gpadc->cal_data[AB8500_CAL_VBAT].offset) / AB8500_GPADC_CALIB_SCALE; | |
327 | break; | |
328 | ||
329 | case AB8505_GPADC_CHAN_DIE_TEMP: | |
330 | res = AB8500_ADC_CH_DIETEMP_MIN + | |
331 | (AB8500_ADC_CH_DIETEMP_MAX - AB8500_ADC_CH_DIETEMP_MIN) * ad_value / | |
332 | AB8500_ADC_RESOLUTION; | |
333 | break; | |
334 | ||
335 | case AB8500_GPADC_CHAN_ACC_DET_2: | |
336 | res = AB8500_ADC_CH_ACCDET2_MIN + | |
337 | (AB8500_ADC_CH_ACCDET2_MAX - AB8500_ADC_CH_ACCDET2_MIN) * ad_value / | |
338 | AB8500_ADC_RESOLUTION; | |
339 | break; | |
340 | ||
341 | case AB8500_GPADC_CHAN_VBUS: | |
342 | res = AB8500_ADC_CH_CHG_V_MIN + | |
343 | (AB8500_ADC_CH_CHG_V_MAX - AB8500_ADC_CH_CHG_V_MIN) * ad_value / | |
344 | AB8500_ADC_RESOLUTION; | |
345 | break; | |
346 | ||
347 | case AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT: | |
348 | case AB8500_GPADC_CHAN_USB_CHARGER_CURRENT: | |
349 | res = AB8500_ADC_CH_CHG_I_MIN + | |
350 | (AB8500_ADC_CH_CHG_I_MAX - AB8500_ADC_CH_CHG_I_MIN) * ad_value / | |
351 | AB8500_ADC_RESOLUTION; | |
352 | break; | |
353 | ||
354 | case AB8500_GPADC_CHAN_BACKUP_BAT: | |
355 | res = AB8500_ADC_CH_BKBAT_MIN + | |
356 | (AB8500_ADC_CH_BKBAT_MAX - AB8500_ADC_CH_BKBAT_MIN) * ad_value / | |
357 | AB8500_ADC_RESOLUTION; | |
358 | break; | |
359 | ||
360 | case AB8500_GPADC_CHAN_IBAT_VIRTUAL: | |
361 | /* No calibration data available: just interpolate */ | |
362 | if (!gpadc->cal_data[AB8500_CAL_IBAT].gain) { | |
363 | res = AB8500_ADC_CH_IBAT_MIN + (AB8500_ADC_CH_IBAT_MAX - | |
364 | AB8500_ADC_CH_IBAT_MIN) * ad_value / | |
365 | AB8500_ADC_RESOLUTION; | |
366 | break; | |
367 | } | |
368 | /* Here we can use calibration */ | |
369 | res = (int) (ad_value * gpadc->cal_data[AB8500_CAL_IBAT].gain + | |
370 | gpadc->cal_data[AB8500_CAL_IBAT].offset) | |
371 | >> AB8500_GPADC_CALIB_SHIFT_IBAT; | |
372 | break; | |
373 | ||
374 | default: | |
375 | dev_err(gpadc->dev, | |
376 | "unknown channel ID: %d, not possible to convert\n", | |
377 | ch); | |
378 | res = -EINVAL; | |
379 | break; | |
380 | ||
381 | } | |
382 | ||
383 | return res; | |
384 | } | |
385 | ||
386 | static int ab8500_gpadc_read(struct ab8500_gpadc *gpadc, | |
387 | const struct ab8500_gpadc_chan_info *ch, | |
388 | int *ibat) | |
389 | { | |
390 | int ret; | |
391 | int looplimit = 0; | |
392 | unsigned long completion_timeout; | |
393 | u8 val; | |
394 | u8 low_data, high_data, low_data2, high_data2; | |
395 | u8 ctrl1; | |
396 | u8 ctrl23; | |
397 | unsigned int delay_min = 0; | |
398 | unsigned int delay_max = 0; | |
399 | u8 data_low_addr, data_high_addr; | |
400 | ||
401 | if (!gpadc) | |
402 | return -ENODEV; | |
403 | ||
404 | /* check if conversion is supported */ | |
405 | if ((gpadc->irq_sw <= 0) && !ch->hardware_control) | |
406 | return -ENOTSUPP; | |
407 | if ((gpadc->irq_hw <= 0) && ch->hardware_control) | |
408 | return -ENOTSUPP; | |
409 | ||
410 | /* Enable vddadc by grabbing PM runtime */ | |
411 | pm_runtime_get_sync(gpadc->dev); | |
412 | ||
413 | /* Check if ADC is not busy, lock and proceed */ | |
414 | do { | |
415 | ret = abx500_get_register_interruptible(gpadc->dev, | |
416 | AB8500_GPADC, AB8500_GPADC_STAT_REG, &val); | |
417 | if (ret < 0) | |
418 | goto out; | |
419 | if (!(val & AB8500_GPADC_STAT_BUSY)) | |
420 | break; | |
421 | msleep(20); | |
422 | } while (++looplimit < 10); | |
423 | if (looplimit >= 10 && (val & AB8500_GPADC_STAT_BUSY)) { | |
424 | dev_err(gpadc->dev, "gpadc_conversion: GPADC busy"); | |
425 | ret = -EINVAL; | |
426 | goto out; | |
427 | } | |
428 | ||
429 | /* Enable GPADC */ | |
430 | ctrl1 = AB8500_GPADC_CTRL1_ENABLE; | |
431 | ||
432 | /* Select the channel source and set average samples */ | |
433 | switch (ch->avg_sample) { | |
434 | case 1: | |
435 | ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_1; | |
436 | break; | |
437 | case 4: | |
438 | ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_4; | |
439 | break; | |
440 | case 8: | |
441 | ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_8; | |
442 | break; | |
443 | default: | |
444 | ctrl23 = ch->id | AB8500_GPADC_CTRL2_AVG_16; | |
445 | break; | |
446 | } | |
447 | ||
448 | if (ch->hardware_control) { | |
449 | ret = abx500_set_register_interruptible(gpadc->dev, | |
450 | AB8500_GPADC, AB8500_GPADC_CTRL3_REG, ctrl23); | |
451 | ctrl1 |= AB8500_GPADC_CTRL1_TRIG_ENA; | |
452 | if (ch->falling_edge) | |
453 | ctrl1 |= AB8500_GPADC_CTRL1_TRIG_EDGE; | |
454 | } else { | |
455 | ret = abx500_set_register_interruptible(gpadc->dev, | |
456 | AB8500_GPADC, AB8500_GPADC_CTRL2_REG, ctrl23); | |
457 | } | |
458 | if (ret < 0) { | |
459 | dev_err(gpadc->dev, | |
460 | "gpadc_conversion: set avg samples failed\n"); | |
461 | goto out; | |
462 | } | |
463 | ||
464 | /* | |
465 | * Enable ADC, buffering, select rising edge and enable ADC path | |
466 | * charging current sense if it needed, ABB 3.0 needs some special | |
467 | * treatment too. | |
468 | */ | |
469 | switch (ch->id) { | |
470 | case AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT: | |
471 | case AB8500_GPADC_CHAN_USB_CHARGER_CURRENT: | |
472 | ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA | | |
473 | AB8500_GPADC_CTRL1_ICHAR_ENA; | |
474 | break; | |
475 | case AB8500_GPADC_CHAN_BAT_TEMP: | |
476 | if (!is_ab8500_2p0_or_earlier(gpadc->ab8500)) { | |
477 | ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA | | |
478 | AB8500_GPADC_CTRL1_BTEMP_PULL_UP; | |
479 | /* | |
480 | * Delay might be needed for ABB8500 cut 3.0, if not, | |
481 | * remove when hardware will be available | |
482 | */ | |
483 | delay_min = 1000; /* Delay in micro seconds */ | |
484 | delay_max = 10000; /* large range optimises sleepmode */ | |
485 | break; | |
486 | } | |
df561f66 | 487 | fallthrough; |
07063bbf LW |
488 | default: |
489 | ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA; | |
490 | break; | |
491 | } | |
492 | ||
493 | /* Write configuration to control register 1 */ | |
494 | ret = abx500_set_register_interruptible(gpadc->dev, | |
495 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, ctrl1); | |
496 | if (ret < 0) { | |
497 | dev_err(gpadc->dev, | |
498 | "gpadc_conversion: set Control register failed\n"); | |
499 | goto out; | |
500 | } | |
501 | ||
502 | if (delay_min != 0) | |
503 | usleep_range(delay_min, delay_max); | |
504 | ||
505 | if (ch->hardware_control) { | |
506 | /* Set trigger delay timer */ | |
507 | ret = abx500_set_register_interruptible(gpadc->dev, | |
508 | AB8500_GPADC, AB8500_GPADC_AUTO_TIMER_REG, | |
509 | ch->trig_timer); | |
510 | if (ret < 0) { | |
511 | dev_err(gpadc->dev, | |
512 | "gpadc_conversion: trig timer failed\n"); | |
513 | goto out; | |
514 | } | |
515 | completion_timeout = 2 * HZ; | |
516 | data_low_addr = AB8500_GPADC_AUTODATAL_REG; | |
517 | data_high_addr = AB8500_GPADC_AUTODATAH_REG; | |
518 | } else { | |
519 | /* Start SW conversion */ | |
520 | ret = abx500_mask_and_set_register_interruptible(gpadc->dev, | |
521 | AB8500_GPADC, AB8500_GPADC_CTRL1_REG, | |
522 | AB8500_GPADC_CTRL1_START_SW_CONV, | |
523 | AB8500_GPADC_CTRL1_START_SW_CONV); | |
524 | if (ret < 0) { | |
525 | dev_err(gpadc->dev, | |
526 | "gpadc_conversion: start s/w conv failed\n"); | |
527 | goto out; | |
528 | } | |
529 | completion_timeout = msecs_to_jiffies(AB8500_GPADC_CONVERSION_TIME); | |
530 | data_low_addr = AB8500_GPADC_MANDATAL_REG; | |
531 | data_high_addr = AB8500_GPADC_MANDATAH_REG; | |
532 | } | |
533 | ||
534 | /* Wait for completion of conversion */ | |
535 | if (!wait_for_completion_timeout(&gpadc->complete, | |
536 | completion_timeout)) { | |
537 | dev_err(gpadc->dev, | |
538 | "timeout didn't receive GPADC conv interrupt\n"); | |
539 | ret = -EINVAL; | |
540 | goto out; | |
541 | } | |
542 | ||
543 | /* Read the converted RAW data */ | |
544 | ret = abx500_get_register_interruptible(gpadc->dev, | |
545 | AB8500_GPADC, data_low_addr, &low_data); | |
546 | if (ret < 0) { | |
547 | dev_err(gpadc->dev, | |
548 | "gpadc_conversion: read low data failed\n"); | |
549 | goto out; | |
550 | } | |
551 | ||
552 | ret = abx500_get_register_interruptible(gpadc->dev, | |
553 | AB8500_GPADC, data_high_addr, &high_data); | |
554 | if (ret < 0) { | |
555 | dev_err(gpadc->dev, | |
556 | "gpadc_conversion: read high data failed\n"); | |
557 | goto out; | |
558 | } | |
559 | ||
560 | /* Check if double conversion is required */ | |
561 | if ((ch->id == AB8500_GPADC_CHAN_BAT_CTRL_AND_IBAT) || | |
562 | (ch->id == AB8500_GPADC_CHAN_VBAT_MEAS_AND_IBAT) || | |
563 | (ch->id == AB8500_GPADC_CHAN_VBAT_TRUE_MEAS_AND_IBAT) || | |
564 | (ch->id == AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT)) { | |
565 | ||
566 | if (ch->hardware_control) { | |
567 | /* not supported */ | |
568 | ret = -ENOTSUPP; | |
569 | dev_err(gpadc->dev, | |
570 | "gpadc_conversion: only SW double conversion supported\n"); | |
571 | goto out; | |
572 | } else { | |
573 | /* Read the converted RAW data 2 */ | |
574 | ret = abx500_get_register_interruptible(gpadc->dev, | |
575 | AB8500_GPADC, AB8540_GPADC_MANDATA2L_REG, | |
576 | &low_data2); | |
577 | if (ret < 0) { | |
578 | dev_err(gpadc->dev, | |
579 | "gpadc_conversion: read sw low data 2 failed\n"); | |
580 | goto out; | |
581 | } | |
582 | ||
583 | ret = abx500_get_register_interruptible(gpadc->dev, | |
584 | AB8500_GPADC, AB8540_GPADC_MANDATA2H_REG, | |
585 | &high_data2); | |
586 | if (ret < 0) { | |
587 | dev_err(gpadc->dev, | |
588 | "gpadc_conversion: read sw high data 2 failed\n"); | |
589 | goto out; | |
590 | } | |
591 | if (ibat != NULL) { | |
592 | *ibat = (high_data2 << 8) | low_data2; | |
593 | } else { | |
594 | dev_warn(gpadc->dev, | |
595 | "gpadc_conversion: ibat not stored\n"); | |
596 | } | |
597 | ||
598 | } | |
599 | } | |
600 | ||
601 | /* Disable GPADC */ | |
602 | ret = abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC, | |
603 | AB8500_GPADC_CTRL1_REG, AB8500_GPADC_CTRL1_DISABLE); | |
604 | if (ret < 0) { | |
605 | dev_err(gpadc->dev, "gpadc_conversion: disable gpadc failed\n"); | |
606 | goto out; | |
607 | } | |
608 | ||
609 | /* This eventually drops the regulator */ | |
610 | pm_runtime_mark_last_busy(gpadc->dev); | |
611 | pm_runtime_put_autosuspend(gpadc->dev); | |
612 | ||
613 | return (high_data << 8) | low_data; | |
614 | ||
615 | out: | |
616 | /* | |
617 | * It has shown to be needed to turn off the GPADC if an error occurs, | |
618 | * otherwise we might have problem when waiting for the busy bit in the | |
619 | * GPADC status register to go low. In V1.1 there wait_for_completion | |
620 | * seems to timeout when waiting for an interrupt.. Not seen in V2.0 | |
621 | */ | |
622 | (void) abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC, | |
623 | AB8500_GPADC_CTRL1_REG, AB8500_GPADC_CTRL1_DISABLE); | |
624 | pm_runtime_put(gpadc->dev); | |
625 | dev_err(gpadc->dev, | |
626 | "gpadc_conversion: Failed to AD convert channel %d\n", ch->id); | |
627 | ||
628 | return ret; | |
629 | } | |
630 | ||
631 | /** | |
632 | * ab8500_bm_gpadcconvend_handler() - isr for gpadc conversion completion | |
633 | * @irq: irq number | |
634 | * @data: pointer to the data passed during request irq | |
635 | * | |
636 | * This is a interrupt service routine for gpadc conversion completion. | |
637 | * Notifies the gpadc completion is completed and the converted raw value | |
638 | * can be read from the registers. | |
639 | * Returns IRQ status(IRQ_HANDLED) | |
640 | */ | |
641 | static irqreturn_t ab8500_bm_gpadcconvend_handler(int irq, void *data) | |
642 | { | |
643 | struct ab8500_gpadc *gpadc = data; | |
644 | ||
645 | complete(&gpadc->complete); | |
646 | ||
647 | return IRQ_HANDLED; | |
648 | } | |
649 | ||
650 | static int otp_cal_regs[] = { | |
651 | AB8500_GPADC_CAL_1, | |
652 | AB8500_GPADC_CAL_2, | |
653 | AB8500_GPADC_CAL_3, | |
654 | AB8500_GPADC_CAL_4, | |
655 | AB8500_GPADC_CAL_5, | |
656 | AB8500_GPADC_CAL_6, | |
657 | AB8500_GPADC_CAL_7, | |
658 | }; | |
659 | ||
660 | static int otp4_cal_regs[] = { | |
661 | AB8540_GPADC_OTP4_REG_7, | |
662 | AB8540_GPADC_OTP4_REG_6, | |
663 | AB8540_GPADC_OTP4_REG_5, | |
664 | }; | |
665 | ||
666 | static void ab8500_gpadc_read_calibration_data(struct ab8500_gpadc *gpadc) | |
667 | { | |
668 | int i; | |
669 | int ret[ARRAY_SIZE(otp_cal_regs)]; | |
670 | u8 gpadc_cal[ARRAY_SIZE(otp_cal_regs)]; | |
671 | int ret_otp4[ARRAY_SIZE(otp4_cal_regs)]; | |
672 | u8 gpadc_otp4[ARRAY_SIZE(otp4_cal_regs)]; | |
673 | int vmain_high, vmain_low; | |
674 | int btemp_high, btemp_low; | |
675 | int vbat_high, vbat_low; | |
676 | int ibat_high, ibat_low; | |
677 | s64 V_gain, V_offset, V2A_gain, V2A_offset; | |
678 | ||
679 | /* First we read all OTP registers and store the error code */ | |
680 | for (i = 0; i < ARRAY_SIZE(otp_cal_regs); i++) { | |
681 | ret[i] = abx500_get_register_interruptible(gpadc->dev, | |
682 | AB8500_OTP_EMUL, otp_cal_regs[i], &gpadc_cal[i]); | |
683 | if (ret[i] < 0) { | |
684 | /* Continue anyway: maybe the other registers are OK */ | |
685 | dev_err(gpadc->dev, "%s: read otp reg 0x%02x failed\n", | |
686 | __func__, otp_cal_regs[i]); | |
687 | } else { | |
688 | /* Put this in the entropy pool as device-unique */ | |
689 | add_device_randomness(&ret[i], sizeof(ret[i])); | |
690 | } | |
691 | } | |
692 | ||
693 | /* | |
694 | * The ADC calibration data is stored in OTP registers. | |
695 | * The layout of the calibration data is outlined below and a more | |
696 | * detailed description can be found in UM0836 | |
697 | * | |
698 | * vm_h/l = vmain_high/low | |
699 | * bt_h/l = btemp_high/low | |
700 | * vb_h/l = vbat_high/low | |
701 | * | |
702 | * Data bits 8500/9540: | |
703 | * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
704 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
705 | * | | vm_h9 | vm_h8 | |
706 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
707 | * | | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2 | |
708 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
709 | * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9 | |
710 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
711 | * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1 | |
712 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
713 | * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8 | |
714 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
715 | * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0 | |
716 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
717 | * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 | | |
718 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
719 | * | |
720 | * Data bits 8540: | |
721 | * OTP2 | |
722 | * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
723 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
724 | * | | |
725 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
726 | * | vm_h9 | vm_h8 | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2 | |
727 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
728 | * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9 | |
729 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
730 | * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1 | |
731 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
732 | * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8 | |
733 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
734 | * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0 | |
735 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
736 | * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 | | |
737 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
738 | * | |
739 | * Data bits 8540: | |
740 | * OTP4 | |
741 | * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
742 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
743 | * | | ib_h9 | ib_h8 | ib_h7 | |
744 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
745 | * | ib_h6 | ib_h5 | ib_h4 | ib_h3 | ib_h2 | ib_h1 | ib_h0 | ib_l5 | |
746 | * |.......|.......|.......|.......|.......|.......|.......|....... | |
747 | * | ib_l4 | ib_l3 | ib_l2 | ib_l1 | ib_l0 | | |
748 | * | |
749 | * | |
750 | * Ideal output ADC codes corresponding to injected input voltages | |
751 | * during manufacturing is: | |
752 | * | |
753 | * vmain_high: Vin = 19500mV / ADC ideal code = 997 | |
754 | * vmain_low: Vin = 315mV / ADC ideal code = 16 | |
755 | * btemp_high: Vin = 1300mV / ADC ideal code = 985 | |
756 | * btemp_low: Vin = 21mV / ADC ideal code = 16 | |
757 | * vbat_high: Vin = 4700mV / ADC ideal code = 982 | |
758 | * vbat_low: Vin = 2380mV / ADC ideal code = 33 | |
759 | */ | |
760 | ||
761 | if (is_ab8540(gpadc->ab8500)) { | |
762 | /* Calculate gain and offset for VMAIN if all reads succeeded*/ | |
763 | if (!(ret[1] < 0 || ret[2] < 0)) { | |
764 | vmain_high = (((gpadc_cal[1] & 0xFF) << 2) | | |
765 | ((gpadc_cal[2] & 0xC0) >> 6)); | |
766 | vmain_low = ((gpadc_cal[2] & 0x3E) >> 1); | |
767 | ||
768 | gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_hi = | |
769 | (u16)vmain_high; | |
770 | gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_lo = | |
771 | (u16)vmain_low; | |
772 | ||
773 | gpadc->cal_data[AB8500_CAL_VMAIN].gain = AB8500_GPADC_CALIB_SCALE * | |
774 | (19500 - 315) / (vmain_high - vmain_low); | |
775 | gpadc->cal_data[AB8500_CAL_VMAIN].offset = AB8500_GPADC_CALIB_SCALE * | |
776 | 19500 - (AB8500_GPADC_CALIB_SCALE * (19500 - 315) / | |
777 | (vmain_high - vmain_low)) * vmain_high; | |
778 | } else { | |
779 | gpadc->cal_data[AB8500_CAL_VMAIN].gain = 0; | |
780 | } | |
781 | ||
782 | /* Read IBAT calibration Data */ | |
783 | for (i = 0; i < ARRAY_SIZE(otp4_cal_regs); i++) { | |
784 | ret_otp4[i] = abx500_get_register_interruptible( | |
785 | gpadc->dev, AB8500_OTP_EMUL, | |
786 | otp4_cal_regs[i], &gpadc_otp4[i]); | |
787 | if (ret_otp4[i] < 0) | |
788 | dev_err(gpadc->dev, | |
789 | "%s: read otp4 reg 0x%02x failed\n", | |
790 | __func__, otp4_cal_regs[i]); | |
791 | } | |
792 | ||
793 | /* Calculate gain and offset for IBAT if all reads succeeded */ | |
794 | if (!(ret_otp4[0] < 0 || ret_otp4[1] < 0 || ret_otp4[2] < 0)) { | |
795 | ibat_high = (((gpadc_otp4[0] & 0x07) << 7) | | |
796 | ((gpadc_otp4[1] & 0xFE) >> 1)); | |
797 | ibat_low = (((gpadc_otp4[1] & 0x01) << 5) | | |
798 | ((gpadc_otp4[2] & 0xF8) >> 3)); | |
799 | ||
800 | gpadc->cal_data[AB8500_CAL_IBAT].otp_calib_hi = | |
801 | (u16)ibat_high; | |
802 | gpadc->cal_data[AB8500_CAL_IBAT].otp_calib_lo = | |
803 | (u16)ibat_low; | |
804 | ||
805 | V_gain = ((AB8500_GPADC_IBAT_VDROP_H - AB8500_GPADC_IBAT_VDROP_L) | |
806 | << AB8500_GPADC_CALIB_SHIFT_IBAT) / (ibat_high - ibat_low); | |
807 | ||
808 | V_offset = (AB8500_GPADC_IBAT_VDROP_H << AB8500_GPADC_CALIB_SHIFT_IBAT) - | |
809 | (((AB8500_GPADC_IBAT_VDROP_H - AB8500_GPADC_IBAT_VDROP_L) << | |
810 | AB8500_GPADC_CALIB_SHIFT_IBAT) / (ibat_high - ibat_low)) | |
811 | * ibat_high; | |
812 | /* | |
813 | * Result obtained is in mV (at a scale factor), | |
814 | * we need to calculate gain and offset to get mA | |
815 | */ | |
816 | V2A_gain = (AB8500_ADC_CH_IBAT_MAX - AB8500_ADC_CH_IBAT_MIN)/ | |
817 | (AB8500_ADC_CH_IBAT_MAX_V - AB8500_ADC_CH_IBAT_MIN_V); | |
818 | V2A_offset = ((AB8500_ADC_CH_IBAT_MAX_V * AB8500_ADC_CH_IBAT_MIN - | |
819 | AB8500_ADC_CH_IBAT_MAX * AB8500_ADC_CH_IBAT_MIN_V) | |
820 | << AB8500_GPADC_CALIB_SHIFT_IBAT) | |
821 | / (AB8500_ADC_CH_IBAT_MAX_V - AB8500_ADC_CH_IBAT_MIN_V); | |
822 | ||
823 | gpadc->cal_data[AB8500_CAL_IBAT].gain = | |
824 | V_gain * V2A_gain; | |
825 | gpadc->cal_data[AB8500_CAL_IBAT].offset = | |
826 | V_offset * V2A_gain + V2A_offset; | |
827 | } else { | |
828 | gpadc->cal_data[AB8500_CAL_IBAT].gain = 0; | |
829 | } | |
830 | } else { | |
831 | /* Calculate gain and offset for VMAIN if all reads succeeded */ | |
832 | if (!(ret[0] < 0 || ret[1] < 0 || ret[2] < 0)) { | |
833 | vmain_high = (((gpadc_cal[0] & 0x03) << 8) | | |
834 | ((gpadc_cal[1] & 0x3F) << 2) | | |
835 | ((gpadc_cal[2] & 0xC0) >> 6)); | |
836 | vmain_low = ((gpadc_cal[2] & 0x3E) >> 1); | |
837 | ||
838 | gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_hi = | |
839 | (u16)vmain_high; | |
840 | gpadc->cal_data[AB8500_CAL_VMAIN].otp_calib_lo = | |
841 | (u16)vmain_low; | |
842 | ||
843 | gpadc->cal_data[AB8500_CAL_VMAIN].gain = AB8500_GPADC_CALIB_SCALE * | |
844 | (19500 - 315) / (vmain_high - vmain_low); | |
845 | ||
846 | gpadc->cal_data[AB8500_CAL_VMAIN].offset = AB8500_GPADC_CALIB_SCALE * | |
847 | 19500 - (AB8500_GPADC_CALIB_SCALE * (19500 - 315) / | |
848 | (vmain_high - vmain_low)) * vmain_high; | |
849 | } else { | |
850 | gpadc->cal_data[AB8500_CAL_VMAIN].gain = 0; | |
851 | } | |
852 | } | |
853 | ||
854 | /* Calculate gain and offset for BTEMP if all reads succeeded */ | |
855 | if (!(ret[2] < 0 || ret[3] < 0 || ret[4] < 0)) { | |
856 | btemp_high = (((gpadc_cal[2] & 0x01) << 9) | | |
857 | (gpadc_cal[3] << 1) | ((gpadc_cal[4] & 0x80) >> 7)); | |
858 | btemp_low = ((gpadc_cal[4] & 0x7C) >> 2); | |
859 | ||
860 | gpadc->cal_data[AB8500_CAL_BTEMP].otp_calib_hi = (u16)btemp_high; | |
861 | gpadc->cal_data[AB8500_CAL_BTEMP].otp_calib_lo = (u16)btemp_low; | |
862 | ||
863 | gpadc->cal_data[AB8500_CAL_BTEMP].gain = | |
864 | AB8500_GPADC_CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low); | |
865 | gpadc->cal_data[AB8500_CAL_BTEMP].offset = AB8500_GPADC_CALIB_SCALE * 1300 - | |
866 | (AB8500_GPADC_CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low)) | |
867 | * btemp_high; | |
868 | } else { | |
869 | gpadc->cal_data[AB8500_CAL_BTEMP].gain = 0; | |
870 | } | |
871 | ||
872 | /* Calculate gain and offset for VBAT if all reads succeeded */ | |
873 | if (!(ret[4] < 0 || ret[5] < 0 || ret[6] < 0)) { | |
874 | vbat_high = (((gpadc_cal[4] & 0x03) << 8) | gpadc_cal[5]); | |
875 | vbat_low = ((gpadc_cal[6] & 0xFC) >> 2); | |
876 | ||
877 | gpadc->cal_data[AB8500_CAL_VBAT].otp_calib_hi = (u16)vbat_high; | |
878 | gpadc->cal_data[AB8500_CAL_VBAT].otp_calib_lo = (u16)vbat_low; | |
879 | ||
880 | gpadc->cal_data[AB8500_CAL_VBAT].gain = AB8500_GPADC_CALIB_SCALE * | |
881 | (4700 - 2380) / (vbat_high - vbat_low); | |
882 | gpadc->cal_data[AB8500_CAL_VBAT].offset = AB8500_GPADC_CALIB_SCALE * 4700 - | |
883 | (AB8500_GPADC_CALIB_SCALE * (4700 - 2380) / | |
884 | (vbat_high - vbat_low)) * vbat_high; | |
885 | } else { | |
886 | gpadc->cal_data[AB8500_CAL_VBAT].gain = 0; | |
887 | } | |
888 | } | |
889 | ||
890 | static int ab8500_gpadc_read_raw(struct iio_dev *indio_dev, | |
891 | struct iio_chan_spec const *chan, | |
892 | int *val, int *val2, long mask) | |
893 | { | |
894 | struct ab8500_gpadc *gpadc = iio_priv(indio_dev); | |
895 | const struct ab8500_gpadc_chan_info *ch; | |
896 | int raw_val; | |
897 | int processed; | |
898 | ||
899 | ch = ab8500_gpadc_get_channel(gpadc, chan->address); | |
900 | if (!ch) { | |
901 | dev_err(gpadc->dev, "no such channel %lu\n", | |
902 | chan->address); | |
903 | return -EINVAL; | |
904 | } | |
905 | ||
906 | raw_val = ab8500_gpadc_read(gpadc, ch, NULL); | |
907 | if (raw_val < 0) | |
908 | return raw_val; | |
909 | ||
910 | if (mask == IIO_CHAN_INFO_RAW) { | |
911 | *val = raw_val; | |
912 | return IIO_VAL_INT; | |
913 | } | |
914 | ||
915 | if (mask == IIO_CHAN_INFO_PROCESSED) { | |
916 | processed = ab8500_gpadc_ad_to_voltage(gpadc, ch->id, raw_val); | |
917 | if (processed < 0) | |
918 | return processed; | |
919 | ||
920 | /* Return millivolt or milliamps or millicentigrades */ | |
4f543408 | 921 | *val = processed; |
07063bbf LW |
922 | return IIO_VAL_INT; |
923 | } | |
924 | ||
925 | return -EINVAL; | |
926 | } | |
927 | ||
dec7e2c8 NS |
928 | static int ab8500_gpadc_fwnode_xlate(struct iio_dev *indio_dev, |
929 | const struct fwnode_reference_args *iiospec) | |
07063bbf LW |
930 | { |
931 | int i; | |
932 | ||
933 | for (i = 0; i < indio_dev->num_channels; i++) | |
934 | if (indio_dev->channels[i].channel == iiospec->args[0]) | |
935 | return i; | |
936 | ||
937 | return -EINVAL; | |
938 | } | |
939 | ||
940 | static const struct iio_info ab8500_gpadc_info = { | |
dec7e2c8 | 941 | .fwnode_xlate = ab8500_gpadc_fwnode_xlate, |
07063bbf LW |
942 | .read_raw = ab8500_gpadc_read_raw, |
943 | }; | |
944 | ||
07063bbf LW |
945 | static int ab8500_gpadc_runtime_suspend(struct device *dev) |
946 | { | |
947 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
948 | struct ab8500_gpadc *gpadc = iio_priv(indio_dev); | |
949 | ||
950 | regulator_disable(gpadc->vddadc); | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
955 | static int ab8500_gpadc_runtime_resume(struct device *dev) | |
956 | { | |
957 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
958 | struct ab8500_gpadc *gpadc = iio_priv(indio_dev); | |
959 | int ret; | |
960 | ||
961 | ret = regulator_enable(gpadc->vddadc); | |
962 | if (ret) | |
963 | dev_err(dev, "Failed to enable vddadc: %d\n", ret); | |
964 | ||
965 | return ret; | |
966 | } | |
07063bbf LW |
967 | |
968 | /** | |
969 | * ab8500_gpadc_parse_channel() - process devicetree channel configuration | |
970 | * @dev: pointer to containing device | |
dec7e2c8 | 971 | * @fwnode: fw node for the channel to configure |
07063bbf LW |
972 | * @ch: channel info to fill in |
973 | * @iio_chan: IIO channel specification to fill in | |
974 | * | |
975 | * The devicetree will set up the channel for use with the specific device, | |
976 | * and define usage for things like AUX GPADC inputs more precisely. | |
977 | */ | |
978 | static int ab8500_gpadc_parse_channel(struct device *dev, | |
dec7e2c8 | 979 | struct fwnode_handle *fwnode, |
07063bbf LW |
980 | struct ab8500_gpadc_chan_info *ch, |
981 | struct iio_chan_spec *iio_chan) | |
982 | { | |
dec7e2c8 | 983 | const char *name = fwnode_get_name(fwnode); |
07063bbf LW |
984 | u32 chan; |
985 | int ret; | |
986 | ||
dec7e2c8 | 987 | ret = fwnode_property_read_u32(fwnode, "reg", &chan); |
07063bbf LW |
988 | if (ret) { |
989 | dev_err(dev, "invalid channel number %s\n", name); | |
990 | return ret; | |
991 | } | |
992 | if (chan > AB8500_GPADC_CHAN_BAT_TEMP_AND_IBAT) { | |
993 | dev_err(dev, "%s channel number out of range %d\n", name, chan); | |
994 | return -EINVAL; | |
995 | } | |
996 | ||
997 | iio_chan->channel = chan; | |
998 | iio_chan->datasheet_name = name; | |
999 | iio_chan->indexed = 1; | |
1000 | iio_chan->address = chan; | |
1001 | iio_chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | | |
1002 | BIT(IIO_CHAN_INFO_PROCESSED); | |
1003 | /* Most are voltages (also temperatures), some are currents */ | |
1004 | if ((chan == AB8500_GPADC_CHAN_MAIN_CHARGER_CURRENT) || | |
1005 | (chan == AB8500_GPADC_CHAN_USB_CHARGER_CURRENT)) | |
1006 | iio_chan->type = IIO_CURRENT; | |
1007 | else | |
1008 | iio_chan->type = IIO_VOLTAGE; | |
1009 | ||
1010 | ch->id = chan; | |
1011 | ||
1012 | /* Sensible defaults */ | |
1013 | ch->avg_sample = 16; | |
1014 | ch->hardware_control = false; | |
1015 | ch->falling_edge = false; | |
1016 | ch->trig_timer = 0; | |
1017 | ||
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | /** | |
1022 | * ab8500_gpadc_parse_channels() - Parse the GPADC channels from DT | |
1023 | * @gpadc: the GPADC to configure the channels for | |
07063bbf LW |
1024 | * @chans: the IIO channels we parsed |
1025 | * @nchans: the number of IIO channels we parsed | |
1026 | */ | |
1027 | static int ab8500_gpadc_parse_channels(struct ab8500_gpadc *gpadc, | |
07063bbf LW |
1028 | struct iio_chan_spec **chans_parsed, |
1029 | unsigned int *nchans_parsed) | |
1030 | { | |
dec7e2c8 | 1031 | struct fwnode_handle *child; |
07063bbf LW |
1032 | struct ab8500_gpadc_chan_info *ch; |
1033 | struct iio_chan_spec *iio_chans; | |
1034 | unsigned int nchans; | |
1035 | int i; | |
1036 | ||
dec7e2c8 | 1037 | nchans = device_get_child_node_count(gpadc->dev); |
07063bbf LW |
1038 | if (!nchans) { |
1039 | dev_err(gpadc->dev, "no channel children\n"); | |
1040 | return -ENODEV; | |
1041 | } | |
1042 | dev_info(gpadc->dev, "found %d ADC channels\n", nchans); | |
1043 | ||
1044 | iio_chans = devm_kcalloc(gpadc->dev, nchans, | |
1045 | sizeof(*iio_chans), GFP_KERNEL); | |
1046 | if (!iio_chans) | |
1047 | return -ENOMEM; | |
1048 | ||
1049 | gpadc->chans = devm_kcalloc(gpadc->dev, nchans, | |
1050 | sizeof(*gpadc->chans), GFP_KERNEL); | |
1051 | if (!gpadc->chans) | |
1052 | return -ENOMEM; | |
1053 | ||
1054 | i = 0; | |
dec7e2c8 | 1055 | device_for_each_child_node(gpadc->dev, child) { |
07063bbf LW |
1056 | struct iio_chan_spec *iio_chan; |
1057 | int ret; | |
1058 | ||
1059 | ch = &gpadc->chans[i]; | |
1060 | iio_chan = &iio_chans[i]; | |
1061 | ||
1062 | ret = ab8500_gpadc_parse_channel(gpadc->dev, child, ch, | |
1063 | iio_chan); | |
1064 | if (ret) { | |
dec7e2c8 | 1065 | fwnode_handle_put(child); |
07063bbf LW |
1066 | return ret; |
1067 | } | |
1068 | i++; | |
1069 | } | |
1070 | gpadc->nchans = nchans; | |
1071 | *chans_parsed = iio_chans; | |
1072 | *nchans_parsed = nchans; | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
1077 | static int ab8500_gpadc_probe(struct platform_device *pdev) | |
1078 | { | |
1079 | struct ab8500_gpadc *gpadc; | |
1080 | struct iio_dev *indio_dev; | |
1081 | struct device *dev = &pdev->dev; | |
07063bbf LW |
1082 | struct iio_chan_spec *iio_chans; |
1083 | unsigned int n_iio_chans; | |
1084 | int ret; | |
1085 | ||
1086 | indio_dev = devm_iio_device_alloc(dev, sizeof(*gpadc)); | |
1087 | if (!indio_dev) | |
1088 | return -ENOMEM; | |
1089 | ||
1090 | platform_set_drvdata(pdev, indio_dev); | |
1091 | gpadc = iio_priv(indio_dev); | |
1092 | ||
1093 | gpadc->dev = dev; | |
1094 | gpadc->ab8500 = dev_get_drvdata(dev->parent); | |
1095 | ||
dec7e2c8 | 1096 | ret = ab8500_gpadc_parse_channels(gpadc, &iio_chans, &n_iio_chans); |
07063bbf LW |
1097 | if (ret) |
1098 | return ret; | |
1099 | ||
1100 | gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END"); | |
08e9734a CH |
1101 | if (gpadc->irq_sw < 0) |
1102 | return dev_err_probe(dev, gpadc->irq_sw, | |
1103 | "failed to get platform sw_conv_end irq\n"); | |
07063bbf | 1104 | |
cef49e5e LW |
1105 | if (is_ab8500(gpadc->ab8500)) { |
1106 | gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END"); | |
08e9734a CH |
1107 | if (gpadc->irq_hw < 0) |
1108 | return dev_err_probe(dev, gpadc->irq_hw, | |
1109 | "failed to get platform hw_conv_end irq\n"); | |
cef49e5e LW |
1110 | } else { |
1111 | gpadc->irq_hw = 0; | |
07063bbf LW |
1112 | } |
1113 | ||
1114 | /* Initialize completion used to notify completion of conversion */ | |
1115 | init_completion(&gpadc->complete); | |
1116 | ||
1117 | /* Request interrupts */ | |
1118 | ret = devm_request_threaded_irq(dev, gpadc->irq_sw, NULL, | |
1119 | ab8500_bm_gpadcconvend_handler, IRQF_NO_SUSPEND | IRQF_ONESHOT, | |
1120 | "ab8500-gpadc-sw", gpadc); | |
1121 | if (ret < 0) { | |
1122 | dev_err(dev, | |
1123 | "failed to request sw conversion irq %d\n", | |
1124 | gpadc->irq_sw); | |
1125 | return ret; | |
1126 | } | |
1127 | ||
cef49e5e LW |
1128 | if (gpadc->irq_hw) { |
1129 | ret = devm_request_threaded_irq(dev, gpadc->irq_hw, NULL, | |
1130 | ab8500_bm_gpadcconvend_handler, IRQF_NO_SUSPEND | IRQF_ONESHOT, | |
1131 | "ab8500-gpadc-hw", gpadc); | |
1132 | if (ret < 0) { | |
1133 | dev_err(dev, | |
1134 | "Failed to request hw conversion irq: %d\n", | |
1135 | gpadc->irq_hw); | |
1136 | return ret; | |
1137 | } | |
07063bbf LW |
1138 | } |
1139 | ||
1140 | /* The VTVout LDO used to power the AB8500 GPADC */ | |
1141 | gpadc->vddadc = devm_regulator_get(dev, "vddadc"); | |
08e9734a CH |
1142 | if (IS_ERR(gpadc->vddadc)) |
1143 | return dev_err_probe(dev, PTR_ERR(gpadc->vddadc), | |
1144 | "failed to get vddadc\n"); | |
07063bbf LW |
1145 | |
1146 | ret = regulator_enable(gpadc->vddadc); | |
1147 | if (ret) { | |
1148 | dev_err(dev, "failed to enable vddadc: %d\n", ret); | |
1149 | return ret; | |
1150 | } | |
1151 | ||
1152 | /* Enable runtime PM */ | |
1153 | pm_runtime_get_noresume(dev); | |
1154 | pm_runtime_set_active(dev); | |
1155 | pm_runtime_enable(dev); | |
1156 | pm_runtime_set_autosuspend_delay(dev, AB8500_GPADC_AUTOSUSPEND_DELAY); | |
1157 | pm_runtime_use_autosuspend(dev); | |
1158 | ||
1159 | ab8500_gpadc_read_calibration_data(gpadc); | |
1160 | ||
1161 | pm_runtime_put(dev); | |
1162 | ||
07063bbf LW |
1163 | indio_dev->name = "ab8500-gpadc"; |
1164 | indio_dev->modes = INDIO_DIRECT_MODE; | |
1165 | indio_dev->info = &ab8500_gpadc_info; | |
1166 | indio_dev->channels = iio_chans; | |
1167 | indio_dev->num_channels = n_iio_chans; | |
1168 | ||
1169 | ret = devm_iio_device_register(dev, indio_dev); | |
1170 | if (ret) | |
1171 | goto out_dis_pm; | |
1172 | ||
1173 | return 0; | |
1174 | ||
1175 | out_dis_pm: | |
1176 | pm_runtime_get_sync(dev); | |
1177 | pm_runtime_put_noidle(dev); | |
1178 | pm_runtime_disable(dev); | |
1179 | regulator_disable(gpadc->vddadc); | |
1180 | ||
1181 | return ret; | |
1182 | } | |
1183 | ||
1184 | static int ab8500_gpadc_remove(struct platform_device *pdev) | |
1185 | { | |
1186 | struct iio_dev *indio_dev = platform_get_drvdata(pdev); | |
1187 | struct ab8500_gpadc *gpadc = iio_priv(indio_dev); | |
1188 | ||
1189 | pm_runtime_get_sync(gpadc->dev); | |
1190 | pm_runtime_put_noidle(gpadc->dev); | |
1191 | pm_runtime_disable(gpadc->dev); | |
1192 | regulator_disable(gpadc->vddadc); | |
1193 | ||
1194 | return 0; | |
1195 | } | |
1196 | ||
c62433f9 JC |
1197 | static DEFINE_RUNTIME_DEV_PM_OPS(ab8500_gpadc_pm_ops, |
1198 | ab8500_gpadc_runtime_suspend, | |
1199 | ab8500_gpadc_runtime_resume, NULL); | |
07063bbf LW |
1200 | |
1201 | static struct platform_driver ab8500_gpadc_driver = { | |
1202 | .probe = ab8500_gpadc_probe, | |
1203 | .remove = ab8500_gpadc_remove, | |
1204 | .driver = { | |
1205 | .name = "ab8500-gpadc", | |
c62433f9 | 1206 | .pm = pm_ptr(&ab8500_gpadc_pm_ops), |
07063bbf LW |
1207 | }, |
1208 | }; | |
1209 | builtin_platform_driver(ab8500_gpadc_driver); |