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iio: mma8452: add support for MMA8453Q accelerometer chip
[linux-2.6-block.git] / drivers / iio / accel / mma8452.c
CommitLineData
c7eeea93 1/*
c5ea1b58
MK		 2 * mma8452.c - Support for following Freescale 3-axis accelerometers:
3 *
4 * MMA8452Q (12 bit)
5 * MMA8453Q (10 bit)
c7eeea93
PM		 6 *
7 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
8 *
9 * This file is subject to the terms and conditions of version 2 of
10 * the GNU General Public License. See the file COPYING in the main
11 * directory of this archive for more details.
12 *
13 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
14 *
28e34278 15 * TODO: orientation / freefall events, autosleep
c7eeea93
PM		 16 */
17
18#include <linux/module.h>
19#include <linux/i2c.h>
20#include <linux/iio/iio.h>
21#include <linux/iio/sysfs.h>
c7eeea93 22#include <linux/iio/buffer.h>
ae6d9ce0
MF		 23#include <linux/iio/trigger.h>
24#include <linux/iio/trigger_consumer.h>
c7eeea93 25#include <linux/iio/triggered_buffer.h>
28e34278 26#include <linux/iio/events.h>
c7eeea93 27#include <linux/delay.h>
c3cdd6e4 28#include <linux/of_device.h>
c7eeea93 29
69abff81
HK		 30#define MMA8452_STATUS 0x00
31#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
c5ea1b58 32#define MMA8452_OUT_X 0x01 /* MSB first */
69abff81
HK		 33#define MMA8452_OUT_Y 0x03
34#define MMA8452_OUT_Z 0x05
35#define MMA8452_INT_SRC 0x0c
36#define MMA8452_WHO_AM_I 0x0d
37#define MMA8452_DATA_CFG 0x0e
38#define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
39#define MMA8452_DATA_CFG_FS_2G 0
40#define MMA8452_DATA_CFG_FS_4G 1
41#define MMA8452_DATA_CFG_FS_8G 2
42#define MMA8452_DATA_CFG_HPF_MASK BIT(4)
43#define MMA8452_HP_FILTER_CUTOFF 0x0f
44#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
45#define MMA8452_TRANSIENT_CFG 0x1d
46#define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
47#define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
48#define MMA8452_TRANSIENT_CFG_ELE BIT(4)
49#define MMA8452_TRANSIENT_SRC 0x1e
50#define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
51#define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
52#define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
53#define MMA8452_TRANSIENT_THS 0x1f
54#define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
55#define MMA8452_TRANSIENT_COUNT 0x20
56#define MMA8452_CTRL_REG1 0x2a
57#define MMA8452_CTRL_ACTIVE BIT(0)
58#define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
59#define MMA8452_CTRL_DR_SHIFT 3
60#define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
61#define MMA8452_CTRL_REG2 0x2b
62#define MMA8452_CTRL_REG2_RST BIT(6)
63#define MMA8452_CTRL_REG4 0x2d
64#define MMA8452_CTRL_REG5 0x2e
65#define MMA8452_OFF_X 0x2f
66#define MMA8452_OFF_Y 0x30
67#define MMA8452_OFF_Z 0x31
c7eeea93 68
69abff81 69#define MMA8452_MAX_REG 0x31
2a17698c 70
69abff81
HK		 71#define MMA8452_INT_DRDY BIT(0)
72#define MMA8452_INT_TRANS BIT(5)
c7eeea93 73
69abff81 74#define MMA8452_DEVICE_ID 0x2a
c5ea1b58 75#define MMA8453_DEVICE_ID 0x3a
c7eeea93
PM		 76
77struct mma8452_data {
78 struct i2c_client *client;
79 struct mutex lock;
80 u8 ctrl_reg1;
81 u8 data_cfg;
c3cdd6e4
MK		 82 const struct mma_chip_info *chip_info;
83};
84
85/**
86 * struct mma_chip_info - chip specific data for Freescale's accelerometers
87 * @chip_id: WHO_AM_I register's value
88 * @channels: struct iio_chan_spec matching the device's
89 * capabilities
90 * @num_channels: number of channels
91 * @mma_scales: scale factors for converting register values
92 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
93 * per mode: m/s^2 and micro m/s^2
94 * @ev_cfg: event config register address
95 * @ev_cfg_ele: latch bit in event config register
96 * @ev_cfg_chan_shift: number of the bit to enable events in X
97 * direction; in event config register
98 * @ev_src: event source register address
99 * @ev_src_xe: bit in event source register that indicates
100 * an event in X direction
101 * @ev_src_ye: bit in event source register that indicates
102 * an event in Y direction
103 * @ev_src_ze: bit in event source register that indicates
104 * an event in Z direction
105 * @ev_ths: event threshold register address
106 * @ev_ths_mask: mask for the threshold value
107 * @ev_count: event count (period) register address
108 *
109 * Since not all chips supported by the driver support comparing high pass
110 * filtered data for events (interrupts), different interrupt sources are
111 * used for different chips and the relevant registers are included here.
112 */
113struct mma_chip_info {
114 u8 chip_id;
115 const struct iio_chan_spec *channels;
116 int num_channels;
117 const int mma_scales[3][2];
118 u8 ev_cfg;
119 u8 ev_cfg_ele;
120 u8 ev_cfg_chan_shift;
121 u8 ev_src;
122 u8 ev_src_xe;
123 u8 ev_src_ye;
124 u8 ev_src_ze;
125 u8 ev_ths;
126 u8 ev_ths_mask;
127 u8 ev_count;
c7eeea93
PM		 128};
129
130static int mma8452_drdy(struct mma8452_data *data)
131{
132 int tries = 150;
133
134 while (tries-- > 0) {
135 int ret = i2c_smbus_read_byte_data(data->client,
136 MMA8452_STATUS);
137 if (ret < 0)
138 return ret;
139 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
140 return 0;
686027fb 141
c7eeea93
PM		 142 msleep(20);
143 }
144
145 dev_err(&data->client->dev, "data not ready\n");
686027fb 146
c7eeea93
PM		 147 return -EIO;
148}
149
150static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
151{
152 int ret = mma8452_drdy(data);
686027fb 153
c7eeea93
PM		 154 if (ret < 0)
155 return ret;
686027fb
HK		 156
157 return i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
158 3 * sizeof(__be16), (u8 *)buf);
c7eeea93
PM		 159}
160
686027fb
HK		 161static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
162 int n)
c7eeea93
PM		 163{
164 size_t len = 0;
165
166 while (n-- > 0)
686027fb
HK		 167 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
168 vals[n][0], vals[n][1]);
c7eeea93
PM		 169
170 /* replace trailing space by newline */
171 buf[len - 1] = '\n';
172
173 return len;
174}
175
176static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
686027fb 177 int val, int val2)
c7eeea93
PM		 178{
179 while (n-- > 0)
180 if (val == vals[n][0] && val2 == vals[n][1])
181 return n;
182
183 return -EINVAL;
184}
185
5dbbd19f
MF		 186static int mma8452_get_odr_index(struct mma8452_data *data)
187{
188 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
189 MMA8452_CTRL_DR_SHIFT;
190}
191
c7eeea93
PM		 192static const int mma8452_samp_freq[8][2] = {
193 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
194 {6, 250000}, {1, 560000}
195};
196
5dbbd19f
MF		 197/* Datasheet table 35 (step time vs sample frequency) */
198static const int mma8452_transient_time_step_us[8] = {
199 1250,
200 2500,
201 5000,
202 10000,
203 20000,
204 20000,
205 20000,
206 20000
207};
208
1e79841a
MF		 209/* Datasheet table 18 (normal mode) */
210static const int mma8452_hp_filter_cutoff[8][4][2] = {
211 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
212 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
213 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
214 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
215 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
216 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
217 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
218 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
219};
220
c7eeea93 221static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
686027fb
HK		 222 struct device_attribute *attr,
223 char *buf)
c7eeea93
PM		 224{
225 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
686027fb 226 ARRAY_SIZE(mma8452_samp_freq));
c7eeea93
PM		 227}
228
229static ssize_t mma8452_show_scale_avail(struct device *dev,
686027fb
HK		 230 struct device_attribute *attr,
231 char *buf)
c7eeea93 232{
c3cdd6e4
MK		 233 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
234 to_i2c_client(dev)));
235
236 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
237 ARRAY_SIZE(data->chip_info->mma_scales));
c7eeea93
PM		 238}
239
1e79841a
MF		 240static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
241 struct device_attribute *attr,
242 char *buf)
243{
244 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
245 struct mma8452_data *data = iio_priv(indio_dev);
246 int i = mma8452_get_odr_index(data);
247
248 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
249 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
250}
251
c7eeea93
PM		 252static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
253static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
686027fb 254 mma8452_show_scale_avail, NULL, 0);
1e79841a 255static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
686027fb 256 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
c7eeea93
PM		 257
258static int mma8452_get_samp_freq_index(struct mma8452_data *data,
686027fb 259 int val, int val2)
c7eeea93
PM		 260{
261 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
686027fb
HK		 262 ARRAY_SIZE(mma8452_samp_freq),
263 val, val2);
c7eeea93
PM		 264}
265
686027fb 266static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
c7eeea93 267{
c3cdd6e4
MK		 268 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
269 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
c7eeea93
PM		 270}
271
1e79841a
MF		 272static int mma8452_get_hp_filter_index(struct mma8452_data *data,
273 int val, int val2)
274{
275 int i = mma8452_get_odr_index(data);
276
277 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
001fceb9 278 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
1e79841a
MF		 279}
280
281static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
282{
283 int i, ret;
284
285 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
286 if (ret < 0)
287 return ret;
288
289 i = mma8452_get_odr_index(data);
290 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
291 *hz = mma8452_hp_filter_cutoff[i][ret][0];
292 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
293
294 return 0;
295}
296
c7eeea93
PM		 297static int mma8452_read_raw(struct iio_dev *indio_dev,
298 struct iio_chan_spec const *chan,
299 int *val, int *val2, long mask)
300{
301 struct mma8452_data *data = iio_priv(indio_dev);
302 __be16 buffer[3];
303 int i, ret;
304
305 switch (mask) {
306 case IIO_CHAN_INFO_RAW:
307 if (iio_buffer_enabled(indio_dev))
308 return -EBUSY;
309
310 mutex_lock(&data->lock);
311 ret = mma8452_read(data, buffer);
312 mutex_unlock(&data->lock);
313 if (ret < 0)
314 return ret;
686027fb 315
c3cdd6e4
MK		 316 *val = sign_extend32(be16_to_cpu(
317 buffer[chan->scan_index]) >> chan->scan_type.shift,
318 chan->scan_type.realbits - 1);
686027fb 319
c7eeea93
PM		 320 return IIO_VAL_INT;
321 case IIO_CHAN_INFO_SCALE:
322 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
c3cdd6e4
MK		 323 *val = data->chip_info->mma_scales[i][0];
324 *val2 = data->chip_info->mma_scales[i][1];
686027fb 325
c7eeea93
PM		 326 return IIO_VAL_INT_PLUS_MICRO;
327 case IIO_CHAN_INFO_SAMP_FREQ:
5dbbd19f 328 i = mma8452_get_odr_index(data);
c7eeea93
PM		 329 *val = mma8452_samp_freq[i][0];
330 *val2 = mma8452_samp_freq[i][1];
686027fb 331
c7eeea93
PM		 332 return IIO_VAL_INT_PLUS_MICRO;
333 case IIO_CHAN_INFO_CALIBBIAS:
686027fb
HK		 334 ret = i2c_smbus_read_byte_data(data->client,
335 MMA8452_OFF_X + chan->scan_index);
c7eeea93
PM		 336 if (ret < 0)
337 return ret;
686027fb 338
c7eeea93 339 *val = sign_extend32(ret, 7);
686027fb 340
c7eeea93 341 return IIO_VAL_INT;
1e79841a
MF		 342 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
343 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
344 ret = mma8452_read_hp_filter(data, val, val2);
345 if (ret < 0)
346 return ret;
347 } else {
348 *val = 0;
349 *val2 = 0;
350 }
686027fb 351
1e79841a 352 return IIO_VAL_INT_PLUS_MICRO;
c7eeea93 353 }
686027fb 354
c7eeea93
PM		 355 return -EINVAL;
356}
357
358static int mma8452_standby(struct mma8452_data *data)
359{
360 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
686027fb 361 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
c7eeea93
PM		 362}
363
364static int mma8452_active(struct mma8452_data *data)
365{
366 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
686027fb 367 data->ctrl_reg1);
c7eeea93
PM		 368}
369
370static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
371{
372 int ret;
373
374 mutex_lock(&data->lock);
375
376 /* config can only be changed when in standby */
377 ret = mma8452_standby(data);
378 if (ret < 0)
379 goto fail;
380
381 ret = i2c_smbus_write_byte_data(data->client, reg, val);
382 if (ret < 0)
383 goto fail;
384
385 ret = mma8452_active(data);
386 if (ret < 0)
387 goto fail;
388
389 ret = 0;
390fail:
391 mutex_unlock(&data->lock);
686027fb 392
c7eeea93
PM		 393 return ret;
394}
395
1e79841a
MF		 396static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
397 int val, int val2)
398{
399 int i, reg;
400
401 i = mma8452_get_hp_filter_index(data, val, val2);
402 if (i < 0)
b9fddcdb 403 return i;
1e79841a
MF		 404
405 reg = i2c_smbus_read_byte_data(data->client,
406 MMA8452_HP_FILTER_CUTOFF);
407 if (reg < 0)
408 return reg;
686027fb 409
1e79841a
MF		 410 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
411 reg |= i;
412
413 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
414}
415
c7eeea93
PM		 416static int mma8452_write_raw(struct iio_dev *indio_dev,
417 struct iio_chan_spec const *chan,
418 int val, int val2, long mask)
419{
420 struct mma8452_data *data = iio_priv(indio_dev);
1e79841a 421 int i, ret;
c7eeea93
PM		 422
423 if (iio_buffer_enabled(indio_dev))
424 return -EBUSY;
425
426 switch (mask) {
427 case IIO_CHAN_INFO_SAMP_FREQ:
428 i = mma8452_get_samp_freq_index(data, val, val2);
429 if (i < 0)
b9fddcdb 430 return i;
c7eeea93
PM		 431
432 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
433 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
686027fb 434
c7eeea93 435 return mma8452_change_config(data, MMA8452_CTRL_REG1,
686027fb 436 data->ctrl_reg1);
c7eeea93
PM		 437 case IIO_CHAN_INFO_SCALE:
438 i = mma8452_get_scale_index(data, val, val2);
439 if (i < 0)
b9fddcdb 440 return i;
686027fb 441
c7eeea93
PM		 442 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
443 data->data_cfg |= i;
686027fb 444
c7eeea93 445 return mma8452_change_config(data, MMA8452_DATA_CFG,
686027fb 446 data->data_cfg);
c7eeea93
PM		 447 case IIO_CHAN_INFO_CALIBBIAS:
448 if (val < -128 || val > 127)
449 return -EINVAL;
686027fb
HK		 450
451 return mma8452_change_config(data,
452 MMA8452_OFF_X + chan->scan_index,
453 val);
1e79841a
MF		 454
455 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
456 if (val == 0 && val2 == 0) {
457 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
458 } else {
459 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
460 ret = mma8452_set_hp_filter_frequency(data, val, val2);
461 if (ret < 0)
462 return ret;
463 }
686027fb 464
1e79841a 465 return mma8452_change_config(data, MMA8452_DATA_CFG,
686027fb 466 data->data_cfg);
1e79841a 467
c7eeea93
PM		 468 default:
469 return -EINVAL;
470 }
471}
472
28e34278
MF		 473static int mma8452_read_thresh(struct iio_dev *indio_dev,
474 const struct iio_chan_spec *chan,
475 enum iio_event_type type,
476 enum iio_event_direction dir,
477 enum iio_event_info info,
478 int *val, int *val2)
479{
480 struct mma8452_data *data = iio_priv(indio_dev);
5dbbd19f 481 int ret, us;
28e34278 482
5dbbd19f
MF		 483 switch (info) {
484 case IIO_EV_INFO_VALUE:
485 ret = i2c_smbus_read_byte_data(data->client,
c3cdd6e4 486 data->chip_info->ev_ths);
5dbbd19f
MF		 487 if (ret < 0)
488 return ret;
489
c3cdd6e4 490 *val = ret & data->chip_info->ev_ths_mask;
686027fb 491
5dbbd19f 492 return IIO_VAL_INT;
28e34278 493
5dbbd19f
MF		 494 case IIO_EV_INFO_PERIOD:
495 ret = i2c_smbus_read_byte_data(data->client,
c3cdd6e4 496 data->chip_info->ev_count);
5dbbd19f
MF		 497 if (ret < 0)
498 return ret;
499
500 us = ret * mma8452_transient_time_step_us[
501 mma8452_get_odr_index(data)];
502 *val = us / USEC_PER_SEC;
503 *val2 = us % USEC_PER_SEC;
686027fb 504
5dbbd19f 505 return IIO_VAL_INT_PLUS_MICRO;
28e34278 506
1e79841a
MF		 507 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
508 ret = i2c_smbus_read_byte_data(data->client,
509 MMA8452_TRANSIENT_CFG);
510 if (ret < 0)
511 return ret;
512
513 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
514 *val = 0;
515 *val2 = 0;
516 } else {
517 ret = mma8452_read_hp_filter(data, val, val2);
518 if (ret < 0)
519 return ret;
520 }
686027fb 521
1e79841a
MF		 522 return IIO_VAL_INT_PLUS_MICRO;
523
5dbbd19f
MF		 524 default:
525 return -EINVAL;
526 }
28e34278
MF		 527}
528
529static int mma8452_write_thresh(struct iio_dev *indio_dev,
530 const struct iio_chan_spec *chan,
531 enum iio_event_type type,
532 enum iio_event_direction dir,
533 enum iio_event_info info,
534 int val, int val2)
535{
536 struct mma8452_data *data = iio_priv(indio_dev);
1e79841a 537 int ret, reg, steps;
28e34278 538
5dbbd19f
MF		 539 switch (info) {
540 case IIO_EV_INFO_VALUE:
11218226
HK		 541 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
542 return -EINVAL;
543
c3cdd6e4
MK		 544 return mma8452_change_config(data, data->chip_info->ev_ths,
545 val);
5dbbd19f
MF		 546
547 case IIO_EV_INFO_PERIOD:
548 steps = (val * USEC_PER_SEC + val2) /
549 mma8452_transient_time_step_us[
550 mma8452_get_odr_index(data)];
551
11218226 552 if (steps < 0 || steps > 0xff)
5dbbd19f
MF		 553 return -EINVAL;
554
c3cdd6e4 555 return mma8452_change_config(data, data->chip_info->ev_count,
5dbbd19f 556 steps);
686027fb 557
1e79841a
MF		 558 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
559 reg = i2c_smbus_read_byte_data(data->client,
560 MMA8452_TRANSIENT_CFG);
561 if (reg < 0)
562 return reg;
563
564 if (val == 0 && val2 == 0) {
565 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
566 } else {
567 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
568 ret = mma8452_set_hp_filter_frequency(data, val, val2);
569 if (ret < 0)
570 return ret;
571 }
686027fb 572
1e79841a
MF		 573 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
574
5dbbd19f
MF		 575 default:
576 return -EINVAL;
577 }
28e34278
MF		 578}
579
580static int mma8452_read_event_config(struct iio_dev *indio_dev,
581 const struct iio_chan_spec *chan,
582 enum iio_event_type type,
583 enum iio_event_direction dir)
584{
585 struct mma8452_data *data = iio_priv(indio_dev);
c3cdd6e4 586 const struct mma_chip_info *chip = data->chip_info;
28e34278
MF		 587 int ret;
588
c3cdd6e4
MK		 589 ret = i2c_smbus_read_byte_data(data->client,
590 data->chip_info->ev_cfg);
28e34278
MF		 591 if (ret < 0)
592 return ret;
593
c3cdd6e4 594 return !!(ret & BIT(chan->scan_index + chip->ev_cfg_chan_shift));
28e34278
MF		 595}
596
597static int mma8452_write_event_config(struct iio_dev *indio_dev,
598 const struct iio_chan_spec *chan,
599 enum iio_event_type type,
600 enum iio_event_direction dir,
601 int state)
602{
603 struct mma8452_data *data = iio_priv(indio_dev);
c3cdd6e4 604 const struct mma_chip_info *chip = data->chip_info;
28e34278
MF		 605 int val;
606
c3cdd6e4 607 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
28e34278
MF		 608 if (val < 0)
609 return val;
610
611 if (state)
c3cdd6e4 612 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
28e34278 613 else
c3cdd6e4 614 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
28e34278
MF		 615
616 val |= MMA8452_TRANSIENT_CFG_ELE;
617
c3cdd6e4 618 return mma8452_change_config(data, chip->ev_cfg, val);
28e34278
MF		 619}
620
621static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
622{
623 struct mma8452_data *data = iio_priv(indio_dev);
624 s64 ts = iio_get_time_ns();
625 int src;
626
c3cdd6e4 627 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
28e34278
MF		 628 if (src < 0)
629 return;
630
c3cdd6e4 631 if (src & data->chip_info->ev_src_xe)
28e34278
MF		 632 iio_push_event(indio_dev,
633 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
c5d0db06 634 IIO_EV_TYPE_MAG,
28e34278
MF		 635 IIO_EV_DIR_RISING),
636 ts);
637
c3cdd6e4 638 if (src & data->chip_info->ev_src_ye)
28e34278
MF		 639 iio_push_event(indio_dev,
640 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
c5d0db06 641 IIO_EV_TYPE_MAG,
28e34278
MF		 642 IIO_EV_DIR_RISING),
643 ts);
644
c3cdd6e4 645 if (src & data->chip_info->ev_src_ze)
28e34278
MF		 646 iio_push_event(indio_dev,
647 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
c5d0db06 648 IIO_EV_TYPE_MAG,
28e34278
MF		 649 IIO_EV_DIR_RISING),
650 ts);
651}
652
653static irqreturn_t mma8452_interrupt(int irq, void *p)
654{
655 struct iio_dev *indio_dev = p;
656 struct mma8452_data *data = iio_priv(indio_dev);
ae6d9ce0 657 int ret = IRQ_NONE;
28e34278
MF		 658 int src;
659
660 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
661 if (src < 0)
662 return IRQ_NONE;
663
ae6d9ce0
MF		 664 if (src & MMA8452_INT_DRDY) {
665 iio_trigger_poll_chained(indio_dev->trig);
666 ret = IRQ_HANDLED;
667 }
668
28e34278
MF		 669 if (src & MMA8452_INT_TRANS) {
670 mma8452_transient_interrupt(indio_dev);
ae6d9ce0 671 ret = IRQ_HANDLED;
28e34278
MF		 672 }
673
ae6d9ce0 674 return ret;
28e34278
MF		 675}
676
c7eeea93
PM		 677static irqreturn_t mma8452_trigger_handler(int irq, void *p)
678{
679 struct iio_poll_func *pf = p;
680 struct iio_dev *indio_dev = pf->indio_dev;
681 struct mma8452_data *data = iio_priv(indio_dev);
682 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
683 int ret;
684
686027fb 685 ret = mma8452_read(data, (__be16 *)buffer);
c7eeea93
PM		 686 if (ret < 0)
687 goto done;
688
689 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
686027fb 690 iio_get_time_ns());
c7eeea93
PM		 691
692done:
693 iio_trigger_notify_done(indio_dev->trig);
686027fb 694
c7eeea93
PM		 695 return IRQ_HANDLED;
696}
697
2a17698c
MF		 698static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
699 unsigned reg, unsigned writeval,
700 unsigned *readval)
701{
702 int ret;
703 struct mma8452_data *data = iio_priv(indio_dev);
704
705 if (reg > MMA8452_MAX_REG)
706 return -EINVAL;
707
708 if (!readval)
709 return mma8452_change_config(data, reg, writeval);
710
711 ret = i2c_smbus_read_byte_data(data->client, reg);
712 if (ret < 0)
713 return ret;
714
715 *readval = ret;
716
717 return 0;
718}
719
28e34278
MF		 720static const struct iio_event_spec mma8452_transient_event[] = {
721 {
c5d0db06 722 .type = IIO_EV_TYPE_MAG,
28e34278
MF		 723 .dir = IIO_EV_DIR_RISING,
724 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
5dbbd19f 725 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1e79841a
MF		 726 BIT(IIO_EV_INFO_PERIOD) |
727 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
28e34278
MF		 728 },
729};
730
731/*
732 * Threshold is configured in fixed 8G/127 steps regardless of
733 * currently selected scale for measurement.
734 */
735static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
736
737static struct attribute *mma8452_event_attributes[] = {
738 &iio_const_attr_accel_transient_scale.dev_attr.attr,
739 NULL,
740};
741
742static struct attribute_group mma8452_event_attribute_group = {
743 .attrs = mma8452_event_attributes,
744 .name = "events",
745};
746
c3cdd6e4 747#define MMA8452_CHANNEL(axis, idx, bits) { \
c7eeea93
PM		 748 .type = IIO_ACCEL, \
749 .modified = 1, \
750 .channel2 = IIO_MOD_##axis, \
751 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
686027fb 752 BIT(IIO_CHAN_INFO_CALIBBIAS), \
c7eeea93 753 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
686027fb
HK		 754 BIT(IIO_CHAN_INFO_SCALE) | \
755 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
c7eeea93
PM		 756 .scan_index = idx, \
757 .scan_type = { \
758 .sign = 's', \
c3cdd6e4 759 .realbits = (bits), \
c7eeea93 760 .storagebits = 16, \
c3cdd6e4 761 .shift = 16 - (bits), \
c7eeea93
PM		 762 .endianness = IIO_BE, \
763 }, \
28e34278
MF		 764 .event_spec = mma8452_transient_event, \
765 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
c7eeea93
PM		 766}
767
768static const struct iio_chan_spec mma8452_channels[] = {
c3cdd6e4
MK		 769 MMA8452_CHANNEL(X, 0, 12),
770 MMA8452_CHANNEL(Y, 1, 12),
771 MMA8452_CHANNEL(Z, 2, 12),
c7eeea93
PM		 772 IIO_CHAN_SOFT_TIMESTAMP(3),
773};
774
c5ea1b58
MK		 775static const struct iio_chan_spec mma8453_channels[] = {
776 MMA8452_CHANNEL(X, 0, 10),
777 MMA8452_CHANNEL(Y, 1, 10),
778 MMA8452_CHANNEL(Z, 2, 10),
779 IIO_CHAN_SOFT_TIMESTAMP(3),
780};
781
c3cdd6e4
MK		 782enum {
783 mma8452,
c5ea1b58 784 mma8453,
c3cdd6e4
MK		 785};
786
787static const struct mma_chip_info mma_chip_info_table[] = {
788 [mma8452] = {
789 .chip_id = MMA8452_DEVICE_ID,
790 .channels = mma8452_channels,
791 .num_channels = ARRAY_SIZE(mma8452_channels),
792 /*
793 * Hardware has fullscale of -2G, -4G, -8G corresponding to
794 * raw value -2048 for 12 bit or -512 for 10 bit.
795 * The userspace interface uses m/s^2 and we declare micro units
796 * So scale factor for 12 bit here is given by:
797 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
798 */
799 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
800 .ev_cfg = MMA8452_TRANSIENT_CFG,
801 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
802 .ev_cfg_chan_shift = 1,
803 .ev_src = MMA8452_TRANSIENT_SRC,
804 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
805 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
806 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
807 .ev_ths = MMA8452_TRANSIENT_THS,
808 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
809 .ev_count = MMA8452_TRANSIENT_COUNT,
810 },
c5ea1b58
MK		 811 [mma8453] = {
812 .chip_id = MMA8453_DEVICE_ID,
813 .channels = mma8453_channels,
814 .num_channels = ARRAY_SIZE(mma8453_channels),
815 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
816 .ev_cfg = MMA8452_TRANSIENT_CFG,
817 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
818 .ev_cfg_chan_shift = 1,
819 .ev_src = MMA8452_TRANSIENT_SRC,
820 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
821 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
822 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
823 .ev_ths = MMA8452_TRANSIENT_THS,
824 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
825 .ev_count = MMA8452_TRANSIENT_COUNT,
826 },
c3cdd6e4
MK		 827};
828
c7eeea93
PM		 829static struct attribute *mma8452_attributes[] = {
830 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
831 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1e79841a 832 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
c7eeea93
PM		 833 NULL
834};
835
836static const struct attribute_group mma8452_group = {
837 .attrs = mma8452_attributes,
838};
839
840static const struct iio_info mma8452_info = {
841 .attrs = &mma8452_group,
842 .read_raw = &mma8452_read_raw,
843 .write_raw = &mma8452_write_raw,
28e34278
MF		 844 .event_attrs = &mma8452_event_attribute_group,
845 .read_event_value = &mma8452_read_thresh,
846 .write_event_value = &mma8452_write_thresh,
847 .read_event_config = &mma8452_read_event_config,
848 .write_event_config = &mma8452_write_event_config,
2a17698c 849 .debugfs_reg_access = &mma8452_reg_access_dbg,
c7eeea93
PM		 850 .driver_module = THIS_MODULE,
851};
852
853static const unsigned long mma8452_scan_masks[] = {0x7, 0};
854
ae6d9ce0
MF		 855static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
856 bool state)
857{
858 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
859 struct mma8452_data *data = iio_priv(indio_dev);
860 int reg;
861
862 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
863 if (reg < 0)
864 return reg;
865
866 if (state)
867 reg |= MMA8452_INT_DRDY;
868 else
869 reg &= ~MMA8452_INT_DRDY;
870
871 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
872}
873
874static int mma8452_validate_device(struct iio_trigger *trig,
875 struct iio_dev *indio_dev)
876{
877 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
878
879 if (indio != indio_dev)
880 return -EINVAL;
881
882 return 0;
883}
884
885static const struct iio_trigger_ops mma8452_trigger_ops = {
886 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
887 .validate_device = mma8452_validate_device,
888 .owner = THIS_MODULE,
889};
890
891static int mma8452_trigger_setup(struct iio_dev *indio_dev)
892{
893 struct mma8452_data *data = iio_priv(indio_dev);
894 struct iio_trigger *trig;
895 int ret;
896
897 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
898 indio_dev->name,
899 indio_dev->id);
900 if (!trig)
901 return -ENOMEM;
902
903 trig->dev.parent = &data->client->dev;
904 trig->ops = &mma8452_trigger_ops;
905 iio_trigger_set_drvdata(trig, indio_dev);
906
907 ret = iio_trigger_register(trig);
908 if (ret)
909 return ret;
910
911 indio_dev->trig = trig;
686027fb 912
ae6d9ce0
MF		 913 return 0;
914}
915
916static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
917{
918 if (indio_dev->trig)
919 iio_trigger_unregister(indio_dev->trig);
920}
921
ecabae71
MF		 922static int mma8452_reset(struct i2c_client *client)
923{
924 int i;
925 int ret;
926
927 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
928 MMA8452_CTRL_REG2_RST);
929 if (ret < 0)
930 return ret;
931
932 for (i = 0; i < 10; i++) {
933 usleep_range(100, 200);
934 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
935 if (ret == -EIO)
936 continue; /* I2C comm reset */
937 if (ret < 0)
938 return ret;
939 if (!(ret & MMA8452_CTRL_REG2_RST))
940 return 0;
941 }
942
943 return -ETIMEDOUT;
944}
945
c3cdd6e4
MK		 946static const struct of_device_id mma8452_dt_ids[] = {
947 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
c5ea1b58 948 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
c3cdd6e4
MK		 949 { }
950};
951MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
952
c7eeea93
PM		 953static int mma8452_probe(struct i2c_client *client,
954 const struct i2c_device_id *id)
955{
956 struct mma8452_data *data;
957 struct iio_dev *indio_dev;
958 int ret;
c3cdd6e4 959 const struct of_device_id *match;
c7eeea93
PM		 960
961 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
962 if (ret < 0)
963 return ret;
c5ea1b58
MK		 964
965 if (ret != MMA8452_DEVICE_ID && ret != MMA8453_DEVICE_ID)
c7eeea93
PM		 966 return -ENODEV;
967
c3cdd6e4
MK		 968 match = of_match_device(mma8452_dt_ids, &client->dev);
969 if (!match) {
970 dev_err(&client->dev, "unknown device model\n");
971 return -ENODEV;
972 }
973
c7eeea93
PM		 974 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
975 if (!indio_dev)
976 return -ENOMEM;
977
978 data = iio_priv(indio_dev);
979 data->client = client;
980 mutex_init(&data->lock);
c3cdd6e4
MK		 981 data->chip_info = match->data;
982
983 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
984 match->compatible, data->chip_info->chip_id);
c7eeea93
PM		 985
986 i2c_set_clientdata(client, indio_dev);
987 indio_dev->info = &mma8452_info;
988 indio_dev->name = id->name;
989 indio_dev->dev.parent = &client->dev;
990 indio_dev->modes = INDIO_DIRECT_MODE;
c3cdd6e4
MK		 991 indio_dev->channels = data->chip_info->channels;
992 indio_dev->num_channels = data->chip_info->num_channels;
c7eeea93
PM		 993 indio_dev->available_scan_masks = mma8452_scan_masks;
994
ecabae71 995 ret = mma8452_reset(client);
c7eeea93
PM		 996 if (ret < 0)
997 return ret;
998
999 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1000 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
686027fb 1001 data->data_cfg);
c7eeea93
PM		 1002 if (ret < 0)
1003 return ret;
1004
28e34278
MF		 1005 /*
1006 * By default set transient threshold to max to avoid events if
1007 * enabling without configuring threshold.
1008 */
1009 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1010 MMA8452_TRANSIENT_THS_MASK);
1011 if (ret < 0)
1012 return ret;
1013
1014 if (client->irq) {
1015 /*
1016 * Although we enable the transient interrupt source once and
1017 * for all here the transient event detection itself is not
1018 * enabled until userspace asks for it by
1019 * mma8452_write_event_config()
1020 */
ae6d9ce0
MF		 1021 int supported_interrupts = MMA8452_INT_DRDY | MMA8452_INT_TRANS;
1022 int enabled_interrupts = MMA8452_INT_TRANS;
28e34278
MF		 1023
1024 /* Assume wired to INT1 pin */
1025 ret = i2c_smbus_write_byte_data(client,
1026 MMA8452_CTRL_REG5,
1027 supported_interrupts);
1028 if (ret < 0)
1029 return ret;
1030
1031 ret = i2c_smbus_write_byte_data(client,
1032 MMA8452_CTRL_REG4,
ae6d9ce0
MF		 1033 enabled_interrupts);
1034 if (ret < 0)
1035 return ret;
1036
1037 ret = mma8452_trigger_setup(indio_dev);
28e34278
MF		 1038 if (ret < 0)
1039 return ret;
1040 }
1041
ecabae71 1042 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
686027fb 1043 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
ecabae71
MF		 1044 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1045 data->ctrl_reg1);
1046 if (ret < 0)
ae6d9ce0 1047 goto trigger_cleanup;
ecabae71 1048
c7eeea93 1049 ret = iio_triggered_buffer_setup(indio_dev, NULL,
686027fb 1050 mma8452_trigger_handler, NULL);
c7eeea93 1051 if (ret < 0)
ae6d9ce0 1052 goto trigger_cleanup;
c7eeea93 1053
28e34278
MF		 1054 if (client->irq) {
1055 ret = devm_request_threaded_irq(&client->dev,
1056 client->irq,
1057 NULL, mma8452_interrupt,
1058 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1059 client->name, indio_dev);
1060 if (ret)
1061 goto buffer_cleanup;
1062 }
1063
c7eeea93
PM		 1064 ret = iio_device_register(indio_dev);
1065 if (ret < 0)
1066 goto buffer_cleanup;
28e34278 1067
c7eeea93
PM		 1068 return 0;
1069
1070buffer_cleanup:
1071 iio_triggered_buffer_cleanup(indio_dev);
ae6d9ce0
MF		 1072
1073trigger_cleanup:
1074 mma8452_trigger_cleanup(indio_dev);
1075
c7eeea93
PM		 1076 return ret;
1077}
1078
1079static int mma8452_remove(struct i2c_client *client)
1080{
1081 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1082
1083 iio_device_unregister(indio_dev);
1084 iio_triggered_buffer_cleanup(indio_dev);
ae6d9ce0 1085 mma8452_trigger_cleanup(indio_dev);
c7eeea93
PM		 1086 mma8452_standby(iio_priv(indio_dev));
1087
1088 return 0;
1089}
1090
1091#ifdef CONFIG_PM_SLEEP
1092static int mma8452_suspend(struct device *dev)
1093{
1094 return mma8452_standby(iio_priv(i2c_get_clientdata(
1095 to_i2c_client(dev))));
1096}
1097
1098static int mma8452_resume(struct device *dev)
1099{
1100 return mma8452_active(iio_priv(i2c_get_clientdata(
1101 to_i2c_client(dev))));
1102}
1103
1104static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume);
1105#define MMA8452_PM_OPS (&mma8452_pm_ops)
1106#else
1107#define MMA8452_PM_OPS NULL
1108#endif
1109
1110static const struct i2c_device_id mma8452_id[] = {
c3cdd6e4 1111 { "mma8452", mma8452 },
c5ea1b58 1112 { "mma8453", mma8453 },
c7eeea93
PM		 1113 { }
1114};
1115MODULE_DEVICE_TABLE(i2c, mma8452_id);
1116
1117static struct i2c_driver mma8452_driver = {
1118 .driver = {
1119 .name = "mma8452",
a3fb96a8 1120 .of_match_table = of_match_ptr(mma8452_dt_ids),
c7eeea93
PM		 1121 .pm = MMA8452_PM_OPS,
1122 },
1123 .probe = mma8452_probe,
1124 .remove = mma8452_remove,
1125 .id_table = mma8452_id,
1126};
1127module_i2c_driver(mma8452_driver);
1128
1129MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1130MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
1131MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)