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a84ef0d1 JE |
1 | /* |
2 | * IIO accel core driver for Freescale MMA7455L 3-axis 10-bit accelerometer | |
3 | * Copyright 2015 Joachim Eastwood <manabian@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * UNSUPPORTED hardware features: | |
10 | * - 8-bit mode with different scales | |
11 | * - INT1/INT2 interrupts | |
12 | * - Offset calibration | |
13 | * - Events | |
14 | */ | |
15 | ||
16 | #include <linux/delay.h> | |
17 | #include <linux/iio/iio.h> | |
18 | #include <linux/iio/sysfs.h> | |
19 | #include <linux/iio/buffer.h> | |
20 | #include <linux/iio/trigger.h> | |
21 | #include <linux/iio/trigger_consumer.h> | |
22 | #include <linux/iio/triggered_buffer.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/regmap.h> | |
25 | ||
26 | #include "mma7455.h" | |
27 | ||
28 | #define MMA7455_REG_XOUTL 0x00 | |
29 | #define MMA7455_REG_XOUTH 0x01 | |
30 | #define MMA7455_REG_YOUTL 0x02 | |
31 | #define MMA7455_REG_YOUTH 0x03 | |
32 | #define MMA7455_REG_ZOUTL 0x04 | |
33 | #define MMA7455_REG_ZOUTH 0x05 | |
34 | #define MMA7455_REG_STATUS 0x09 | |
35 | #define MMA7455_STATUS_DRDY BIT(0) | |
36 | #define MMA7455_REG_WHOAMI 0x0f | |
37 | #define MMA7455_WHOAMI_ID 0x55 | |
38 | #define MMA7455_REG_MCTL 0x16 | |
39 | #define MMA7455_MCTL_MODE_STANDBY 0x00 | |
40 | #define MMA7455_MCTL_MODE_MEASURE 0x01 | |
41 | #define MMA7455_REG_CTL1 0x18 | |
42 | #define MMA7455_CTL1_DFBW_MASK BIT(7) | |
43 | #define MMA7455_CTL1_DFBW_125HZ BIT(7) | |
44 | #define MMA7455_CTL1_DFBW_62_5HZ 0 | |
45 | #define MMA7455_REG_TW 0x1e | |
46 | ||
47 | /* | |
48 | * When MMA7455 is used in 10-bit it has a fullscale of -8g | |
49 | * corresponding to raw value -512. The userspace interface | |
50 | * uses m/s^2 and we declare micro units. | |
51 | * So scale factor is given by: | |
52 | * g * 8 * 1e6 / 512 = 153228.90625, with g = 9.80665 | |
53 | */ | |
54 | #define MMA7455_10BIT_SCALE 153229 | |
55 | ||
56 | struct mma7455_data { | |
57 | struct regmap *regmap; | |
a84ef0d1 JE |
58 | }; |
59 | ||
60 | static int mma7455_drdy(struct mma7455_data *mma7455) | |
61 | { | |
c455e583 | 62 | struct device *dev = regmap_get_device(mma7455->regmap); |
a84ef0d1 JE |
63 | unsigned int reg; |
64 | int tries = 3; | |
65 | int ret; | |
66 | ||
67 | while (tries-- > 0) { | |
68 | ret = regmap_read(mma7455->regmap, MMA7455_REG_STATUS, ®); | |
69 | if (ret) | |
70 | return ret; | |
71 | ||
72 | if (reg & MMA7455_STATUS_DRDY) | |
73 | return 0; | |
74 | ||
75 | msleep(20); | |
76 | } | |
77 | ||
c455e583 | 78 | dev_warn(dev, "data not ready\n"); |
a84ef0d1 JE |
79 | |
80 | return -EIO; | |
81 | } | |
82 | ||
83 | static irqreturn_t mma7455_trigger_handler(int irq, void *p) | |
84 | { | |
85 | struct iio_poll_func *pf = p; | |
86 | struct iio_dev *indio_dev = pf->indio_dev; | |
87 | struct mma7455_data *mma7455 = iio_priv(indio_dev); | |
88 | u8 buf[16]; /* 3 x 16-bit channels + padding + ts */ | |
89 | int ret; | |
90 | ||
91 | ret = mma7455_drdy(mma7455); | |
92 | if (ret) | |
93 | goto done; | |
94 | ||
95 | ret = regmap_bulk_read(mma7455->regmap, MMA7455_REG_XOUTL, buf, | |
96 | sizeof(__le16) * 3); | |
97 | if (ret) | |
98 | goto done; | |
99 | ||
100 | iio_push_to_buffers_with_timestamp(indio_dev, buf, iio_get_time_ns()); | |
101 | ||
102 | done: | |
103 | iio_trigger_notify_done(indio_dev->trig); | |
104 | ||
105 | return IRQ_HANDLED; | |
106 | } | |
107 | ||
108 | static int mma7455_read_raw(struct iio_dev *indio_dev, | |
109 | struct iio_chan_spec const *chan, | |
110 | int *val, int *val2, long mask) | |
111 | { | |
112 | struct mma7455_data *mma7455 = iio_priv(indio_dev); | |
113 | unsigned int reg; | |
114 | __le16 data; | |
115 | int ret; | |
116 | ||
117 | switch (mask) { | |
118 | case IIO_CHAN_INFO_RAW: | |
119 | if (iio_buffer_enabled(indio_dev)) | |
120 | return -EBUSY; | |
121 | ||
122 | ret = mma7455_drdy(mma7455); | |
123 | if (ret) | |
124 | return ret; | |
125 | ||
126 | ret = regmap_bulk_read(mma7455->regmap, chan->address, &data, | |
127 | sizeof(data)); | |
128 | if (ret) | |
129 | return ret; | |
130 | ||
131 | *val = sign_extend32(le16_to_cpu(data), 9); | |
132 | ||
133 | return IIO_VAL_INT; | |
134 | ||
135 | case IIO_CHAN_INFO_SCALE: | |
136 | *val = 0; | |
137 | *val2 = MMA7455_10BIT_SCALE; | |
138 | ||
139 | return IIO_VAL_INT_PLUS_MICRO; | |
140 | ||
141 | case IIO_CHAN_INFO_SAMP_FREQ: | |
142 | ret = regmap_read(mma7455->regmap, MMA7455_REG_CTL1, ®); | |
143 | if (ret) | |
144 | return ret; | |
145 | ||
146 | if (reg & MMA7455_CTL1_DFBW_MASK) | |
147 | *val = 250; | |
148 | else | |
149 | *val = 125; | |
150 | ||
151 | return IIO_VAL_INT; | |
152 | } | |
153 | ||
154 | return -EINVAL; | |
155 | } | |
156 | ||
157 | static int mma7455_write_raw(struct iio_dev *indio_dev, | |
158 | struct iio_chan_spec const *chan, | |
159 | int val, int val2, long mask) | |
160 | { | |
161 | struct mma7455_data *mma7455 = iio_priv(indio_dev); | |
162 | int i; | |
163 | ||
164 | switch (mask) { | |
165 | case IIO_CHAN_INFO_SAMP_FREQ: | |
166 | if (val == 250 && val2 == 0) | |
167 | i = MMA7455_CTL1_DFBW_125HZ; | |
168 | else if (val == 125 && val2 == 0) | |
169 | i = MMA7455_CTL1_DFBW_62_5HZ; | |
170 | else | |
171 | return -EINVAL; | |
172 | ||
173 | return regmap_update_bits(mma7455->regmap, MMA7455_REG_CTL1, | |
174 | MMA7455_CTL1_DFBW_MASK, i); | |
175 | ||
176 | case IIO_CHAN_INFO_SCALE: | |
177 | /* In 10-bit mode there is only one scale available */ | |
178 | if (val == 0 && val2 == MMA7455_10BIT_SCALE) | |
179 | return 0; | |
180 | break; | |
181 | } | |
182 | ||
183 | return -EINVAL; | |
184 | } | |
185 | ||
186 | static IIO_CONST_ATTR(sampling_frequency_available, "125 250"); | |
187 | ||
188 | static struct attribute *mma7455_attributes[] = { | |
189 | &iio_const_attr_sampling_frequency_available.dev_attr.attr, | |
190 | NULL | |
191 | }; | |
192 | ||
193 | static const struct attribute_group mma7455_group = { | |
194 | .attrs = mma7455_attributes, | |
195 | }; | |
196 | ||
197 | static const struct iio_info mma7455_info = { | |
198 | .attrs = &mma7455_group, | |
199 | .read_raw = mma7455_read_raw, | |
200 | .write_raw = mma7455_write_raw, | |
201 | .driver_module = THIS_MODULE, | |
202 | }; | |
203 | ||
204 | #define MMA7455_CHANNEL(axis, idx) { \ | |
205 | .type = IIO_ACCEL, \ | |
206 | .modified = 1, \ | |
207 | .address = MMA7455_REG_##axis##OUTL,\ | |
208 | .channel2 = IIO_MOD_##axis, \ | |
209 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ | |
210 | .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ | |
211 | BIT(IIO_CHAN_INFO_SCALE), \ | |
212 | .scan_index = idx, \ | |
213 | .scan_type = { \ | |
214 | .sign = 's', \ | |
215 | .realbits = 10, \ | |
216 | .storagebits = 16, \ | |
217 | .endianness = IIO_LE, \ | |
218 | }, \ | |
219 | } | |
220 | ||
221 | static const struct iio_chan_spec mma7455_channels[] = { | |
222 | MMA7455_CHANNEL(X, 0), | |
223 | MMA7455_CHANNEL(Y, 1), | |
224 | MMA7455_CHANNEL(Z, 2), | |
225 | IIO_CHAN_SOFT_TIMESTAMP(3), | |
226 | }; | |
227 | ||
228 | static const unsigned long mma7455_scan_masks[] = {0x7, 0}; | |
229 | ||
230 | const struct regmap_config mma7455_core_regmap = { | |
231 | .reg_bits = 8, | |
232 | .val_bits = 8, | |
233 | .max_register = MMA7455_REG_TW, | |
234 | }; | |
235 | EXPORT_SYMBOL_GPL(mma7455_core_regmap); | |
236 | ||
237 | int mma7455_core_probe(struct device *dev, struct regmap *regmap, | |
238 | const char *name) | |
239 | { | |
240 | struct mma7455_data *mma7455; | |
241 | struct iio_dev *indio_dev; | |
242 | unsigned int reg; | |
243 | int ret; | |
244 | ||
245 | ret = regmap_read(regmap, MMA7455_REG_WHOAMI, ®); | |
246 | if (ret) { | |
247 | dev_err(dev, "unable to read reg\n"); | |
248 | return ret; | |
249 | } | |
250 | ||
251 | if (reg != MMA7455_WHOAMI_ID) { | |
252 | dev_err(dev, "device id mismatch\n"); | |
253 | return -ENODEV; | |
254 | } | |
255 | ||
256 | indio_dev = devm_iio_device_alloc(dev, sizeof(*mma7455)); | |
257 | if (!indio_dev) | |
258 | return -ENOMEM; | |
259 | ||
260 | dev_set_drvdata(dev, indio_dev); | |
261 | mma7455 = iio_priv(indio_dev); | |
262 | mma7455->regmap = regmap; | |
a84ef0d1 JE |
263 | |
264 | indio_dev->info = &mma7455_info; | |
265 | indio_dev->name = name; | |
266 | indio_dev->dev.parent = dev; | |
267 | indio_dev->modes = INDIO_DIRECT_MODE; | |
268 | indio_dev->channels = mma7455_channels; | |
269 | indio_dev->num_channels = ARRAY_SIZE(mma7455_channels); | |
270 | indio_dev->available_scan_masks = mma7455_scan_masks; | |
271 | ||
272 | regmap_write(mma7455->regmap, MMA7455_REG_MCTL, | |
273 | MMA7455_MCTL_MODE_MEASURE); | |
274 | ||
275 | ret = iio_triggered_buffer_setup(indio_dev, NULL, | |
276 | mma7455_trigger_handler, NULL); | |
277 | if (ret) { | |
278 | dev_err(dev, "unable to setup triggered buffer\n"); | |
279 | return ret; | |
280 | } | |
281 | ||
282 | ret = iio_device_register(indio_dev); | |
283 | if (ret) { | |
284 | dev_err(dev, "unable to register device\n"); | |
285 | iio_triggered_buffer_cleanup(indio_dev); | |
286 | return ret; | |
287 | } | |
288 | ||
289 | return 0; | |
290 | } | |
291 | EXPORT_SYMBOL_GPL(mma7455_core_probe); | |
292 | ||
293 | int mma7455_core_remove(struct device *dev) | |
294 | { | |
295 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
296 | struct mma7455_data *mma7455 = iio_priv(indio_dev); | |
297 | ||
298 | iio_device_unregister(indio_dev); | |
299 | iio_triggered_buffer_cleanup(indio_dev); | |
300 | ||
301 | regmap_write(mma7455->regmap, MMA7455_REG_MCTL, | |
302 | MMA7455_MCTL_MODE_STANDBY); | |
303 | ||
304 | return 0; | |
305 | } | |
306 | EXPORT_SYMBOL_GPL(mma7455_core_remove); | |
307 | ||
308 | MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>"); | |
309 | MODULE_DESCRIPTION("Freescale MMA7455L core accelerometer driver"); | |
310 | MODULE_LICENSE("GPL v2"); |