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1da177e4 LT |
1 | /* |
2 | * ohci1394.c - driver for OHCI 1394 boards | |
3 | * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au> | |
4 | * Gord Peters <GordPeters@smarttech.com> | |
5 | * 2001 Ben Collins <bcollins@debian.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software Foundation, | |
19 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * Things known to be working: | |
24 | * . Async Request Transmit | |
25 | * . Async Response Receive | |
26 | * . Async Request Receive | |
27 | * . Async Response Transmit | |
28 | * . Iso Receive | |
29 | * . DMA mmap for iso receive | |
30 | * . Config ROM generation | |
31 | * | |
32 | * Things implemented, but still in test phase: | |
33 | * . Iso Transmit | |
34 | * . Async Stream Packets Transmit (Receive done via Iso interface) | |
35 | * | |
36 | * Things not implemented: | |
37 | * . DMA error recovery | |
38 | * | |
39 | * Known bugs: | |
40 | * . devctl BUS_RESET arg confusion (reset type or root holdoff?) | |
41 | * added LONG_RESET_ROOT and SHORT_RESET_ROOT for root holdoff --kk | |
42 | */ | |
43 | ||
44 | /* | |
45 | * Acknowledgments: | |
46 | * | |
47 | * Adam J Richter <adam@yggdrasil.com> | |
48 | * . Use of pci_class to find device | |
49 | * | |
50 | * Emilie Chung <emilie.chung@axis.com> | |
51 | * . Tip on Async Request Filter | |
52 | * | |
53 | * Pascal Drolet <pascal.drolet@informission.ca> | |
54 | * . Various tips for optimization and functionnalities | |
55 | * | |
56 | * Robert Ficklin <rficklin@westengineering.com> | |
57 | * . Loop in irq_handler | |
58 | * | |
59 | * James Goodwin <jamesg@Filanet.com> | |
60 | * . Various tips on initialization, self-id reception, etc. | |
61 | * | |
62 | * Albrecht Dress <ad@mpifr-bonn.mpg.de> | |
63 | * . Apple PowerBook detection | |
64 | * | |
65 | * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de> | |
66 | * . Reset the board properly before leaving + misc cleanups | |
67 | * | |
68 | * Leon van Stuivenberg <leonvs@iae.nl> | |
69 | * . Bug fixes | |
70 | * | |
71 | * Ben Collins <bcollins@debian.org> | |
72 | * . Working big-endian support | |
73 | * . Updated to 2.4.x module scheme (PCI aswell) | |
74 | * . Config ROM generation | |
75 | * | |
76 | * Manfred Weihs <weihs@ict.tuwien.ac.at> | |
77 | * . Reworked code for initiating bus resets | |
78 | * (long, short, with or without hold-off) | |
79 | * | |
80 | * Nandu Santhi <contactnandu@users.sourceforge.net> | |
81 | * . Added support for nVidia nForce2 onboard Firewire chipset | |
82 | * | |
83 | */ | |
84 | ||
1da177e4 LT |
85 | #include <linux/kernel.h> |
86 | #include <linux/list.h> | |
87 | #include <linux/slab.h> | |
88 | #include <linux/interrupt.h> | |
89 | #include <linux/wait.h> | |
90 | #include <linux/errno.h> | |
91 | #include <linux/module.h> | |
92 | #include <linux/moduleparam.h> | |
93 | #include <linux/pci.h> | |
94 | #include <linux/fs.h> | |
95 | #include <linux/poll.h> | |
96 | #include <asm/byteorder.h> | |
97 | #include <asm/atomic.h> | |
98 | #include <asm/uaccess.h> | |
99 | #include <linux/delay.h> | |
100 | #include <linux/spinlock.h> | |
101 | ||
102 | #include <asm/pgtable.h> | |
103 | #include <asm/page.h> | |
104 | #include <asm/irq.h> | |
105 | #include <linux/sched.h> | |
106 | #include <linux/types.h> | |
107 | #include <linux/vmalloc.h> | |
108 | #include <linux/init.h> | |
109 | ||
110 | #ifdef CONFIG_PPC_PMAC | |
111 | #include <asm/machdep.h> | |
112 | #include <asm/pmac_feature.h> | |
113 | #include <asm/prom.h> | |
114 | #include <asm/pci-bridge.h> | |
115 | #endif | |
116 | ||
117 | #include "csr1212.h" | |
118 | #include "ieee1394.h" | |
119 | #include "ieee1394_types.h" | |
120 | #include "hosts.h" | |
121 | #include "dma.h" | |
122 | #include "iso.h" | |
123 | #include "ieee1394_core.h" | |
124 | #include "highlevel.h" | |
125 | #include "ohci1394.h" | |
126 | ||
127 | #ifdef CONFIG_IEEE1394_VERBOSEDEBUG | |
128 | #define OHCI1394_DEBUG | |
129 | #endif | |
130 | ||
131 | #ifdef DBGMSG | |
132 | #undef DBGMSG | |
133 | #endif | |
134 | ||
135 | #ifdef OHCI1394_DEBUG | |
136 | #define DBGMSG(fmt, args...) \ | |
137 | printk(KERN_INFO "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args) | |
138 | #else | |
611aa19f | 139 | #define DBGMSG(fmt, args...) do {} while (0) |
1da177e4 LT |
140 | #endif |
141 | ||
142 | #ifdef CONFIG_IEEE1394_OHCI_DMA_DEBUG | |
143 | #define OHCI_DMA_ALLOC(fmt, args...) \ | |
144 | HPSB_ERR("%s(%s)alloc(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \ | |
145 | ++global_outstanding_dmas, ## args) | |
146 | #define OHCI_DMA_FREE(fmt, args...) \ | |
147 | HPSB_ERR("%s(%s)free(%d): "fmt, OHCI1394_DRIVER_NAME, __FUNCTION__, \ | |
148 | --global_outstanding_dmas, ## args) | |
149 | static int global_outstanding_dmas = 0; | |
150 | #else | |
611aa19f SR |
151 | #define OHCI_DMA_ALLOC(fmt, args...) do {} while (0) |
152 | #define OHCI_DMA_FREE(fmt, args...) do {} while (0) | |
1da177e4 LT |
153 | #endif |
154 | ||
155 | /* print general (card independent) information */ | |
156 | #define PRINT_G(level, fmt, args...) \ | |
157 | printk(level "%s: " fmt "\n" , OHCI1394_DRIVER_NAME , ## args) | |
158 | ||
159 | /* print card specific information */ | |
160 | #define PRINT(level, fmt, args...) \ | |
161 | printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args) | |
162 | ||
1da177e4 LT |
163 | /* Module Parameters */ |
164 | static int phys_dma = 1; | |
fa9b7399 | 165 | module_param(phys_dma, int, 0444); |
1da177e4 LT |
166 | MODULE_PARM_DESC(phys_dma, "Enable physical dma (default = 1)."); |
167 | ||
168 | static void dma_trm_tasklet(unsigned long data); | |
169 | static void dma_trm_reset(struct dma_trm_ctx *d); | |
170 | ||
171 | static int alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d, | |
172 | enum context_type type, int ctx, int num_desc, | |
173 | int buf_size, int split_buf_size, int context_base); | |
174 | static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d); | |
175 | static void free_dma_rcv_ctx(struct dma_rcv_ctx *d); | |
176 | ||
177 | static int alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d, | |
178 | enum context_type type, int ctx, int num_desc, | |
179 | int context_base); | |
180 | ||
181 | static void ohci1394_pci_remove(struct pci_dev *pdev); | |
182 | ||
183 | #ifndef __LITTLE_ENDIAN | |
9531f13a | 184 | const static size_t hdr_sizes[] = { |
1da177e4 LT |
185 | 3, /* TCODE_WRITEQ */ |
186 | 4, /* TCODE_WRITEB */ | |
187 | 3, /* TCODE_WRITE_RESPONSE */ | |
9531f13a | 188 | 0, /* reserved */ |
1da177e4 LT |
189 | 3, /* TCODE_READQ */ |
190 | 4, /* TCODE_READB */ | |
191 | 3, /* TCODE_READQ_RESPONSE */ | |
192 | 4, /* TCODE_READB_RESPONSE */ | |
9531f13a | 193 | 1, /* TCODE_CYCLE_START */ |
1da177e4 LT |
194 | 4, /* TCODE_LOCK_REQUEST */ |
195 | 2, /* TCODE_ISO_DATA */ | |
196 | 4, /* TCODE_LOCK_RESPONSE */ | |
9531f13a | 197 | /* rest is reserved or link-internal */ |
1da177e4 LT |
198 | }; |
199 | ||
9531f13a | 200 | static inline void header_le32_to_cpu(quadlet_t *data, unsigned char tcode) |
1da177e4 | 201 | { |
9531f13a | 202 | size_t size; |
1da177e4 | 203 | |
9531f13a | 204 | if (unlikely(tcode >= ARRAY_SIZE(hdr_sizes))) |
1da177e4 LT |
205 | return; |
206 | ||
9531f13a | 207 | size = hdr_sizes[tcode]; |
1da177e4 | 208 | while (size--) |
9531f13a | 209 | data[size] = le32_to_cpu(data[size]); |
1da177e4 LT |
210 | } |
211 | #else | |
9531f13a | 212 | #define header_le32_to_cpu(w,x) do {} while (0) |
1da177e4 LT |
213 | #endif /* !LITTLE_ENDIAN */ |
214 | ||
215 | /*********************************** | |
216 | * IEEE-1394 functionality section * | |
217 | ***********************************/ | |
218 | ||
219 | static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr) | |
220 | { | |
221 | int i; | |
222 | unsigned long flags; | |
223 | quadlet_t r; | |
224 | ||
225 | spin_lock_irqsave (&ohci->phy_reg_lock, flags); | |
226 | ||
227 | reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000); | |
228 | ||
229 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
230 | if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000) | |
231 | break; | |
232 | ||
233 | mdelay(1); | |
234 | } | |
235 | ||
236 | r = reg_read(ohci, OHCI1394_PhyControl); | |
237 | ||
238 | if (i >= OHCI_LOOP_COUNT) | |
239 | PRINT (KERN_ERR, "Get PHY Reg timeout [0x%08x/0x%08x/%d]", | |
240 | r, r & 0x80000000, i); | |
241 | ||
242 | spin_unlock_irqrestore (&ohci->phy_reg_lock, flags); | |
243 | ||
244 | return (r & 0x00ff0000) >> 16; | |
245 | } | |
246 | ||
247 | static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data) | |
248 | { | |
249 | int i; | |
250 | unsigned long flags; | |
251 | u32 r = 0; | |
252 | ||
253 | spin_lock_irqsave (&ohci->phy_reg_lock, flags); | |
254 | ||
255 | reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000); | |
256 | ||
257 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
258 | r = reg_read(ohci, OHCI1394_PhyControl); | |
259 | if (!(r & 0x00004000)) | |
260 | break; | |
261 | ||
262 | mdelay(1); | |
263 | } | |
264 | ||
265 | if (i == OHCI_LOOP_COUNT) | |
266 | PRINT (KERN_ERR, "Set PHY Reg timeout [0x%08x/0x%08x/%d]", | |
267 | r, r & 0x00004000, i); | |
268 | ||
269 | spin_unlock_irqrestore (&ohci->phy_reg_lock, flags); | |
270 | ||
271 | return; | |
272 | } | |
273 | ||
274 | /* Or's our value into the current value */ | |
275 | static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data) | |
276 | { | |
277 | u8 old; | |
278 | ||
279 | old = get_phy_reg (ohci, addr); | |
280 | old |= data; | |
281 | set_phy_reg (ohci, addr, old); | |
282 | ||
283 | return; | |
284 | } | |
285 | ||
286 | static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host, | |
287 | int phyid, int isroot) | |
288 | { | |
289 | quadlet_t *q = ohci->selfid_buf_cpu; | |
290 | quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount); | |
291 | size_t size; | |
292 | quadlet_t q0, q1; | |
293 | ||
294 | /* Check status of self-id reception */ | |
295 | ||
296 | if (ohci->selfid_swap) | |
297 | q0 = le32_to_cpu(q[0]); | |
298 | else | |
299 | q0 = q[0]; | |
300 | ||
301 | if ((self_id_count & 0x80000000) || | |
302 | ((self_id_count & 0x00FF0000) != (q0 & 0x00FF0000))) { | |
303 | PRINT(KERN_ERR, | |
304 | "Error in reception of SelfID packets [0x%08x/0x%08x] (count: %d)", | |
305 | self_id_count, q0, ohci->self_id_errors); | |
306 | ||
307 | /* Tip by James Goodwin <jamesg@Filanet.com>: | |
308 | * We had an error, generate another bus reset in response. */ | |
309 | if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) { | |
310 | set_phy_reg_mask (ohci, 1, 0x40); | |
311 | ohci->self_id_errors++; | |
312 | } else { | |
313 | PRINT(KERN_ERR, | |
314 | "Too many errors on SelfID error reception, giving up!"); | |
315 | } | |
316 | return; | |
317 | } | |
318 | ||
319 | /* SelfID Ok, reset error counter. */ | |
320 | ohci->self_id_errors = 0; | |
321 | ||
322 | size = ((self_id_count & 0x00001FFC) >> 2) - 1; | |
323 | q++; | |
324 | ||
325 | while (size > 0) { | |
326 | if (ohci->selfid_swap) { | |
327 | q0 = le32_to_cpu(q[0]); | |
328 | q1 = le32_to_cpu(q[1]); | |
329 | } else { | |
330 | q0 = q[0]; | |
331 | q1 = q[1]; | |
332 | } | |
333 | ||
334 | if (q0 == ~q1) { | |
335 | DBGMSG ("SelfID packet 0x%x received", q0); | |
336 | hpsb_selfid_received(host, cpu_to_be32(q0)); | |
337 | if (((q0 & 0x3f000000) >> 24) == phyid) | |
338 | DBGMSG ("SelfID for this node is 0x%08x", q0); | |
339 | } else { | |
340 | PRINT(KERN_ERR, | |
341 | "SelfID is inconsistent [0x%08x/0x%08x]", q0, q1); | |
342 | } | |
343 | q += 2; | |
344 | size -= 2; | |
345 | } | |
346 | ||
347 | DBGMSG("SelfID complete"); | |
348 | ||
349 | return; | |
350 | } | |
351 | ||
352 | static void ohci_soft_reset(struct ti_ohci *ohci) { | |
353 | int i; | |
354 | ||
355 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
356 | ||
357 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
358 | if (!(reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_softReset)) | |
359 | break; | |
360 | mdelay(1); | |
361 | } | |
362 | DBGMSG ("Soft reset finished"); | |
363 | } | |
364 | ||
365 | ||
366 | /* Generate the dma receive prgs and start the context */ | |
367 | static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d, int generate_irq) | |
368 | { | |
369 | struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci); | |
370 | int i; | |
371 | ||
372 | ohci1394_stop_context(ohci, d->ctrlClear, NULL); | |
373 | ||
374 | for (i=0; i<d->num_desc; i++) { | |
375 | u32 c; | |
376 | ||
377 | c = DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | DMA_CTL_BRANCH; | |
378 | if (generate_irq) | |
379 | c |= DMA_CTL_IRQ; | |
380 | ||
381 | d->prg_cpu[i]->control = cpu_to_le32(c | d->buf_size); | |
382 | ||
383 | /* End of descriptor list? */ | |
384 | if (i + 1 < d->num_desc) { | |
385 | d->prg_cpu[i]->branchAddress = | |
386 | cpu_to_le32((d->prg_bus[i+1] & 0xfffffff0) | 0x1); | |
387 | } else { | |
388 | d->prg_cpu[i]->branchAddress = | |
389 | cpu_to_le32((d->prg_bus[0] & 0xfffffff0)); | |
390 | } | |
391 | ||
392 | d->prg_cpu[i]->address = cpu_to_le32(d->buf_bus[i]); | |
393 | d->prg_cpu[i]->status = cpu_to_le32(d->buf_size); | |
394 | } | |
395 | ||
396 | d->buf_ind = 0; | |
397 | d->buf_offset = 0; | |
398 | ||
399 | if (d->type == DMA_CTX_ISO) { | |
400 | /* Clear contextControl */ | |
401 | reg_write(ohci, d->ctrlClear, 0xffffffff); | |
402 | ||
403 | /* Set bufferFill, isochHeader, multichannel for IR context */ | |
404 | reg_write(ohci, d->ctrlSet, 0xd0000000); | |
405 | ||
406 | /* Set the context match register to match on all tags */ | |
407 | reg_write(ohci, d->ctxtMatch, 0xf0000000); | |
408 | ||
409 | /* Clear the multi channel mask high and low registers */ | |
410 | reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff); | |
411 | reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff); | |
412 | ||
413 | /* Set up isoRecvIntMask to generate interrupts */ | |
414 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << d->ctx); | |
415 | } | |
416 | ||
417 | /* Tell the controller where the first AR program is */ | |
418 | reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1); | |
419 | ||
420 | /* Run context */ | |
421 | reg_write(ohci, d->ctrlSet, 0x00008000); | |
422 | ||
423 | DBGMSG("Receive DMA ctx=%d initialized", d->ctx); | |
424 | } | |
425 | ||
426 | /* Initialize the dma transmit context */ | |
427 | static void initialize_dma_trm_ctx(struct dma_trm_ctx *d) | |
428 | { | |
429 | struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci); | |
430 | ||
431 | /* Stop the context */ | |
432 | ohci1394_stop_context(ohci, d->ctrlClear, NULL); | |
433 | ||
434 | d->prg_ind = 0; | |
435 | d->sent_ind = 0; | |
436 | d->free_prgs = d->num_desc; | |
437 | d->branchAddrPtr = NULL; | |
438 | INIT_LIST_HEAD(&d->fifo_list); | |
439 | INIT_LIST_HEAD(&d->pending_list); | |
440 | ||
441 | if (d->type == DMA_CTX_ISO) { | |
442 | /* enable interrupts */ | |
443 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << d->ctx); | |
444 | } | |
445 | ||
446 | DBGMSG("Transmit DMA ctx=%d initialized", d->ctx); | |
447 | } | |
448 | ||
449 | /* Count the number of available iso contexts */ | |
450 | static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg) | |
451 | { | |
452 | int i,ctx=0; | |
453 | u32 tmp; | |
454 | ||
455 | reg_write(ohci, reg, 0xffffffff); | |
456 | tmp = reg_read(ohci, reg); | |
457 | ||
458 | DBGMSG("Iso contexts reg: %08x implemented: %08x", reg, tmp); | |
459 | ||
460 | /* Count the number of contexts */ | |
461 | for (i=0; i<32; i++) { | |
462 | if (tmp & 1) ctx++; | |
463 | tmp >>= 1; | |
464 | } | |
465 | return ctx; | |
466 | } | |
467 | ||
468 | /* Global initialization */ | |
469 | static void ohci_initialize(struct ti_ohci *ohci) | |
470 | { | |
471 | char irq_buf[16]; | |
472 | quadlet_t buf; | |
473 | int num_ports, i; | |
474 | ||
475 | spin_lock_init(&ohci->phy_reg_lock); | |
1da177e4 LT |
476 | |
477 | /* Put some defaults to these undefined bus options */ | |
478 | buf = reg_read(ohci, OHCI1394_BusOptions); | |
479 | buf |= 0x60000000; /* Enable CMC and ISC */ | |
1934b8b6 BC |
480 | if (hpsb_disable_irm) |
481 | buf &= ~0x80000000; | |
482 | else | |
1da177e4 LT |
483 | buf |= 0x80000000; /* Enable IRMC */ |
484 | buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */ | |
485 | buf &= ~0x18000000; /* Disable PMC and BMC */ | |
486 | reg_write(ohci, OHCI1394_BusOptions, buf); | |
487 | ||
488 | /* Set the bus number */ | |
489 | reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0); | |
490 | ||
491 | /* Enable posted writes */ | |
492 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable); | |
493 | ||
494 | /* Clear link control register */ | |
495 | reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); | |
496 | ||
497 | /* Enable cycle timer and cycle master and set the IRM | |
498 | * contender bit in our self ID packets if appropriate. */ | |
499 | reg_write(ohci, OHCI1394_LinkControlSet, | |
500 | OHCI1394_LinkControl_CycleTimerEnable | | |
501 | OHCI1394_LinkControl_CycleMaster); | |
1934b8b6 BC |
502 | i = get_phy_reg(ohci, 4) | PHY_04_LCTRL; |
503 | if (hpsb_disable_irm) | |
504 | i &= ~PHY_04_CONTENDER; | |
505 | else | |
506 | i |= PHY_04_CONTENDER; | |
507 | set_phy_reg(ohci, 4, i); | |
1da177e4 LT |
508 | |
509 | /* Set up self-id dma buffer */ | |
510 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus); | |
511 | ||
512 | /* enable self-id and phys */ | |
513 | reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID | | |
514 | OHCI1394_LinkControl_RcvPhyPkt); | |
515 | ||
516 | /* Set the Config ROM mapping register */ | |
517 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus); | |
518 | ||
519 | /* Now get our max packet size */ | |
520 | ohci->max_packet_size = | |
521 | 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1); | |
522 | ||
523 | /* Don't accept phy packets into AR request context */ | |
524 | reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400); | |
525 | ||
526 | /* Clear the interrupt mask */ | |
527 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff); | |
528 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff); | |
529 | ||
530 | /* Clear the interrupt mask */ | |
531 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff); | |
532 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff); | |
533 | ||
534 | /* Initialize AR dma */ | |
535 | initialize_dma_rcv_ctx(&ohci->ar_req_context, 0); | |
536 | initialize_dma_rcv_ctx(&ohci->ar_resp_context, 0); | |
537 | ||
538 | /* Initialize AT dma */ | |
539 | initialize_dma_trm_ctx(&ohci->at_req_context); | |
540 | initialize_dma_trm_ctx(&ohci->at_resp_context); | |
541 | ||
e4ec0f23 | 542 | /* Initialize IR Legacy DMA channel mask */ |
1da177e4 | 543 | ohci->ir_legacy_channels = 0; |
1da177e4 | 544 | |
180a4304 SR |
545 | /* Accept AR requests from all nodes */ |
546 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
547 | ||
548 | /* Set the address range of the physical response unit. | |
549 | * Most controllers do not implement it as a writable register though. | |
550 | * They will keep a hardwired offset of 0x00010000 and show 0x0 as | |
551 | * register content. | |
552 | * To actually enable physical responses is the job of our interrupt | |
553 | * handler which programs the physical request filter. */ | |
4611ed38 BC |
554 | reg_write(ohci, OHCI1394_PhyUpperBound, |
555 | OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED >> 16); | |
180a4304 SR |
556 | |
557 | DBGMSG("physUpperBoundOffset=%08x", | |
558 | reg_read(ohci, OHCI1394_PhyUpperBound)); | |
1da177e4 LT |
559 | |
560 | /* Specify AT retries */ | |
561 | reg_write(ohci, OHCI1394_ATRetries, | |
562 | OHCI1394_MAX_AT_REQ_RETRIES | | |
563 | (OHCI1394_MAX_AT_RESP_RETRIES<<4) | | |
564 | (OHCI1394_MAX_PHYS_RESP_RETRIES<<8)); | |
565 | ||
566 | /* We don't want hardware swapping */ | |
567 | reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap); | |
568 | ||
569 | /* Enable interrupts */ | |
570 | reg_write(ohci, OHCI1394_IntMaskSet, | |
571 | OHCI1394_unrecoverableError | | |
572 | OHCI1394_masterIntEnable | | |
573 | OHCI1394_busReset | | |
574 | OHCI1394_selfIDComplete | | |
575 | OHCI1394_RSPkt | | |
576 | OHCI1394_RQPkt | | |
577 | OHCI1394_respTxComplete | | |
578 | OHCI1394_reqTxComplete | | |
579 | OHCI1394_isochRx | | |
580 | OHCI1394_isochTx | | |
e2f8165d | 581 | OHCI1394_postedWriteErr | |
57fdb58f | 582 | OHCI1394_cycleTooLong | |
1da177e4 LT |
583 | OHCI1394_cycleInconsistent); |
584 | ||
585 | /* Enable link */ | |
586 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable); | |
587 | ||
588 | buf = reg_read(ohci, OHCI1394_Version); | |
1da177e4 | 589 | sprintf (irq_buf, "%d", ohci->dev->irq); |
1da177e4 | 590 | PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%s] " |
e29419ff | 591 | "MMIO=[%llx-%llx] Max Packet=[%d] IR/IT contexts=[%d/%d]", |
1da177e4 LT |
592 | ((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10), |
593 | ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), irq_buf, | |
e29419ff GKH |
594 | (unsigned long long)pci_resource_start(ohci->dev, 0), |
595 | (unsigned long long)pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1, | |
209171a1 SR |
596 | ohci->max_packet_size, |
597 | ohci->nb_iso_rcv_ctx, ohci->nb_iso_xmit_ctx); | |
1da177e4 LT |
598 | |
599 | /* Check all of our ports to make sure that if anything is | |
600 | * connected, we enable that port. */ | |
601 | num_ports = get_phy_reg(ohci, 2) & 0xf; | |
602 | for (i = 0; i < num_ports; i++) { | |
603 | unsigned int status; | |
604 | ||
605 | set_phy_reg(ohci, 7, i); | |
606 | status = get_phy_reg(ohci, 8); | |
607 | ||
608 | if (status & 0x20) | |
609 | set_phy_reg(ohci, 8, status & ~1); | |
610 | } | |
611 | ||
612 | /* Serial EEPROM Sanity check. */ | |
613 | if ((ohci->max_packet_size < 512) || | |
614 | (ohci->max_packet_size > 4096)) { | |
615 | /* Serial EEPROM contents are suspect, set a sane max packet | |
616 | * size and print the raw contents for bug reports if verbose | |
617 | * debug is enabled. */ | |
618 | #ifdef CONFIG_IEEE1394_VERBOSEDEBUG | |
619 | int i; | |
620 | #endif | |
621 | ||
622 | PRINT(KERN_DEBUG, "Serial EEPROM has suspicious values, " | |
623 | "attempting to setting max_packet_size to 512 bytes"); | |
624 | reg_write(ohci, OHCI1394_BusOptions, | |
625 | (reg_read(ohci, OHCI1394_BusOptions) & 0xf007) | 0x8002); | |
626 | ohci->max_packet_size = 512; | |
627 | #ifdef CONFIG_IEEE1394_VERBOSEDEBUG | |
628 | PRINT(KERN_DEBUG, " EEPROM Present: %d", | |
629 | (reg_read(ohci, OHCI1394_Version) >> 24) & 0x1); | |
630 | reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000); | |
631 | ||
632 | for (i = 0; | |
633 | ((i < 1000) && | |
634 | (reg_read(ohci, OHCI1394_GUID_ROM) & 0x80000000)); i++) | |
635 | udelay(10); | |
636 | ||
637 | for (i = 0; i < 0x20; i++) { | |
638 | reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000); | |
639 | PRINT(KERN_DEBUG, " EEPROM %02x: %02x", i, | |
640 | (reg_read(ohci, OHCI1394_GUID_ROM) >> 16) & 0xff); | |
641 | } | |
642 | #endif | |
643 | } | |
644 | } | |
645 | ||
646 | /* | |
647 | * Insert a packet in the DMA fifo and generate the DMA prg | |
648 | * FIXME: rewrite the program in order to accept packets crossing | |
649 | * page boundaries. | |
650 | * check also that a single dma descriptor doesn't cross a | |
651 | * page boundary. | |
652 | */ | |
653 | static void insert_packet(struct ti_ohci *ohci, | |
654 | struct dma_trm_ctx *d, struct hpsb_packet *packet) | |
655 | { | |
656 | u32 cycleTimer; | |
657 | int idx = d->prg_ind; | |
658 | ||
659 | DBGMSG("Inserting packet for node " NODE_BUS_FMT | |
660 | ", tlabel=%d, tcode=0x%x, speed=%d", | |
661 | NODE_BUS_ARGS(ohci->host, packet->node_id), packet->tlabel, | |
662 | packet->tcode, packet->speed_code); | |
663 | ||
664 | d->prg_cpu[idx]->begin.address = 0; | |
665 | d->prg_cpu[idx]->begin.branchAddress = 0; | |
666 | ||
667 | if (d->type == DMA_CTX_ASYNC_RESP) { | |
668 | /* | |
669 | * For response packets, we need to put a timeout value in | |
670 | * the 16 lower bits of the status... let's try 1 sec timeout | |
671 | */ | |
672 | cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
673 | d->prg_cpu[idx]->begin.status = cpu_to_le32( | |
674 | (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) | | |
675 | ((cycleTimer&0x01fff000)>>12)); | |
676 | ||
677 | DBGMSG("cycleTimer: %08x timeStamp: %08x", | |
678 | cycleTimer, d->prg_cpu[idx]->begin.status); | |
679 | } else | |
680 | d->prg_cpu[idx]->begin.status = 0; | |
681 | ||
682 | if ( (packet->type == hpsb_async) || (packet->type == hpsb_raw) ) { | |
683 | ||
684 | if (packet->type == hpsb_raw) { | |
685 | d->prg_cpu[idx]->data[0] = cpu_to_le32(OHCI1394_TCODE_PHY<<4); | |
686 | d->prg_cpu[idx]->data[1] = cpu_to_le32(packet->header[0]); | |
687 | d->prg_cpu[idx]->data[2] = cpu_to_le32(packet->header[1]); | |
688 | } else { | |
689 | d->prg_cpu[idx]->data[0] = packet->speed_code<<16 | | |
690 | (packet->header[0] & 0xFFFF); | |
691 | ||
692 | if (packet->tcode == TCODE_ISO_DATA) { | |
693 | /* Sending an async stream packet */ | |
694 | d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000; | |
695 | } else { | |
696 | /* Sending a normal async request or response */ | |
697 | d->prg_cpu[idx]->data[1] = | |
698 | (packet->header[1] & 0xFFFF) | | |
699 | (packet->header[0] & 0xFFFF0000); | |
700 | d->prg_cpu[idx]->data[2] = packet->header[2]; | |
701 | d->prg_cpu[idx]->data[3] = packet->header[3]; | |
702 | } | |
9531f13a | 703 | header_le32_to_cpu(d->prg_cpu[idx]->data, packet->tcode); |
1da177e4 LT |
704 | } |
705 | ||
706 | if (packet->data_size) { /* block transmit */ | |
707 | if (packet->tcode == TCODE_STREAM_DATA){ | |
708 | d->prg_cpu[idx]->begin.control = | |
709 | cpu_to_le32(DMA_CTL_OUTPUT_MORE | | |
710 | DMA_CTL_IMMEDIATE | 0x8); | |
711 | } else { | |
712 | d->prg_cpu[idx]->begin.control = | |
713 | cpu_to_le32(DMA_CTL_OUTPUT_MORE | | |
714 | DMA_CTL_IMMEDIATE | 0x10); | |
715 | } | |
716 | d->prg_cpu[idx]->end.control = | |
717 | cpu_to_le32(DMA_CTL_OUTPUT_LAST | | |
718 | DMA_CTL_IRQ | | |
719 | DMA_CTL_BRANCH | | |
720 | packet->data_size); | |
721 | /* | |
722 | * Check that the packet data buffer | |
723 | * does not cross a page boundary. | |
724 | * | |
725 | * XXX Fix this some day. eth1394 seems to trigger | |
726 | * it, but ignoring it doesn't seem to cause a | |
727 | * problem. | |
728 | */ | |
729 | #if 0 | |
730 | if (cross_bound((unsigned long)packet->data, | |
731 | packet->data_size)>0) { | |
732 | /* FIXME: do something about it */ | |
733 | PRINT(KERN_ERR, | |
734 | "%s: packet data addr: %p size %Zd bytes " | |
735 | "cross page boundary", __FUNCTION__, | |
736 | packet->data, packet->data_size); | |
737 | } | |
738 | #endif | |
739 | d->prg_cpu[idx]->end.address = cpu_to_le32( | |
740 | pci_map_single(ohci->dev, packet->data, | |
741 | packet->data_size, | |
742 | PCI_DMA_TODEVICE)); | |
743 | OHCI_DMA_ALLOC("single, block transmit packet"); | |
744 | ||
745 | d->prg_cpu[idx]->end.branchAddress = 0; | |
746 | d->prg_cpu[idx]->end.status = 0; | |
747 | if (d->branchAddrPtr) | |
748 | *(d->branchAddrPtr) = | |
749 | cpu_to_le32(d->prg_bus[idx] | 0x3); | |
750 | d->branchAddrPtr = | |
751 | &(d->prg_cpu[idx]->end.branchAddress); | |
752 | } else { /* quadlet transmit */ | |
753 | if (packet->type == hpsb_raw) | |
754 | d->prg_cpu[idx]->begin.control = | |
755 | cpu_to_le32(DMA_CTL_OUTPUT_LAST | | |
756 | DMA_CTL_IMMEDIATE | | |
757 | DMA_CTL_IRQ | | |
758 | DMA_CTL_BRANCH | | |
759 | (packet->header_size + 4)); | |
760 | else | |
761 | d->prg_cpu[idx]->begin.control = | |
762 | cpu_to_le32(DMA_CTL_OUTPUT_LAST | | |
763 | DMA_CTL_IMMEDIATE | | |
764 | DMA_CTL_IRQ | | |
765 | DMA_CTL_BRANCH | | |
766 | packet->header_size); | |
767 | ||
768 | if (d->branchAddrPtr) | |
769 | *(d->branchAddrPtr) = | |
770 | cpu_to_le32(d->prg_bus[idx] | 0x2); | |
771 | d->branchAddrPtr = | |
772 | &(d->prg_cpu[idx]->begin.branchAddress); | |
773 | } | |
774 | ||
775 | } else { /* iso packet */ | |
776 | d->prg_cpu[idx]->data[0] = packet->speed_code<<16 | | |
777 | (packet->header[0] & 0xFFFF); | |
778 | d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000; | |
9531f13a | 779 | header_le32_to_cpu(d->prg_cpu[idx]->data, packet->tcode); |
1da177e4 LT |
780 | |
781 | d->prg_cpu[idx]->begin.control = | |
782 | cpu_to_le32(DMA_CTL_OUTPUT_MORE | | |
783 | DMA_CTL_IMMEDIATE | 0x8); | |
784 | d->prg_cpu[idx]->end.control = | |
785 | cpu_to_le32(DMA_CTL_OUTPUT_LAST | | |
786 | DMA_CTL_UPDATE | | |
787 | DMA_CTL_IRQ | | |
788 | DMA_CTL_BRANCH | | |
789 | packet->data_size); | |
790 | d->prg_cpu[idx]->end.address = cpu_to_le32( | |
791 | pci_map_single(ohci->dev, packet->data, | |
792 | packet->data_size, PCI_DMA_TODEVICE)); | |
793 | OHCI_DMA_ALLOC("single, iso transmit packet"); | |
794 | ||
795 | d->prg_cpu[idx]->end.branchAddress = 0; | |
796 | d->prg_cpu[idx]->end.status = 0; | |
797 | DBGMSG("Iso xmit context info: header[%08x %08x]\n" | |
798 | " begin=%08x %08x %08x %08x\n" | |
799 | " %08x %08x %08x %08x\n" | |
800 | " end =%08x %08x %08x %08x", | |
801 | d->prg_cpu[idx]->data[0], d->prg_cpu[idx]->data[1], | |
802 | d->prg_cpu[idx]->begin.control, | |
803 | d->prg_cpu[idx]->begin.address, | |
804 | d->prg_cpu[idx]->begin.branchAddress, | |
805 | d->prg_cpu[idx]->begin.status, | |
806 | d->prg_cpu[idx]->data[0], | |
807 | d->prg_cpu[idx]->data[1], | |
808 | d->prg_cpu[idx]->data[2], | |
809 | d->prg_cpu[idx]->data[3], | |
810 | d->prg_cpu[idx]->end.control, | |
811 | d->prg_cpu[idx]->end.address, | |
812 | d->prg_cpu[idx]->end.branchAddress, | |
813 | d->prg_cpu[idx]->end.status); | |
814 | if (d->branchAddrPtr) | |
815 | *(d->branchAddrPtr) = cpu_to_le32(d->prg_bus[idx] | 0x3); | |
816 | d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress); | |
817 | } | |
818 | d->free_prgs--; | |
819 | ||
820 | /* queue the packet in the appropriate context queue */ | |
821 | list_add_tail(&packet->driver_list, &d->fifo_list); | |
822 | d->prg_ind = (d->prg_ind + 1) % d->num_desc; | |
823 | } | |
824 | ||
825 | /* | |
826 | * This function fills the FIFO with the (eventual) pending packets | |
827 | * and runs or wakes up the DMA prg if necessary. | |
828 | * | |
829 | * The function MUST be called with the d->lock held. | |
830 | */ | |
831 | static void dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d) | |
832 | { | |
833 | struct hpsb_packet *packet, *ptmp; | |
834 | int idx = d->prg_ind; | |
835 | int z = 0; | |
836 | ||
837 | /* insert the packets into the dma fifo */ | |
838 | list_for_each_entry_safe(packet, ptmp, &d->pending_list, driver_list) { | |
839 | if (!d->free_prgs) | |
840 | break; | |
841 | ||
842 | /* For the first packet only */ | |
843 | if (!z) | |
844 | z = (packet->data_size) ? 3 : 2; | |
845 | ||
846 | /* Insert the packet */ | |
847 | list_del_init(&packet->driver_list); | |
848 | insert_packet(ohci, d, packet); | |
849 | } | |
850 | ||
851 | /* Nothing must have been done, either no free_prgs or no packets */ | |
852 | if (z == 0) | |
853 | return; | |
854 | ||
855 | /* Is the context running ? (should be unless it is | |
856 | the first packet to be sent in this context) */ | |
857 | if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) { | |
858 | u32 nodeId = reg_read(ohci, OHCI1394_NodeID); | |
859 | ||
860 | DBGMSG("Starting transmit DMA ctx=%d",d->ctx); | |
861 | reg_write(ohci, d->cmdPtr, d->prg_bus[idx] | z); | |
862 | ||
863 | /* Check that the node id is valid, and not 63 */ | |
864 | if (!(nodeId & 0x80000000) || (nodeId & 0x3f) == 63) | |
865 | PRINT(KERN_ERR, "Running dma failed because Node ID is not valid"); | |
866 | else | |
867 | reg_write(ohci, d->ctrlSet, 0x8000); | |
868 | } else { | |
869 | /* Wake up the dma context if necessary */ | |
870 | if (!(reg_read(ohci, d->ctrlSet) & 0x400)) | |
871 | DBGMSG("Waking transmit DMA ctx=%d",d->ctx); | |
872 | ||
873 | /* do this always, to avoid race condition */ | |
874 | reg_write(ohci, d->ctrlSet, 0x1000); | |
875 | } | |
876 | ||
877 | return; | |
878 | } | |
879 | ||
880 | /* Transmission of an async or iso packet */ | |
881 | static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet) | |
882 | { | |
883 | struct ti_ohci *ohci = host->hostdata; | |
884 | struct dma_trm_ctx *d; | |
885 | unsigned long flags; | |
886 | ||
887 | if (packet->data_size > ohci->max_packet_size) { | |
888 | PRINT(KERN_ERR, | |
889 | "Transmit packet size %Zd is too big", | |
890 | packet->data_size); | |
891 | return -EOVERFLOW; | |
892 | } | |
893 | ||
894 | /* Decide whether we have an iso, a request, or a response packet */ | |
895 | if (packet->type == hpsb_raw) | |
896 | d = &ohci->at_req_context; | |
897 | else if ((packet->tcode == TCODE_ISO_DATA) && (packet->type == hpsb_iso)) { | |
898 | /* The legacy IT DMA context is initialized on first | |
899 | * use. However, the alloc cannot be run from | |
900 | * interrupt context, so we bail out if that is the | |
901 | * case. I don't see anyone sending ISO packets from | |
902 | * interrupt context anyway... */ | |
903 | ||
904 | if (ohci->it_legacy_context.ohci == NULL) { | |
905 | if (in_interrupt()) { | |
906 | PRINT(KERN_ERR, | |
907 | "legacy IT context cannot be initialized during interrupt"); | |
908 | return -EINVAL; | |
909 | } | |
910 | ||
911 | if (alloc_dma_trm_ctx(ohci, &ohci->it_legacy_context, | |
912 | DMA_CTX_ISO, 0, IT_NUM_DESC, | |
913 | OHCI1394_IsoXmitContextBase) < 0) { | |
914 | PRINT(KERN_ERR, | |
915 | "error initializing legacy IT context"); | |
916 | return -ENOMEM; | |
917 | } | |
918 | ||
919 | initialize_dma_trm_ctx(&ohci->it_legacy_context); | |
920 | } | |
921 | ||
922 | d = &ohci->it_legacy_context; | |
923 | } else if ((packet->tcode & 0x02) && (packet->tcode != TCODE_ISO_DATA)) | |
924 | d = &ohci->at_resp_context; | |
925 | else | |
926 | d = &ohci->at_req_context; | |
927 | ||
928 | spin_lock_irqsave(&d->lock,flags); | |
929 | ||
930 | list_add_tail(&packet->driver_list, &d->pending_list); | |
931 | ||
932 | dma_trm_flush(ohci, d); | |
933 | ||
934 | spin_unlock_irqrestore(&d->lock,flags); | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
939 | static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg) | |
940 | { | |
941 | struct ti_ohci *ohci = host->hostdata; | |
942 | int retval = 0; | |
943 | unsigned long flags; | |
944 | int phy_reg; | |
945 | ||
946 | switch (cmd) { | |
947 | case RESET_BUS: | |
948 | switch (arg) { | |
949 | case SHORT_RESET: | |
950 | phy_reg = get_phy_reg(ohci, 5); | |
951 | phy_reg |= 0x40; | |
952 | set_phy_reg(ohci, 5, phy_reg); /* set ISBR */ | |
953 | break; | |
954 | case LONG_RESET: | |
955 | phy_reg = get_phy_reg(ohci, 1); | |
956 | phy_reg |= 0x40; | |
957 | set_phy_reg(ohci, 1, phy_reg); /* set IBR */ | |
958 | break; | |
959 | case SHORT_RESET_NO_FORCE_ROOT: | |
960 | phy_reg = get_phy_reg(ohci, 1); | |
961 | if (phy_reg & 0x80) { | |
962 | phy_reg &= ~0x80; | |
963 | set_phy_reg(ohci, 1, phy_reg); /* clear RHB */ | |
964 | } | |
965 | ||
966 | phy_reg = get_phy_reg(ohci, 5); | |
967 | phy_reg |= 0x40; | |
968 | set_phy_reg(ohci, 5, phy_reg); /* set ISBR */ | |
969 | break; | |
970 | case LONG_RESET_NO_FORCE_ROOT: | |
971 | phy_reg = get_phy_reg(ohci, 1); | |
972 | phy_reg &= ~0x80; | |
973 | phy_reg |= 0x40; | |
974 | set_phy_reg(ohci, 1, phy_reg); /* clear RHB, set IBR */ | |
975 | break; | |
976 | case SHORT_RESET_FORCE_ROOT: | |
977 | phy_reg = get_phy_reg(ohci, 1); | |
978 | if (!(phy_reg & 0x80)) { | |
979 | phy_reg |= 0x80; | |
980 | set_phy_reg(ohci, 1, phy_reg); /* set RHB */ | |
981 | } | |
982 | ||
983 | phy_reg = get_phy_reg(ohci, 5); | |
984 | phy_reg |= 0x40; | |
985 | set_phy_reg(ohci, 5, phy_reg); /* set ISBR */ | |
986 | break; | |
987 | case LONG_RESET_FORCE_ROOT: | |
988 | phy_reg = get_phy_reg(ohci, 1); | |
989 | phy_reg |= 0xc0; | |
990 | set_phy_reg(ohci, 1, phy_reg); /* set RHB and IBR */ | |
991 | break; | |
992 | default: | |
993 | retval = -1; | |
994 | } | |
995 | break; | |
996 | ||
997 | case GET_CYCLE_COUNTER: | |
998 | retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
999 | break; | |
1000 | ||
1001 | case SET_CYCLE_COUNTER: | |
1002 | reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg); | |
1003 | break; | |
1004 | ||
1005 | case SET_BUS_ID: | |
1006 | PRINT(KERN_ERR, "devctl command SET_BUS_ID err"); | |
1007 | break; | |
1008 | ||
1009 | case ACT_CYCLE_MASTER: | |
1010 | if (arg) { | |
1011 | /* check if we are root and other nodes are present */ | |
1012 | u32 nodeId = reg_read(ohci, OHCI1394_NodeID); | |
1013 | if ((nodeId & (1<<30)) && (nodeId & 0x3f)) { | |
1014 | /* | |
1015 | * enable cycleTimer, cycleMaster | |
1016 | */ | |
1017 | DBGMSG("Cycle master enabled"); | |
1018 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1019 | OHCI1394_LinkControl_CycleTimerEnable | | |
1020 | OHCI1394_LinkControl_CycleMaster); | |
1021 | } | |
1022 | } else { | |
1023 | /* disable cycleTimer, cycleMaster, cycleSource */ | |
1024 | reg_write(ohci, OHCI1394_LinkControlClear, | |
1025 | OHCI1394_LinkControl_CycleTimerEnable | | |
1026 | OHCI1394_LinkControl_CycleMaster | | |
1027 | OHCI1394_LinkControl_CycleSource); | |
1028 | } | |
1029 | break; | |
1030 | ||
1031 | case CANCEL_REQUESTS: | |
1032 | DBGMSG("Cancel request received"); | |
1033 | dma_trm_reset(&ohci->at_req_context); | |
1034 | dma_trm_reset(&ohci->at_resp_context); | |
1035 | break; | |
1036 | ||
1037 | case ISO_LISTEN_CHANNEL: | |
1038 | { | |
1039 | u64 mask; | |
e4ec0f23 JM |
1040 | struct dma_rcv_ctx *d = &ohci->ir_legacy_context; |
1041 | int ir_legacy_active; | |
1da177e4 LT |
1042 | |
1043 | if (arg<0 || arg>63) { | |
1044 | PRINT(KERN_ERR, | |
1045 | "%s: IS0 listen channel %d is out of range", | |
1046 | __FUNCTION__, arg); | |
1047 | return -EFAULT; | |
1048 | } | |
1049 | ||
1050 | mask = (u64)0x1<<arg; | |
1051 | ||
1052 | spin_lock_irqsave(&ohci->IR_channel_lock, flags); | |
1053 | ||
1054 | if (ohci->ISO_channel_usage & mask) { | |
1055 | PRINT(KERN_ERR, | |
1056 | "%s: IS0 listen channel %d is already used", | |
1057 | __FUNCTION__, arg); | |
1058 | spin_unlock_irqrestore(&ohci->IR_channel_lock, flags); | |
1059 | return -EFAULT; | |
1060 | } | |
1061 | ||
e4ec0f23 JM |
1062 | ir_legacy_active = ohci->ir_legacy_channels; |
1063 | ||
1da177e4 LT |
1064 | ohci->ISO_channel_usage |= mask; |
1065 | ohci->ir_legacy_channels |= mask; | |
1066 | ||
e4ec0f23 JM |
1067 | spin_unlock_irqrestore(&ohci->IR_channel_lock, flags); |
1068 | ||
1069 | if (!ir_legacy_active) { | |
1070 | if (ohci1394_register_iso_tasklet(ohci, | |
1071 | &ohci->ir_legacy_tasklet) < 0) { | |
1072 | PRINT(KERN_ERR, "No IR DMA context available"); | |
1073 | return -EBUSY; | |
1074 | } | |
1075 | ||
1076 | /* the IR context can be assigned to any DMA context | |
1077 | * by ohci1394_register_iso_tasklet */ | |
1078 | d->ctx = ohci->ir_legacy_tasklet.context; | |
1079 | d->ctrlSet = OHCI1394_IsoRcvContextControlSet + | |
1080 | 32*d->ctx; | |
1081 | d->ctrlClear = OHCI1394_IsoRcvContextControlClear + | |
1082 | 32*d->ctx; | |
1083 | d->cmdPtr = OHCI1394_IsoRcvCommandPtr + 32*d->ctx; | |
1084 | d->ctxtMatch = OHCI1394_IsoRcvContextMatch + 32*d->ctx; | |
1085 | ||
1086 | initialize_dma_rcv_ctx(&ohci->ir_legacy_context, 1); | |
1087 | ||
98848fa8 | 1088 | if (printk_ratelimit()) |
32e7a04f | 1089 | DBGMSG("IR legacy activated"); |
e4ec0f23 JM |
1090 | } |
1091 | ||
1092 | spin_lock_irqsave(&ohci->IR_channel_lock, flags); | |
1093 | ||
1da177e4 LT |
1094 | if (arg>31) |
1095 | reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, | |
1096 | 1<<(arg-32)); | |
1097 | else | |
1098 | reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, | |
1099 | 1<<arg); | |
1100 | ||
1101 | spin_unlock_irqrestore(&ohci->IR_channel_lock, flags); | |
1102 | DBGMSG("Listening enabled on channel %d", arg); | |
1103 | break; | |
1104 | } | |
1105 | case ISO_UNLISTEN_CHANNEL: | |
1106 | { | |
1107 | u64 mask; | |
1108 | ||
1109 | if (arg<0 || arg>63) { | |
1110 | PRINT(KERN_ERR, | |
1111 | "%s: IS0 unlisten channel %d is out of range", | |
1112 | __FUNCTION__, arg); | |
1113 | return -EFAULT; | |
1114 | } | |
1115 | ||
1116 | mask = (u64)0x1<<arg; | |
1117 | ||
1118 | spin_lock_irqsave(&ohci->IR_channel_lock, flags); | |
1119 | ||
1120 | if (!(ohci->ISO_channel_usage & mask)) { | |
1121 | PRINT(KERN_ERR, | |
1122 | "%s: IS0 unlisten channel %d is not used", | |
1123 | __FUNCTION__, arg); | |
1124 | spin_unlock_irqrestore(&ohci->IR_channel_lock, flags); | |
1125 | return -EFAULT; | |
1126 | } | |
1127 | ||
1128 | ohci->ISO_channel_usage &= ~mask; | |
1129 | ohci->ir_legacy_channels &= ~mask; | |
1130 | ||
1131 | if (arg>31) | |
1132 | reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, | |
1133 | 1<<(arg-32)); | |
1134 | else | |
1135 | reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, | |
1136 | 1<<arg); | |
1137 | ||
1138 | spin_unlock_irqrestore(&ohci->IR_channel_lock, flags); | |
1139 | DBGMSG("Listening disabled on channel %d", arg); | |
e4ec0f23 JM |
1140 | |
1141 | if (ohci->ir_legacy_channels == 0) { | |
1142 | stop_dma_rcv_ctx(&ohci->ir_legacy_context); | |
1143 | DBGMSG("ISO legacy receive context stopped"); | |
1144 | } | |
1145 | ||
1da177e4 LT |
1146 | break; |
1147 | } | |
1148 | default: | |
1149 | PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet", | |
1150 | cmd); | |
1151 | break; | |
1152 | } | |
1153 | return retval; | |
1154 | } | |
1155 | ||
1156 | /*********************************** | |
1157 | * rawiso ISO reception * | |
1158 | ***********************************/ | |
1159 | ||
1160 | /* | |
1161 | We use either buffer-fill or packet-per-buffer DMA mode. The DMA | |
1162 | buffer is split into "blocks" (regions described by one DMA | |
1163 | descriptor). Each block must be one page or less in size, and | |
1164 | must not cross a page boundary. | |
1165 | ||
1166 | There is one little wrinkle with buffer-fill mode: a packet that | |
1167 | starts in the final block may wrap around into the first block. But | |
1168 | the user API expects all packets to be contiguous. Our solution is | |
1169 | to keep the very last page of the DMA buffer in reserve - if a | |
1170 | packet spans the gap, we copy its tail into this page. | |
1171 | */ | |
1172 | ||
1173 | struct ohci_iso_recv { | |
1174 | struct ti_ohci *ohci; | |
1175 | ||
1176 | struct ohci1394_iso_tasklet task; | |
1177 | int task_active; | |
1178 | ||
1179 | enum { BUFFER_FILL_MODE = 0, | |
1180 | PACKET_PER_BUFFER_MODE = 1 } dma_mode; | |
1181 | ||
1182 | /* memory and PCI mapping for the DMA descriptors */ | |
1183 | struct dma_prog_region prog; | |
1184 | struct dma_cmd *block; /* = (struct dma_cmd*) prog.virt */ | |
1185 | ||
1186 | /* how many DMA blocks fit in the buffer */ | |
1187 | unsigned int nblocks; | |
1188 | ||
1189 | /* stride of DMA blocks */ | |
1190 | unsigned int buf_stride; | |
1191 | ||
1192 | /* number of blocks to batch between interrupts */ | |
1193 | int block_irq_interval; | |
1194 | ||
1195 | /* block that DMA will finish next */ | |
1196 | int block_dma; | |
1197 | ||
1198 | /* (buffer-fill only) block that the reader will release next */ | |
1199 | int block_reader; | |
1200 | ||
1201 | /* (buffer-fill only) bytes of buffer the reader has released, | |
1202 | less than one block */ | |
1203 | int released_bytes; | |
1204 | ||
1205 | /* (buffer-fill only) buffer offset at which the next packet will appear */ | |
1206 | int dma_offset; | |
1207 | ||
1208 | /* OHCI DMA context control registers */ | |
1209 | u32 ContextControlSet; | |
1210 | u32 ContextControlClear; | |
1211 | u32 CommandPtr; | |
1212 | u32 ContextMatch; | |
1213 | }; | |
1214 | ||
1215 | static void ohci_iso_recv_task(unsigned long data); | |
1216 | static void ohci_iso_recv_stop(struct hpsb_iso *iso); | |
1217 | static void ohci_iso_recv_shutdown(struct hpsb_iso *iso); | |
1218 | static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync); | |
1219 | static void ohci_iso_recv_program(struct hpsb_iso *iso); | |
1220 | ||
1221 | static int ohci_iso_recv_init(struct hpsb_iso *iso) | |
1222 | { | |
1223 | struct ti_ohci *ohci = iso->host->hostdata; | |
1224 | struct ohci_iso_recv *recv; | |
1225 | int ctx; | |
1226 | int ret = -ENOMEM; | |
1227 | ||
1228 | recv = kmalloc(sizeof(*recv), SLAB_KERNEL); | |
1229 | if (!recv) | |
1230 | return -ENOMEM; | |
1231 | ||
1232 | iso->hostdata = recv; | |
1233 | recv->ohci = ohci; | |
1234 | recv->task_active = 0; | |
1235 | dma_prog_region_init(&recv->prog); | |
1236 | recv->block = NULL; | |
1237 | ||
1238 | /* use buffer-fill mode, unless irq_interval is 1 | |
1239 | (note: multichannel requires buffer-fill) */ | |
1240 | ||
1241 | if (((iso->irq_interval == 1 && iso->dma_mode == HPSB_ISO_DMA_OLD_ABI) || | |
1242 | iso->dma_mode == HPSB_ISO_DMA_PACKET_PER_BUFFER) && iso->channel != -1) { | |
1243 | recv->dma_mode = PACKET_PER_BUFFER_MODE; | |
1244 | } else { | |
1245 | recv->dma_mode = BUFFER_FILL_MODE; | |
1246 | } | |
1247 | ||
1248 | /* set nblocks, buf_stride, block_irq_interval */ | |
1249 | ||
1250 | if (recv->dma_mode == BUFFER_FILL_MODE) { | |
1251 | recv->buf_stride = PAGE_SIZE; | |
1252 | ||
1253 | /* one block per page of data in the DMA buffer, minus the final guard page */ | |
1254 | recv->nblocks = iso->buf_size/PAGE_SIZE - 1; | |
1255 | if (recv->nblocks < 3) { | |
1256 | DBGMSG("ohci_iso_recv_init: DMA buffer too small"); | |
1257 | goto err; | |
1258 | } | |
1259 | ||
1260 | /* iso->irq_interval is in packets - translate that to blocks */ | |
1261 | if (iso->irq_interval == 1) | |
1262 | recv->block_irq_interval = 1; | |
1263 | else | |
1264 | recv->block_irq_interval = iso->irq_interval * | |
1265 | ((recv->nblocks+1)/iso->buf_packets); | |
1266 | if (recv->block_irq_interval*4 > recv->nblocks) | |
1267 | recv->block_irq_interval = recv->nblocks/4; | |
1268 | if (recv->block_irq_interval < 1) | |
1269 | recv->block_irq_interval = 1; | |
1270 | ||
1271 | } else { | |
1272 | int max_packet_size; | |
1273 | ||
1274 | recv->nblocks = iso->buf_packets; | |
1275 | recv->block_irq_interval = iso->irq_interval; | |
1276 | if (recv->block_irq_interval * 4 > iso->buf_packets) | |
1277 | recv->block_irq_interval = iso->buf_packets / 4; | |
1278 | if (recv->block_irq_interval < 1) | |
1279 | recv->block_irq_interval = 1; | |
1280 | ||
1281 | /* choose a buffer stride */ | |
1282 | /* must be a power of 2, and <= PAGE_SIZE */ | |
1283 | ||
1284 | max_packet_size = iso->buf_size / iso->buf_packets; | |
1285 | ||
1286 | for (recv->buf_stride = 8; recv->buf_stride < max_packet_size; | |
1287 | recv->buf_stride *= 2); | |
1288 | ||
1289 | if (recv->buf_stride*iso->buf_packets > iso->buf_size || | |
1290 | recv->buf_stride > PAGE_SIZE) { | |
1291 | /* this shouldn't happen, but anyway... */ | |
1292 | DBGMSG("ohci_iso_recv_init: problem choosing a buffer stride"); | |
1293 | goto err; | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | recv->block_reader = 0; | |
1298 | recv->released_bytes = 0; | |
1299 | recv->block_dma = 0; | |
1300 | recv->dma_offset = 0; | |
1301 | ||
1302 | /* size of DMA program = one descriptor per block */ | |
1303 | if (dma_prog_region_alloc(&recv->prog, | |
1304 | sizeof(struct dma_cmd) * recv->nblocks, | |
1305 | recv->ohci->dev)) | |
1306 | goto err; | |
1307 | ||
1308 | recv->block = (struct dma_cmd*) recv->prog.kvirt; | |
1309 | ||
1310 | ohci1394_init_iso_tasklet(&recv->task, | |
1311 | iso->channel == -1 ? OHCI_ISO_MULTICHANNEL_RECEIVE : | |
1312 | OHCI_ISO_RECEIVE, | |
1313 | ohci_iso_recv_task, (unsigned long) iso); | |
1314 | ||
e4ec0f23 JM |
1315 | if (ohci1394_register_iso_tasklet(recv->ohci, &recv->task) < 0) { |
1316 | ret = -EBUSY; | |
1da177e4 | 1317 | goto err; |
e4ec0f23 | 1318 | } |
1da177e4 LT |
1319 | |
1320 | recv->task_active = 1; | |
1321 | ||
1322 | /* recv context registers are spaced 32 bytes apart */ | |
1323 | ctx = recv->task.context; | |
1324 | recv->ContextControlSet = OHCI1394_IsoRcvContextControlSet + 32 * ctx; | |
1325 | recv->ContextControlClear = OHCI1394_IsoRcvContextControlClear + 32 * ctx; | |
1326 | recv->CommandPtr = OHCI1394_IsoRcvCommandPtr + 32 * ctx; | |
1327 | recv->ContextMatch = OHCI1394_IsoRcvContextMatch + 32 * ctx; | |
1328 | ||
1329 | if (iso->channel == -1) { | |
1330 | /* clear multi-channel selection mask */ | |
1331 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, 0xFFFFFFFF); | |
1332 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, 0xFFFFFFFF); | |
1333 | } | |
1334 | ||
1335 | /* write the DMA program */ | |
1336 | ohci_iso_recv_program(iso); | |
1337 | ||
1338 | DBGMSG("ohci_iso_recv_init: %s mode, DMA buffer is %lu pages" | |
1339 | " (%u bytes), using %u blocks, buf_stride %u, block_irq_interval %d", | |
1340 | recv->dma_mode == BUFFER_FILL_MODE ? | |
1341 | "buffer-fill" : "packet-per-buffer", | |
1342 | iso->buf_size/PAGE_SIZE, iso->buf_size, | |
1343 | recv->nblocks, recv->buf_stride, recv->block_irq_interval); | |
1344 | ||
1345 | return 0; | |
1346 | ||
1347 | err: | |
1348 | ohci_iso_recv_shutdown(iso); | |
1349 | return ret; | |
1350 | } | |
1351 | ||
1352 | static void ohci_iso_recv_stop(struct hpsb_iso *iso) | |
1353 | { | |
1354 | struct ohci_iso_recv *recv = iso->hostdata; | |
1355 | ||
1356 | /* disable interrupts */ | |
1357 | reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << recv->task.context); | |
1358 | ||
1359 | /* halt DMA */ | |
1360 | ohci1394_stop_context(recv->ohci, recv->ContextControlClear, NULL); | |
1361 | } | |
1362 | ||
1363 | static void ohci_iso_recv_shutdown(struct hpsb_iso *iso) | |
1364 | { | |
1365 | struct ohci_iso_recv *recv = iso->hostdata; | |
1366 | ||
1367 | if (recv->task_active) { | |
1368 | ohci_iso_recv_stop(iso); | |
1369 | ohci1394_unregister_iso_tasklet(recv->ohci, &recv->task); | |
1370 | recv->task_active = 0; | |
1371 | } | |
1372 | ||
1373 | dma_prog_region_free(&recv->prog); | |
1374 | kfree(recv); | |
1375 | iso->hostdata = NULL; | |
1376 | } | |
1377 | ||
1378 | /* set up a "gapped" ring buffer DMA program */ | |
1379 | static void ohci_iso_recv_program(struct hpsb_iso *iso) | |
1380 | { | |
1381 | struct ohci_iso_recv *recv = iso->hostdata; | |
1382 | int blk; | |
1383 | ||
1384 | /* address of 'branch' field in previous DMA descriptor */ | |
1385 | u32 *prev_branch = NULL; | |
1386 | ||
1387 | for (blk = 0; blk < recv->nblocks; blk++) { | |
1388 | u32 control; | |
1389 | ||
1390 | /* the DMA descriptor */ | |
1391 | struct dma_cmd *cmd = &recv->block[blk]; | |
1392 | ||
1393 | /* offset of the DMA descriptor relative to the DMA prog buffer */ | |
1394 | unsigned long prog_offset = blk * sizeof(struct dma_cmd); | |
1395 | ||
1396 | /* offset of this packet's data within the DMA buffer */ | |
1397 | unsigned long buf_offset = blk * recv->buf_stride; | |
1398 | ||
1399 | if (recv->dma_mode == BUFFER_FILL_MODE) { | |
1400 | control = 2 << 28; /* INPUT_MORE */ | |
1401 | } else { | |
1402 | control = 3 << 28; /* INPUT_LAST */ | |
1403 | } | |
1404 | ||
1405 | control |= 8 << 24; /* s = 1, update xferStatus and resCount */ | |
1406 | ||
1407 | /* interrupt on last block, and at intervals */ | |
1408 | if (blk == recv->nblocks-1 || (blk % recv->block_irq_interval) == 0) { | |
1409 | control |= 3 << 20; /* want interrupt */ | |
1410 | } | |
1411 | ||
1412 | control |= 3 << 18; /* enable branch to address */ | |
1413 | control |= recv->buf_stride; | |
1414 | ||
1415 | cmd->control = cpu_to_le32(control); | |
1416 | cmd->address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, buf_offset)); | |
1417 | cmd->branchAddress = 0; /* filled in on next loop */ | |
1418 | cmd->status = cpu_to_le32(recv->buf_stride); | |
1419 | ||
1420 | /* link the previous descriptor to this one */ | |
1421 | if (prev_branch) { | |
1422 | *prev_branch = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog, prog_offset) | 1); | |
1423 | } | |
1424 | ||
1425 | prev_branch = &cmd->branchAddress; | |
1426 | } | |
1427 | ||
1428 | /* the final descriptor's branch address and Z should be left at 0 */ | |
1429 | } | |
1430 | ||
1431 | /* listen or unlisten to a specific channel (multi-channel mode only) */ | |
1432 | static void ohci_iso_recv_change_channel(struct hpsb_iso *iso, unsigned char channel, int listen) | |
1433 | { | |
1434 | struct ohci_iso_recv *recv = iso->hostdata; | |
1435 | int reg, i; | |
1436 | ||
1437 | if (channel < 32) { | |
1438 | reg = listen ? OHCI1394_IRMultiChanMaskLoSet : OHCI1394_IRMultiChanMaskLoClear; | |
1439 | i = channel; | |
1440 | } else { | |
1441 | reg = listen ? OHCI1394_IRMultiChanMaskHiSet : OHCI1394_IRMultiChanMaskHiClear; | |
1442 | i = channel - 32; | |
1443 | } | |
1444 | ||
1445 | reg_write(recv->ohci, reg, (1 << i)); | |
1446 | ||
1447 | /* issue a dummy read to force all PCI writes to be posted immediately */ | |
1448 | mb(); | |
1449 | reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer); | |
1450 | } | |
1451 | ||
1452 | static void ohci_iso_recv_set_channel_mask(struct hpsb_iso *iso, u64 mask) | |
1453 | { | |
1454 | struct ohci_iso_recv *recv = iso->hostdata; | |
1455 | int i; | |
1456 | ||
1457 | for (i = 0; i < 64; i++) { | |
1458 | if (mask & (1ULL << i)) { | |
1459 | if (i < 32) | |
1460 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoSet, (1 << i)); | |
1461 | else | |
1462 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiSet, (1 << (i-32))); | |
1463 | } else { | |
1464 | if (i < 32) | |
1465 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskLoClear, (1 << i)); | |
1466 | else | |
1467 | reg_write(recv->ohci, OHCI1394_IRMultiChanMaskHiClear, (1 << (i-32))); | |
1468 | } | |
1469 | } | |
1470 | ||
1471 | /* issue a dummy read to force all PCI writes to be posted immediately */ | |
1472 | mb(); | |
1473 | reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer); | |
1474 | } | |
1475 | ||
1476 | static int ohci_iso_recv_start(struct hpsb_iso *iso, int cycle, int tag_mask, int sync) | |
1477 | { | |
1478 | struct ohci_iso_recv *recv = iso->hostdata; | |
1479 | struct ti_ohci *ohci = recv->ohci; | |
1480 | u32 command, contextMatch; | |
1481 | ||
1482 | reg_write(recv->ohci, recv->ContextControlClear, 0xFFFFFFFF); | |
1483 | wmb(); | |
1484 | ||
1485 | /* always keep ISO headers */ | |
1486 | command = (1 << 30); | |
1487 | ||
1488 | if (recv->dma_mode == BUFFER_FILL_MODE) | |
1489 | command |= (1 << 31); | |
1490 | ||
1491 | reg_write(recv->ohci, recv->ContextControlSet, command); | |
1492 | ||
1493 | /* match on specified tags */ | |
1494 | contextMatch = tag_mask << 28; | |
1495 | ||
1496 | if (iso->channel == -1) { | |
1497 | /* enable multichannel reception */ | |
1498 | reg_write(recv->ohci, recv->ContextControlSet, (1 << 28)); | |
1499 | } else { | |
1500 | /* listen on channel */ | |
1501 | contextMatch |= iso->channel; | |
1502 | } | |
1503 | ||
1504 | if (cycle != -1) { | |
1505 | u32 seconds; | |
1506 | ||
1507 | /* enable cycleMatch */ | |
1508 | reg_write(recv->ohci, recv->ContextControlSet, (1 << 29)); | |
1509 | ||
1510 | /* set starting cycle */ | |
1511 | cycle &= 0x1FFF; | |
1512 | ||
1513 | /* 'cycle' is only mod 8000, but we also need two 'seconds' bits - | |
1514 | just snarf them from the current time */ | |
1515 | seconds = reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer) >> 25; | |
1516 | ||
1517 | /* advance one second to give some extra time for DMA to start */ | |
1518 | seconds += 1; | |
1519 | ||
1520 | cycle |= (seconds & 3) << 13; | |
1521 | ||
1522 | contextMatch |= cycle << 12; | |
1523 | } | |
1524 | ||
1525 | if (sync != -1) { | |
1526 | /* set sync flag on first DMA descriptor */ | |
1527 | struct dma_cmd *cmd = &recv->block[recv->block_dma]; | |
1528 | cmd->control |= cpu_to_le32(DMA_CTL_WAIT); | |
1529 | ||
1530 | /* match sync field */ | |
1531 | contextMatch |= (sync&0xf)<<8; | |
1532 | } | |
1533 | ||
1534 | reg_write(recv->ohci, recv->ContextMatch, contextMatch); | |
1535 | ||
1536 | /* address of first descriptor block */ | |
1537 | command = dma_prog_region_offset_to_bus(&recv->prog, | |
1538 | recv->block_dma * sizeof(struct dma_cmd)); | |
1539 | command |= 1; /* Z=1 */ | |
1540 | ||
1541 | reg_write(recv->ohci, recv->CommandPtr, command); | |
1542 | ||
1543 | /* enable interrupts */ | |
1544 | reg_write(recv->ohci, OHCI1394_IsoRecvIntMaskSet, 1 << recv->task.context); | |
1545 | ||
1546 | wmb(); | |
1547 | ||
1548 | /* run */ | |
1549 | reg_write(recv->ohci, recv->ContextControlSet, 0x8000); | |
1550 | ||
1551 | /* issue a dummy read of the cycle timer register to force | |
1552 | all PCI writes to be posted immediately */ | |
1553 | mb(); | |
1554 | reg_read(recv->ohci, OHCI1394_IsochronousCycleTimer); | |
1555 | ||
1556 | /* check RUN */ | |
1557 | if (!(reg_read(recv->ohci, recv->ContextControlSet) & 0x8000)) { | |
1558 | PRINT(KERN_ERR, | |
1559 | "Error starting IR DMA (ContextControl 0x%08x)\n", | |
1560 | reg_read(recv->ohci, recv->ContextControlSet)); | |
1561 | return -1; | |
1562 | } | |
1563 | ||
1564 | return 0; | |
1565 | } | |
1566 | ||
1567 | static void ohci_iso_recv_release_block(struct ohci_iso_recv *recv, int block) | |
1568 | { | |
1569 | /* re-use the DMA descriptor for the block */ | |
1570 | /* by linking the previous descriptor to it */ | |
1571 | ||
1572 | int next_i = block; | |
1573 | int prev_i = (next_i == 0) ? (recv->nblocks - 1) : (next_i - 1); | |
1574 | ||
1575 | struct dma_cmd *next = &recv->block[next_i]; | |
1576 | struct dma_cmd *prev = &recv->block[prev_i]; | |
1934b8b6 BC |
1577 | |
1578 | /* ignore out-of-range requests */ | |
1579 | if ((block < 0) || (block > recv->nblocks)) | |
1580 | return; | |
1da177e4 LT |
1581 | |
1582 | /* 'next' becomes the new end of the DMA chain, | |
1583 | so disable branch and enable interrupt */ | |
1584 | next->branchAddress = 0; | |
1585 | next->control |= cpu_to_le32(3 << 20); | |
1586 | next->status = cpu_to_le32(recv->buf_stride); | |
1587 | ||
1588 | /* link prev to next */ | |
1589 | prev->branchAddress = cpu_to_le32(dma_prog_region_offset_to_bus(&recv->prog, | |
1590 | sizeof(struct dma_cmd) * next_i) | |
1591 | | 1); /* Z=1 */ | |
1592 | ||
1593 | /* disable interrupt on previous DMA descriptor, except at intervals */ | |
1594 | if ((prev_i % recv->block_irq_interval) == 0) { | |
1595 | prev->control |= cpu_to_le32(3 << 20); /* enable interrupt */ | |
1596 | } else { | |
1597 | prev->control &= cpu_to_le32(~(3<<20)); /* disable interrupt */ | |
1598 | } | |
1599 | wmb(); | |
1600 | ||
1601 | /* wake up DMA in case it fell asleep */ | |
1602 | reg_write(recv->ohci, recv->ContextControlSet, (1 << 12)); | |
1603 | } | |
1604 | ||
1605 | static void ohci_iso_recv_bufferfill_release(struct ohci_iso_recv *recv, | |
1606 | struct hpsb_iso_packet_info *info) | |
1607 | { | |
1da177e4 | 1608 | /* release the memory where the packet was */ |
1934b8b6 | 1609 | recv->released_bytes += info->total_len; |
1da177e4 LT |
1610 | |
1611 | /* have we released enough memory for one block? */ | |
1612 | while (recv->released_bytes > recv->buf_stride) { | |
1613 | ohci_iso_recv_release_block(recv, recv->block_reader); | |
1614 | recv->block_reader = (recv->block_reader + 1) % recv->nblocks; | |
1615 | recv->released_bytes -= recv->buf_stride; | |
1616 | } | |
1617 | } | |
1618 | ||
1619 | static inline void ohci_iso_recv_release(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info) | |
1620 | { | |
1621 | struct ohci_iso_recv *recv = iso->hostdata; | |
1622 | if (recv->dma_mode == BUFFER_FILL_MODE) { | |
1623 | ohci_iso_recv_bufferfill_release(recv, info); | |
1624 | } else { | |
1625 | ohci_iso_recv_release_block(recv, info - iso->infos); | |
1626 | } | |
1627 | } | |
1628 | ||
1629 | /* parse all packets from blocks that have been fully received */ | |
1630 | static void ohci_iso_recv_bufferfill_parse(struct hpsb_iso *iso, struct ohci_iso_recv *recv) | |
1631 | { | |
1632 | int wake = 0; | |
1633 | int runaway = 0; | |
1634 | struct ti_ohci *ohci = recv->ohci; | |
1635 | ||
1636 | while (1) { | |
1637 | /* we expect the next parsable packet to begin at recv->dma_offset */ | |
1638 | /* note: packet layout is as shown in section 10.6.1.1 of the OHCI spec */ | |
1639 | ||
1640 | unsigned int offset; | |
1934b8b6 | 1641 | unsigned short len, cycle, total_len; |
1da177e4 LT |
1642 | unsigned char channel, tag, sy; |
1643 | ||
1644 | unsigned char *p = iso->data_buf.kvirt; | |
1645 | ||
1646 | unsigned int this_block = recv->dma_offset/recv->buf_stride; | |
1647 | ||
1648 | /* don't loop indefinitely */ | |
1649 | if (runaway++ > 100000) { | |
1650 | atomic_inc(&iso->overflows); | |
1651 | PRINT(KERN_ERR, | |
1652 | "IR DMA error - Runaway during buffer parsing!\n"); | |
1653 | break; | |
1654 | } | |
1655 | ||
1656 | /* stop parsing once we arrive at block_dma (i.e. don't get ahead of DMA) */ | |
1657 | if (this_block == recv->block_dma) | |
1658 | break; | |
1659 | ||
1660 | wake = 1; | |
1661 | ||
1662 | /* parse data length, tag, channel, and sy */ | |
1663 | ||
1664 | /* note: we keep our own local copies of 'len' and 'offset' | |
1665 | so the user can't mess with them by poking in the mmap area */ | |
1666 | ||
1667 | len = p[recv->dma_offset+2] | (p[recv->dma_offset+3] << 8); | |
1668 | ||
1669 | if (len > 4096) { | |
1670 | PRINT(KERN_ERR, | |
1671 | "IR DMA error - bogus 'len' value %u\n", len); | |
1672 | } | |
1673 | ||
1674 | channel = p[recv->dma_offset+1] & 0x3F; | |
1675 | tag = p[recv->dma_offset+1] >> 6; | |
1676 | sy = p[recv->dma_offset+0] & 0xF; | |
1677 | ||
1678 | /* advance to data payload */ | |
1679 | recv->dma_offset += 4; | |
1680 | ||
1681 | /* check for wrap-around */ | |
1682 | if (recv->dma_offset >= recv->buf_stride*recv->nblocks) { | |
1683 | recv->dma_offset -= recv->buf_stride*recv->nblocks; | |
1684 | } | |
1685 | ||
1686 | /* dma_offset now points to the first byte of the data payload */ | |
1687 | offset = recv->dma_offset; | |
1688 | ||
1689 | /* advance to xferStatus/timeStamp */ | |
1690 | recv->dma_offset += len; | |
1691 | ||
1934b8b6 | 1692 | total_len = len + 8; /* 8 bytes header+trailer in OHCI packet */ |
1da177e4 LT |
1693 | /* payload is padded to 4 bytes */ |
1694 | if (len % 4) { | |
1695 | recv->dma_offset += 4 - (len%4); | |
1934b8b6 | 1696 | total_len += 4 - (len%4); |
1da177e4 LT |
1697 | } |
1698 | ||
1699 | /* check for wrap-around */ | |
1700 | if (recv->dma_offset >= recv->buf_stride*recv->nblocks) { | |
1701 | /* uh oh, the packet data wraps from the last | |
1702 | to the first DMA block - make the packet | |
1703 | contiguous by copying its "tail" into the | |
1704 | guard page */ | |
1705 | ||
1706 | int guard_off = recv->buf_stride*recv->nblocks; | |
1707 | int tail_len = len - (guard_off - offset); | |
1708 | ||
1709 | if (tail_len > 0 && tail_len < recv->buf_stride) { | |
1710 | memcpy(iso->data_buf.kvirt + guard_off, | |
1711 | iso->data_buf.kvirt, | |
1712 | tail_len); | |
1713 | } | |
1714 | ||
1715 | recv->dma_offset -= recv->buf_stride*recv->nblocks; | |
1716 | } | |
1717 | ||
1718 | /* parse timestamp */ | |
1719 | cycle = p[recv->dma_offset+0] | (p[recv->dma_offset+1]<<8); | |
1720 | cycle &= 0x1FFF; | |
1721 | ||
1722 | /* advance to next packet */ | |
1723 | recv->dma_offset += 4; | |
1724 | ||
1725 | /* check for wrap-around */ | |
1726 | if (recv->dma_offset >= recv->buf_stride*recv->nblocks) { | |
1727 | recv->dma_offset -= recv->buf_stride*recv->nblocks; | |
1728 | } | |
1729 | ||
1934b8b6 | 1730 | hpsb_iso_packet_received(iso, offset, len, total_len, cycle, channel, tag, sy); |
1da177e4 LT |
1731 | } |
1732 | ||
1733 | if (wake) | |
1734 | hpsb_iso_wake(iso); | |
1735 | } | |
1736 | ||
1737 | static void ohci_iso_recv_bufferfill_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv) | |
1738 | { | |
1739 | int loop; | |
1740 | struct ti_ohci *ohci = recv->ohci; | |
1741 | ||
1742 | /* loop over all blocks */ | |
1743 | for (loop = 0; loop < recv->nblocks; loop++) { | |
1744 | ||
1745 | /* check block_dma to see if it's done */ | |
1746 | struct dma_cmd *im = &recv->block[recv->block_dma]; | |
1747 | ||
1748 | /* check the DMA descriptor for new writes to xferStatus */ | |
1749 | u16 xferstatus = le32_to_cpu(im->status) >> 16; | |
1750 | ||
1751 | /* rescount is the number of bytes *remaining to be written* in the block */ | |
1752 | u16 rescount = le32_to_cpu(im->status) & 0xFFFF; | |
1753 | ||
1754 | unsigned char event = xferstatus & 0x1F; | |
1755 | ||
1756 | if (!event) { | |
1757 | /* nothing has happened to this block yet */ | |
1758 | break; | |
1759 | } | |
1760 | ||
1761 | if (event != 0x11) { | |
1762 | atomic_inc(&iso->overflows); | |
1763 | PRINT(KERN_ERR, | |
1764 | "IR DMA error - OHCI error code 0x%02x\n", event); | |
1765 | } | |
1766 | ||
1767 | if (rescount != 0) { | |
1768 | /* the card is still writing to this block; | |
1769 | we can't touch it until it's done */ | |
1770 | break; | |
1771 | } | |
1772 | ||
1773 | /* OK, the block is finished... */ | |
1774 | ||
1775 | /* sync our view of the block */ | |
1776 | dma_region_sync_for_cpu(&iso->data_buf, recv->block_dma*recv->buf_stride, recv->buf_stride); | |
1777 | ||
1778 | /* reset the DMA descriptor */ | |
1779 | im->status = recv->buf_stride; | |
1780 | ||
1781 | /* advance block_dma */ | |
1782 | recv->block_dma = (recv->block_dma + 1) % recv->nblocks; | |
1783 | ||
1784 | if ((recv->block_dma+1) % recv->nblocks == recv->block_reader) { | |
1785 | atomic_inc(&iso->overflows); | |
1786 | DBGMSG("ISO reception overflow - " | |
1787 | "ran out of DMA blocks"); | |
1788 | } | |
1789 | } | |
1790 | ||
1791 | /* parse any packets that have arrived */ | |
1792 | ohci_iso_recv_bufferfill_parse(iso, recv); | |
1793 | } | |
1794 | ||
1795 | static void ohci_iso_recv_packetperbuf_task(struct hpsb_iso *iso, struct ohci_iso_recv *recv) | |
1796 | { | |
1797 | int count; | |
1798 | int wake = 0; | |
1799 | struct ti_ohci *ohci = recv->ohci; | |
1800 | ||
1801 | /* loop over the entire buffer */ | |
1802 | for (count = 0; count < recv->nblocks; count++) { | |
1803 | u32 packet_len = 0; | |
1804 | ||
1805 | /* pointer to the DMA descriptor */ | |
1806 | struct dma_cmd *il = ((struct dma_cmd*) recv->prog.kvirt) + iso->pkt_dma; | |
1807 | ||
1808 | /* check the DMA descriptor for new writes to xferStatus */ | |
1809 | u16 xferstatus = le32_to_cpu(il->status) >> 16; | |
1810 | u16 rescount = le32_to_cpu(il->status) & 0xFFFF; | |
1811 | ||
1812 | unsigned char event = xferstatus & 0x1F; | |
1813 | ||
1814 | if (!event) { | |
1815 | /* this packet hasn't come in yet; we are done for now */ | |
1816 | goto out; | |
1817 | } | |
1818 | ||
1819 | if (event == 0x11) { | |
1820 | /* packet received successfully! */ | |
1821 | ||
1822 | /* rescount is the number of bytes *remaining* in the packet buffer, | |
1823 | after the packet was written */ | |
1824 | packet_len = recv->buf_stride - rescount; | |
1825 | ||
1826 | } else if (event == 0x02) { | |
1827 | PRINT(KERN_ERR, "IR DMA error - packet too long for buffer\n"); | |
1828 | } else if (event) { | |
1829 | PRINT(KERN_ERR, "IR DMA error - OHCI error code 0x%02x\n", event); | |
1830 | } | |
1831 | ||
1832 | /* sync our view of the buffer */ | |
1833 | dma_region_sync_for_cpu(&iso->data_buf, iso->pkt_dma * recv->buf_stride, recv->buf_stride); | |
1834 | ||
1835 | /* record the per-packet info */ | |
1836 | { | |
1837 | /* iso header is 8 bytes ahead of the data payload */ | |
1838 | unsigned char *hdr; | |
1839 | ||
1840 | unsigned int offset; | |
1841 | unsigned short cycle; | |
1842 | unsigned char channel, tag, sy; | |
1843 | ||
1844 | offset = iso->pkt_dma * recv->buf_stride; | |
1845 | hdr = iso->data_buf.kvirt + offset; | |
1846 | ||
1847 | /* skip iso header */ | |
1848 | offset += 8; | |
1849 | packet_len -= 8; | |
1850 | ||
1851 | cycle = (hdr[0] | (hdr[1] << 8)) & 0x1FFF; | |
1852 | channel = hdr[5] & 0x3F; | |
1853 | tag = hdr[5] >> 6; | |
1854 | sy = hdr[4] & 0xF; | |
1855 | ||
1934b8b6 BC |
1856 | hpsb_iso_packet_received(iso, offset, packet_len, |
1857 | recv->buf_stride, cycle, channel, tag, sy); | |
1da177e4 LT |
1858 | } |
1859 | ||
1860 | /* reset the DMA descriptor */ | |
1861 | il->status = recv->buf_stride; | |
1862 | ||
1863 | wake = 1; | |
1864 | recv->block_dma = iso->pkt_dma; | |
1865 | } | |
1866 | ||
1867 | out: | |
1868 | if (wake) | |
1869 | hpsb_iso_wake(iso); | |
1870 | } | |
1871 | ||
1872 | static void ohci_iso_recv_task(unsigned long data) | |
1873 | { | |
1874 | struct hpsb_iso *iso = (struct hpsb_iso*) data; | |
1875 | struct ohci_iso_recv *recv = iso->hostdata; | |
1876 | ||
1877 | if (recv->dma_mode == BUFFER_FILL_MODE) | |
1878 | ohci_iso_recv_bufferfill_task(iso, recv); | |
1879 | else | |
1880 | ohci_iso_recv_packetperbuf_task(iso, recv); | |
1881 | } | |
1882 | ||
1883 | /*********************************** | |
1884 | * rawiso ISO transmission * | |
1885 | ***********************************/ | |
1886 | ||
1887 | struct ohci_iso_xmit { | |
1888 | struct ti_ohci *ohci; | |
1889 | struct dma_prog_region prog; | |
1890 | struct ohci1394_iso_tasklet task; | |
1891 | int task_active; | |
1892 | ||
1893 | u32 ContextControlSet; | |
1894 | u32 ContextControlClear; | |
1895 | u32 CommandPtr; | |
1896 | }; | |
1897 | ||
1898 | /* transmission DMA program: | |
1899 | one OUTPUT_MORE_IMMEDIATE for the IT header | |
1900 | one OUTPUT_LAST for the buffer data */ | |
1901 | ||
1902 | struct iso_xmit_cmd { | |
1903 | struct dma_cmd output_more_immediate; | |
1904 | u8 iso_hdr[8]; | |
1905 | u32 unused[2]; | |
1906 | struct dma_cmd output_last; | |
1907 | }; | |
1908 | ||
1909 | static int ohci_iso_xmit_init(struct hpsb_iso *iso); | |
1910 | static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle); | |
1911 | static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso); | |
1912 | static void ohci_iso_xmit_task(unsigned long data); | |
1913 | ||
1914 | static int ohci_iso_xmit_init(struct hpsb_iso *iso) | |
1915 | { | |
1916 | struct ohci_iso_xmit *xmit; | |
1917 | unsigned int prog_size; | |
1918 | int ctx; | |
1919 | int ret = -ENOMEM; | |
1920 | ||
1921 | xmit = kmalloc(sizeof(*xmit), SLAB_KERNEL); | |
1922 | if (!xmit) | |
1923 | return -ENOMEM; | |
1924 | ||
1925 | iso->hostdata = xmit; | |
1926 | xmit->ohci = iso->host->hostdata; | |
1927 | xmit->task_active = 0; | |
1928 | ||
1929 | dma_prog_region_init(&xmit->prog); | |
1930 | ||
1931 | prog_size = sizeof(struct iso_xmit_cmd) * iso->buf_packets; | |
1932 | ||
1933 | if (dma_prog_region_alloc(&xmit->prog, prog_size, xmit->ohci->dev)) | |
1934 | goto err; | |
1935 | ||
1936 | ohci1394_init_iso_tasklet(&xmit->task, OHCI_ISO_TRANSMIT, | |
1937 | ohci_iso_xmit_task, (unsigned long) iso); | |
1938 | ||
e4ec0f23 JM |
1939 | if (ohci1394_register_iso_tasklet(xmit->ohci, &xmit->task) < 0) { |
1940 | ret = -EBUSY; | |
1da177e4 | 1941 | goto err; |
e4ec0f23 | 1942 | } |
1da177e4 LT |
1943 | |
1944 | xmit->task_active = 1; | |
1945 | ||
1946 | /* xmit context registers are spaced 16 bytes apart */ | |
1947 | ctx = xmit->task.context; | |
1948 | xmit->ContextControlSet = OHCI1394_IsoXmitContextControlSet + 16 * ctx; | |
1949 | xmit->ContextControlClear = OHCI1394_IsoXmitContextControlClear + 16 * ctx; | |
1950 | xmit->CommandPtr = OHCI1394_IsoXmitCommandPtr + 16 * ctx; | |
1951 | ||
1952 | return 0; | |
1953 | ||
1954 | err: | |
1955 | ohci_iso_xmit_shutdown(iso); | |
1956 | return ret; | |
1957 | } | |
1958 | ||
1959 | static void ohci_iso_xmit_stop(struct hpsb_iso *iso) | |
1960 | { | |
1961 | struct ohci_iso_xmit *xmit = iso->hostdata; | |
1962 | struct ti_ohci *ohci = xmit->ohci; | |
1963 | ||
1964 | /* disable interrupts */ | |
1965 | reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskClear, 1 << xmit->task.context); | |
1966 | ||
1967 | /* halt DMA */ | |
1968 | if (ohci1394_stop_context(xmit->ohci, xmit->ContextControlClear, NULL)) { | |
1969 | /* XXX the DMA context will lock up if you try to send too much data! */ | |
1970 | PRINT(KERN_ERR, | |
1971 | "you probably exceeded the OHCI card's bandwidth limit - " | |
1972 | "reload the module and reduce xmit bandwidth"); | |
1973 | } | |
1974 | } | |
1975 | ||
1976 | static void ohci_iso_xmit_shutdown(struct hpsb_iso *iso) | |
1977 | { | |
1978 | struct ohci_iso_xmit *xmit = iso->hostdata; | |
1979 | ||
1980 | if (xmit->task_active) { | |
1981 | ohci_iso_xmit_stop(iso); | |
1982 | ohci1394_unregister_iso_tasklet(xmit->ohci, &xmit->task); | |
1983 | xmit->task_active = 0; | |
1984 | } | |
1985 | ||
1986 | dma_prog_region_free(&xmit->prog); | |
1987 | kfree(xmit); | |
1988 | iso->hostdata = NULL; | |
1989 | } | |
1990 | ||
1991 | static void ohci_iso_xmit_task(unsigned long data) | |
1992 | { | |
1993 | struct hpsb_iso *iso = (struct hpsb_iso*) data; | |
1994 | struct ohci_iso_xmit *xmit = iso->hostdata; | |
1995 | struct ti_ohci *ohci = xmit->ohci; | |
1996 | int wake = 0; | |
1997 | int count; | |
1998 | ||
1999 | /* check the whole buffer if necessary, starting at pkt_dma */ | |
2000 | for (count = 0; count < iso->buf_packets; count++) { | |
2001 | int cycle; | |
2002 | ||
2003 | /* DMA descriptor */ | |
2004 | struct iso_xmit_cmd *cmd = dma_region_i(&xmit->prog, struct iso_xmit_cmd, iso->pkt_dma); | |
2005 | ||
2006 | /* check for new writes to xferStatus */ | |
2007 | u16 xferstatus = le32_to_cpu(cmd->output_last.status) >> 16; | |
2008 | u8 event = xferstatus & 0x1F; | |
2009 | ||
2010 | if (!event) { | |
2011 | /* packet hasn't been sent yet; we are done for now */ | |
2012 | break; | |
2013 | } | |
2014 | ||
2015 | if (event != 0x11) | |
2016 | PRINT(KERN_ERR, | |
2017 | "IT DMA error - OHCI error code 0x%02x\n", event); | |
2018 | ||
2019 | /* at least one packet went out, so wake up the writer */ | |
2020 | wake = 1; | |
2021 | ||
2022 | /* parse cycle */ | |
2023 | cycle = le32_to_cpu(cmd->output_last.status) & 0x1FFF; | |
2024 | ||
2025 | /* tell the subsystem the packet has gone out */ | |
2026 | hpsb_iso_packet_sent(iso, cycle, event != 0x11); | |
2027 | ||
2028 | /* reset the DMA descriptor for next time */ | |
2029 | cmd->output_last.status = 0; | |
2030 | } | |
2031 | ||
2032 | if (wake) | |
2033 | hpsb_iso_wake(iso); | |
2034 | } | |
2035 | ||
2036 | static int ohci_iso_xmit_queue(struct hpsb_iso *iso, struct hpsb_iso_packet_info *info) | |
2037 | { | |
2038 | struct ohci_iso_xmit *xmit = iso->hostdata; | |
2039 | struct ti_ohci *ohci = xmit->ohci; | |
2040 | ||
2041 | int next_i, prev_i; | |
2042 | struct iso_xmit_cmd *next, *prev; | |
2043 | ||
2044 | unsigned int offset; | |
2045 | unsigned short len; | |
2046 | unsigned char tag, sy; | |
2047 | ||
2048 | /* check that the packet doesn't cross a page boundary | |
2049 | (we could allow this if we added OUTPUT_MORE descriptor support) */ | |
2050 | if (cross_bound(info->offset, info->len)) { | |
2051 | PRINT(KERN_ERR, | |
2052 | "rawiso xmit: packet %u crosses a page boundary", | |
2053 | iso->first_packet); | |
2054 | return -EINVAL; | |
2055 | } | |
2056 | ||
2057 | offset = info->offset; | |
2058 | len = info->len; | |
2059 | tag = info->tag; | |
2060 | sy = info->sy; | |
2061 | ||
2062 | /* sync up the card's view of the buffer */ | |
2063 | dma_region_sync_for_device(&iso->data_buf, offset, len); | |
2064 | ||
2065 | /* append first_packet to the DMA chain */ | |
2066 | /* by linking the previous descriptor to it */ | |
2067 | /* (next will become the new end of the DMA chain) */ | |
2068 | ||
2069 | next_i = iso->first_packet; | |
2070 | prev_i = (next_i == 0) ? (iso->buf_packets - 1) : (next_i - 1); | |
2071 | ||
2072 | next = dma_region_i(&xmit->prog, struct iso_xmit_cmd, next_i); | |
2073 | prev = dma_region_i(&xmit->prog, struct iso_xmit_cmd, prev_i); | |
2074 | ||
2075 | /* set up the OUTPUT_MORE_IMMEDIATE descriptor */ | |
2076 | memset(next, 0, sizeof(struct iso_xmit_cmd)); | |
2077 | next->output_more_immediate.control = cpu_to_le32(0x02000008); | |
2078 | ||
2079 | /* ISO packet header is embedded in the OUTPUT_MORE_IMMEDIATE */ | |
2080 | ||
2081 | /* tcode = 0xA, and sy */ | |
2082 | next->iso_hdr[0] = 0xA0 | (sy & 0xF); | |
2083 | ||
2084 | /* tag and channel number */ | |
2085 | next->iso_hdr[1] = (tag << 6) | (iso->channel & 0x3F); | |
2086 | ||
2087 | /* transmission speed */ | |
2088 | next->iso_hdr[2] = iso->speed & 0x7; | |
2089 | ||
2090 | /* payload size */ | |
2091 | next->iso_hdr[6] = len & 0xFF; | |
2092 | next->iso_hdr[7] = len >> 8; | |
2093 | ||
2094 | /* set up the OUTPUT_LAST */ | |
2095 | next->output_last.control = cpu_to_le32(1 << 28); | |
2096 | next->output_last.control |= cpu_to_le32(1 << 27); /* update timeStamp */ | |
2097 | next->output_last.control |= cpu_to_le32(3 << 20); /* want interrupt */ | |
2098 | next->output_last.control |= cpu_to_le32(3 << 18); /* enable branch */ | |
2099 | next->output_last.control |= cpu_to_le32(len); | |
2100 | ||
2101 | /* payload bus address */ | |
2102 | next->output_last.address = cpu_to_le32(dma_region_offset_to_bus(&iso->data_buf, offset)); | |
2103 | ||
2104 | /* leave branchAddress at zero for now */ | |
2105 | ||
2106 | /* re-write the previous DMA descriptor to chain to this one */ | |
2107 | ||
2108 | /* set prev branch address to point to next (Z=3) */ | |
2109 | prev->output_last.branchAddress = cpu_to_le32( | |
2110 | dma_prog_region_offset_to_bus(&xmit->prog, sizeof(struct iso_xmit_cmd) * next_i) | 3); | |
2111 | ||
2112 | /* disable interrupt, unless required by the IRQ interval */ | |
2113 | if (prev_i % iso->irq_interval) { | |
2114 | prev->output_last.control &= cpu_to_le32(~(3 << 20)); /* no interrupt */ | |
2115 | } else { | |
2116 | prev->output_last.control |= cpu_to_le32(3 << 20); /* enable interrupt */ | |
2117 | } | |
2118 | ||
2119 | wmb(); | |
2120 | ||
2121 | /* wake DMA in case it is sleeping */ | |
2122 | reg_write(xmit->ohci, xmit->ContextControlSet, 1 << 12); | |
2123 | ||
2124 | /* issue a dummy read of the cycle timer to force all PCI | |
2125 | writes to be posted immediately */ | |
2126 | mb(); | |
2127 | reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer); | |
2128 | ||
2129 | return 0; | |
2130 | } | |
2131 | ||
2132 | static int ohci_iso_xmit_start(struct hpsb_iso *iso, int cycle) | |
2133 | { | |
2134 | struct ohci_iso_xmit *xmit = iso->hostdata; | |
2135 | struct ti_ohci *ohci = xmit->ohci; | |
2136 | ||
2137 | /* clear out the control register */ | |
2138 | reg_write(xmit->ohci, xmit->ContextControlClear, 0xFFFFFFFF); | |
2139 | wmb(); | |
2140 | ||
2141 | /* address and length of first descriptor block (Z=3) */ | |
2142 | reg_write(xmit->ohci, xmit->CommandPtr, | |
2143 | dma_prog_region_offset_to_bus(&xmit->prog, iso->pkt_dma * sizeof(struct iso_xmit_cmd)) | 3); | |
2144 | ||
2145 | /* cycle match */ | |
2146 | if (cycle != -1) { | |
2147 | u32 start = cycle & 0x1FFF; | |
2148 | ||
2149 | /* 'cycle' is only mod 8000, but we also need two 'seconds' bits - | |
2150 | just snarf them from the current time */ | |
2151 | u32 seconds = reg_read(xmit->ohci, OHCI1394_IsochronousCycleTimer) >> 25; | |
2152 | ||
2153 | /* advance one second to give some extra time for DMA to start */ | |
2154 | seconds += 1; | |
2155 | ||
2156 | start |= (seconds & 3) << 13; | |
2157 | ||
2158 | reg_write(xmit->ohci, xmit->ContextControlSet, 0x80000000 | (start << 16)); | |
2159 | } | |
2160 | ||
2161 | /* enable interrupts */ | |
2162 | reg_write(xmit->ohci, OHCI1394_IsoXmitIntMaskSet, 1 << xmit->task.context); | |
2163 | ||
2164 | /* run */ | |
2165 | reg_write(xmit->ohci, xmit->ContextControlSet, 0x8000); | |
2166 | mb(); | |
2167 | ||
2168 | /* wait 100 usec to give the card time to go active */ | |
2169 | udelay(100); | |
2170 | ||
2171 | /* check the RUN bit */ | |
2172 | if (!(reg_read(xmit->ohci, xmit->ContextControlSet) & 0x8000)) { | |
2173 | PRINT(KERN_ERR, "Error starting IT DMA (ContextControl 0x%08x)\n", | |
2174 | reg_read(xmit->ohci, xmit->ContextControlSet)); | |
2175 | return -1; | |
2176 | } | |
2177 | ||
2178 | return 0; | |
2179 | } | |
2180 | ||
2181 | static int ohci_isoctl(struct hpsb_iso *iso, enum isoctl_cmd cmd, unsigned long arg) | |
2182 | { | |
2183 | ||
2184 | switch(cmd) { | |
2185 | case XMIT_INIT: | |
2186 | return ohci_iso_xmit_init(iso); | |
2187 | case XMIT_START: | |
2188 | return ohci_iso_xmit_start(iso, arg); | |
2189 | case XMIT_STOP: | |
2190 | ohci_iso_xmit_stop(iso); | |
2191 | return 0; | |
2192 | case XMIT_QUEUE: | |
2193 | return ohci_iso_xmit_queue(iso, (struct hpsb_iso_packet_info*) arg); | |
2194 | case XMIT_SHUTDOWN: | |
2195 | ohci_iso_xmit_shutdown(iso); | |
2196 | return 0; | |
2197 | ||
2198 | case RECV_INIT: | |
2199 | return ohci_iso_recv_init(iso); | |
2200 | case RECV_START: { | |
2201 | int *args = (int*) arg; | |
2202 | return ohci_iso_recv_start(iso, args[0], args[1], args[2]); | |
2203 | } | |
2204 | case RECV_STOP: | |
2205 | ohci_iso_recv_stop(iso); | |
2206 | return 0; | |
2207 | case RECV_RELEASE: | |
2208 | ohci_iso_recv_release(iso, (struct hpsb_iso_packet_info*) arg); | |
2209 | return 0; | |
2210 | case RECV_FLUSH: | |
2211 | ohci_iso_recv_task((unsigned long) iso); | |
2212 | return 0; | |
2213 | case RECV_SHUTDOWN: | |
2214 | ohci_iso_recv_shutdown(iso); | |
2215 | return 0; | |
2216 | case RECV_LISTEN_CHANNEL: | |
2217 | ohci_iso_recv_change_channel(iso, arg, 1); | |
2218 | return 0; | |
2219 | case RECV_UNLISTEN_CHANNEL: | |
2220 | ohci_iso_recv_change_channel(iso, arg, 0); | |
2221 | return 0; | |
2222 | case RECV_SET_CHANNEL_MASK: | |
2223 | ohci_iso_recv_set_channel_mask(iso, *((u64*) arg)); | |
2224 | return 0; | |
2225 | ||
2226 | default: | |
2227 | PRINT_G(KERN_ERR, "ohci_isoctl cmd %d not implemented yet", | |
2228 | cmd); | |
2229 | break; | |
2230 | } | |
2231 | return -EINVAL; | |
2232 | } | |
2233 | ||
2234 | /*************************************** | |
2235 | * IEEE-1394 functionality section END * | |
2236 | ***************************************/ | |
2237 | ||
2238 | ||
2239 | /******************************************************** | |
2240 | * Global stuff (interrupt handler, init/shutdown code) * | |
2241 | ********************************************************/ | |
2242 | ||
2243 | static void dma_trm_reset(struct dma_trm_ctx *d) | |
2244 | { | |
2245 | unsigned long flags; | |
2246 | LIST_HEAD(packet_list); | |
2247 | struct ti_ohci *ohci = d->ohci; | |
2248 | struct hpsb_packet *packet, *ptmp; | |
2249 | ||
2250 | ohci1394_stop_context(ohci, d->ctrlClear, NULL); | |
2251 | ||
2252 | /* Lock the context, reset it and release it. Move the packets | |
2253 | * that were pending in the context to packet_list and free | |
2254 | * them after releasing the lock. */ | |
2255 | ||
2256 | spin_lock_irqsave(&d->lock, flags); | |
2257 | ||
2258 | list_splice(&d->fifo_list, &packet_list); | |
2259 | list_splice(&d->pending_list, &packet_list); | |
2260 | INIT_LIST_HEAD(&d->fifo_list); | |
2261 | INIT_LIST_HEAD(&d->pending_list); | |
2262 | ||
2263 | d->branchAddrPtr = NULL; | |
2264 | d->sent_ind = d->prg_ind; | |
2265 | d->free_prgs = d->num_desc; | |
2266 | ||
2267 | spin_unlock_irqrestore(&d->lock, flags); | |
2268 | ||
2269 | if (list_empty(&packet_list)) | |
2270 | return; | |
2271 | ||
2272 | PRINT(KERN_INFO, "AT dma reset ctx=%d, aborting transmission", d->ctx); | |
2273 | ||
2274 | /* Now process subsystem callbacks for the packets from this | |
2275 | * context. */ | |
2276 | list_for_each_entry_safe(packet, ptmp, &packet_list, driver_list) { | |
2277 | list_del_init(&packet->driver_list); | |
2278 | hpsb_packet_sent(ohci->host, packet, ACKX_ABORTED); | |
2279 | } | |
2280 | } | |
2281 | ||
2282 | static void ohci_schedule_iso_tasklets(struct ti_ohci *ohci, | |
2283 | quadlet_t rx_event, | |
2284 | quadlet_t tx_event) | |
2285 | { | |
2286 | struct ohci1394_iso_tasklet *t; | |
2287 | unsigned long mask; | |
4a9949d7 | 2288 | unsigned long flags; |
1da177e4 | 2289 | |
4a9949d7 | 2290 | spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags); |
1da177e4 LT |
2291 | |
2292 | list_for_each_entry(t, &ohci->iso_tasklet_list, link) { | |
2293 | mask = 1 << t->context; | |
2294 | ||
2295 | if (t->type == OHCI_ISO_TRANSMIT && tx_event & mask) | |
2296 | tasklet_schedule(&t->tasklet); | |
2297 | else if (rx_event & mask) | |
2298 | tasklet_schedule(&t->tasklet); | |
2299 | } | |
2300 | ||
4a9949d7 | 2301 | spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags); |
1da177e4 LT |
2302 | } |
2303 | ||
7d12e780 | 2304 | static irqreturn_t ohci_irq_handler(int irq, void *dev_id) |
1da177e4 LT |
2305 | { |
2306 | quadlet_t event, node_id; | |
2307 | struct ti_ohci *ohci = (struct ti_ohci *)dev_id; | |
2308 | struct hpsb_host *host = ohci->host; | |
2309 | int phyid = -1, isroot = 0; | |
2310 | unsigned long flags; | |
2311 | ||
2312 | /* Read and clear the interrupt event register. Don't clear | |
2313 | * the busReset event, though. This is done when we get the | |
2314 | * selfIDComplete interrupt. */ | |
2315 | spin_lock_irqsave(&ohci->event_lock, flags); | |
2316 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
2317 | reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset); | |
2318 | spin_unlock_irqrestore(&ohci->event_lock, flags); | |
2319 | ||
2320 | if (!event) | |
2321 | return IRQ_NONE; | |
2322 | ||
2323 | /* If event is ~(u32)0 cardbus card was ejected. In this case | |
2324 | * we just return, and clean up in the ohci1394_pci_remove | |
2325 | * function. */ | |
2326 | if (event == ~(u32) 0) { | |
2327 | DBGMSG("Device removed."); | |
2328 | return IRQ_NONE; | |
2329 | } | |
2330 | ||
2331 | DBGMSG("IntEvent: %08x", event); | |
2332 | ||
2333 | if (event & OHCI1394_unrecoverableError) { | |
2334 | int ctx; | |
2335 | PRINT(KERN_ERR, "Unrecoverable error!"); | |
2336 | ||
2337 | if (reg_read(ohci, OHCI1394_AsReqTrContextControlSet) & 0x800) | |
2338 | PRINT(KERN_ERR, "Async Req Tx Context died: " | |
2339 | "ctrl[%08x] cmdptr[%08x]", | |
2340 | reg_read(ohci, OHCI1394_AsReqTrContextControlSet), | |
2341 | reg_read(ohci, OHCI1394_AsReqTrCommandPtr)); | |
2342 | ||
2343 | if (reg_read(ohci, OHCI1394_AsRspTrContextControlSet) & 0x800) | |
2344 | PRINT(KERN_ERR, "Async Rsp Tx Context died: " | |
2345 | "ctrl[%08x] cmdptr[%08x]", | |
2346 | reg_read(ohci, OHCI1394_AsRspTrContextControlSet), | |
2347 | reg_read(ohci, OHCI1394_AsRspTrCommandPtr)); | |
2348 | ||
2349 | if (reg_read(ohci, OHCI1394_AsReqRcvContextControlSet) & 0x800) | |
2350 | PRINT(KERN_ERR, "Async Req Rcv Context died: " | |
2351 | "ctrl[%08x] cmdptr[%08x]", | |
2352 | reg_read(ohci, OHCI1394_AsReqRcvContextControlSet), | |
2353 | reg_read(ohci, OHCI1394_AsReqRcvCommandPtr)); | |
2354 | ||
2355 | if (reg_read(ohci, OHCI1394_AsRspRcvContextControlSet) & 0x800) | |
2356 | PRINT(KERN_ERR, "Async Rsp Rcv Context died: " | |
2357 | "ctrl[%08x] cmdptr[%08x]", | |
2358 | reg_read(ohci, OHCI1394_AsRspRcvContextControlSet), | |
2359 | reg_read(ohci, OHCI1394_AsRspRcvCommandPtr)); | |
2360 | ||
2361 | for (ctx = 0; ctx < ohci->nb_iso_xmit_ctx; ctx++) { | |
2362 | if (reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)) & 0x800) | |
2363 | PRINT(KERN_ERR, "Iso Xmit %d Context died: " | |
2364 | "ctrl[%08x] cmdptr[%08x]", ctx, | |
2365 | reg_read(ohci, OHCI1394_IsoXmitContextControlSet + (16 * ctx)), | |
2366 | reg_read(ohci, OHCI1394_IsoXmitCommandPtr + (16 * ctx))); | |
2367 | } | |
2368 | ||
2369 | for (ctx = 0; ctx < ohci->nb_iso_rcv_ctx; ctx++) { | |
2370 | if (reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)) & 0x800) | |
2371 | PRINT(KERN_ERR, "Iso Recv %d Context died: " | |
2372 | "ctrl[%08x] cmdptr[%08x] match[%08x]", ctx, | |
2373 | reg_read(ohci, OHCI1394_IsoRcvContextControlSet + (32 * ctx)), | |
2374 | reg_read(ohci, OHCI1394_IsoRcvCommandPtr + (32 * ctx)), | |
2375 | reg_read(ohci, OHCI1394_IsoRcvContextMatch + (32 * ctx))); | |
2376 | } | |
2377 | ||
2378 | event &= ~OHCI1394_unrecoverableError; | |
2379 | } | |
e2f8165d JM |
2380 | if (event & OHCI1394_postedWriteErr) { |
2381 | PRINT(KERN_ERR, "physical posted write error"); | |
2382 | /* no recovery strategy yet, had to involve protocol drivers */ | |
2383 | } | |
57fdb58f BC |
2384 | if (event & OHCI1394_cycleTooLong) { |
2385 | if(printk_ratelimit()) | |
2386 | PRINT(KERN_WARNING, "isochronous cycle too long"); | |
2387 | else | |
2388 | DBGMSG("OHCI1394_cycleTooLong"); | |
2389 | reg_write(ohci, OHCI1394_LinkControlSet, | |
2390 | OHCI1394_LinkControl_CycleMaster); | |
2391 | event &= ~OHCI1394_cycleTooLong; | |
2392 | } | |
1da177e4 LT |
2393 | if (event & OHCI1394_cycleInconsistent) { |
2394 | /* We subscribe to the cycleInconsistent event only to | |
2395 | * clear the corresponding event bit... otherwise, | |
2396 | * isochronous cycleMatch DMA won't work. */ | |
2397 | DBGMSG("OHCI1394_cycleInconsistent"); | |
2398 | event &= ~OHCI1394_cycleInconsistent; | |
2399 | } | |
1da177e4 LT |
2400 | if (event & OHCI1394_busReset) { |
2401 | /* The busReset event bit can't be cleared during the | |
2402 | * selfID phase, so we disable busReset interrupts, to | |
2403 | * avoid burying the cpu in interrupt requests. */ | |
2404 | spin_lock_irqsave(&ohci->event_lock, flags); | |
2405 | reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset); | |
2406 | ||
2407 | if (ohci->check_busreset) { | |
2408 | int loop_count = 0; | |
2409 | ||
2410 | udelay(10); | |
2411 | ||
2412 | while (reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { | |
2413 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); | |
2414 | ||
2415 | spin_unlock_irqrestore(&ohci->event_lock, flags); | |
2416 | udelay(10); | |
2417 | spin_lock_irqsave(&ohci->event_lock, flags); | |
2418 | ||
2419 | /* The loop counter check is to prevent the driver | |
2420 | * from remaining in this state forever. For the | |
2421 | * initial bus reset, the loop continues for ever | |
2422 | * and the system hangs, until some device is plugged-in | |
2423 | * or out manually into a port! The forced reset seems | |
2424 | * to solve this problem. This mainly effects nForce2. */ | |
2425 | if (loop_count > 10000) { | |
2426 | ohci_devctl(host, RESET_BUS, LONG_RESET); | |
2427 | DBGMSG("Detected bus-reset loop. Forced a bus reset!"); | |
2428 | loop_count = 0; | |
2429 | } | |
2430 | ||
2431 | loop_count++; | |
2432 | } | |
2433 | } | |
2434 | spin_unlock_irqrestore(&ohci->event_lock, flags); | |
2435 | if (!host->in_bus_reset) { | |
2436 | DBGMSG("irq_handler: Bus reset requested"); | |
2437 | ||
2438 | /* Subsystem call */ | |
2439 | hpsb_bus_reset(ohci->host); | |
2440 | } | |
2441 | event &= ~OHCI1394_busReset; | |
2442 | } | |
1da177e4 LT |
2443 | if (event & OHCI1394_reqTxComplete) { |
2444 | struct dma_trm_ctx *d = &ohci->at_req_context; | |
2445 | DBGMSG("Got reqTxComplete interrupt " | |
2446 | "status=0x%08X", reg_read(ohci, d->ctrlSet)); | |
2447 | if (reg_read(ohci, d->ctrlSet) & 0x800) | |
2448 | ohci1394_stop_context(ohci, d->ctrlClear, | |
2449 | "reqTxComplete"); | |
2450 | else | |
2451 | dma_trm_tasklet((unsigned long)d); | |
2452 | //tasklet_schedule(&d->task); | |
2453 | event &= ~OHCI1394_reqTxComplete; | |
2454 | } | |
2455 | if (event & OHCI1394_respTxComplete) { | |
2456 | struct dma_trm_ctx *d = &ohci->at_resp_context; | |
2457 | DBGMSG("Got respTxComplete interrupt " | |
2458 | "status=0x%08X", reg_read(ohci, d->ctrlSet)); | |
2459 | if (reg_read(ohci, d->ctrlSet) & 0x800) | |
2460 | ohci1394_stop_context(ohci, d->ctrlClear, | |
2461 | "respTxComplete"); | |
2462 | else | |
2463 | tasklet_schedule(&d->task); | |
2464 | event &= ~OHCI1394_respTxComplete; | |
2465 | } | |
2466 | if (event & OHCI1394_RQPkt) { | |
2467 | struct dma_rcv_ctx *d = &ohci->ar_req_context; | |
2468 | DBGMSG("Got RQPkt interrupt status=0x%08X", | |
2469 | reg_read(ohci, d->ctrlSet)); | |
2470 | if (reg_read(ohci, d->ctrlSet) & 0x800) | |
2471 | ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt"); | |
2472 | else | |
2473 | tasklet_schedule(&d->task); | |
2474 | event &= ~OHCI1394_RQPkt; | |
2475 | } | |
2476 | if (event & OHCI1394_RSPkt) { | |
2477 | struct dma_rcv_ctx *d = &ohci->ar_resp_context; | |
2478 | DBGMSG("Got RSPkt interrupt status=0x%08X", | |
2479 | reg_read(ohci, d->ctrlSet)); | |
2480 | if (reg_read(ohci, d->ctrlSet) & 0x800) | |
2481 | ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt"); | |
2482 | else | |
2483 | tasklet_schedule(&d->task); | |
2484 | event &= ~OHCI1394_RSPkt; | |
2485 | } | |
2486 | if (event & OHCI1394_isochRx) { | |
2487 | quadlet_t rx_event; | |
2488 | ||
2489 | rx_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet); | |
2490 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, rx_event); | |
2491 | ohci_schedule_iso_tasklets(ohci, rx_event, 0); | |
2492 | event &= ~OHCI1394_isochRx; | |
2493 | } | |
2494 | if (event & OHCI1394_isochTx) { | |
2495 | quadlet_t tx_event; | |
2496 | ||
2497 | tx_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet); | |
2498 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, tx_event); | |
2499 | ohci_schedule_iso_tasklets(ohci, 0, tx_event); | |
2500 | event &= ~OHCI1394_isochTx; | |
2501 | } | |
2502 | if (event & OHCI1394_selfIDComplete) { | |
2503 | if (host->in_bus_reset) { | |
2504 | node_id = reg_read(ohci, OHCI1394_NodeID); | |
2505 | ||
2506 | if (!(node_id & 0x80000000)) { | |
2507 | PRINT(KERN_ERR, | |
2508 | "SelfID received, but NodeID invalid " | |
2509 | "(probably new bus reset occurred): %08X", | |
2510 | node_id); | |
2511 | goto selfid_not_valid; | |
2512 | } | |
2513 | ||
2514 | phyid = node_id & 0x0000003f; | |
2515 | isroot = (node_id & 0x40000000) != 0; | |
2516 | ||
2517 | DBGMSG("SelfID interrupt received " | |
2518 | "(phyid %d, %s)", phyid, | |
2519 | (isroot ? "root" : "not root")); | |
2520 | ||
2521 | handle_selfid(ohci, host, phyid, isroot); | |
2522 | ||
2523 | /* Clear the bus reset event and re-enable the | |
2524 | * busReset interrupt. */ | |
2525 | spin_lock_irqsave(&ohci->event_lock, flags); | |
2526 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); | |
2527 | reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); | |
2528 | spin_unlock_irqrestore(&ohci->event_lock, flags); | |
2529 | ||
1da177e4 LT |
2530 | /* Turn on phys dma reception. |
2531 | * | |
2532 | * TODO: Enable some sort of filtering management. | |
2533 | */ | |
2534 | if (phys_dma) { | |
180a4304 SR |
2535 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, |
2536 | 0xffffffff); | |
2537 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, | |
2538 | 0xffffffff); | |
1da177e4 LT |
2539 | } |
2540 | ||
2541 | DBGMSG("PhyReqFilter=%08x%08x", | |
180a4304 SR |
2542 | reg_read(ohci, OHCI1394_PhyReqFilterHiSet), |
2543 | reg_read(ohci, OHCI1394_PhyReqFilterLoSet)); | |
1da177e4 LT |
2544 | |
2545 | hpsb_selfid_complete(host, phyid, isroot); | |
2546 | } else | |
2547 | PRINT(KERN_ERR, | |
2548 | "SelfID received outside of bus reset sequence"); | |
2549 | ||
2550 | selfid_not_valid: | |
2551 | event &= ~OHCI1394_selfIDComplete; | |
2552 | } | |
2553 | ||
2554 | /* Make sure we handle everything, just in case we accidentally | |
2555 | * enabled an interrupt that we didn't write a handler for. */ | |
2556 | if (event) | |
2557 | PRINT(KERN_ERR, "Unhandled interrupt(s) 0x%08x", | |
2558 | event); | |
2559 | ||
2560 | return IRQ_HANDLED; | |
2561 | } | |
2562 | ||
2563 | /* Put the buffer back into the dma context */ | |
2564 | static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx) | |
2565 | { | |
2566 | struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci); | |
2567 | DBGMSG("Inserting dma buf ctx=%d idx=%d", d->ctx, idx); | |
2568 | ||
2569 | d->prg_cpu[idx]->status = cpu_to_le32(d->buf_size); | |
2570 | d->prg_cpu[idx]->branchAddress &= le32_to_cpu(0xfffffff0); | |
2571 | idx = (idx + d->num_desc - 1 ) % d->num_desc; | |
2572 | d->prg_cpu[idx]->branchAddress |= le32_to_cpu(0x00000001); | |
2573 | ||
2574 | /* To avoid a race, ensure 1394 interface hardware sees the inserted | |
2575 | * context program descriptors before it sees the wakeup bit set. */ | |
2576 | wmb(); | |
2577 | ||
2578 | /* wake up the dma context if necessary */ | |
2579 | if (!(reg_read(ohci, d->ctrlSet) & 0x400)) { | |
2580 | PRINT(KERN_INFO, | |
2581 | "Waking dma ctx=%d ... processing is probably too slow", | |
2582 | d->ctx); | |
2583 | } | |
2584 | ||
2585 | /* do this always, to avoid race condition */ | |
2586 | reg_write(ohci, d->ctrlSet, 0x1000); | |
2587 | } | |
2588 | ||
2589 | #define cond_le32_to_cpu(data, noswap) \ | |
2590 | (noswap ? data : le32_to_cpu(data)) | |
2591 | ||
2592 | static const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0, | |
2593 | -1, 0, -1, 0, -1, -1, 16, -1}; | |
2594 | ||
2595 | /* | |
2596 | * Determine the length of a packet in the buffer | |
2597 | * Optimization suggested by Pascal Drolet <pascal.drolet@informission.ca> | |
2598 | */ | |
2b01b80b SR |
2599 | static inline int packet_length(struct dma_rcv_ctx *d, int idx, |
2600 | quadlet_t *buf_ptr, int offset, | |
2601 | unsigned char tcode, int noswap) | |
1da177e4 LT |
2602 | { |
2603 | int length = -1; | |
2604 | ||
2605 | if (d->type == DMA_CTX_ASYNC_REQ || d->type == DMA_CTX_ASYNC_RESP) { | |
2606 | length = TCODE_SIZE[tcode]; | |
2607 | if (length == 0) { | |
2608 | if (offset + 12 >= d->buf_size) { | |
2609 | length = (cond_le32_to_cpu(d->buf_cpu[(idx + 1) % d->num_desc] | |
2610 | [3 - ((d->buf_size - offset) >> 2)], noswap) >> 16); | |
2611 | } else { | |
2612 | length = (cond_le32_to_cpu(buf_ptr[3], noswap) >> 16); | |
2613 | } | |
2614 | length += 20; | |
2615 | } | |
2616 | } else if (d->type == DMA_CTX_ISO) { | |
2617 | /* Assumption: buffer fill mode with header/trailer */ | |
2618 | length = (cond_le32_to_cpu(buf_ptr[0], noswap) >> 16) + 8; | |
2619 | } | |
2620 | ||
2621 | if (length > 0 && length % 4) | |
2622 | length += 4 - (length % 4); | |
2623 | ||
2624 | return length; | |
2625 | } | |
2626 | ||
2627 | /* Tasklet that processes dma receive buffers */ | |
2628 | static void dma_rcv_tasklet (unsigned long data) | |
2629 | { | |
2630 | struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data; | |
2631 | struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci); | |
2632 | unsigned int split_left, idx, offset, rescount; | |
2633 | unsigned char tcode; | |
2634 | int length, bytes_left, ack; | |
2635 | unsigned long flags; | |
2636 | quadlet_t *buf_ptr; | |
2637 | char *split_ptr; | |
2638 | char msg[256]; | |
2639 | ||
2640 | spin_lock_irqsave(&d->lock, flags); | |
2641 | ||
2642 | idx = d->buf_ind; | |
2643 | offset = d->buf_offset; | |
2644 | buf_ptr = d->buf_cpu[idx] + offset/4; | |
2645 | ||
2646 | rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff; | |
2647 | bytes_left = d->buf_size - rescount - offset; | |
2648 | ||
2649 | while (bytes_left > 0) { | |
2650 | tcode = (cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming) >> 4) & 0xf; | |
2651 | ||
2652 | /* packet_length() will return < 4 for an error */ | |
2653 | length = packet_length(d, idx, buf_ptr, offset, tcode, ohci->no_swap_incoming); | |
2654 | ||
2655 | if (length < 4) { /* something is wrong */ | |
2656 | sprintf(msg,"Unexpected tcode 0x%x(0x%08x) in AR ctx=%d, length=%d", | |
2657 | tcode, cond_le32_to_cpu(buf_ptr[0], ohci->no_swap_incoming), | |
2658 | d->ctx, length); | |
2659 | ohci1394_stop_context(ohci, d->ctrlClear, msg); | |
2660 | spin_unlock_irqrestore(&d->lock, flags); | |
2661 | return; | |
2662 | } | |
2663 | ||
2664 | /* The first case is where we have a packet that crosses | |
2665 | * over more than one descriptor. The next case is where | |
2666 | * it's all in the first descriptor. */ | |
2667 | if ((offset + length) > d->buf_size) { | |
2668 | DBGMSG("Split packet rcv'd"); | |
2669 | if (length > d->split_buf_size) { | |
2670 | ohci1394_stop_context(ohci, d->ctrlClear, | |
2671 | "Split packet size exceeded"); | |
2672 | d->buf_ind = idx; | |
2673 | d->buf_offset = offset; | |
2674 | spin_unlock_irqrestore(&d->lock, flags); | |
2675 | return; | |
2676 | } | |
2677 | ||
2678 | if (le32_to_cpu(d->prg_cpu[(idx+1)%d->num_desc]->status) | |
2679 | == d->buf_size) { | |
2680 | /* Other part of packet not written yet. | |
2681 | * this should never happen I think | |
2682 | * anyway we'll get it on the next call. */ | |
2683 | PRINT(KERN_INFO, | |
2684 | "Got only half a packet!"); | |
2685 | d->buf_ind = idx; | |
2686 | d->buf_offset = offset; | |
2687 | spin_unlock_irqrestore(&d->lock, flags); | |
2688 | return; | |
2689 | } | |
2690 | ||
2691 | split_left = length; | |
2692 | split_ptr = (char *)d->spb; | |
2693 | memcpy(split_ptr,buf_ptr,d->buf_size-offset); | |
2694 | split_left -= d->buf_size-offset; | |
2695 | split_ptr += d->buf_size-offset; | |
2696 | insert_dma_buffer(d, idx); | |
2697 | idx = (idx+1) % d->num_desc; | |
2698 | buf_ptr = d->buf_cpu[idx]; | |
2699 | offset=0; | |
2700 | ||
2701 | while (split_left >= d->buf_size) { | |
2702 | memcpy(split_ptr,buf_ptr,d->buf_size); | |
2703 | split_ptr += d->buf_size; | |
2704 | split_left -= d->buf_size; | |
2705 | insert_dma_buffer(d, idx); | |
2706 | idx = (idx+1) % d->num_desc; | |
2707 | buf_ptr = d->buf_cpu[idx]; | |
2708 | } | |
2709 | ||
2710 | if (split_left > 0) { | |
2711 | memcpy(split_ptr, buf_ptr, split_left); | |
2712 | offset = split_left; | |
2713 | buf_ptr += offset/4; | |
2714 | } | |
2715 | } else { | |
2716 | DBGMSG("Single packet rcv'd"); | |
2717 | memcpy(d->spb, buf_ptr, length); | |
2718 | offset += length; | |
2719 | buf_ptr += length/4; | |
2720 | if (offset==d->buf_size) { | |
2721 | insert_dma_buffer(d, idx); | |
2722 | idx = (idx+1) % d->num_desc; | |
2723 | buf_ptr = d->buf_cpu[idx]; | |
2724 | offset=0; | |
2725 | } | |
2726 | } | |
2727 | ||
2728 | /* We get one phy packet to the async descriptor for each | |
2729 | * bus reset. We always ignore it. */ | |
2730 | if (tcode != OHCI1394_TCODE_PHY) { | |
2731 | if (!ohci->no_swap_incoming) | |
9531f13a | 2732 | header_le32_to_cpu(d->spb, tcode); |
1da177e4 LT |
2733 | DBGMSG("Packet received from node" |
2734 | " %d ack=0x%02X spd=%d tcode=0x%X" | |
2735 | " length=%d ctx=%d tlabel=%d", | |
2736 | (d->spb[1]>>16)&0x3f, | |
2737 | (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f, | |
2738 | (cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>21)&0x3, | |
2739 | tcode, length, d->ctx, | |
cf82703d | 2740 | (d->spb[0]>>10)&0x3f); |
1da177e4 LT |
2741 | |
2742 | ack = (((cond_le32_to_cpu(d->spb[length/4-1], ohci->no_swap_incoming)>>16)&0x1f) | |
2743 | == 0x11) ? 1 : 0; | |
2744 | ||
2745 | hpsb_packet_received(ohci->host, d->spb, | |
2746 | length-4, ack); | |
2747 | } | |
2748 | #ifdef OHCI1394_DEBUG | |
2749 | else | |
2750 | PRINT (KERN_DEBUG, "Got phy packet ctx=%d ... discarded", | |
2751 | d->ctx); | |
2752 | #endif | |
2753 | ||
2754 | rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff; | |
2755 | ||
2756 | bytes_left = d->buf_size - rescount - offset; | |
2757 | ||
2758 | } | |
2759 | ||
2760 | d->buf_ind = idx; | |
2761 | d->buf_offset = offset; | |
2762 | ||
2763 | spin_unlock_irqrestore(&d->lock, flags); | |
2764 | } | |
2765 | ||
2766 | /* Bottom half that processes sent packets */ | |
2767 | static void dma_trm_tasklet (unsigned long data) | |
2768 | { | |
2769 | struct dma_trm_ctx *d = (struct dma_trm_ctx*)data; | |
2770 | struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci); | |
2771 | struct hpsb_packet *packet, *ptmp; | |
2772 | unsigned long flags; | |
2773 | u32 status, ack; | |
2774 | size_t datasize; | |
2775 | ||
2776 | spin_lock_irqsave(&d->lock, flags); | |
2777 | ||
2778 | list_for_each_entry_safe(packet, ptmp, &d->fifo_list, driver_list) { | |
2779 | datasize = packet->data_size; | |
2780 | if (datasize && packet->type != hpsb_raw) | |
2781 | status = le32_to_cpu( | |
2782 | d->prg_cpu[d->sent_ind]->end.status) >> 16; | |
2783 | else | |
2784 | status = le32_to_cpu( | |
2785 | d->prg_cpu[d->sent_ind]->begin.status) >> 16; | |
2786 | ||
2787 | if (status == 0) | |
2788 | /* this packet hasn't been sent yet*/ | |
2789 | break; | |
2790 | ||
2791 | #ifdef OHCI1394_DEBUG | |
2792 | if (datasize) | |
2793 | if (((le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf) == 0xa) | |
2794 | DBGMSG("Stream packet sent to channel %d tcode=0x%X " | |
2795 | "ack=0x%X spd=%d dataLength=%d ctx=%d", | |
2796 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>8)&0x3f, | |
2797 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf, | |
2798 | status&0x1f, (status>>5)&0x3, | |
2799 | le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16, | |
2800 | d->ctx); | |
2801 | else | |
2802 | DBGMSG("Packet sent to node %d tcode=0x%X tLabel=" | |
dfe547ab | 2803 | "%d ack=0x%X spd=%d dataLength=%d ctx=%d", |
1da177e4 LT |
2804 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])>>16)&0x3f, |
2805 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>4)&0xf, | |
2806 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])>>10)&0x3f, | |
2807 | status&0x1f, (status>>5)&0x3, | |
2808 | le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3])>>16, | |
2809 | d->ctx); | |
2810 | else | |
2811 | DBGMSG("Packet sent to node %d tcode=0x%X tLabel=" | |
dfe547ab | 2812 | "%d ack=0x%X spd=%d data=0x%08X ctx=%d", |
1da177e4 LT |
2813 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1]) |
2814 | >>16)&0x3f, | |
2815 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0]) | |
2816 | >>4)&0xf, | |
2817 | (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0]) | |
2818 | >>10)&0x3f, | |
2819 | status&0x1f, (status>>5)&0x3, | |
2820 | le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3]), | |
2821 | d->ctx); | |
2822 | #endif | |
2823 | ||
2824 | if (status & 0x10) { | |
2825 | ack = status & 0xf; | |
2826 | } else { | |
2827 | switch (status & 0x1f) { | |
2828 | case EVT_NO_STATUS: /* that should never happen */ | |
2829 | case EVT_RESERVED_A: /* that should never happen */ | |
2830 | case EVT_LONG_PACKET: /* that should never happen */ | |
2831 | PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f); | |
2832 | ack = ACKX_SEND_ERROR; | |
2833 | break; | |
2834 | case EVT_MISSING_ACK: | |
2835 | ack = ACKX_TIMEOUT; | |
2836 | break; | |
2837 | case EVT_UNDERRUN: | |
2838 | ack = ACKX_SEND_ERROR; | |
2839 | break; | |
2840 | case EVT_OVERRUN: /* that should never happen */ | |
2841 | PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f); | |
2842 | ack = ACKX_SEND_ERROR; | |
2843 | break; | |
2844 | case EVT_DESCRIPTOR_READ: | |
2845 | case EVT_DATA_READ: | |
2846 | case EVT_DATA_WRITE: | |
2847 | ack = ACKX_SEND_ERROR; | |
2848 | break; | |
2849 | case EVT_BUS_RESET: /* that should never happen */ | |
2850 | PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f); | |
2851 | ack = ACKX_SEND_ERROR; | |
2852 | break; | |
2853 | case EVT_TIMEOUT: | |
2854 | ack = ACKX_TIMEOUT; | |
2855 | break; | |
2856 | case EVT_TCODE_ERR: | |
2857 | ack = ACKX_SEND_ERROR; | |
2858 | break; | |
2859 | case EVT_RESERVED_B: /* that should never happen */ | |
2860 | case EVT_RESERVED_C: /* that should never happen */ | |
2861 | PRINT(KERN_WARNING, "Received OHCI evt_* error 0x%x", status & 0x1f); | |
2862 | ack = ACKX_SEND_ERROR; | |
2863 | break; | |
2864 | case EVT_UNKNOWN: | |
2865 | case EVT_FLUSHED: | |
2866 | ack = ACKX_SEND_ERROR; | |
2867 | break; | |
2868 | default: | |
2869 | PRINT(KERN_ERR, "Unhandled OHCI evt_* error 0x%x", status & 0x1f); | |
2870 | ack = ACKX_SEND_ERROR; | |
2871 | BUG(); | |
2872 | } | |
2873 | } | |
2874 | ||
2875 | list_del_init(&packet->driver_list); | |
2876 | hpsb_packet_sent(ohci->host, packet, ack); | |
2877 | ||
2878 | if (datasize) { | |
2879 | pci_unmap_single(ohci->dev, | |
2880 | cpu_to_le32(d->prg_cpu[d->sent_ind]->end.address), | |
2881 | datasize, PCI_DMA_TODEVICE); | |
2882 | OHCI_DMA_FREE("single Xmit data packet"); | |
2883 | } | |
2884 | ||
2885 | d->sent_ind = (d->sent_ind+1)%d->num_desc; | |
2886 | d->free_prgs++; | |
2887 | } | |
2888 | ||
2889 | dma_trm_flush(ohci, d); | |
2890 | ||
2891 | spin_unlock_irqrestore(&d->lock, flags); | |
2892 | } | |
2893 | ||
2894 | static void stop_dma_rcv_ctx(struct dma_rcv_ctx *d) | |
2895 | { | |
2896 | if (d->ctrlClear) { | |
2897 | ohci1394_stop_context(d->ohci, d->ctrlClear, NULL); | |
2898 | ||
2899 | if (d->type == DMA_CTX_ISO) { | |
2900 | /* disable interrupts */ | |
2901 | reg_write(d->ohci, OHCI1394_IsoRecvIntMaskClear, 1 << d->ctx); | |
2902 | ohci1394_unregister_iso_tasklet(d->ohci, &d->ohci->ir_legacy_tasklet); | |
2903 | } else { | |
2904 | tasklet_kill(&d->task); | |
2905 | } | |
2906 | } | |
2907 | } | |
2908 | ||
2909 | ||
2910 | static void free_dma_rcv_ctx(struct dma_rcv_ctx *d) | |
2911 | { | |
2912 | int i; | |
2913 | struct ti_ohci *ohci = d->ohci; | |
2914 | ||
2915 | if (ohci == NULL) | |
2916 | return; | |
2917 | ||
2918 | DBGMSG("Freeing dma_rcv_ctx %d", d->ctx); | |
2919 | ||
2920 | if (d->buf_cpu) { | |
2921 | for (i=0; i<d->num_desc; i++) | |
2922 | if (d->buf_cpu[i] && d->buf_bus[i]) { | |
2923 | pci_free_consistent( | |
2924 | ohci->dev, d->buf_size, | |
2925 | d->buf_cpu[i], d->buf_bus[i]); | |
2926 | OHCI_DMA_FREE("consistent dma_rcv buf[%d]", i); | |
2927 | } | |
2928 | kfree(d->buf_cpu); | |
2929 | kfree(d->buf_bus); | |
2930 | } | |
2931 | if (d->prg_cpu) { | |
2932 | for (i=0; i<d->num_desc; i++) | |
2933 | if (d->prg_cpu[i] && d->prg_bus[i]) { | |
2934 | pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]); | |
2935 | OHCI_DMA_FREE("consistent dma_rcv prg[%d]", i); | |
2936 | } | |
2937 | pci_pool_destroy(d->prg_pool); | |
2938 | OHCI_DMA_FREE("dma_rcv prg pool"); | |
2939 | kfree(d->prg_cpu); | |
2940 | kfree(d->prg_bus); | |
2941 | } | |
616b859f | 2942 | kfree(d->spb); |
1da177e4 LT |
2943 | |
2944 | /* Mark this context as freed. */ | |
2945 | d->ohci = NULL; | |
2946 | } | |
2947 | ||
2948 | static int | |
2949 | alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d, | |
2950 | enum context_type type, int ctx, int num_desc, | |
2951 | int buf_size, int split_buf_size, int context_base) | |
2952 | { | |
2953 | int i, len; | |
2954 | static int num_allocs; | |
2955 | static char pool_name[20]; | |
2956 | ||
2957 | d->ohci = ohci; | |
2958 | d->type = type; | |
2959 | d->ctx = ctx; | |
2960 | ||
2961 | d->num_desc = num_desc; | |
2962 | d->buf_size = buf_size; | |
2963 | d->split_buf_size = split_buf_size; | |
2964 | ||
2965 | d->ctrlSet = 0; | |
2966 | d->ctrlClear = 0; | |
2967 | d->cmdPtr = 0; | |
2968 | ||
8551158a SR |
2969 | d->buf_cpu = kzalloc(d->num_desc * sizeof(*d->buf_cpu), GFP_ATOMIC); |
2970 | d->buf_bus = kzalloc(d->num_desc * sizeof(*d->buf_bus), GFP_ATOMIC); | |
1da177e4 LT |
2971 | |
2972 | if (d->buf_cpu == NULL || d->buf_bus == NULL) { | |
2973 | PRINT(KERN_ERR, "Failed to allocate dma buffer"); | |
2974 | free_dma_rcv_ctx(d); | |
2975 | return -ENOMEM; | |
2976 | } | |
1da177e4 | 2977 | |
8551158a SR |
2978 | d->prg_cpu = kzalloc(d->num_desc * sizeof(*d->prg_cpu), GFP_ATOMIC); |
2979 | d->prg_bus = kzalloc(d->num_desc * sizeof(*d->prg_bus), GFP_ATOMIC); | |
1da177e4 LT |
2980 | |
2981 | if (d->prg_cpu == NULL || d->prg_bus == NULL) { | |
2982 | PRINT(KERN_ERR, "Failed to allocate dma prg"); | |
2983 | free_dma_rcv_ctx(d); | |
2984 | return -ENOMEM; | |
2985 | } | |
1da177e4 LT |
2986 | |
2987 | d->spb = kmalloc(d->split_buf_size, GFP_ATOMIC); | |
2988 | ||
2989 | if (d->spb == NULL) { | |
2990 | PRINT(KERN_ERR, "Failed to allocate split buffer"); | |
2991 | free_dma_rcv_ctx(d); | |
2992 | return -ENOMEM; | |
2993 | } | |
2994 | ||
2995 | len = sprintf(pool_name, "ohci1394_rcv_prg"); | |
2996 | sprintf(pool_name+len, "%d", num_allocs); | |
2997 | d->prg_pool = pci_pool_create(pool_name, ohci->dev, | |
2998 | sizeof(struct dma_cmd), 4, 0); | |
2999 | if(d->prg_pool == NULL) | |
3000 | { | |
3001 | PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name); | |
3002 | free_dma_rcv_ctx(d); | |
3003 | return -ENOMEM; | |
3004 | } | |
3005 | num_allocs++; | |
3006 | ||
3007 | OHCI_DMA_ALLOC("dma_rcv prg pool"); | |
3008 | ||
3009 | for (i=0; i<d->num_desc; i++) { | |
3010 | d->buf_cpu[i] = pci_alloc_consistent(ohci->dev, | |
3011 | d->buf_size, | |
3012 | d->buf_bus+i); | |
3013 | OHCI_DMA_ALLOC("consistent dma_rcv buf[%d]", i); | |
3014 | ||
3015 | if (d->buf_cpu[i] != NULL) { | |
3016 | memset(d->buf_cpu[i], 0, d->buf_size); | |
3017 | } else { | |
3018 | PRINT(KERN_ERR, | |
3019 | "Failed to allocate dma buffer"); | |
3020 | free_dma_rcv_ctx(d); | |
3021 | return -ENOMEM; | |
3022 | } | |
3023 | ||
3024 | d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, SLAB_KERNEL, d->prg_bus+i); | |
3025 | OHCI_DMA_ALLOC("pool dma_rcv prg[%d]", i); | |
3026 | ||
3027 | if (d->prg_cpu[i] != NULL) { | |
3028 | memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd)); | |
3029 | } else { | |
3030 | PRINT(KERN_ERR, | |
3031 | "Failed to allocate dma prg"); | |
3032 | free_dma_rcv_ctx(d); | |
3033 | return -ENOMEM; | |
3034 | } | |
3035 | } | |
3036 | ||
3037 | spin_lock_init(&d->lock); | |
3038 | ||
3039 | if (type == DMA_CTX_ISO) { | |
3040 | ohci1394_init_iso_tasklet(&ohci->ir_legacy_tasklet, | |
3041 | OHCI_ISO_MULTICHANNEL_RECEIVE, | |
3042 | dma_rcv_tasklet, (unsigned long) d); | |
1da177e4 LT |
3043 | } else { |
3044 | d->ctrlSet = context_base + OHCI1394_ContextControlSet; | |
3045 | d->ctrlClear = context_base + OHCI1394_ContextControlClear; | |
3046 | d->cmdPtr = context_base + OHCI1394_ContextCommandPtr; | |
3047 | ||
3048 | tasklet_init (&d->task, dma_rcv_tasklet, (unsigned long) d); | |
3049 | } | |
3050 | ||
3051 | return 0; | |
3052 | } | |
3053 | ||
3054 | static void free_dma_trm_ctx(struct dma_trm_ctx *d) | |
3055 | { | |
3056 | int i; | |
3057 | struct ti_ohci *ohci = d->ohci; | |
3058 | ||
3059 | if (ohci == NULL) | |
3060 | return; | |
3061 | ||
3062 | DBGMSG("Freeing dma_trm_ctx %d", d->ctx); | |
3063 | ||
3064 | if (d->prg_cpu) { | |
3065 | for (i=0; i<d->num_desc; i++) | |
3066 | if (d->prg_cpu[i] && d->prg_bus[i]) { | |
3067 | pci_pool_free(d->prg_pool, d->prg_cpu[i], d->prg_bus[i]); | |
3068 | OHCI_DMA_FREE("pool dma_trm prg[%d]", i); | |
3069 | } | |
3070 | pci_pool_destroy(d->prg_pool); | |
3071 | OHCI_DMA_FREE("dma_trm prg pool"); | |
3072 | kfree(d->prg_cpu); | |
3073 | kfree(d->prg_bus); | |
3074 | } | |
3075 | ||
3076 | /* Mark this context as freed. */ | |
3077 | d->ohci = NULL; | |
3078 | } | |
3079 | ||
3080 | static int | |
3081 | alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d, | |
3082 | enum context_type type, int ctx, int num_desc, | |
3083 | int context_base) | |
3084 | { | |
3085 | int i, len; | |
3086 | static char pool_name[20]; | |
3087 | static int num_allocs=0; | |
3088 | ||
3089 | d->ohci = ohci; | |
3090 | d->type = type; | |
3091 | d->ctx = ctx; | |
3092 | d->num_desc = num_desc; | |
3093 | d->ctrlSet = 0; | |
3094 | d->ctrlClear = 0; | |
3095 | d->cmdPtr = 0; | |
3096 | ||
8551158a SR |
3097 | d->prg_cpu = kzalloc(d->num_desc * sizeof(*d->prg_cpu), GFP_KERNEL); |
3098 | d->prg_bus = kzalloc(d->num_desc * sizeof(*d->prg_bus), GFP_KERNEL); | |
1da177e4 LT |
3099 | |
3100 | if (d->prg_cpu == NULL || d->prg_bus == NULL) { | |
3101 | PRINT(KERN_ERR, "Failed to allocate at dma prg"); | |
3102 | free_dma_trm_ctx(d); | |
3103 | return -ENOMEM; | |
3104 | } | |
1da177e4 LT |
3105 | |
3106 | len = sprintf(pool_name, "ohci1394_trm_prg"); | |
3107 | sprintf(pool_name+len, "%d", num_allocs); | |
3108 | d->prg_pool = pci_pool_create(pool_name, ohci->dev, | |
3109 | sizeof(struct at_dma_prg), 4, 0); | |
3110 | if (d->prg_pool == NULL) { | |
3111 | PRINT(KERN_ERR, "pci_pool_create failed for %s", pool_name); | |
3112 | free_dma_trm_ctx(d); | |
3113 | return -ENOMEM; | |
3114 | } | |
3115 | num_allocs++; | |
3116 | ||
3117 | OHCI_DMA_ALLOC("dma_rcv prg pool"); | |
3118 | ||
3119 | for (i = 0; i < d->num_desc; i++) { | |
3120 | d->prg_cpu[i] = pci_pool_alloc(d->prg_pool, SLAB_KERNEL, d->prg_bus+i); | |
3121 | OHCI_DMA_ALLOC("pool dma_trm prg[%d]", i); | |
3122 | ||
3123 | if (d->prg_cpu[i] != NULL) { | |
3124 | memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg)); | |
3125 | } else { | |
3126 | PRINT(KERN_ERR, | |
3127 | "Failed to allocate at dma prg"); | |
3128 | free_dma_trm_ctx(d); | |
3129 | return -ENOMEM; | |
3130 | } | |
3131 | } | |
3132 | ||
3133 | spin_lock_init(&d->lock); | |
3134 | ||
3135 | /* initialize tasklet */ | |
3136 | if (type == DMA_CTX_ISO) { | |
3137 | ohci1394_init_iso_tasklet(&ohci->it_legacy_tasklet, OHCI_ISO_TRANSMIT, | |
3138 | dma_trm_tasklet, (unsigned long) d); | |
3139 | if (ohci1394_register_iso_tasklet(ohci, | |
3140 | &ohci->it_legacy_tasklet) < 0) { | |
3141 | PRINT(KERN_ERR, "No IT DMA context available"); | |
3142 | free_dma_trm_ctx(d); | |
3143 | return -EBUSY; | |
3144 | } | |
3145 | ||
3146 | /* IT can be assigned to any context by register_iso_tasklet */ | |
3147 | d->ctx = ohci->it_legacy_tasklet.context; | |
3148 | d->ctrlSet = OHCI1394_IsoXmitContextControlSet + 16 * d->ctx; | |
3149 | d->ctrlClear = OHCI1394_IsoXmitContextControlClear + 16 * d->ctx; | |
3150 | d->cmdPtr = OHCI1394_IsoXmitCommandPtr + 16 * d->ctx; | |
3151 | } else { | |
3152 | d->ctrlSet = context_base + OHCI1394_ContextControlSet; | |
3153 | d->ctrlClear = context_base + OHCI1394_ContextControlClear; | |
3154 | d->cmdPtr = context_base + OHCI1394_ContextCommandPtr; | |
3155 | tasklet_init (&d->task, dma_trm_tasklet, (unsigned long)d); | |
3156 | } | |
3157 | ||
3158 | return 0; | |
3159 | } | |
3160 | ||
3161 | static void ohci_set_hw_config_rom(struct hpsb_host *host, quadlet_t *config_rom) | |
3162 | { | |
3163 | struct ti_ohci *ohci = host->hostdata; | |
3164 | ||
3165 | reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(config_rom[0])); | |
3166 | reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(config_rom[2])); | |
3167 | ||
3168 | memcpy(ohci->csr_config_rom_cpu, config_rom, OHCI_CONFIG_ROM_LEN); | |
3169 | } | |
3170 | ||
3171 | ||
3172 | static quadlet_t ohci_hw_csr_reg(struct hpsb_host *host, int reg, | |
3173 | quadlet_t data, quadlet_t compare) | |
3174 | { | |
3175 | struct ti_ohci *ohci = host->hostdata; | |
3176 | int i; | |
3177 | ||
3178 | reg_write(ohci, OHCI1394_CSRData, data); | |
3179 | reg_write(ohci, OHCI1394_CSRCompareData, compare); | |
3180 | reg_write(ohci, OHCI1394_CSRControl, reg & 0x3); | |
3181 | ||
3182 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
3183 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
3184 | break; | |
3185 | ||
3186 | mdelay(1); | |
3187 | } | |
3188 | ||
3189 | return reg_read(ohci, OHCI1394_CSRData); | |
3190 | } | |
3191 | ||
3192 | static struct hpsb_host_driver ohci1394_driver = { | |
3193 | .owner = THIS_MODULE, | |
3194 | .name = OHCI1394_DRIVER_NAME, | |
3195 | .set_hw_config_rom = ohci_set_hw_config_rom, | |
3196 | .transmit_packet = ohci_transmit, | |
3197 | .devctl = ohci_devctl, | |
3198 | .isoctl = ohci_isoctl, | |
3199 | .hw_csr_reg = ohci_hw_csr_reg, | |
3200 | }; | |
3201 | ||
1da177e4 LT |
3202 | /*********************************** |
3203 | * PCI Driver Interface functions * | |
3204 | ***********************************/ | |
3205 | ||
3206 | #define FAIL(err, fmt, args...) \ | |
3207 | do { \ | |
3208 | PRINT_G(KERN_ERR, fmt , ## args); \ | |
3209 | ohci1394_pci_remove(dev); \ | |
3210 | return err; \ | |
3211 | } while (0) | |
3212 | ||
3213 | static int __devinit ohci1394_pci_probe(struct pci_dev *dev, | |
3214 | const struct pci_device_id *ent) | |
3215 | { | |
1da177e4 LT |
3216 | struct hpsb_host *host; |
3217 | struct ti_ohci *ohci; /* shortcut to currently handled device */ | |
2427ddd8 | 3218 | resource_size_t ohci_base; |
1da177e4 | 3219 | |
1da177e4 LT |
3220 | if (pci_enable_device(dev)) |
3221 | FAIL(-ENXIO, "Failed to enable OHCI hardware"); | |
3222 | pci_set_master(dev); | |
3223 | ||
3224 | host = hpsb_alloc_host(&ohci1394_driver, sizeof(struct ti_ohci), &dev->dev); | |
3225 | if (!host) FAIL(-ENOMEM, "Failed to allocate host structure"); | |
3226 | ||
3227 | ohci = host->hostdata; | |
3228 | ohci->dev = dev; | |
3229 | ohci->host = host; | |
3230 | ohci->init_state = OHCI_INIT_ALLOC_HOST; | |
3231 | host->pdev = dev; | |
3232 | pci_set_drvdata(dev, ohci); | |
3233 | ||
3234 | /* We don't want hardware swapping */ | |
3235 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
3236 | ||
3237 | /* Some oddball Apple controllers do not order the selfid | |
3238 | * properly, so we make up for it here. */ | |
3239 | #ifndef __LITTLE_ENDIAN | |
3240 | /* XXX: Need a better way to check this. I'm wondering if we can | |
3241 | * read the values of the OHCI1394_PCI_HCI_Control and the | |
3242 | * noByteSwapData registers to see if they were not cleared to | |
3243 | * zero. Should this work? Obviously it's not defined what these | |
3244 | * registers will read when they aren't supported. Bleh! */ | |
3245 | if (dev->vendor == PCI_VENDOR_ID_APPLE && | |
3246 | dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) { | |
3247 | ohci->no_swap_incoming = 1; | |
3248 | ohci->selfid_swap = 0; | |
3249 | } else | |
3250 | ohci->selfid_swap = 1; | |
3251 | #endif | |
3252 | ||
3253 | ||
3254 | #ifndef PCI_DEVICE_ID_NVIDIA_NFORCE2_FW | |
3255 | #define PCI_DEVICE_ID_NVIDIA_NFORCE2_FW 0x006e | |
3256 | #endif | |
3257 | ||
3258 | /* These chipsets require a bit of extra care when checking after | |
3259 | * a busreset. */ | |
3260 | if ((dev->vendor == PCI_VENDOR_ID_APPLE && | |
3261 | dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW) || | |
3262 | (dev->vendor == PCI_VENDOR_ID_NVIDIA && | |
3263 | dev->device == PCI_DEVICE_ID_NVIDIA_NFORCE2_FW)) | |
3264 | ohci->check_busreset = 1; | |
3265 | ||
3266 | /* We hardwire the MMIO length, since some CardBus adaptors | |
3267 | * fail to report the right length. Anyway, the ohci spec | |
3268 | * clearly says it's 2kb, so this shouldn't be a problem. */ | |
3269 | ohci_base = pci_resource_start(dev, 0); | |
94c2d01a | 3270 | if (pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) |
e29419ff GKH |
3271 | PRINT(KERN_WARNING, "PCI resource length of 0x%llx too small!", |
3272 | (unsigned long long)pci_resource_len(dev, 0)); | |
1da177e4 LT |
3273 | |
3274 | /* Seems PCMCIA handles this internally. Not sure why. Seems | |
3275 | * pretty bogus to force a driver to special case this. */ | |
3276 | #ifndef PCMCIA | |
3277 | if (!request_mem_region (ohci_base, OHCI1394_REGISTER_SIZE, OHCI1394_DRIVER_NAME)) | |
e29419ff GKH |
3278 | FAIL(-ENOMEM, "MMIO resource (0x%llx - 0x%llx) unavailable", |
3279 | (unsigned long long)ohci_base, | |
3280 | (unsigned long long)ohci_base + OHCI1394_REGISTER_SIZE); | |
1da177e4 LT |
3281 | #endif |
3282 | ohci->init_state = OHCI_INIT_HAVE_MEM_REGION; | |
3283 | ||
3284 | ohci->registers = ioremap(ohci_base, OHCI1394_REGISTER_SIZE); | |
3285 | if (ohci->registers == NULL) | |
3286 | FAIL(-ENXIO, "Failed to remap registers - card not accessible"); | |
3287 | ohci->init_state = OHCI_INIT_HAVE_IOMAPPING; | |
3288 | DBGMSG("Remapped memory spaces reg 0x%p", ohci->registers); | |
3289 | ||
3290 | /* csr_config rom allocation */ | |
3291 | ohci->csr_config_rom_cpu = | |
3292 | pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN, | |
3293 | &ohci->csr_config_rom_bus); | |
3294 | OHCI_DMA_ALLOC("consistent csr_config_rom"); | |
3295 | if (ohci->csr_config_rom_cpu == NULL) | |
3296 | FAIL(-ENOMEM, "Failed to allocate buffer config rom"); | |
3297 | ohci->init_state = OHCI_INIT_HAVE_CONFIG_ROM_BUFFER; | |
3298 | ||
3299 | /* self-id dma buffer allocation */ | |
3300 | ohci->selfid_buf_cpu = | |
3301 | pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE, | |
3302 | &ohci->selfid_buf_bus); | |
3303 | OHCI_DMA_ALLOC("consistent selfid_buf"); | |
3304 | ||
3305 | if (ohci->selfid_buf_cpu == NULL) | |
3306 | FAIL(-ENOMEM, "Failed to allocate DMA buffer for self-id packets"); | |
3307 | ohci->init_state = OHCI_INIT_HAVE_SELFID_BUFFER; | |
3308 | ||
3309 | if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff) | |
3310 | PRINT(KERN_INFO, "SelfID buffer %p is not aligned on " | |
3311 | "8Kb boundary... may cause problems on some CXD3222 chip", | |
3312 | ohci->selfid_buf_cpu); | |
3313 | ||
3314 | /* No self-id errors at startup */ | |
3315 | ohci->self_id_errors = 0; | |
3316 | ||
3317 | ohci->init_state = OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE; | |
3318 | /* AR DMA request context allocation */ | |
3319 | if (alloc_dma_rcv_ctx(ohci, &ohci->ar_req_context, | |
3320 | DMA_CTX_ASYNC_REQ, 0, AR_REQ_NUM_DESC, | |
3321 | AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE, | |
3322 | OHCI1394_AsReqRcvContextBase) < 0) | |
3323 | FAIL(-ENOMEM, "Failed to allocate AR Req context"); | |
3324 | ||
3325 | /* AR DMA response context allocation */ | |
3326 | if (alloc_dma_rcv_ctx(ohci, &ohci->ar_resp_context, | |
3327 | DMA_CTX_ASYNC_RESP, 0, AR_RESP_NUM_DESC, | |
3328 | AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE, | |
3329 | OHCI1394_AsRspRcvContextBase) < 0) | |
3330 | FAIL(-ENOMEM, "Failed to allocate AR Resp context"); | |
3331 | ||
3332 | /* AT DMA request context */ | |
3333 | if (alloc_dma_trm_ctx(ohci, &ohci->at_req_context, | |
3334 | DMA_CTX_ASYNC_REQ, 0, AT_REQ_NUM_DESC, | |
3335 | OHCI1394_AsReqTrContextBase) < 0) | |
3336 | FAIL(-ENOMEM, "Failed to allocate AT Req context"); | |
3337 | ||
3338 | /* AT DMA response context */ | |
3339 | if (alloc_dma_trm_ctx(ohci, &ohci->at_resp_context, | |
3340 | DMA_CTX_ASYNC_RESP, 1, AT_RESP_NUM_DESC, | |
3341 | OHCI1394_AsRspTrContextBase) < 0) | |
3342 | FAIL(-ENOMEM, "Failed to allocate AT Resp context"); | |
3343 | ||
3344 | /* Start off with a soft reset, to clear everything to a sane | |
3345 | * state. */ | |
3346 | ohci_soft_reset(ohci); | |
3347 | ||
3348 | /* Now enable LPS, which we need in order to start accessing | |
3349 | * most of the registers. In fact, on some cards (ALI M5251), | |
3350 | * accessing registers in the SClk domain without LPS enabled | |
3351 | * will lock up the machine. Wait 50msec to make sure we have | |
3352 | * full link enabled. */ | |
3353 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS); | |
3354 | ||
3355 | /* Disable and clear interrupts */ | |
3356 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); | |
3357 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); | |
3358 | ||
3359 | mdelay(50); | |
3360 | ||
3361 | /* Determine the number of available IR and IT contexts. */ | |
3362 | ohci->nb_iso_rcv_ctx = | |
3363 | get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet); | |
1da177e4 LT |
3364 | ohci->nb_iso_xmit_ctx = |
3365 | get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet); | |
1da177e4 LT |
3366 | |
3367 | /* Set the usage bits for non-existent contexts so they can't | |
3368 | * be allocated */ | |
3369 | ohci->ir_ctx_usage = ~0 << ohci->nb_iso_rcv_ctx; | |
3370 | ohci->it_ctx_usage = ~0 << ohci->nb_iso_xmit_ctx; | |
3371 | ||
3372 | INIT_LIST_HEAD(&ohci->iso_tasklet_list); | |
3373 | spin_lock_init(&ohci->iso_tasklet_list_lock); | |
3374 | ohci->ISO_channel_usage = 0; | |
3375 | spin_lock_init(&ohci->IR_channel_lock); | |
3376 | ||
3377 | /* Allocate the IR DMA context right here so we don't have | |
3378 | * to do it in interrupt path - note that this doesn't | |
3379 | * waste much memory and avoids the jugglery required to | |
3380 | * allocate it in IRQ path. */ | |
3381 | if (alloc_dma_rcv_ctx(ohci, &ohci->ir_legacy_context, | |
3382 | DMA_CTX_ISO, 0, IR_NUM_DESC, | |
3383 | IR_BUF_SIZE, IR_SPLIT_BUF_SIZE, | |
3384 | OHCI1394_IsoRcvContextBase) < 0) { | |
3385 | FAIL(-ENOMEM, "Cannot allocate IR Legacy DMA context"); | |
3386 | } | |
3387 | ||
3388 | /* We hopefully don't have to pre-allocate IT DMA like we did | |
3389 | * for IR DMA above. Allocate it on-demand and mark inactive. */ | |
3390 | ohci->it_legacy_context.ohci = NULL; | |
3515d016 | 3391 | spin_lock_init(&ohci->event_lock); |
1da177e4 | 3392 | |
3515d016 | 3393 | /* |
272ee69c | 3394 | * interrupts are disabled, all right, but... due to IRQF_SHARED we |
3515d016 AV |
3395 | * might get called anyway. We'll see no event, of course, but |
3396 | * we need to get to that "no event", so enough should be initialized | |
3397 | * by that point. | |
3398 | */ | |
272ee69c | 3399 | if (request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED, |
1da177e4 LT |
3400 | OHCI1394_DRIVER_NAME, ohci)) |
3401 | FAIL(-ENOMEM, "Failed to allocate shared interrupt %d", dev->irq); | |
3402 | ||
3403 | ohci->init_state = OHCI_INIT_HAVE_IRQ; | |
3404 | ohci_initialize(ohci); | |
3405 | ||
3406 | /* Set certain csr values */ | |
3407 | host->csr.guid_hi = reg_read(ohci, OHCI1394_GUIDHi); | |
3408 | host->csr.guid_lo = reg_read(ohci, OHCI1394_GUIDLo); | |
3409 | host->csr.cyc_clk_acc = 100; /* how do we determine clk accuracy? */ | |
3410 | host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf; | |
3411 | host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7; | |
3412 | ||
4611ed38 BC |
3413 | if (phys_dma) { |
3414 | host->low_addr_space = | |
3415 | (u64) reg_read(ohci, OHCI1394_PhyUpperBound) << 16; | |
3416 | if (!host->low_addr_space) | |
3417 | host->low_addr_space = OHCI1394_PHYS_UPPER_BOUND_FIXED; | |
3418 | } | |
3419 | host->middle_addr_space = OHCI1394_MIDDLE_ADDRESS_SPACE; | |
3420 | ||
1da177e4 LT |
3421 | /* Tell the highlevel this host is ready */ |
3422 | if (hpsb_add_host(host)) | |
3423 | FAIL(-ENOMEM, "Failed to register host with highlevel"); | |
3424 | ||
3425 | ohci->init_state = OHCI_INIT_DONE; | |
3426 | ||
3427 | return 0; | |
3428 | #undef FAIL | |
3429 | } | |
3430 | ||
3431 | static void ohci1394_pci_remove(struct pci_dev *pdev) | |
3432 | { | |
3433 | struct ti_ohci *ohci; | |
3434 | struct device *dev; | |
3435 | ||
3436 | ohci = pci_get_drvdata(pdev); | |
3437 | if (!ohci) | |
3438 | return; | |
3439 | ||
3440 | dev = get_device(&ohci->host->device); | |
3441 | ||
3442 | switch (ohci->init_state) { | |
3443 | case OHCI_INIT_DONE: | |
1da177e4 LT |
3444 | hpsb_remove_host(ohci->host); |
3445 | ||
3446 | /* Clear out BUS Options */ | |
3447 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
3448 | reg_write(ohci, OHCI1394_BusOptions, | |
3449 | (reg_read(ohci, OHCI1394_BusOptions) & 0x0000f007) | | |
3450 | 0x00ff0000); | |
3451 | memset(ohci->csr_config_rom_cpu, 0, OHCI_CONFIG_ROM_LEN); | |
3452 | ||
3453 | case OHCI_INIT_HAVE_IRQ: | |
3454 | /* Clear interrupt registers */ | |
3455 | reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff); | |
3456 | reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); | |
3457 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff); | |
3458 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff); | |
3459 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff); | |
3460 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff); | |
3461 | ||
3462 | /* Disable IRM Contender */ | |
3463 | set_phy_reg(ohci, 4, ~0xc0 & get_phy_reg(ohci, 4)); | |
3464 | ||
3465 | /* Clear link control register */ | |
3466 | reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); | |
3467 | ||
3468 | /* Let all other nodes know to ignore us */ | |
3469 | ohci_devctl(ohci->host, RESET_BUS, LONG_RESET_NO_FORCE_ROOT); | |
3470 | ||
3471 | /* Soft reset before we start - this disables | |
3472 | * interrupts and clears linkEnable and LPS. */ | |
3473 | ohci_soft_reset(ohci); | |
3474 | free_irq(ohci->dev->irq, ohci); | |
3475 | ||
3476 | case OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE: | |
3477 | /* The ohci_soft_reset() stops all DMA contexts, so we | |
3478 | * dont need to do this. */ | |
1da177e4 LT |
3479 | free_dma_rcv_ctx(&ohci->ar_req_context); |
3480 | free_dma_rcv_ctx(&ohci->ar_resp_context); | |
1da177e4 LT |
3481 | free_dma_trm_ctx(&ohci->at_req_context); |
3482 | free_dma_trm_ctx(&ohci->at_resp_context); | |
1da177e4 | 3483 | free_dma_rcv_ctx(&ohci->ir_legacy_context); |
1da177e4 LT |
3484 | free_dma_trm_ctx(&ohci->it_legacy_context); |
3485 | ||
1da177e4 LT |
3486 | case OHCI_INIT_HAVE_SELFID_BUFFER: |
3487 | pci_free_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE, | |
3488 | ohci->selfid_buf_cpu, | |
3489 | ohci->selfid_buf_bus); | |
3490 | OHCI_DMA_FREE("consistent selfid_buf"); | |
3491 | ||
3492 | case OHCI_INIT_HAVE_CONFIG_ROM_BUFFER: | |
3493 | pci_free_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN, | |
3494 | ohci->csr_config_rom_cpu, | |
3495 | ohci->csr_config_rom_bus); | |
3496 | OHCI_DMA_FREE("consistent csr_config_rom"); | |
3497 | ||
3498 | case OHCI_INIT_HAVE_IOMAPPING: | |
3499 | iounmap(ohci->registers); | |
3500 | ||
3501 | case OHCI_INIT_HAVE_MEM_REGION: | |
3502 | #ifndef PCMCIA | |
3503 | release_mem_region(pci_resource_start(ohci->dev, 0), | |
3504 | OHCI1394_REGISTER_SIZE); | |
3505 | #endif | |
3506 | ||
3507 | #ifdef CONFIG_PPC_PMAC | |
3508 | /* On UniNorth, power down the cable and turn off the chip | |
3509 | * clock when the module is removed to save power on | |
3510 | * laptops. Turning it back ON is done by the arch code when | |
3511 | * pci_enable_device() is called */ | |
3512 | { | |
3513 | struct device_node* of_node; | |
3514 | ||
3515 | of_node = pci_device_to_OF_node(ohci->dev); | |
3516 | if (of_node) { | |
3517 | pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0); | |
3518 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, of_node, 0, 0); | |
3519 | } | |
3520 | } | |
3521 | #endif /* CONFIG_PPC_PMAC */ | |
3522 | ||
3523 | case OHCI_INIT_ALLOC_HOST: | |
3524 | pci_set_drvdata(ohci->dev, NULL); | |
3525 | } | |
3526 | ||
3527 | if (dev) | |
3528 | put_device(dev); | |
3529 | } | |
3530 | ||
2a874182 | 3531 | #ifdef CONFIG_PM |
1da177e4 LT |
3532 | static int ohci1394_pci_resume (struct pci_dev *pdev) |
3533 | { | |
f0645e77 | 3534 | /* PowerMac resume code comes first */ |
8c870933 | 3535 | #ifdef CONFIG_PPC_PMAC |
e8222502 | 3536 | if (machine_is(powermac)) { |
1da177e4 LT |
3537 | struct device_node *of_node; |
3538 | ||
3539 | /* Re-enable 1394 */ | |
3540 | of_node = pci_device_to_OF_node (pdev); | |
3541 | if (of_node) | |
3542 | pmac_call_feature (PMAC_FTR_1394_ENABLE, of_node, 0, 1); | |
3543 | } | |
8c870933 | 3544 | #endif /* CONFIG_PPC_PMAC */ |
1da177e4 | 3545 | |
f0645e77 | 3546 | pci_set_power_state(pdev, PCI_D0); |
b21efb59 | 3547 | pci_restore_state(pdev); |
ea6104c2 | 3548 | return pci_enable_device(pdev); |
1da177e4 LT |
3549 | } |
3550 | ||
1da177e4 LT |
3551 | static int ohci1394_pci_suspend (struct pci_dev *pdev, pm_message_t state) |
3552 | { | |
ea6104c2 SR |
3553 | int err; |
3554 | ||
3555 | err = pci_save_state(pdev); | |
3556 | if (err) | |
3557 | goto out; | |
3558 | err = pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
3559 | if (err) | |
3560 | goto out; | |
7334bb4a | 3561 | |
f0645e77 | 3562 | /* PowerMac suspend code comes last */ |
8c870933 | 3563 | #ifdef CONFIG_PPC_PMAC |
e8222502 | 3564 | if (machine_is(powermac)) { |
1da177e4 LT |
3565 | struct device_node *of_node; |
3566 | ||
3567 | /* Disable 1394 */ | |
3568 | of_node = pci_device_to_OF_node (pdev); | |
3569 | if (of_node) | |
3570 | pmac_call_feature(PMAC_FTR_1394_ENABLE, of_node, 0, 0); | |
3571 | } | |
f0645e77 | 3572 | #endif /* CONFIG_PPC_PMAC */ |
ea6104c2 SR |
3573 | out: |
3574 | return err; | |
1da177e4 | 3575 | } |
f0645e77 | 3576 | #endif /* CONFIG_PM */ |
1da177e4 LT |
3577 | |
3578 | #define PCI_CLASS_FIREWIRE_OHCI ((PCI_CLASS_SERIAL_FIREWIRE << 8) | 0x10) | |
3579 | ||
3580 | static struct pci_device_id ohci1394_pci_tbl[] = { | |
3581 | { | |
3582 | .class = PCI_CLASS_FIREWIRE_OHCI, | |
3583 | .class_mask = PCI_ANY_ID, | |
3584 | .vendor = PCI_ANY_ID, | |
3585 | .device = PCI_ANY_ID, | |
3586 | .subvendor = PCI_ANY_ID, | |
3587 | .subdevice = PCI_ANY_ID, | |
3588 | }, | |
3589 | { 0, }, | |
3590 | }; | |
3591 | ||
3592 | MODULE_DEVICE_TABLE(pci, ohci1394_pci_tbl); | |
3593 | ||
3594 | static struct pci_driver ohci1394_pci_driver = { | |
3595 | .name = OHCI1394_DRIVER_NAME, | |
3596 | .id_table = ohci1394_pci_tbl, | |
3597 | .probe = ohci1394_pci_probe, | |
3598 | .remove = ohci1394_pci_remove, | |
2a874182 | 3599 | #ifdef CONFIG_PM |
1da177e4 LT |
3600 | .resume = ohci1394_pci_resume, |
3601 | .suspend = ohci1394_pci_suspend, | |
2a874182 | 3602 | #endif |
1da177e4 LT |
3603 | }; |
3604 | ||
1da177e4 LT |
3605 | /*********************************** |
3606 | * OHCI1394 Video Interface * | |
3607 | ***********************************/ | |
3608 | ||
3609 | /* essentially the only purpose of this code is to allow another | |
3610 | module to hook into ohci's interrupt handler */ | |
3611 | ||
3612 | int ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg) | |
3613 | { | |
3614 | int i=0; | |
3615 | ||
3616 | /* stop the channel program if it's still running */ | |
3617 | reg_write(ohci, reg, 0x8000); | |
3618 | ||
3619 | /* Wait until it effectively stops */ | |
3620 | while (reg_read(ohci, reg) & 0x400) { | |
3621 | i++; | |
3622 | if (i>5000) { | |
3623 | PRINT(KERN_ERR, | |
3624 | "Runaway loop while stopping context: %s...", msg ? msg : ""); | |
3625 | return 1; | |
3626 | } | |
3627 | ||
3628 | mb(); | |
3629 | udelay(10); | |
3630 | } | |
3631 | if (msg) PRINT(KERN_ERR, "%s: dma prg stopped", msg); | |
3632 | return 0; | |
3633 | } | |
3634 | ||
3635 | void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet, int type, | |
3636 | void (*func)(unsigned long), unsigned long data) | |
3637 | { | |
3638 | tasklet_init(&tasklet->tasklet, func, data); | |
3639 | tasklet->type = type; | |
3640 | /* We init the tasklet->link field, so we can list_del() it | |
3641 | * without worrying whether it was added to the list or not. */ | |
3642 | INIT_LIST_HEAD(&tasklet->link); | |
3643 | } | |
3644 | ||
3645 | int ohci1394_register_iso_tasklet(struct ti_ohci *ohci, | |
3646 | struct ohci1394_iso_tasklet *tasklet) | |
3647 | { | |
3648 | unsigned long flags, *usage; | |
3649 | int n, i, r = -EBUSY; | |
3650 | ||
3651 | if (tasklet->type == OHCI_ISO_TRANSMIT) { | |
3652 | n = ohci->nb_iso_xmit_ctx; | |
3653 | usage = &ohci->it_ctx_usage; | |
3654 | } | |
3655 | else { | |
3656 | n = ohci->nb_iso_rcv_ctx; | |
3657 | usage = &ohci->ir_ctx_usage; | |
3658 | ||
3659 | /* only one receive context can be multichannel (OHCI sec 10.4.1) */ | |
3660 | if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) { | |
3661 | if (test_and_set_bit(0, &ohci->ir_multichannel_used)) { | |
3662 | return r; | |
3663 | } | |
3664 | } | |
3665 | } | |
3666 | ||
3667 | spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags); | |
3668 | ||
3669 | for (i = 0; i < n; i++) | |
3670 | if (!test_and_set_bit(i, usage)) { | |
3671 | tasklet->context = i; | |
3672 | list_add_tail(&tasklet->link, &ohci->iso_tasklet_list); | |
3673 | r = 0; | |
3674 | break; | |
3675 | } | |
3676 | ||
3677 | spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags); | |
3678 | ||
3679 | return r; | |
3680 | } | |
3681 | ||
3682 | void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci, | |
3683 | struct ohci1394_iso_tasklet *tasklet) | |
3684 | { | |
3685 | unsigned long flags; | |
3686 | ||
3687 | tasklet_kill(&tasklet->tasklet); | |
3688 | ||
3689 | spin_lock_irqsave(&ohci->iso_tasklet_list_lock, flags); | |
3690 | ||
3691 | if (tasklet->type == OHCI_ISO_TRANSMIT) | |
3692 | clear_bit(tasklet->context, &ohci->it_ctx_usage); | |
3693 | else { | |
3694 | clear_bit(tasklet->context, &ohci->ir_ctx_usage); | |
3695 | ||
3696 | if (tasklet->type == OHCI_ISO_MULTICHANNEL_RECEIVE) { | |
3697 | clear_bit(0, &ohci->ir_multichannel_used); | |
3698 | } | |
3699 | } | |
3700 | ||
3701 | list_del(&tasklet->link); | |
3702 | ||
3703 | spin_unlock_irqrestore(&ohci->iso_tasklet_list_lock, flags); | |
3704 | } | |
3705 | ||
3706 | EXPORT_SYMBOL(ohci1394_stop_context); | |
3707 | EXPORT_SYMBOL(ohci1394_init_iso_tasklet); | |
3708 | EXPORT_SYMBOL(ohci1394_register_iso_tasklet); | |
3709 | EXPORT_SYMBOL(ohci1394_unregister_iso_tasklet); | |
3710 | ||
1da177e4 LT |
3711 | /*********************************** |
3712 | * General module initialization * | |
3713 | ***********************************/ | |
3714 | ||
3715 | MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>"); | |
3716 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE-1394 controllers"); | |
3717 | MODULE_LICENSE("GPL"); | |
3718 | ||
3719 | static void __exit ohci1394_cleanup (void) | |
3720 | { | |
3721 | pci_unregister_driver(&ohci1394_pci_driver); | |
3722 | } | |
3723 | ||
3724 | static int __init ohci1394_init(void) | |
3725 | { | |
3726 | return pci_register_driver(&ohci1394_pci_driver); | |
3727 | } | |
3728 | ||
8df4083c AK |
3729 | /* Register before most other device drivers. |
3730 | * Useful for remote debugging via physical DMA, e.g. using firescope. */ | |
3731 | fs_initcall(ohci1394_init); | |
1da177e4 | 3732 | module_exit(ohci1394_cleanup); |