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Merge branch 'core-objtool-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / drivers / idle / intel_idle.c
CommitLineData
a61127c2 1// SPDX-License-Identifier: GPL-2.0-only
26717172
LB		 2/*
3 * intel_idle.c - native hardware idle loop for modern Intel processors
4 *
317e5ec3 5 * Copyright (c) 2013 - 2020, Intel Corporation.
26717172 6 * Len Brown <len.brown@intel.com>
317e5ec3 7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
26717172
LB		 8 */
9
10/*
11 * intel_idle is a cpuidle driver that loads on specific Intel processors
12 * in lieu of the legacy ACPI processor_idle driver. The intent is to
13 * make Linux more efficient on these processors, as intel_idle knows
14 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
15 */
16
17/*
18 * Design Assumptions
19 *
20 * All CPUs have same idle states as boot CPU
21 *
22 * Chipset BM_STS (bus master status) bit is a NOP
23 * for preventing entry into deep C-stats
24 */
25
26/*
27 * Known limitations
28 *
26717172
LB		 29 * ACPI has a .suspend hack to turn off deep c-statees during suspend
30 * to avoid complications with the lapic timer workaround.
31 * Have not seen issues with suspend, but may need same workaround here.
32 *
26717172
LB		 33 */
34
35/* un-comment DEBUG to enable pr_debug() statements */
36#define DEBUG
37
654d08a4
JP		 38#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
39
18734958 40#include <linux/acpi.h>
26717172
LB		 41#include <linux/kernel.h>
42#include <linux/cpuidle.h>
76962caa 43#include <linux/tick.h>
26717172
LB		 44#include <trace/events/power.h>
45#include <linux/sched.h>
2a2d31c8
SL		 46#include <linux/notifier.h>
47#include <linux/cpu.h>
02c4fae9 48#include <linux/moduleparam.h>
b66b8b9a 49#include <asm/cpu_device_id.h>
db73c5a8 50#include <asm/intel-family.h>
bc83cccc 51#include <asm/mwait.h>
14796fca 52#include <asm/msr.h>
26717172 53
317e5ec3 54#define INTEL_IDLE_VERSION "0.5.1"
26717172 55
26717172
LB		 56static struct cpuidle_driver intel_idle_driver = {
57 .name = "intel_idle",
58 .owner = THIS_MODULE,
59};
60/* intel_idle.max_cstate=0 disables driver */
137ecc77 61static int max_cstate = CPUIDLE_STATE_MAX - 1;
4dcb78ee 62static unsigned int disabled_states_mask;
26717172 63
6eb0443a 64static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
7f843dd7
RW		 65
66static unsigned long auto_demotion_disable_flags;
67static bool disable_promotion_to_c1e;
68
40ab82e0 69static bool lapic_timer_always_reliable;
26717172 70
b66b8b9a
AK		 71struct idle_cpu {
72 struct cpuidle_state *state_table;
73
74 /*
75 * Hardware C-state auto-demotion may not always be optimal.
76 * Indicate which enable bits to clear here.
77 */
78 unsigned long auto_demotion_disable_flags;
8c058d53 79 bool byt_auto_demotion_disable_flag;
32e95180 80 bool disable_promotion_to_c1e;
bff8e60a 81 bool use_acpi;
b66b8b9a
AK		 82};
83
7f843dd7 84static const struct idle_cpu *icpu __initdata;
7f843dd7 85static struct cpuidle_state *cpuidle_state_table __initdata;
26717172 86
6eb0443a
RW		 87static unsigned int mwait_substates __initdata;
88
bff8e60a
RW		 89/*
90 * Enable this state by default even if the ACPI _CST does not list it.
91 */
92#define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15)
93
956d033f
LB		 94/*
95 * Set this flag for states where the HW flushes the TLB for us
96 * and so we don't need cross-calls to keep it consistent.
97 * If this flag is set, SW flushes the TLB, so even if the
98 * HW doesn't do the flushing, this flag is safe to use.
99 */
a472e4b5 100#define CPUIDLE_FLAG_TLB_FLUSHED BIT(16)
956d033f 101
b1beab48
LB		 102/*
103 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
104 * the C-state (top nibble) and sub-state (bottom nibble)
105 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
106 *
107 * We store the hint at the top of our "flags" for each state.
108 */
109#define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
110#define MWAIT2flg(eax) ((eax & 0xFF) << 24)
111
30a996fb
RW		 112/**
113 * intel_idle - Ask the processor to enter the given idle state.
114 * @dev: cpuidle device of the target CPU.
115 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
116 * @index: Target idle state index.
117 *
118 * Use the MWAIT instruction to notify the processor that the CPU represented by
119 * @dev is idle and it can try to enter the idle state corresponding to @index.
120 *
121 * If the local APIC timer is not known to be reliable in the target idle state,
122 * enable one-shot tick broadcasting for the target CPU before executing MWAIT.
123 *
124 * Optionally call leave_mm() for the target CPU upfront to avoid wakeups due to
125 * flushing user TLBs.
126 *
127 * Must be called under local_irq_disable().
128 */
129static __cpuidle int intel_idle(struct cpuidle_device *dev,
130 struct cpuidle_driver *drv, int index)
131{
132 struct cpuidle_state *state = &drv->states[index];
133 unsigned long eax = flg2MWAIT(state->flags);
134 unsigned long ecx = 1; /* break on interrupt flag */
135 bool uninitialized_var(tick);
136 int cpu = smp_processor_id();
137
138 /*
139 * leave_mm() to avoid costly and often unnecessary wakeups
140 * for flushing the user TLB's associated with the active mm.
141 */
142 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
143 leave_mm(cpu);
144
145 if (!static_cpu_has(X86_FEATURE_ARAT) && !lapic_timer_always_reliable) {
146 /*
147 * Switch over to one-shot tick broadcast if the target C-state
148 * is deeper than C1.
149 */
150 if ((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) {
151 tick = true;
152 tick_broadcast_enter();
153 } else {
154 tick = false;
155 }
156 }
157
158 mwait_idle_with_hints(eax, ecx);
159
160 if (!static_cpu_has(X86_FEATURE_ARAT) && tick)
161 tick_broadcast_exit();
162
163 return index;
164}
165
166/**
167 * intel_idle_s2idle - Ask the processor to enter the given idle state.
168 * @dev: cpuidle device of the target CPU.
169 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
170 * @index: Target idle state index.
171 *
172 * Use the MWAIT instruction to notify the processor that the CPU represented by
173 * @dev is idle and it can try to enter the idle state corresponding to @index.
174 *
175 * Invoked as a suspend-to-idle callback routine with frozen user space, frozen
176 * scheduler tick and suspended scheduler clock on the target CPU.
177 */
178static __cpuidle void intel_idle_s2idle(struct cpuidle_device *dev,
179 struct cpuidle_driver *drv, int index)
180{
181 unsigned long eax = flg2MWAIT(drv->states[index].flags);
182 unsigned long ecx = 1; /* break on interrupt flag */
183
184 mwait_idle_with_hints(eax, ecx);
185}
186
26717172
LB		 187/*
188 * States are indexed by the cstate number,
189 * which is also the index into the MWAIT hint array.
190 * Thus C0 is a dummy.
191 */
ab1a8522 192static struct cpuidle_state nehalem_cstates[] __initdata = {
e022e7eb 193 {
de09cdd0 194 .name = "C1",
26717172 195 .desc = "MWAIT 0x00",
b82b6cca 196 .flags = MWAIT2flg(0x00),
26717172 197 .exit_latency = 3,
26717172 198 .target_residency = 6,
5fe2e527 199 .enter = &intel_idle,
28ba086e 200 .enter_s2idle = intel_idle_s2idle, },
32e95180 201 {
de09cdd0 202 .name = "C1E",
32e95180 203 .desc = "MWAIT 0x01",
e6d4f08a 204 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
32e95180
LB		 205 .exit_latency = 10,
206 .target_residency = 20,
5fe2e527 207 .enter = &intel_idle,
28ba086e 208 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 209 {
de09cdd0 210 .name = "C3",
26717172 211 .desc = "MWAIT 0x10",
b82b6cca 212 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
26717172 213 .exit_latency = 20,
26717172 214 .target_residency = 80,
5fe2e527 215 .enter = &intel_idle,
28ba086e 216 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 217 {
de09cdd0 218 .name = "C6",
26717172 219 .desc = "MWAIT 0x20",
b82b6cca 220 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
26717172 221 .exit_latency = 200,
26717172 222 .target_residency = 800,
5fe2e527 223 .enter = &intel_idle,
28ba086e 224 .enter_s2idle = intel_idle_s2idle, },
e022e7eb
LB		 225 {
226 .enter = NULL }
26717172
LB		 227};
228
ab1a8522 229static struct cpuidle_state snb_cstates[] __initdata = {
e022e7eb 230 {
de09cdd0 231 .name = "C1",
d13780d4 232 .desc = "MWAIT 0x00",
b82b6cca 233 .flags = MWAIT2flg(0x00),
32e95180
LB		 234 .exit_latency = 2,
235 .target_residency = 2,
5fe2e527 236 .enter = &intel_idle,
28ba086e 237 .enter_s2idle = intel_idle_s2idle, },
32e95180 238 {
de09cdd0 239 .name = "C1E",
32e95180 240 .desc = "MWAIT 0x01",
e6d4f08a 241 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
32e95180
LB		 242 .exit_latency = 10,
243 .target_residency = 20,
5fe2e527 244 .enter = &intel_idle,
28ba086e 245 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 246 {
de09cdd0 247 .name = "C3",
d13780d4 248 .desc = "MWAIT 0x10",
b82b6cca 249 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4 250 .exit_latency = 80,
ddbd550d 251 .target_residency = 211,
5fe2e527 252 .enter = &intel_idle,
28ba086e 253 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 254 {
de09cdd0 255 .name = "C6",
d13780d4 256 .desc = "MWAIT 0x20",
b82b6cca 257 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4 258 .exit_latency = 104,
ddbd550d 259 .target_residency = 345,
5fe2e527 260 .enter = &intel_idle,
28ba086e 261 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 262 {
de09cdd0 263 .name = "C7",
d13780d4 264 .desc = "MWAIT 0x30",
b82b6cca 265 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
d13780d4 266 .exit_latency = 109,
ddbd550d 267 .target_residency = 345,
5fe2e527 268 .enter = &intel_idle,
28ba086e 269 .enter_s2idle = intel_idle_s2idle, },
e022e7eb
LB		 270 {
271 .enter = NULL }
d13780d4
LB		 272};
273
ab1a8522 274static struct cpuidle_state byt_cstates[] __initdata = {
718987d6 275 {
de09cdd0 276 .name = "C1",
718987d6 277 .desc = "MWAIT 0x00",
b82b6cca 278 .flags = MWAIT2flg(0x00),
718987d6
LB		 279 .exit_latency = 1,
280 .target_residency = 1,
5fe2e527 281 .enter = &intel_idle,
28ba086e 282 .enter_s2idle = intel_idle_s2idle, },
718987d6 283 {
de09cdd0 284 .name = "C6N",
718987d6 285 .desc = "MWAIT 0x58",
b82b6cca 286 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
d7ef7671 287 .exit_latency = 300,
718987d6 288 .target_residency = 275,
5fe2e527 289 .enter = &intel_idle,
28ba086e 290 .enter_s2idle = intel_idle_s2idle, },
718987d6 291 {
de09cdd0 292 .name = "C6S",
718987d6 293 .desc = "MWAIT 0x52",
b82b6cca 294 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
d7ef7671 295 .exit_latency = 500,
718987d6 296 .target_residency = 560,
5fe2e527 297 .enter = &intel_idle,
28ba086e 298 .enter_s2idle = intel_idle_s2idle, },
718987d6 299 {
de09cdd0 300 .name = "C7",
718987d6 301 .desc = "MWAIT 0x60",
b82b6cca 302 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
718987d6 303 .exit_latency = 1200,
d7ef7671 304 .target_residency = 4000,
5fe2e527 305 .enter = &intel_idle,
28ba086e 306 .enter_s2idle = intel_idle_s2idle, },
718987d6 307 {
de09cdd0 308 .name = "C7S",
718987d6 309 .desc = "MWAIT 0x64",
b82b6cca 310 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
718987d6
LB		 311 .exit_latency = 10000,
312 .target_residency = 20000,
5fe2e527 313 .enter = &intel_idle,
28ba086e 314 .enter_s2idle = intel_idle_s2idle, },
718987d6
LB		 315 {
316 .enter = NULL }
317};
318
ab1a8522 319static struct cpuidle_state cht_cstates[] __initdata = {
cab07a56 320 {
de09cdd0 321 .name = "C1",
cab07a56
LB		 322 .desc = "MWAIT 0x00",
323 .flags = MWAIT2flg(0x00),
324 .exit_latency = 1,
325 .target_residency = 1,
326 .enter = &intel_idle,
28ba086e 327 .enter_s2idle = intel_idle_s2idle, },
cab07a56 328 {
de09cdd0 329 .name = "C6N",
cab07a56
LB		 330 .desc = "MWAIT 0x58",
331 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
332 .exit_latency = 80,
333 .target_residency = 275,
334 .enter = &intel_idle,
28ba086e 335 .enter_s2idle = intel_idle_s2idle, },
cab07a56 336 {
de09cdd0 337 .name = "C6S",
cab07a56
LB		 338 .desc = "MWAIT 0x52",
339 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
340 .exit_latency = 200,
341 .target_residency = 560,
342 .enter = &intel_idle,
28ba086e 343 .enter_s2idle = intel_idle_s2idle, },
cab07a56 344 {
de09cdd0 345 .name = "C7",
cab07a56
LB		 346 .desc = "MWAIT 0x60",
347 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
348 .exit_latency = 1200,
349 .target_residency = 4000,
350 .enter = &intel_idle,
28ba086e 351 .enter_s2idle = intel_idle_s2idle, },
cab07a56 352 {
de09cdd0 353 .name = "C7S",
cab07a56
LB		 354 .desc = "MWAIT 0x64",
355 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
356 .exit_latency = 10000,
357 .target_residency = 20000,
358 .enter = &intel_idle,
28ba086e 359 .enter_s2idle = intel_idle_s2idle, },
cab07a56
LB		 360 {
361 .enter = NULL }
362};
363
ab1a8522 364static struct cpuidle_state ivb_cstates[] __initdata = {
e022e7eb 365 {
de09cdd0 366 .name = "C1",
6edab08c 367 .desc = "MWAIT 0x00",
b82b6cca 368 .flags = MWAIT2flg(0x00),
6edab08c
LB		 369 .exit_latency = 1,
370 .target_residency = 1,
5fe2e527 371 .enter = &intel_idle,
28ba086e 372 .enter_s2idle = intel_idle_s2idle, },
32e95180 373 {
de09cdd0 374 .name = "C1E",
32e95180 375 .desc = "MWAIT 0x01",
e6d4f08a 376 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
32e95180
LB		 377 .exit_latency = 10,
378 .target_residency = 20,
5fe2e527 379 .enter = &intel_idle,
28ba086e 380 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 381 {
de09cdd0 382 .name = "C3",
6edab08c 383 .desc = "MWAIT 0x10",
b82b6cca 384 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
6edab08c
LB		 385 .exit_latency = 59,
386 .target_residency = 156,
5fe2e527 387 .enter = &intel_idle,
28ba086e 388 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 389 {
de09cdd0 390 .name = "C6",
6edab08c 391 .desc = "MWAIT 0x20",
b82b6cca 392 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
6edab08c
LB		 393 .exit_latency = 80,
394 .target_residency = 300,
5fe2e527 395 .enter = &intel_idle,
28ba086e 396 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 397 {
de09cdd0 398 .name = "C7",
6edab08c 399 .desc = "MWAIT 0x30",
b82b6cca 400 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
6edab08c
LB		 401 .exit_latency = 87,
402 .target_residency = 300,
5fe2e527 403 .enter = &intel_idle,
28ba086e 404 .enter_s2idle = intel_idle_s2idle, },
e022e7eb
LB		 405 {
406 .enter = NULL }
6edab08c
LB		 407};
408
ab1a8522 409static struct cpuidle_state ivt_cstates[] __initdata = {
0138d8f0 410 {
de09cdd0 411 .name = "C1",
0138d8f0 412 .desc = "MWAIT 0x00",
b82b6cca 413 .flags = MWAIT2flg(0x00),
0138d8f0
LB		 414 .exit_latency = 1,
415 .target_residency = 1,
5fe2e527 416 .enter = &intel_idle,
28ba086e 417 .enter_s2idle = intel_idle_s2idle, },
0138d8f0 418 {
de09cdd0 419 .name = "C1E",
0138d8f0 420 .desc = "MWAIT 0x01",
e6d4f08a 421 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
0138d8f0
LB		 422 .exit_latency = 10,
423 .target_residency = 80,
5fe2e527 424 .enter = &intel_idle,
28ba086e 425 .enter_s2idle = intel_idle_s2idle, },
0138d8f0 426 {
de09cdd0 427 .name = "C3",
0138d8f0 428 .desc = "MWAIT 0x10",
b82b6cca 429 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
0138d8f0
LB		 430 .exit_latency = 59,
431 .target_residency = 156,
5fe2e527 432 .enter = &intel_idle,
28ba086e 433 .enter_s2idle = intel_idle_s2idle, },
0138d8f0 434 {
de09cdd0 435 .name = "C6",
0138d8f0 436 .desc = "MWAIT 0x20",
b82b6cca 437 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
0138d8f0
LB		 438 .exit_latency = 82,
439 .target_residency = 300,
5fe2e527 440 .enter = &intel_idle,
28ba086e 441 .enter_s2idle = intel_idle_s2idle, },
0138d8f0
LB		 442 {
443 .enter = NULL }
444};
445
ab1a8522 446static struct cpuidle_state ivt_cstates_4s[] __initdata = {
0138d8f0 447 {
de09cdd0 448 .name = "C1",
0138d8f0 449 .desc = "MWAIT 0x00",
b82b6cca 450 .flags = MWAIT2flg(0x00),
0138d8f0
LB		 451 .exit_latency = 1,
452 .target_residency = 1,
5fe2e527 453 .enter = &intel_idle,
28ba086e 454 .enter_s2idle = intel_idle_s2idle, },
0138d8f0 455 {
de09cdd0 456 .name = "C1E",
0138d8f0 457 .desc = "MWAIT 0x01",
e6d4f08a 458 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
0138d8f0
LB		 459 .exit_latency = 10,
460 .target_residency = 250,
5fe2e527 461 .enter = &intel_idle,
28ba086e 462 .enter_s2idle = intel_idle_s2idle, },
0138d8f0 463 {
de09cdd0 464 .name = "C3",
0138d8f0 465 .desc = "MWAIT 0x10",
b82b6cca 466 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
0138d8f0
LB		 467 .exit_latency = 59,
468 .target_residency = 300,
5fe2e527 469 .enter = &intel_idle,
28ba086e 470 .enter_s2idle = intel_idle_s2idle, },
0138d8f0 471 {
de09cdd0 472 .name = "C6",
0138d8f0 473 .desc = "MWAIT 0x20",
b82b6cca 474 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
0138d8f0
LB		 475 .exit_latency = 84,
476 .target_residency = 400,
5fe2e527 477 .enter = &intel_idle,
28ba086e 478 .enter_s2idle = intel_idle_s2idle, },
0138d8f0
LB		 479 {
480 .enter = NULL }
481};
482
ab1a8522 483static struct cpuidle_state ivt_cstates_8s[] __initdata = {
0138d8f0 484 {
de09cdd0 485 .name = "C1",
0138d8f0 486 .desc = "MWAIT 0x00",
b82b6cca 487 .flags = MWAIT2flg(0x00),
0138d8f0
LB		 488 .exit_latency = 1,
489 .target_residency = 1,
5fe2e527 490 .enter = &intel_idle,
28ba086e 491 .enter_s2idle = intel_idle_s2idle, },
0138d8f0 492 {
de09cdd0 493 .name = "C1E",
0138d8f0 494 .desc = "MWAIT 0x01",
e6d4f08a 495 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
0138d8f0
LB		 496 .exit_latency = 10,
497 .target_residency = 500,
5fe2e527 498 .enter = &intel_idle,
28ba086e 499 .enter_s2idle = intel_idle_s2idle, },
0138d8f0 500 {
de09cdd0 501 .name = "C3",
0138d8f0 502 .desc = "MWAIT 0x10",
b82b6cca 503 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
0138d8f0
LB		 504 .exit_latency = 59,
505 .target_residency = 600,
5fe2e527 506 .enter = &intel_idle,
28ba086e 507 .enter_s2idle = intel_idle_s2idle, },
0138d8f0 508 {
de09cdd0 509 .name = "C6",
0138d8f0 510 .desc = "MWAIT 0x20",
b82b6cca 511 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
0138d8f0
LB		 512 .exit_latency = 88,
513 .target_residency = 700,
5fe2e527 514 .enter = &intel_idle,
28ba086e 515 .enter_s2idle = intel_idle_s2idle, },
0138d8f0
LB		 516 {
517 .enter = NULL }
518};
519
ab1a8522 520static struct cpuidle_state hsw_cstates[] __initdata = {
e022e7eb 521 {
de09cdd0 522 .name = "C1",
85a4d2d4 523 .desc = "MWAIT 0x00",
b82b6cca 524 .flags = MWAIT2flg(0x00),
85a4d2d4
LB		 525 .exit_latency = 2,
526 .target_residency = 2,
5fe2e527 527 .enter = &intel_idle,
28ba086e 528 .enter_s2idle = intel_idle_s2idle, },
32e95180 529 {
de09cdd0 530 .name = "C1E",
32e95180 531 .desc = "MWAIT 0x01",
e6d4f08a 532 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
32e95180
LB		 533 .exit_latency = 10,
534 .target_residency = 20,
5fe2e527 535 .enter = &intel_idle,
28ba086e 536 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 537 {
de09cdd0 538 .name = "C3",
85a4d2d4 539 .desc = "MWAIT 0x10",
b82b6cca 540 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
85a4d2d4
LB		 541 .exit_latency = 33,
542 .target_residency = 100,
5fe2e527 543 .enter = &intel_idle,
28ba086e 544 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 545 {
de09cdd0 546 .name = "C6",
85a4d2d4 547 .desc = "MWAIT 0x20",
b82b6cca 548 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
85a4d2d4
LB		 549 .exit_latency = 133,
550 .target_residency = 400,
5fe2e527 551 .enter = &intel_idle,
28ba086e 552 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 553 {
de09cdd0 554 .name = "C7s",
85a4d2d4 555 .desc = "MWAIT 0x32",
b82b6cca 556 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
85a4d2d4
LB		 557 .exit_latency = 166,
558 .target_residency = 500,
5fe2e527 559 .enter = &intel_idle,
28ba086e 560 .enter_s2idle = intel_idle_s2idle, },
86239ceb 561 {
de09cdd0 562 .name = "C8",
86239ceb 563 .desc = "MWAIT 0x40",
b82b6cca 564 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
86239ceb
LB		 565 .exit_latency = 300,
566 .target_residency = 900,
5fe2e527 567 .enter = &intel_idle,
28ba086e 568 .enter_s2idle = intel_idle_s2idle, },
86239ceb 569 {
de09cdd0 570 .name = "C9",
86239ceb 571 .desc = "MWAIT 0x50",
b82b6cca 572 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
86239ceb
LB		 573 .exit_latency = 600,
574 .target_residency = 1800,
5fe2e527 575 .enter = &intel_idle,
28ba086e 576 .enter_s2idle = intel_idle_s2idle, },
86239ceb 577 {
de09cdd0 578 .name = "C10",
86239ceb 579 .desc = "MWAIT 0x60",
b82b6cca 580 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
86239ceb
LB		 581 .exit_latency = 2600,
582 .target_residency = 7700,
5fe2e527 583 .enter = &intel_idle,
28ba086e 584 .enter_s2idle = intel_idle_s2idle, },
e022e7eb
LB		 585 {
586 .enter = NULL }
85a4d2d4 587};
ab1a8522 588static struct cpuidle_state bdw_cstates[] __initdata = {
a138b568 589 {
de09cdd0 590 .name = "C1",
a138b568 591 .desc = "MWAIT 0x00",
b82b6cca 592 .flags = MWAIT2flg(0x00),
a138b568
LB		 593 .exit_latency = 2,
594 .target_residency = 2,
5fe2e527 595 .enter = &intel_idle,
28ba086e 596 .enter_s2idle = intel_idle_s2idle, },
a138b568 597 {
de09cdd0 598 .name = "C1E",
a138b568 599 .desc = "MWAIT 0x01",
e6d4f08a 600 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
a138b568
LB		 601 .exit_latency = 10,
602 .target_residency = 20,
5fe2e527 603 .enter = &intel_idle,
28ba086e 604 .enter_s2idle = intel_idle_s2idle, },
a138b568 605 {
de09cdd0 606 .name = "C3",
a138b568 607 .desc = "MWAIT 0x10",
b82b6cca 608 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
a138b568
LB		 609 .exit_latency = 40,
610 .target_residency = 100,
5fe2e527 611 .enter = &intel_idle,
28ba086e 612 .enter_s2idle = intel_idle_s2idle, },
a138b568 613 {
de09cdd0 614 .name = "C6",
a138b568 615 .desc = "MWAIT 0x20",
b82b6cca 616 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
a138b568
LB		 617 .exit_latency = 133,
618 .target_residency = 400,
5fe2e527 619 .enter = &intel_idle,
28ba086e 620 .enter_s2idle = intel_idle_s2idle, },
a138b568 621 {
de09cdd0 622 .name = "C7s",
a138b568 623 .desc = "MWAIT 0x32",
b82b6cca 624 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
a138b568
LB		 625 .exit_latency = 166,
626 .target_residency = 500,
5fe2e527 627 .enter = &intel_idle,
28ba086e 628 .enter_s2idle = intel_idle_s2idle, },
a138b568 629 {
de09cdd0 630 .name = "C8",
a138b568 631 .desc = "MWAIT 0x40",
b82b6cca 632 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
a138b568
LB		 633 .exit_latency = 300,
634 .target_residency = 900,
5fe2e527 635 .enter = &intel_idle,
28ba086e 636 .enter_s2idle = intel_idle_s2idle, },
a138b568 637 {
de09cdd0 638 .name = "C9",
a138b568 639 .desc = "MWAIT 0x50",
b82b6cca 640 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
a138b568
LB		 641 .exit_latency = 600,
642 .target_residency = 1800,
5fe2e527 643 .enter = &intel_idle,
28ba086e 644 .enter_s2idle = intel_idle_s2idle, },
a138b568 645 {
de09cdd0 646 .name = "C10",
a138b568 647 .desc = "MWAIT 0x60",
b82b6cca 648 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
a138b568
LB		 649 .exit_latency = 2600,
650 .target_residency = 7700,
5fe2e527 651 .enter = &intel_idle,
28ba086e 652 .enter_s2idle = intel_idle_s2idle, },
a138b568
LB		 653 {
654 .enter = NULL }
655};
85a4d2d4 656
ab1a8522 657static struct cpuidle_state skl_cstates[] __initdata = {
493f133f 658 {
de09cdd0 659 .name = "C1",
493f133f
LB		 660 .desc = "MWAIT 0x00",
661 .flags = MWAIT2flg(0x00),
662 .exit_latency = 2,
663 .target_residency = 2,
664 .enter = &intel_idle,
28ba086e 665 .enter_s2idle = intel_idle_s2idle, },
493f133f 666 {
de09cdd0 667 .name = "C1E",
493f133f 668 .desc = "MWAIT 0x01",
e6d4f08a 669 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
493f133f
LB		 670 .exit_latency = 10,
671 .target_residency = 20,
672 .enter = &intel_idle,
28ba086e 673 .enter_s2idle = intel_idle_s2idle, },
493f133f 674 {
de09cdd0 675 .name = "C3",
493f133f
LB		 676 .desc = "MWAIT 0x10",
677 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
678 .exit_latency = 70,
679 .target_residency = 100,
680 .enter = &intel_idle,
28ba086e 681 .enter_s2idle = intel_idle_s2idle, },
493f133f 682 {
de09cdd0 683 .name = "C6",
493f133f
LB		 684 .desc = "MWAIT 0x20",
685 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
135919a3 686 .exit_latency = 85,
493f133f
LB		 687 .target_residency = 200,
688 .enter = &intel_idle,
28ba086e 689 .enter_s2idle = intel_idle_s2idle, },
493f133f 690 {
de09cdd0 691 .name = "C7s",
493f133f
LB		 692 .desc = "MWAIT 0x33",
693 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
694 .exit_latency = 124,
695 .target_residency = 800,
696 .enter = &intel_idle,
28ba086e 697 .enter_s2idle = intel_idle_s2idle, },
493f133f 698 {
de09cdd0 699 .name = "C8",
493f133f
LB		 700 .desc = "MWAIT 0x40",
701 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
135919a3 702 .exit_latency = 200,
493f133f
LB		 703 .target_residency = 800,
704 .enter = &intel_idle,
28ba086e 705 .enter_s2idle = intel_idle_s2idle, },
135919a3 706 {
de09cdd0 707 .name = "C9",
135919a3
LB		 708 .desc = "MWAIT 0x50",
709 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
710 .exit_latency = 480,
711 .target_residency = 5000,
712 .enter = &intel_idle,
28ba086e 713 .enter_s2idle = intel_idle_s2idle, },
493f133f 714 {
de09cdd0 715 .name = "C10",
493f133f
LB		 716 .desc = "MWAIT 0x60",
717 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
718 .exit_latency = 890,
719 .target_residency = 5000,
720 .enter = &intel_idle,
28ba086e 721 .enter_s2idle = intel_idle_s2idle, },
493f133f
LB		 722 {
723 .enter = NULL }
724};
725
ab1a8522 726static struct cpuidle_state skx_cstates[] __initdata = {
f9e71657 727 {
de09cdd0 728 .name = "C1",
f9e71657
LB		 729 .desc = "MWAIT 0x00",
730 .flags = MWAIT2flg(0x00),
731 .exit_latency = 2,
732 .target_residency = 2,
733 .enter = &intel_idle,
28ba086e 734 .enter_s2idle = intel_idle_s2idle, },
f9e71657 735 {
de09cdd0 736 .name = "C1E",
f9e71657 737 .desc = "MWAIT 0x01",
e6d4f08a 738 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
f9e71657
LB		 739 .exit_latency = 10,
740 .target_residency = 20,
741 .enter = &intel_idle,
28ba086e 742 .enter_s2idle = intel_idle_s2idle, },
f9e71657 743 {
de09cdd0 744 .name = "C6",
f9e71657
LB		 745 .desc = "MWAIT 0x20",
746 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
747 .exit_latency = 133,
748 .target_residency = 600,
749 .enter = &intel_idle,
28ba086e 750 .enter_s2idle = intel_idle_s2idle, },
f9e71657
LB		 751 {
752 .enter = NULL }
753};
754
ab1a8522 755static struct cpuidle_state atom_cstates[] __initdata = {
e022e7eb 756 {
de09cdd0 757 .name = "C1E",
26717172 758 .desc = "MWAIT 0x00",
b82b6cca 759 .flags = MWAIT2flg(0x00),
32e95180
LB		 760 .exit_latency = 10,
761 .target_residency = 20,
5fe2e527 762 .enter = &intel_idle,
28ba086e 763 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 764 {
de09cdd0 765 .name = "C2",
26717172 766 .desc = "MWAIT 0x10",
b82b6cca 767 .flags = MWAIT2flg(0x10),
26717172 768 .exit_latency = 20,
26717172 769 .target_residency = 80,
5fe2e527 770 .enter = &intel_idle,
28ba086e 771 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 772 {
de09cdd0 773 .name = "C4",
26717172 774 .desc = "MWAIT 0x30",
b82b6cca 775 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
26717172 776 .exit_latency = 100,
26717172 777 .target_residency = 400,
5fe2e527 778 .enter = &intel_idle,
28ba086e 779 .enter_s2idle = intel_idle_s2idle, },
e022e7eb 780 {
de09cdd0 781 .name = "C6",
7fcca7d9 782 .desc = "MWAIT 0x52",
b82b6cca 783 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
7fcca7d9 784 .exit_latency = 140,
7fcca7d9 785 .target_residency = 560,
5fe2e527 786 .enter = &intel_idle,
28ba086e 787 .enter_s2idle = intel_idle_s2idle, },
e022e7eb
LB		 788 {
789 .enter = NULL }
26717172 790};
ab1a8522 791static struct cpuidle_state tangier_cstates[] __initdata = {
5e7ec268 792 {
de09cdd0 793 .name = "C1",
5e7ec268
AS		 794 .desc = "MWAIT 0x00",
795 .flags = MWAIT2flg(0x00),
796 .exit_latency = 1,
797 .target_residency = 4,
798 .enter = &intel_idle,
28ba086e 799 .enter_s2idle = intel_idle_s2idle, },
5e7ec268 800 {
de09cdd0 801 .name = "C4",
5e7ec268
AS		 802 .desc = "MWAIT 0x30",
803 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
804 .exit_latency = 100,
805 .target_residency = 400,
806 .enter = &intel_idle,
28ba086e 807 .enter_s2idle = intel_idle_s2idle, },
5e7ec268 808 {
de09cdd0 809 .name = "C6",
5e7ec268
AS		 810 .desc = "MWAIT 0x52",
811 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
812 .exit_latency = 140,
813 .target_residency = 560,
814 .enter = &intel_idle,
28ba086e 815 .enter_s2idle = intel_idle_s2idle, },
5e7ec268 816 {
de09cdd0 817 .name = "C7",
5e7ec268
AS		 818 .desc = "MWAIT 0x60",
819 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
820 .exit_latency = 1200,
821 .target_residency = 4000,
822 .enter = &intel_idle,
28ba086e 823 .enter_s2idle = intel_idle_s2idle, },
5e7ec268 824 {
de09cdd0 825 .name = "C9",
5e7ec268
AS		 826 .desc = "MWAIT 0x64",
827 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
828 .exit_latency = 10000,
829 .target_residency = 20000,
830 .enter = &intel_idle,
28ba086e 831 .enter_s2idle = intel_idle_s2idle, },
5e7ec268
AS		 832 {
833 .enter = NULL }
834};
ab1a8522 835static struct cpuidle_state avn_cstates[] __initdata = {
fab04b22 836 {
de09cdd0 837 .name = "C1",
fab04b22 838 .desc = "MWAIT 0x00",
b82b6cca 839 .flags = MWAIT2flg(0x00),
fab04b22
LB		 840 .exit_latency = 2,
841 .target_residency = 2,
5fe2e527 842 .enter = &intel_idle,
28ba086e 843 .enter_s2idle = intel_idle_s2idle, },
fab04b22 844 {
de09cdd0 845 .name = "C6",
fab04b22 846 .desc = "MWAIT 0x51",
b82b6cca 847 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
fab04b22
LB		 848 .exit_latency = 15,
849 .target_residency = 45,
5fe2e527 850 .enter = &intel_idle,
28ba086e 851 .enter_s2idle = intel_idle_s2idle, },
88390996
JL		 852 {
853 .enter = NULL }
fab04b22 854};
ab1a8522 855static struct cpuidle_state knl_cstates[] __initdata = {
281baf7a 856 {
de09cdd0 857 .name = "C1",
281baf7a
DC		 858 .desc = "MWAIT 0x00",
859 .flags = MWAIT2flg(0x00),
860 .exit_latency = 1,
861 .target_residency = 2,
862 .enter = &intel_idle,
28ba086e 863 .enter_s2idle = intel_idle_s2idle },
281baf7a 864 {
de09cdd0 865 .name = "C6",
281baf7a
DC		 866 .desc = "MWAIT 0x10",
867 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
868 .exit_latency = 120,
869 .target_residency = 500,
870 .enter = &intel_idle,
28ba086e 871 .enter_s2idle = intel_idle_s2idle },
281baf7a
DC		 872 {
873 .enter = NULL }
874};
26717172 875
ab1a8522 876static struct cpuidle_state bxt_cstates[] __initdata = {
5dcef694 877 {
de09cdd0 878 .name = "C1",
5dcef694
LB		 879 .desc = "MWAIT 0x00",
880 .flags = MWAIT2flg(0x00),
881 .exit_latency = 2,
882 .target_residency = 2,
883 .enter = &intel_idle,
28ba086e 884 .enter_s2idle = intel_idle_s2idle, },
5dcef694 885 {
de09cdd0 886 .name = "C1E",
5dcef694 887 .desc = "MWAIT 0x01",
e6d4f08a 888 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
5dcef694
LB		 889 .exit_latency = 10,
890 .target_residency = 20,
891 .enter = &intel_idle,
28ba086e 892 .enter_s2idle = intel_idle_s2idle, },
5dcef694 893 {
de09cdd0 894 .name = "C6",
5dcef694
LB		 895 .desc = "MWAIT 0x20",
896 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
897 .exit_latency = 133,
898 .target_residency = 133,
899 .enter = &intel_idle,
28ba086e 900 .enter_s2idle = intel_idle_s2idle, },
5dcef694 901 {
de09cdd0 902 .name = "C7s",
5dcef694
LB		 903 .desc = "MWAIT 0x31",
904 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
905 .exit_latency = 155,
906 .target_residency = 155,
907 .enter = &intel_idle,
28ba086e 908 .enter_s2idle = intel_idle_s2idle, },
5dcef694 909 {
de09cdd0 910 .name = "C8",
5dcef694
LB		 911 .desc = "MWAIT 0x40",
912 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
913 .exit_latency = 1000,
914 .target_residency = 1000,
915 .enter = &intel_idle,
28ba086e 916 .enter_s2idle = intel_idle_s2idle, },
5dcef694 917 {
de09cdd0 918 .name = "C9",
5dcef694
LB		 919 .desc = "MWAIT 0x50",
920 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
921 .exit_latency = 2000,
922 .target_residency = 2000,
923 .enter = &intel_idle,
28ba086e 924 .enter_s2idle = intel_idle_s2idle, },
5dcef694 925 {
de09cdd0 926 .name = "C10",
5dcef694
LB		 927 .desc = "MWAIT 0x60",
928 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
929 .exit_latency = 10000,
930 .target_residency = 10000,
931 .enter = &intel_idle,
28ba086e 932 .enter_s2idle = intel_idle_s2idle, },
5dcef694
LB		 933 {
934 .enter = NULL }
935};
936
ab1a8522 937static struct cpuidle_state dnv_cstates[] __initdata = {
0080d65b 938 {
de09cdd0 939 .name = "C1",
0080d65b
JP		 940 .desc = "MWAIT 0x00",
941 .flags = MWAIT2flg(0x00),
942 .exit_latency = 2,
943 .target_residency = 2,
944 .enter = &intel_idle,
28ba086e 945 .enter_s2idle = intel_idle_s2idle, },
0080d65b 946 {
de09cdd0 947 .name = "C1E",
0080d65b 948 .desc = "MWAIT 0x01",
e6d4f08a 949 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
0080d65b
JP		 950 .exit_latency = 10,
951 .target_residency = 20,
952 .enter = &intel_idle,
28ba086e 953 .enter_s2idle = intel_idle_s2idle, },
0080d65b 954 {
de09cdd0 955 .name = "C6",
0080d65b
JP		 956 .desc = "MWAIT 0x20",
957 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
958 .exit_latency = 50,
959 .target_residency = 500,
960 .enter = &intel_idle,
28ba086e 961 .enter_s2idle = intel_idle_s2idle, },
0080d65b
JP		 962 {
963 .enter = NULL }
964};
965
ab1a8522 966static const struct idle_cpu idle_cpu_nehalem __initconst = {
b66b8b9a 967 .state_table = nehalem_cstates,
b66b8b9a 968 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
32e95180 969 .disable_promotion_to_c1e = true,
b66b8b9a
AK		 970};
971
ab1a8522 972static const struct idle_cpu idle_cpu_nhx __initconst = {
e6d4f08a
RW		 973 .state_table = nehalem_cstates,
974 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
975 .disable_promotion_to_c1e = true,
976 .use_acpi = true,
977};
978
ab1a8522 979static const struct idle_cpu idle_cpu_atom __initconst = {
b66b8b9a
AK		 980 .state_table = atom_cstates,
981};
982
ab1a8522 983static const struct idle_cpu idle_cpu_tangier __initconst = {
5e7ec268
AS		 984 .state_table = tangier_cstates,
985};
986
ab1a8522 987static const struct idle_cpu idle_cpu_lincroft __initconst = {
b66b8b9a
AK		 988 .state_table = atom_cstates,
989 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
990};
991
ab1a8522 992static const struct idle_cpu idle_cpu_snb __initconst = {
b66b8b9a 993 .state_table = snb_cstates,
32e95180 994 .disable_promotion_to_c1e = true,
b66b8b9a
AK		 995};
996
ab1a8522 997static const struct idle_cpu idle_cpu_snx __initconst = {
e6d4f08a
RW		 998 .state_table = snb_cstates,
999 .disable_promotion_to_c1e = true,
1000 .use_acpi = true,
1001};
1002
ab1a8522 1003static const struct idle_cpu idle_cpu_byt __initconst = {
718987d6
LB		 1004 .state_table = byt_cstates,
1005 .disable_promotion_to_c1e = true,
8c058d53 1006 .byt_auto_demotion_disable_flag = true,
718987d6
LB		 1007};
1008
ab1a8522 1009static const struct idle_cpu idle_cpu_cht __initconst = {
cab07a56
LB		 1010 .state_table = cht_cstates,
1011 .disable_promotion_to_c1e = true,
1012 .byt_auto_demotion_disable_flag = true,
1013};
1014
ab1a8522 1015static const struct idle_cpu idle_cpu_ivb __initconst = {
6edab08c 1016 .state_table = ivb_cstates,
32e95180 1017 .disable_promotion_to_c1e = true,
6edab08c
LB		 1018};
1019
ab1a8522 1020static const struct idle_cpu idle_cpu_ivt __initconst = {
0138d8f0
LB		 1021 .state_table = ivt_cstates,
1022 .disable_promotion_to_c1e = true,
e6d4f08a 1023 .use_acpi = true,
0138d8f0
LB		 1024};
1025
ab1a8522 1026static const struct idle_cpu idle_cpu_hsw __initconst = {
85a4d2d4 1027 .state_table = hsw_cstates,
32e95180 1028 .disable_promotion_to_c1e = true,
85a4d2d4
LB		 1029};
1030
ab1a8522 1031static const struct idle_cpu idle_cpu_hsx __initconst = {
e6d4f08a
RW		 1032 .state_table = hsw_cstates,
1033 .disable_promotion_to_c1e = true,
1034 .use_acpi = true,
1035};
1036
ab1a8522 1037static const struct idle_cpu idle_cpu_bdw __initconst = {
a138b568
LB		 1038 .state_table = bdw_cstates,
1039 .disable_promotion_to_c1e = true,
1040};
1041
ab1a8522 1042static const struct idle_cpu idle_cpu_bdx __initconst = {
e6d4f08a
RW		 1043 .state_table = bdw_cstates,
1044 .disable_promotion_to_c1e = true,
1045 .use_acpi = true,
1046};
1047
ab1a8522 1048static const struct idle_cpu idle_cpu_skl __initconst = {
493f133f
LB		 1049 .state_table = skl_cstates,
1050 .disable_promotion_to_c1e = true,
1051};
1052
ab1a8522 1053static const struct idle_cpu idle_cpu_skx __initconst = {
f9e71657
LB		 1054 .state_table = skx_cstates,
1055 .disable_promotion_to_c1e = true,
e6d4f08a 1056 .use_acpi = true,
f9e71657 1057};
493f133f 1058
ab1a8522 1059static const struct idle_cpu idle_cpu_avn __initconst = {
fab04b22
LB		 1060 .state_table = avn_cstates,
1061 .disable_promotion_to_c1e = true,
e6d4f08a 1062 .use_acpi = true,
fab04b22
LB		 1063};
1064
ab1a8522 1065static const struct idle_cpu idle_cpu_knl __initconst = {
281baf7a 1066 .state_table = knl_cstates,
e6d4f08a 1067 .use_acpi = true,
281baf7a
DC		 1068};
1069
ab1a8522 1070static const struct idle_cpu idle_cpu_bxt __initconst = {
5dcef694
LB		 1071 .state_table = bxt_cstates,
1072 .disable_promotion_to_c1e = true,
1073};
1074
ab1a8522 1075static const struct idle_cpu idle_cpu_dnv __initconst = {
0080d65b
JP		 1076 .state_table = dnv_cstates,
1077 .disable_promotion_to_c1e = true,
e6d4f08a 1078 .use_acpi = true,
0080d65b
JP		 1079};
1080
d5cdc3c4 1081static const struct x86_cpu_id intel_idle_ids[] __initconst = {
e6d4f08a 1082 INTEL_CPU_FAM6(NEHALEM_EP, idle_cpu_nhx),
a4a008e5
AS		 1083 INTEL_CPU_FAM6(NEHALEM, idle_cpu_nehalem),
1084 INTEL_CPU_FAM6(NEHALEM_G, idle_cpu_nehalem),
1085 INTEL_CPU_FAM6(WESTMERE, idle_cpu_nehalem),
e6d4f08a
RW		 1086 INTEL_CPU_FAM6(WESTMERE_EP, idle_cpu_nhx),
1087 INTEL_CPU_FAM6(NEHALEM_EX, idle_cpu_nhx),
c05f3642
LT		 1088 INTEL_CPU_FAM6(ATOM_BONNELL, idle_cpu_atom),
1089 INTEL_CPU_FAM6(ATOM_BONNELL_MID, idle_cpu_lincroft),
e6d4f08a 1090 INTEL_CPU_FAM6(WESTMERE_EX, idle_cpu_nhx),
a4a008e5 1091 INTEL_CPU_FAM6(SANDYBRIDGE, idle_cpu_snb),
e6d4f08a 1092 INTEL_CPU_FAM6(SANDYBRIDGE_X, idle_cpu_snx),
c05f3642
LT		 1093 INTEL_CPU_FAM6(ATOM_SALTWELL, idle_cpu_atom),
1094 INTEL_CPU_FAM6(ATOM_SILVERMONT, idle_cpu_byt),
1095 INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, idle_cpu_tangier),
a4a008e5
AS		 1096 INTEL_CPU_FAM6(ATOM_AIRMONT, idle_cpu_cht),
1097 INTEL_CPU_FAM6(IVYBRIDGE, idle_cpu_ivb),
1098 INTEL_CPU_FAM6(IVYBRIDGE_X, idle_cpu_ivt),
c66f78a6 1099 INTEL_CPU_FAM6(HASWELL, idle_cpu_hsw),
e6d4f08a 1100 INTEL_CPU_FAM6(HASWELL_X, idle_cpu_hsx),
af239c44 1101 INTEL_CPU_FAM6(HASWELL_L, idle_cpu_hsw),
5e741407 1102 INTEL_CPU_FAM6(HASWELL_G, idle_cpu_hsw),
5ebb34ed 1103 INTEL_CPU_FAM6(ATOM_SILVERMONT_D, idle_cpu_avn),
c66f78a6 1104 INTEL_CPU_FAM6(BROADWELL, idle_cpu_bdw),
5e741407 1105 INTEL_CPU_FAM6(BROADWELL_G, idle_cpu_bdw),
e6d4f08a
RW		 1106 INTEL_CPU_FAM6(BROADWELL_X, idle_cpu_bdx),
1107 INTEL_CPU_FAM6(BROADWELL_D, idle_cpu_bdx),
af239c44 1108 INTEL_CPU_FAM6(SKYLAKE_L, idle_cpu_skl),
c66f78a6 1109 INTEL_CPU_FAM6(SKYLAKE, idle_cpu_skl),
af239c44 1110 INTEL_CPU_FAM6(KABYLAKE_L, idle_cpu_skl),
c66f78a6 1111 INTEL_CPU_FAM6(KABYLAKE, idle_cpu_skl),
a4a008e5
AS		 1112 INTEL_CPU_FAM6(SKYLAKE_X, idle_cpu_skx),
1113 INTEL_CPU_FAM6(XEON_PHI_KNL, idle_cpu_knl),
1114 INTEL_CPU_FAM6(XEON_PHI_KNM, idle_cpu_knl),
1115 INTEL_CPU_FAM6(ATOM_GOLDMONT, idle_cpu_bxt),
c05f3642 1116 INTEL_CPU_FAM6(ATOM_GOLDMONT_PLUS, idle_cpu_bxt),
5ebb34ed
PZ		 1117 INTEL_CPU_FAM6(ATOM_GOLDMONT_D, idle_cpu_dnv),
1118 INTEL_CPU_FAM6(ATOM_TREMONT_D, idle_cpu_dnv),
b66b8b9a
AK		 1119 {}
1120};
b66b8b9a 1121
18734958
RW		 1122#define INTEL_CPU_FAM6_MWAIT \
1123 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_MWAIT, 0 }
1124
1125static const struct x86_cpu_id intel_mwait_ids[] __initconst = {
1126 INTEL_CPU_FAM6_MWAIT,
1127 {}
1128};
1129
095928ae 1130static bool __init intel_idle_max_cstate_reached(int cstate)
18734958
RW		 1131{
1132 if (cstate + 1 > max_cstate) {
1133 pr_info("max_cstate %d reached\n", max_cstate);
1134 return true;
1135 }
1136 return false;
1137}
1138
1139#ifdef CONFIG_ACPI_PROCESSOR_CSTATE
1140#include <acpi/processor.h>
1141
4ec32d9e
RW		 1142static bool no_acpi __read_mostly;
1143module_param(no_acpi, bool, 0444);
1144MODULE_PARM_DESC(no_acpi, "Do not use ACPI _CST for building the idle states list");
1145
3a5be9b8
RW		 1146static bool force_use_acpi __read_mostly; /* No effect if no_acpi is set. */
1147module_param_named(use_acpi, force_use_acpi, bool, 0444);
1148MODULE_PARM_DESC(use_acpi, "Use ACPI _CST for building the idle states list");
1149
095928ae 1150static struct acpi_processor_power acpi_state_table __initdata;
18734958
RW		 1151
1152/**
1153 * intel_idle_cst_usable - Check if the _CST information can be used.
1154 *
1155 * Check if all of the C-states listed by _CST in the max_cstate range are
1156 * ACPI_CSTATE_FFH, which means that they should be entered via MWAIT.
1157 */
095928ae 1158static bool __init intel_idle_cst_usable(void)
18734958
RW		 1159{
1160 int cstate, limit;
1161
1162 limit = min_t(int, min_t(int, CPUIDLE_STATE_MAX, max_cstate + 1),
1163 acpi_state_table.count);
1164
1165 for (cstate = 1; cstate < limit; cstate++) {
1166 struct acpi_processor_cx *cx = &acpi_state_table.states[cstate];
1167
1168 if (cx->entry_method != ACPI_CSTATE_FFH)
1169 return false;
1170 }
1171
1172 return true;
1173}
1174
095928ae 1175static bool __init intel_idle_acpi_cst_extract(void)
18734958
RW		 1176{
1177 unsigned int cpu;
1178
4ec32d9e
RW		 1179 if (no_acpi) {
1180 pr_debug("Not allowed to use ACPI _CST\n");
1181 return false;
1182 }
1183
18734958
RW		 1184 for_each_possible_cpu(cpu) {
1185 struct acpi_processor *pr = per_cpu(processors, cpu);
1186
1187 if (!pr)
1188 continue;
1189
1190 if (acpi_processor_evaluate_cst(pr->handle, cpu, &acpi_state_table))
1191 continue;
1192
1193 acpi_state_table.count++;
1194
1195 if (!intel_idle_cst_usable())
1196 continue;
1197
1198 if (!acpi_processor_claim_cst_control()) {
1199 acpi_state_table.count = 0;
1200 return false;
1201 }
1202
1203 return true;
1204 }
1205
1206 pr_debug("ACPI _CST not found or not usable\n");
1207 return false;
1208}
1209
095928ae 1210static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
18734958
RW		 1211{
1212 int cstate, limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1213
1214 /*
1215 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1216 * the interesting states are ACPI_CSTATE_FFH.
1217 */
1218 for (cstate = 1; cstate < limit; cstate++) {
1219 struct acpi_processor_cx *cx;
1220 struct cpuidle_state *state;
1221
1222 if (intel_idle_max_cstate_reached(cstate))
1223 break;
1224
1225 cx = &acpi_state_table.states[cstate];
1226
1227 state = &drv->states[drv->state_count++];
1228
1229 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d_ACPI", cstate);
1230 strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1231 state->exit_latency = cx->latency;
1232 /*
1233 * For C1-type C-states use the same number for both the exit
1234 * latency and target residency, because that is the case for
1235 * C1 in the majority of the static C-states tables above.
1236 * For the other types of C-states, however, set the target
1237 * residency to 3 times the exit latency which should lead to
1238 * a reasonable balance between energy-efficiency and
1239 * performance in the majority of interesting cases.
1240 */
1241 state->target_residency = cx->latency;
1242 if (cx->type > ACPI_STATE_C1)
1243 state->target_residency *= 3;
1244
1245 state->flags = MWAIT2flg(cx->address);
1246 if (cx->type > ACPI_STATE_C2)
1247 state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
1248
4dcb78ee
RW		 1249 if (disabled_states_mask & BIT(cstate))
1250 state->flags |= CPUIDLE_FLAG_OFF;
1251
18734958
RW		 1252 state->enter = intel_idle;
1253 state->enter_s2idle = intel_idle_s2idle;
1254 }
1255}
bff8e60a 1256
095928ae 1257static bool __init intel_idle_off_by_default(u32 mwait_hint)
bff8e60a
RW		 1258{
1259 int cstate, limit;
1260
1261 /*
1262 * If there are no _CST C-states, do not disable any C-states by
1263 * default.
1264 */
1265 if (!acpi_state_table.count)
1266 return false;
1267
1268 limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1269 /*
1270 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1271 * the interesting states are ACPI_CSTATE_FFH.
1272 */
1273 for (cstate = 1; cstate < limit; cstate++) {
1274 if (acpi_state_table.states[cstate].address == mwait_hint)
1275 return false;
1276 }
1277 return true;
1278}
18734958 1279#else /* !CONFIG_ACPI_PROCESSOR_CSTATE */
3a5be9b8
RW		 1280#define force_use_acpi (false)
1281
18734958
RW		 1282static inline bool intel_idle_acpi_cst_extract(void) { return false; }
1283static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
bff8e60a 1284static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
18734958
RW		 1285#endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1286
6eacb15f
RW		 1287/**
1288 * ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
0138d8f0 1289 *
6eacb15f
RW		 1290 * Tune IVT multi-socket targets.
1291 * Assumption: num_sockets == (max_package_num + 1).
0138d8f0 1292 */
095928ae 1293static void __init ivt_idle_state_table_update(void)
0138d8f0
LB		 1294{
1295 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
d70e28f5
LB		 1296 int cpu, package_num, num_sockets = 1;
1297
1298 for_each_online_cpu(cpu) {
1299 package_num = topology_physical_package_id(cpu);
1300 if (package_num + 1 > num_sockets) {
1301 num_sockets = package_num + 1;
1302
1303 if (num_sockets > 4) {
1304 cpuidle_state_table = ivt_cstates_8s;
1305 return;
0138d8f0
LB		 1306 }
1307 }
d70e28f5
LB		 1308 }
1309
1310 if (num_sockets > 2)
1311 cpuidle_state_table = ivt_cstates_4s;
1312
1313 /* else, 1 and 2 socket systems use default ivt_cstates */
1314}
5dcef694 1315
86e9466a
RW		 1316/**
1317 * irtl_2_usec - IRTL to microseconds conversion.
1318 * @irtl: IRTL MSR value.
1319 *
1320 * Translate the IRTL (Interrupt Response Time Limit) MSR value to microseconds.
5dcef694 1321 */
095928ae 1322static unsigned long long __init irtl_2_usec(unsigned long long irtl)
5dcef694 1323{
86e9466a
RW		 1324 static const unsigned int irtl_ns_units[] __initconst = {
1325 1, 32, 1024, 32768, 1048576, 33554432, 0, 0
1326 };
5dcef694
LB		 1327 unsigned long long ns;
1328
3451ab3e
JB		 1329 if (!irtl)
1330 return 0;
1331
bef45096 1332 ns = irtl_ns_units[(irtl >> 10) & 0x7];
5dcef694 1333
86e9466a 1334 return div_u64((irtl & 0x3FF) * ns, NSEC_PER_USEC);
5dcef694 1335}
86e9466a 1336
6eacb15f
RW		 1337/**
1338 * bxt_idle_state_table_update - Fix up the Broxton idle states table.
5dcef694 1339 *
6eacb15f
RW		 1340 * On BXT, trust the IRTL (Interrupt Response Time Limit) MSR to show the
1341 * definitive maximum latency and use the same value for target_residency.
5dcef694 1342 */
095928ae 1343static void __init bxt_idle_state_table_update(void)
5dcef694
LB		 1344{
1345 unsigned long long msr;
3451ab3e 1346 unsigned int usec;
5dcef694
LB		 1347
1348 rdmsrl(MSR_PKGC6_IRTL, msr);
3451ab3e
JB		 1349 usec = irtl_2_usec(msr);
1350 if (usec) {
5dcef694
LB		 1351 bxt_cstates[2].exit_latency = usec;
1352 bxt_cstates[2].target_residency = usec;
1353 }
1354
1355 rdmsrl(MSR_PKGC7_IRTL, msr);
3451ab3e
JB		 1356 usec = irtl_2_usec(msr);
1357 if (usec) {
5dcef694
LB		 1358 bxt_cstates[3].exit_latency = usec;
1359 bxt_cstates[3].target_residency = usec;
1360 }
1361
1362 rdmsrl(MSR_PKGC8_IRTL, msr);
3451ab3e
JB		 1363 usec = irtl_2_usec(msr);
1364 if (usec) {
5dcef694
LB		 1365 bxt_cstates[4].exit_latency = usec;
1366 bxt_cstates[4].target_residency = usec;
1367 }
1368
1369 rdmsrl(MSR_PKGC9_IRTL, msr);
3451ab3e
JB		 1370 usec = irtl_2_usec(msr);
1371 if (usec) {
5dcef694
LB		 1372 bxt_cstates[5].exit_latency = usec;
1373 bxt_cstates[5].target_residency = usec;
1374 }
1375
1376 rdmsrl(MSR_PKGC10_IRTL, msr);
3451ab3e
JB		 1377 usec = irtl_2_usec(msr);
1378 if (usec) {
5dcef694
LB		 1379 bxt_cstates[6].exit_latency = usec;
1380 bxt_cstates[6].target_residency = usec;
1381 }
1382
1383}
6eacb15f
RW		 1384
1385/**
1386 * sklh_idle_state_table_update - Fix up the Sky Lake idle states table.
d70e28f5 1387 *
6eacb15f 1388 * On SKL-H (model 0x5e) skip C8 and C9 if C10 is enabled and SGX disabled.
d70e28f5 1389 */
095928ae 1390static void __init sklh_idle_state_table_update(void)
d70e28f5
LB		 1391{
1392 unsigned long long msr;
1393 unsigned int eax, ebx, ecx, edx;
1394
1395
1396 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1397 if (max_cstate <= 7)
1398 return;
1399
1400 /* if PC10 not present in CPUID.MWAIT.EDX */
1401 if ((mwait_substates & (0xF << 28)) == 0)
1402 return;
1403
6cfb2374 1404 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
d70e28f5
LB		 1405
1406 /* PC10 is not enabled in PKG C-state limit */
1407 if ((msr & 0xF) != 8)
1408 return;
1409
1410 ecx = 0;
1411 cpuid(7, &eax, &ebx, &ecx, &edx);
1412
1413 /* if SGX is present */
1414 if (ebx & (1 << 2)) {
0138d8f0 1415
32ad73db 1416 rdmsrl(MSR_IA32_FEAT_CTL, msr);
d70e28f5
LB		 1417
1418 /* if SGX is enabled */
1419 if (msr & (1 << 18))
1420 return;
1421 }
1422
ba1e78a1
RW		 1423 skl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE; /* C8-SKL */
1424 skl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE; /* C9-SKL */
d70e28f5 1425}
d70e28f5 1426
1aefbd7a
RW		 1427static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
1428{
1429 unsigned int mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint) + 1;
1430 unsigned int num_substates = (mwait_substates >> mwait_cstate * 4) &
1431 MWAIT_SUBSTATE_MASK;
1432
1433 /* Ignore the C-state if there are NO sub-states in CPUID for it. */
1434 if (num_substates == 0)
1435 return false;
1436
1437 if (mwait_cstate > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1438 mark_tsc_unstable("TSC halts in idle states deeper than C2");
1439
1440 return true;
1441}
1442
095928ae 1443static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
d70e28f5 1444{
3d3a1ae9 1445 int cstate;
d70e28f5 1446
3d3a1ae9 1447 switch (boot_cpu_data.x86_model) {
db73c5a8 1448 case INTEL_FAM6_IVYBRIDGE_X:
d70e28f5
LB		 1449 ivt_idle_state_table_update();
1450 break;
db73c5a8 1451 case INTEL_FAM6_ATOM_GOLDMONT:
f2c4db1b 1452 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5dcef694
LB		 1453 bxt_idle_state_table_update();
1454 break;
c66f78a6 1455 case INTEL_FAM6_SKYLAKE:
d70e28f5
LB		 1456 sklh_idle_state_table_update();
1457 break;
0138d8f0 1458 }
46bcfad7 1459
e022e7eb 1460 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
9f3d6daf 1461 unsigned int mwait_hint;
46bcfad7 1462
18734958 1463 if (intel_idle_max_cstate_reached(cstate))
e022e7eb
LB		 1464 break;
1465
18734958
RW		 1466 if (!cpuidle_state_table[cstate].enter &&
1467 !cpuidle_state_table[cstate].enter_s2idle)
46bcfad7 1468 break;
46bcfad7 1469
9f3d6daf 1470 /* If marked as unusable, skip this state. */
ba1e78a1 1471 if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) {
654d08a4
JP		 1472 pr_debug("state %s is disabled\n",
1473 cpuidle_state_table[cstate].name);
d70e28f5
LB		 1474 continue;
1475 }
1476
9f3d6daf
RW		 1477 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1478 if (!intel_idle_verify_cstate(mwait_hint))
1479 continue;
d70e28f5 1480
9f3d6daf 1481 /* Structure copy. */
bff8e60a
RW		 1482 drv->states[drv->state_count] = cpuidle_state_table[cstate];
1483
4dcb78ee
RW		 1484 if ((disabled_states_mask & BIT(drv->state_count)) ||
1485 ((icpu->use_acpi || force_use_acpi) &&
1486 intel_idle_off_by_default(mwait_hint) &&
1487 !(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
bff8e60a
RW		 1488 drv->states[drv->state_count].flags |= CPUIDLE_FLAG_OFF;
1489
1490 drv->state_count++;
46bcfad7
DD		 1491 }
1492
8c058d53
LB		 1493 if (icpu->byt_auto_demotion_disable_flag) {
1494 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1495 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1496 }
46bcfad7
DD		 1497}
1498
6eacb15f
RW		 1499/**
1500 * intel_idle_cpuidle_driver_init - Create the list of available idle states.
1501 * @drv: cpuidle driver structure to initialize.
18734958 1502 */
3d3a1ae9 1503static void __init intel_idle_cpuidle_driver_init(struct cpuidle_driver *drv)
18734958 1504{
18734958 1505 cpuidle_poll_state_init(drv);
4dcb78ee
RW		 1506
1507 if (disabled_states_mask & BIT(0))
1508 drv->states[0].flags |= CPUIDLE_FLAG_OFF;
1509
18734958
RW		 1510 drv->state_count = 1;
1511
1512 if (icpu)
1513 intel_idle_init_cstates_icpu(drv);
1514 else
1515 intel_idle_init_cstates_acpi(drv);
1516}
46bcfad7 1517
1aefbd7a
RW		 1518static void auto_demotion_disable(void)
1519{
1520 unsigned long long msr_bits;
1521
1522 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
7f843dd7 1523 msr_bits &= ~auto_demotion_disable_flags;
1aefbd7a
RW		 1524 wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1525}
1526
1527static void c1e_promotion_disable(void)
1528{
1529 unsigned long long msr_bits;
1530
1531 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
1532 msr_bits &= ~0x2;
1533 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
1534}
1535
6eacb15f
RW		 1536/**
1537 * intel_idle_cpu_init - Register the target CPU with the cpuidle core.
1538 * @cpu: CPU to initialize.
1539 *
1540 * Register a cpuidle device object for @cpu and update its MSRs in accordance
1541 * with the processor model flags.
26717172 1542 */
fb1013a0 1543static int intel_idle_cpu_init(unsigned int cpu)
26717172 1544{
26717172
LB		 1545 struct cpuidle_device *dev;
1546
65b7f839 1547 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
65b7f839 1548 dev->cpu = cpu;
26717172 1549
65b7f839 1550 if (cpuidle_register_device(dev)) {
654d08a4 1551 pr_debug("cpuidle_register_device %d failed!\n", cpu);
65b7f839 1552 return -EIO;
26717172
LB		 1553 }
1554
7f843dd7 1555 if (auto_demotion_disable_flags)
fb1013a0 1556 auto_demotion_disable();
65b7f839 1557
7f843dd7 1558 if (disable_promotion_to_c1e)
fb1013a0
SAS		 1559 c1e_promotion_disable();
1560
1561 return 0;
1562}
1563
1564static int intel_idle_cpu_online(unsigned int cpu)
1565{
1566 struct cpuidle_device *dev;
1567
40ab82e0 1568 if (!lapic_timer_always_reliable)
cbd2c4c2 1569 tick_broadcast_enable();
fb1013a0
SAS		 1570
1571 /*
1572 * Some systems can hotplug a cpu at runtime after
1573 * the kernel has booted, we have to initialize the
1574 * driver in this case
1575 */
1576 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1577 if (!dev->registered)
1578 return intel_idle_cpu_init(cpu);
dbf87ab8 1579
26717172
LB		 1580 return 0;
1581}
26717172 1582
0755a9bd
RW		 1583/**
1584 * intel_idle_cpuidle_devices_uninit - Unregister all cpuidle devices.
1585 */
1586static void __init intel_idle_cpuidle_devices_uninit(void)
1587{
1588 int i;
1589
1590 for_each_online_cpu(i)
1591 cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
1592}
1593
26717172
LB		 1594static int __init intel_idle_init(void)
1595{
a6c86e33
RW		 1596 const struct x86_cpu_id *id;
1597 unsigned int eax, ebx, ecx;
fb1013a0 1598 int retval;
26717172 1599
d1896049
TR		 1600 /* Do not load intel_idle at all for now if idle= is passed */
1601 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1602 return -ENODEV;
1603
a6c86e33
RW		 1604 if (max_cstate == 0) {
1605 pr_debug("disabled\n");
1606 return -EPERM;
1607 }
1608
1609 id = x86_match_cpu(intel_idle_ids);
1610 if (id) {
1611 if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
1612 pr_debug("Please enable MWAIT in BIOS SETUP\n");
1613 return -ENODEV;
1614 }
1615 } else {
1616 id = x86_match_cpu(intel_mwait_ids);
1617 if (!id)
1618 return -ENODEV;
1619 }
1620
1621 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1622 return -ENODEV;
1623
1624 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1625
1626 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1627 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1628 !mwait_substates)
1629 return -ENODEV;
1630
1631 pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
1632
1633 icpu = (const struct idle_cpu *)id->driver_data;
1634 if (icpu) {
1635 cpuidle_state_table = icpu->state_table;
7f843dd7
RW		 1636 auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
1637 disable_promotion_to_c1e = icpu->disable_promotion_to_c1e;
3a5be9b8 1638 if (icpu->use_acpi || force_use_acpi)
a6c86e33
RW		 1639 intel_idle_acpi_cst_extract();
1640 } else if (!intel_idle_acpi_cst_extract()) {
1641 return -ENODEV;
1642 }
1643
1644 pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
1645 boot_cpu_data.x86_model);
26717172 1646
e9df69cc 1647 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
533da74a 1648 if (!intel_idle_cpuidle_devices)
e9df69cc
RC		 1649 return -ENOMEM;
1650
3d3a1ae9
RW		 1651 intel_idle_cpuidle_driver_init(&intel_idle_driver);
1652
26717172
LB		 1653 retval = cpuidle_register_driver(&intel_idle_driver);
1654 if (retval) {
3735d524 1655 struct cpuidle_driver *drv = cpuidle_get_driver();
654d08a4
JP		 1656 printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
1657 drv ? drv->name : "none");
fb1013a0 1658 goto init_driver_fail;
26717172
LB		 1659 }
1660
2259a819 1661 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
40ab82e0 1662 lapic_timer_always_reliable = true;
2259a819 1663
fb1013a0
SAS		 1664 retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
1665 intel_idle_cpu_online, NULL);
1666 if (retval < 0)
1667 goto hp_setup_fail;
26717172 1668
40ab82e0
RW		 1669 pr_debug("Local APIC timer is reliable in %s\n",
1670 lapic_timer_always_reliable ? "all C-states" : "C1");
2259a819 1671
26717172 1672 return 0;
fb1013a0
SAS		 1673
1674hp_setup_fail:
1675 intel_idle_cpuidle_devices_uninit();
1676 cpuidle_unregister_driver(&intel_idle_driver);
1677init_driver_fail:
1678 free_percpu(intel_idle_cpuidle_devices);
1679 return retval;
1680
26717172 1681}
02c4fae9 1682device_initcall(intel_idle_init);
26717172 1683
02c4fae9
PG		 1684/*
1685 * We are not really modular, but we used to support that. Meaning we also
1686 * support "intel_idle.max_cstate=..." at boot and also a read-only export of
1687 * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
1688 * is the easiest way (currently) to continue doing that.
1689 */
26717172 1690module_param(max_cstate, int, 0444);
4dcb78ee
RW		 1691/*
1692 * The positions of the bits that are set in this number are the indices of the
1693 * idle states to be disabled by default (as reflected by the names of the
1694 * corresponding idle state directories in sysfs, "state0", "state1" ...
1695 * "state<i>" ..., where <i> is the index of the given state).
1696 */
1697module_param_named(states_off, disabled_states_mask, uint, 0444);
1698MODULE_PARM_DESC(states_off, "Mask of disabled idle states");
Linux 6.x block layer and io_uring tree(s)