[linux-block.git] / drivers / ide / tx4939ide.c

/*
 * TX4939 internal IDE driver
 * Based on RBTX49xx patch from CELF patch archive.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * (C) Copyright TOSHIBA CORPORATION 2005-2007
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/ide.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/scatterlist.h>

#include <asm/ide.h>

#define MODNAME	"tx4939ide"

/* ATA Shadow Registers (8-bit except for Data which is 16-bit) */
#define TX4939IDE_Data			0x000
#define TX4939IDE_Error_Feature		0x001
#define TX4939IDE_Sec			0x002
#define TX4939IDE_LBA0			0x003
#define TX4939IDE_LBA1			0x004
#define TX4939IDE_LBA2			0x005
#define TX4939IDE_DevHead		0x006
#define TX4939IDE_Stat_Cmd		0x007
#define TX4939IDE_AltStat_DevCtl	0x402
/* H/W DMA Registers  */
#define TX4939IDE_DMA_Cmd	0x800	/* 8-bit */
#define TX4939IDE_DMA_Stat	0x802	/* 8-bit */
#define TX4939IDE_PRD_Ptr	0x804	/* 32-bit */
/* ATA100 CORE Registers (16-bit) */
#define TX4939IDE_Sys_Ctl	0xc00
#define TX4939IDE_Xfer_Cnt_1	0xc08
#define TX4939IDE_Xfer_Cnt_2	0xc0a
#define TX4939IDE_Sec_Cnt	0xc10
#define TX4939IDE_Start_Lo_Addr	0xc18
#define TX4939IDE_Start_Up_Addr	0xc20
#define TX4939IDE_Add_Ctl	0xc28
#define TX4939IDE_Lo_Burst_Cnt	0xc30
#define TX4939IDE_Up_Burst_Cnt	0xc38
#define TX4939IDE_PIO_Addr	0xc88
#define TX4939IDE_H_Rst_Tim	0xc90
#define TX4939IDE_Int_Ctl	0xc98
#define TX4939IDE_Pkt_Cmd	0xcb8
#define TX4939IDE_Bxfer_Cnt_Hi	0xcc0
#define TX4939IDE_Bxfer_Cnt_Lo	0xcc8
#define TX4939IDE_Dev_TErr	0xcd0
#define TX4939IDE_Pkt_Xfer_Ctl	0xcd8
#define TX4939IDE_Start_TAddr	0xce0

/* bits for Int_Ctl */
#define TX4939IDE_INT_ADDRERR	0x80
#define TX4939IDE_INT_REACHMUL	0x40
#define TX4939IDE_INT_DEVTIMING	0x20
#define TX4939IDE_INT_UDMATERM	0x10
#define TX4939IDE_INT_TIMER	0x08
#define TX4939IDE_INT_BUSERR	0x04
#define TX4939IDE_INT_XFEREND	0x02
#define TX4939IDE_INT_HOST	0x01

#define TX4939IDE_IGNORE_INTS	\
	(TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \
	 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \
	 TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND)

#ifdef __BIG_ENDIAN
#define tx4939ide_swizzlel(a)	((a) ^ 4)
#define tx4939ide_swizzlew(a)	((a) ^ 6)
#define tx4939ide_swizzleb(a)	((a) ^ 7)
#else
#define tx4939ide_swizzlel(a)	(a)
#define tx4939ide_swizzlew(a)	(a)
#define tx4939ide_swizzleb(a)	(a)
#endif

static u16 tx4939ide_readw(void __iomem *base, u32 reg)
{
	return __raw_readw(base + tx4939ide_swizzlew(reg));
}
static u8 tx4939ide_readb(void __iomem *base, u32 reg)
{
	return __raw_readb(base + tx4939ide_swizzleb(reg));
}
static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg)
{
	__raw_writel(val, base + tx4939ide_swizzlel(reg));
}
static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg)
{
	__raw_writew(val, base + tx4939ide_swizzlew(reg));
}
static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
{
	__raw_writeb(val, base + tx4939ide_swizzleb(reg));
}

#define TX4939IDE_BASE(hwif)	((void __iomem *)(hwif)->extra_base)

static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	int is_slave = drive->dn;
	u32 mask, val;
	const u8 pio = drive->pio_mode - XFER_PIO_0;
	u8 safe = pio;
	ide_drive_t *pair;

	pair = ide_get_pair_dev(drive);
	if (pair)
		safe = min_t(u8, safe, pair->pio_mode - XFER_PIO_0);
	/*
	 * Update Command Transfer Mode for master/slave and Data
	 * Transfer Mode for this drive.
	 */
	mask = is_slave ? 0x07f00000 : 0x000007f0;
	val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0);
	hwif->select_data = (hwif->select_data & ~mask) | val;
	/* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
}

static void tx4939ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	u32 mask, val;
	const u8 mode = drive->dma_mode;

	/* Update Data Transfer Mode for this drive. */
	if (mode >= XFER_UDMA_0)
		val = mode - XFER_UDMA_0 + 8;
	else
		val = mode - XFER_MW_DMA_0 + 5;
	if (drive->dn) {
		mask = 0x00f00000;
		val <<= 20;
	} else {
		mask = 0x000000f0;
		val <<= 4;
	}
	hwif->select_data = (hwif->select_data & ~mask) | val;
	/* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
}

static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif)
{
	void __iomem *base = TX4939IDE_BASE(hwif);
	u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);

	if (ctl & TX4939IDE_INT_BUSERR) {
		/* reset FIFO */
		u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl);

		tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl);
		/* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */
		ndelay(270);
		tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
	}
	if (ctl & (TX4939IDE_INT_ADDRERR |
		   TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
		pr_err("%s: Error interrupt %#x (%s%s%s )\n",
		       hwif->name, ctl,
		       ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "",
		       ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "",
		       ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : "");
	return ctl;
}

static void tx4939ide_clear_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif;
	void __iomem *base;
	u16 ctl;

	/*
	 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job
	 * for DMA case.
	 */
	if (drive->waiting_for_dma)
		return;
	hwif = drive->hwif;
	base = TX4939IDE_BASE(hwif);
	ctl = tx4939ide_check_error_ints(hwif);
	tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
}

static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
{
	void __iomem *base = TX4939IDE_BASE(hwif);

	return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ?
		ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

#ifdef __BIG_ENDIAN
static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 unit = drive->dn;
	void __iomem *base = TX4939IDE_BASE(hwif);
	u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);

	if (on)
		dma_stat |= (1 << (5 + unit));
	else
		dma_stat &= ~(1 << (5 + unit));

	tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat);
}
#else
#define tx4939ide_dma_host_set	ide_dma_host_set
#endif

static u8 tx4939ide_clear_dma_status(void __iomem *base)
{
	u8 dma_stat;

	/* read DMA status for INTR & ERROR flags */
	dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
	/* clear INTR & ERROR flags */
	tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base,
			 TX4939IDE_DMA_Stat);
	/* recover intmask cleared by writing to bit2 of DMA_Stat */
	tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl);
	return dma_stat;
}

#ifdef __BIG_ENDIAN
/* custom ide_build_dmatable to handle swapped layout */
static int tx4939ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
{
	ide_hwif_t *hwif = drive->hwif;
	u32 *table = (u32 *)hwif->dmatable_cpu;
	unsigned int count = 0;
	int i;
	struct scatterlist *sg;

	for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) {
		u32 cur_addr, cur_len, bcount;

		cur_addr = sg_dma_address(sg);
		cur_len = sg_dma_len(sg);

		/*
		 * Fill in the DMA table, without crossing any 64kB boundaries.
		 */

		while (cur_len) {
			if (count++ >= PRD_ENTRIES)
				goto use_pio_instead;

			bcount = 0x10000 - (cur_addr & 0xffff);
			if (bcount > cur_len)
				bcount = cur_len;
			/*
			 * This workaround for zero count seems required.
			 * (standard ide_build_dmatable does it too)
			 */
			if (bcount == 0x10000)
				bcount = 0x8000;
			*table++ = bcount & 0xffff;
			*table++ = cur_addr;
			cur_addr += bcount;
			cur_len -= bcount;
		}
	}

	if (count) {
		*(table - 2) |= 0x80000000;
		return count;
	}

use_pio_instead:
	printk(KERN_ERR "%s: %s\n", drive->name,
		count ? "DMA table too small" : "empty DMA table?");

	return 0; /* revert to PIO for this request */
}
#else
#define tx4939ide_build_dmatable	ide_build_dmatable
#endif

static int tx4939ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
{
	ide_hwif_t *hwif = drive->hwif;
	void __iomem *base = TX4939IDE_BASE(hwif);
	u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;

	/* fall back to PIO! */
	if (tx4939ide_build_dmatable(drive, cmd) == 0)
		return 1;

	/* PRD table */
	tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr);

	/* specify r/w */
	tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd);

	/* clear INTR & ERROR flags */
	tx4939ide_clear_dma_status(base);

	tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ?
			 TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1);

	tx4939ide_writew(blk_rq_sectors(cmd->rq), base, TX4939IDE_Sec_Cnt);

	return 0;
}

static int tx4939ide_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat, dma_cmd;
	void __iomem *base = TX4939IDE_BASE(hwif);
	u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);

	/* get DMA command mode */
	dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd);
	/* stop DMA */
	tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd);

	/* read and clear the INTR & ERROR bits */
	dma_stat = tx4939ide_clear_dma_status(base);

#define CHECK_DMA_MASK (ATA_DMA_ACTIVE | ATA_DMA_ERR | ATA_DMA_INTR)

	/* verify good DMA status */
	if ((dma_stat & CHECK_DMA_MASK) == 0 &&
	    (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
	    (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
		/* INT_IDE lost... bug? */
		return 0;
	return ((dma_stat & CHECK_DMA_MASK) !=
		ATA_DMA_INTR) ? 0x10 | dma_stat : 0;
}

/* returns 1 if DMA IRQ issued, 0 otherwise */
static int tx4939ide_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	void __iomem *base = TX4939IDE_BASE(hwif);
	u16 ctl, ide_int;
	u8 dma_stat, stat;
	int found = 0;

	ctl = tx4939ide_check_error_ints(hwif);
	ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
	switch (ide_int) {
	case TX4939IDE_INT_HOST:
		/* On error, XFEREND might not be asserted. */
		stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl);
		if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR)
			found = 1;
		else
			/* Wait for XFEREND (Mask HOST and unmask XFEREND) */
			ctl &= ~TX4939IDE_INT_XFEREND << 8;
		ctl |= ide_int << 8;
		break;
	case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
		dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
		if (!(dma_stat & ATA_DMA_INTR))
			pr_warn("%s: weird interrupt status. "
				"DMA_Stat %#02x int_ctl %#04x\n",
				hwif->name, dma_stat, ctl);
		found = 1;
		break;
	}
	/*
	 * Do not clear XFEREND, HOST now.  They will be cleared by
	 * clearing bit2 of DMA_Stat.
	 */
	ctl &= ~ide_int;
	tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
	return found;
}

#ifdef __BIG_ENDIAN
static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif)
{
	void __iomem *base = TX4939IDE_BASE(hwif);

	return tx4939ide_readb(base, TX4939IDE_DMA_Stat);
}
#else
#define tx4939ide_dma_sff_read_status ide_dma_sff_read_status
#endif

static void tx4939ide_init_hwif(ide_hwif_t *hwif)
{
	void __iomem *base = TX4939IDE_BASE(hwif);

	/* Soft Reset */
	tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);
	/* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */
	ndelay(450);
	tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);
	/* mask some interrupts and clear all interrupts */
	tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base,
			 TX4939IDE_Int_Ctl);

	tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt);
	tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt);
}

static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
{
	hwif->dma_base =
		hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd);
	/*
	 * Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS
	 * for big endian.
	 */
	return ide_allocate_dma_engine(hwif);
}

static void tx4939ide_tf_load_fixup(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	void __iomem *base = TX4939IDE_BASE(hwif);
	u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0);

	/*
	 * Fix ATA100 CORE System Control Register. (The write to the
	 * Device/Head register may write wrong data to the System
	 * Control Register)
	 * While Sys_Ctl is written here, dev_select() is not needed.
	 */
	tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
}

static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_taskfile *tf,
			      u8 valid)
{
	ide_tf_load(drive, tf, valid);

	if (valid & IDE_VALID_DEVICE)
		tx4939ide_tf_load_fixup(drive);
}

#ifdef __BIG_ENDIAN

/* custom iops (independent from SWAP_IO_SPACE) */
static void tx4939ide_input_data_swap(ide_drive_t *drive, struct ide_cmd *cmd,
				void *buf, unsigned int len)
{
	unsigned long port = drive->hwif->io_ports.data_addr;
	unsigned short *ptr = buf;
	unsigned int count = (len + 1) / 2;

	while (count--)
		*ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port));
	__ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
}

static void tx4939ide_output_data_swap(ide_drive_t *drive, struct ide_cmd *cmd,
				void *buf, unsigned int len)
{
	unsigned long port = drive->hwif->io_ports.data_addr;
	unsigned short *ptr = buf;
	unsigned int count = (len + 1) / 2;

	while (count--) {
		__raw_writew(le16_to_cpu(*ptr), (void __iomem *)port);
		ptr++;
	}
	__ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
}

static const struct ide_tp_ops tx4939ide_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= ide_read_status,
	.read_altstatus		= ide_read_altstatus,
	.write_devctl		= ide_write_devctl,

	.dev_select		= ide_dev_select,
	.tf_load		= tx4939ide_tf_load,
	.tf_read		= ide_tf_read,

	.input_data		= tx4939ide_input_data_swap,
	.output_data		= tx4939ide_output_data_swap,
};

#else	/* __LITTLE_ENDIAN */

static const struct ide_tp_ops tx4939ide_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= ide_read_status,
	.read_altstatus		= ide_read_altstatus,
	.write_devctl		= ide_write_devctl,

	.dev_select		= ide_dev_select,
	.tf_load		= tx4939ide_tf_load,
	.tf_read		= ide_tf_read,

	.input_data		= ide_input_data,
	.output_data		= ide_output_data,
};

#endif	/* __LITTLE_ENDIAN */

static const struct ide_port_ops tx4939ide_port_ops = {
	.set_pio_mode		= tx4939ide_set_pio_mode,
	.set_dma_mode		= tx4939ide_set_dma_mode,
	.clear_irq		= tx4939ide_clear_irq,
	.cable_detect		= tx4939ide_cable_detect,
};

static const struct ide_dma_ops tx4939ide_dma_ops = {
	.dma_host_set		= tx4939ide_dma_host_set,
	.dma_setup		= tx4939ide_dma_setup,
	.dma_start		= ide_dma_start,
	.dma_end		= tx4939ide_dma_end,
	.dma_test_irq		= tx4939ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= tx4939ide_dma_sff_read_status,
};

static const struct ide_port_info tx4939ide_port_info __initconst = {
	.init_hwif		= tx4939ide_init_hwif,
	.init_dma		= tx4939ide_init_dma,
	.port_ops		= &tx4939ide_port_ops,
	.dma_ops		= &tx4939ide_dma_ops,
	.tp_ops			= &tx4939ide_tp_ops,
	.host_flags		= IDE_HFLAG_MMIO,
	.pio_mask		= ATA_PIO4,
	.mwdma_mask		= ATA_MWDMA2,
	.udma_mask		= ATA_UDMA5,
	.chipset		= ide_generic,
};

static int __init tx4939ide_probe(struct platform_device *pdev)
{
	struct ide_hw hw, *hws[] = { &hw };
	struct ide_host *host;
	struct resource *res;
	int irq, ret;
	unsigned long mapbase;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return -ENODEV;
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	if (!devm_request_mem_region(&pdev->dev, res->start,
				     resource_size(res), MODNAME))
		return -EBUSY;
	mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
					      resource_size(res));
	if (!mapbase)
		return -EBUSY;
	memset(&hw, 0, sizeof(hw));
	hw.io_ports.data_addr =
		mapbase + tx4939ide_swizzlew(TX4939IDE_Data);
	hw.io_ports.error_addr =
		mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature);
	hw.io_ports.nsect_addr =
		mapbase + tx4939ide_swizzleb(TX4939IDE_Sec);
	hw.io_ports.lbal_addr =
		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0);
	hw.io_ports.lbam_addr =
		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1);
	hw.io_ports.lbah_addr =
		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2);
	hw.io_ports.device_addr =
		mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead);
	hw.io_ports.command_addr =
		mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd);
	hw.io_ports.ctl_addr =
		mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl);
	hw.irq = irq;
	hw.dev = &pdev->dev;

	pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq);
	host = ide_host_alloc(&tx4939ide_port_info, hws, 1);
	if (!host)
		return -ENOMEM;
	/* use extra_base for base address of the all registers */
	host->ports[0]->extra_base = mapbase;
	ret = ide_host_register(host, &tx4939ide_port_info, hws);
	if (ret) {
		ide_host_free(host);
		return ret;
	}
	platform_set_drvdata(pdev, host);
	return 0;
}

static int __exit tx4939ide_remove(struct platform_device *pdev)
{
	struct ide_host *host = platform_get_drvdata(pdev);

	ide_host_remove(host);
	return 0;
}

#ifdef CONFIG_PM
static int tx4939ide_resume(struct platform_device *dev)
{
	struct ide_host *host = platform_get_drvdata(dev);
	ide_hwif_t *hwif = host->ports[0];

	tx4939ide_init_hwif(hwif);
	return 0;
}
#else
#define tx4939ide_resume	NULL
#endif

static struct platform_driver tx4939ide_driver = {
	.driver = {
		.name = MODNAME,
	},
	.remove = __exit_p(tx4939ide_remove),
	.resume = tx4939ide_resume,
};

module_platform_driver_probe(tx4939ide_driver, tx4939ide_probe);

MODULE_DESCRIPTION("TX4939 internal IDE driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:tx4939ide");
Commit	Line	Data
37897989 AN	1	/*
	2	* TX4939 internal IDE driver
	3	* Based on RBTX49xx patch from CELF patch archive.
	4	*
	5	* This file is subject to the terms and conditions of the GNU General Public
	6	* License. See the file "COPYING" in the main directory of this archive
	7	* for more details.
	8	*
	9	* (C) Copyright TOSHIBA CORPORATION 2005-2007
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/types.h>
	14	#include <linux/ide.h>
	15	#include <linux/init.h>
	16	#include <linux/delay.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/io.h>
	19	#include <linux/scatterlist.h>
	20
15a453a9 BZ	21	#include <asm/ide.h>
15a453a9 BZ	22
37897989 AN	23	#define MODNAME "tx4939ide"
	24
	25	/* ATA Shadow Registers (8-bit except for Data which is 16-bit) */
	26	#define TX4939IDE_Data 0x000
	27	#define TX4939IDE_Error_Feature 0x001
	28	#define TX4939IDE_Sec 0x002
	29	#define TX4939IDE_LBA0 0x003
	30	#define TX4939IDE_LBA1 0x004
	31	#define TX4939IDE_LBA2 0x005
	32	#define TX4939IDE_DevHead 0x006
	33	#define TX4939IDE_Stat_Cmd 0x007
	34	#define TX4939IDE_AltStat_DevCtl 0x402
	35	/* H/W DMA Registers */
	36	#define TX4939IDE_DMA_Cmd 0x800 /* 8-bit */
	37	#define TX4939IDE_DMA_Stat 0x802 /* 8-bit */
	38	#define TX4939IDE_PRD_Ptr 0x804 /* 32-bit */
	39	/* ATA100 CORE Registers (16-bit) */
	40	#define TX4939IDE_Sys_Ctl 0xc00
	41	#define TX4939IDE_Xfer_Cnt_1 0xc08
	42	#define TX4939IDE_Xfer_Cnt_2 0xc0a
	43	#define TX4939IDE_Sec_Cnt 0xc10
	44	#define TX4939IDE_Start_Lo_Addr 0xc18
	45	#define TX4939IDE_Start_Up_Addr 0xc20
	46	#define TX4939IDE_Add_Ctl 0xc28
	47	#define TX4939IDE_Lo_Burst_Cnt 0xc30
	48	#define TX4939IDE_Up_Burst_Cnt 0xc38
	49	#define TX4939IDE_PIO_Addr 0xc88
	50	#define TX4939IDE_H_Rst_Tim 0xc90
	51	#define TX4939IDE_Int_Ctl 0xc98
	52	#define TX4939IDE_Pkt_Cmd 0xcb8
	53	#define TX4939IDE_Bxfer_Cnt_Hi 0xcc0
	54	#define TX4939IDE_Bxfer_Cnt_Lo 0xcc8
	55	#define TX4939IDE_Dev_TErr 0xcd0
	56	#define TX4939IDE_Pkt_Xfer_Ctl 0xcd8
	57	#define TX4939IDE_Start_TAddr 0xce0
	58
	59	/* bits for Int_Ctl */
	60	#define TX4939IDE_INT_ADDRERR 0x80
	61	#define TX4939IDE_INT_REACHMUL 0x40
	62	#define TX4939IDE_INT_DEVTIMING 0x20
	63	#define TX4939IDE_INT_UDMATERM 0x10
	64	#define TX4939IDE_INT_TIMER 0x08
	65	#define TX4939IDE_INT_BUSERR 0x04
	66	#define TX4939IDE_INT_XFEREND 0x02
	67	#define TX4939IDE_INT_HOST 0x01
	68
	69	#define TX4939IDE_IGNORE_INTS \
	70	(TX4939IDE_INT_ADDRERR \| TX4939IDE_INT_REACHMUL \| \
	71	TX4939IDE_INT_DEVTIMING \| TX4939IDE_INT_UDMATERM \| \
	72	TX4939IDE_INT_TIMER \| TX4939IDE_INT_XFEREND)
	73
	74	#ifdef __BIG_ENDIAN
	75	#define tx4939ide_swizzlel(a) ((a) ^ 4)
	76	#define tx4939ide_swizzlew(a) ((a) ^ 6)
	77	#define tx4939ide_swizzleb(a) ((a) ^ 7)
	78	#else
	79	#define tx4939ide_swizzlel(a) (a)
	80	#define tx4939ide_swizzlew(a) (a)
	81	#define tx4939ide_swizzleb(a) (a)
	82	#endif
	83
	84	static u16 tx4939ide_readw(void __iomem *base, u32 reg)
	85	{
	86	return __raw_readw(base + tx4939ide_swizzlew(reg));
87	}
88	static u8 tx4939ide_readb(void __iomem *base, u32 reg)
89	{
90	return __raw_readb(base + tx4939ide_swizzleb(reg));
91	}
92	static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg)
93	{
94	__raw_writel(val, base + tx4939ide_swizzlel(reg));
95	}
96	static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg)
97	{
98	__raw_writew(val, base + tx4939ide_swizzlew(reg));
99	}
100	static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
101	{
102	__raw_writeb(val, base + tx4939ide_swizzleb(reg));
103	}
104
105	#define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base)
106
e085b3ca	107	static void tx4939ide_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
37897989	108	{
37897989 AN	109	int is_slave = drive->dn;
37897989 AN	110	u32 mask, val;
e085b3ca	111	const u8 pio = drive->pio_mode - XFER_PIO_0;
37897989 AN	112	u8 safe = pio;
	113	ide_drive_t *pair;
	114
	115	pair = ide_get_pair_dev(drive);
	116	if (pair)
cd078af6	117	safe = min_t(u8, safe, pair->pio_mode - XFER_PIO_0);
37897989 AN	118	/*
	119	* Update Command Transfer Mode for master/slave and Data
	120	* Transfer Mode for this drive.
	121	*/
	122	mask = is_slave ? 0x07f00000 : 0x000007f0;
	123	val = ((safe << 8) \| (pio << 4)) << (is_slave ? 16 : 0);
	124	hwif->select_data = (hwif->select_data & ~mask) \| val;
	125	/* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
	126	}
	127
8776168c	128	static void tx4939ide_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
37897989	129	{
37897989	130	u32 mask, val;
8776168c	131	const u8 mode = drive->dma_mode;
37897989 AN	132
	133	/* Update Data Transfer Mode for this drive. */
	134	if (mode >= XFER_UDMA_0)
	135	val = mode - XFER_UDMA_0 + 8;
	136	else
	137	val = mode - XFER_MW_DMA_0 + 5;
	138	if (drive->dn) {
	139	mask = 0x00f00000;
	140	val <<= 20;
	141	} else {
	142	mask = 0x000000f0;
	143	val <<= 4;
	144	}
	145	hwif->select_data = (hwif->select_data & ~mask) \| val;
	146	/* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
	147	}
	148
	149	static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif)
	150	{
	151	void __iomem *base = TX4939IDE_BASE(hwif);
	152	u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
	153
	154	if (ctl & TX4939IDE_INT_BUSERR) {
	155	/* reset FIFO */
	156	u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl);
	157
	158	tx4939ide_writew(sysctl \| 0x4000, base, TX4939IDE_Sys_Ctl);
37897989 AN	159	/* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */
	160	ndelay(270);
	161	tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
	162	}
	163	if (ctl & (TX4939IDE_INT_ADDRERR \|
	164	TX4939IDE_INT_DEVTIMING \| TX4939IDE_INT_BUSERR))
	165	pr_err("%s: Error interrupt %#x (%s%s%s )\n",
	166	hwif->name, ctl,
	167	ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "",
	168	ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "",
	169	ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : "");
	170	return ctl;
	171	}
	172
	173	static void tx4939ide_clear_irq(ide_drive_t *drive)
	174	{
	175	ide_hwif_t *hwif;
	176	void __iomem *base;
	177	u16 ctl;
	178
	179	/*
	180	* tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job
	181	* for DMA case.
	182	*/
	183	if (drive->waiting_for_dma)
	184	return;
	185	hwif = drive->hwif;
	186	base = TX4939IDE_BASE(hwif);
	187	ctl = tx4939ide_check_error_ints(hwif);
	188	tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
	189	}
	190
	191	static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
	192	{
	193	void __iomem *base = TX4939IDE_BASE(hwif);
	194
	195	return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ?
	196	ATA_CBL_PATA40 : ATA_CBL_PATA80;
	197	}
	198
	199	#ifdef __BIG_ENDIAN
	200	static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
	201	{
	202	ide_hwif_t *hwif = drive->hwif;
	203	u8 unit = drive->dn;
	204	void __iomem *base = TX4939IDE_BASE(hwif);
	205	u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
	206
	207	if (on)
	208	dma_stat \|= (1 << (5 + unit));
	209	else
	210	dma_stat &= ~(1 << (5 + unit));
	211
	212	tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat);
	213	}
	214	#else
	215	#define tx4939ide_dma_host_set ide_dma_host_set
	216	#endif
	217
	218	static u8 tx4939ide_clear_dma_status(void __iomem *base)
	219	{
	220	u8 dma_stat;
	221
	222	/* read DMA status for INTR & ERROR flags */
223	dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
224	/* clear INTR & ERROR flags */
225	tx4939ide_writeb(dma_stat \| ATA_DMA_INTR \| ATA_DMA_ERR, base,
226	TX4939IDE_DMA_Stat);
227	/* recover intmask cleared by writing to bit2 of DMA_Stat */
228	tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl);
229	return dma_stat;
230	}
231
232	#ifdef __BIG_ENDIAN
233	/* custom ide_build_dmatable to handle swapped layout */
22981694	234	static int tx4939ide_build_dmatable(ide_drive_t drive, struct ide_cmd cmd)
37897989 AN	235	{
	236	ide_hwif_t *hwif = drive->hwif;
	237	u32 table = (u32 )hwif->dmatable_cpu;
	238	unsigned int count = 0;
	239	int i;
	240	struct scatterlist *sg;
	241
22981694	242	for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) {
37897989 AN	243	u32 cur_addr, cur_len, bcount;
	244
	245	cur_addr = sg_dma_address(sg);
	246	cur_len = sg_dma_len(sg);
	247
	248	/*
	249	* Fill in the DMA table, without crossing any 64kB boundaries.
	250	*/
	251
	252	while (cur_len) {
	253	if (count++ >= PRD_ENTRIES)
	254	goto use_pio_instead;
	255
	256	bcount = 0x10000 - (cur_addr & 0xffff);
	257	if (bcount > cur_len)
	258	bcount = cur_len;
a0fce792 AN	259	/*
a0fce792 AN	260	* This workaround for zero count seems required.
9711a537	261	* (standard ide_build_dmatable does it too)
a0fce792	262	*/
9711a537	263	if (bcount == 0x10000)
a0fce792	264	bcount = 0x8000;
37897989 AN	265	*table++ = bcount & 0xffff;
	266	*table++ = cur_addr;
	267	cur_addr += bcount;
	268	cur_len -= bcount;
	269	}
	270	}
	271
	272	if (count) {
	273	*(table - 2) \|= 0x80000000;
	274	return count;
	275	}
	276
	277	use_pio_instead:
	278	printk(KERN_ERR "%s: %s\n", drive->name,
	279	count ? "DMA table too small" : "empty DMA table?");
	280
37897989 AN	281	return 0; /* revert to PIO for this request */
	282	}
	283	#else
	284	#define tx4939ide_build_dmatable ide_build_dmatable
	285	#endif
	286
22981694	287	static int tx4939ide_dma_setup(ide_drive_t drive, struct ide_cmd cmd)
37897989 AN	288	{
	289	ide_hwif_t *hwif = drive->hwif;
	290	void __iomem *base = TX4939IDE_BASE(hwif);
22981694	291	u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
37897989 AN	292
37897989 AN	293	/* fall back to PIO! */
11998b31	294	if (tx4939ide_build_dmatable(drive, cmd) == 0)
37897989	295	return 1;
37897989 AN	296
	297	/* PRD table */
	298	tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr);
	299
	300	/* specify r/w */
22981694	301	tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd);
37897989 AN	302
	303	/* clear INTR & ERROR flags */
	304	tx4939ide_clear_dma_status(base);
	305
37897989 AN	306	tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ?
37897989 AN	307	TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1);
22981694	308
9780e2dd	309	tx4939ide_writew(blk_rq_sectors(cmd->rq), base, TX4939IDE_Sec_Cnt);
22981694	310
37897989 AN	311	return 0;
	312	}
	313
	314	static int tx4939ide_dma_end(ide_drive_t *drive)
	315	{
	316	ide_hwif_t *hwif = drive->hwif;
	317	u8 dma_stat, dma_cmd;
	318	void __iomem *base = TX4939IDE_BASE(hwif);
	319	u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
	320
37897989 AN	321	/* get DMA command mode */
	322	dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd);
	323	/* stop DMA */
	324	tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd);
	325
	326	/* read and clear the INTR & ERROR bits */
	327	dma_stat = tx4939ide_clear_dma_status(base);
	328
253275c5	329	#define CHECK_DMA_MASK (ATA_DMA_ACTIVE \| ATA_DMA_ERR \| ATA_DMA_INTR)
37897989	330
4453011f	331	/* verify good DMA status */
253275c5	332	if ((dma_stat & CHECK_DMA_MASK) == 0 &&
37897989 AN	333	(ctl & (TX4939IDE_INT_XFEREND \| TX4939IDE_INT_HOST)) ==
	334	(TX4939IDE_INT_XFEREND \| TX4939IDE_INT_HOST))
	335	/* INT_IDE lost... bug? */
	336	return 0;
253275c5	337	return ((dma_stat & CHECK_DMA_MASK) !=
37897989 AN	338	ATA_DMA_INTR) ? 0x10 \| dma_stat : 0;
	339	}
	340
	341	/* returns 1 if DMA IRQ issued, 0 otherwise */
	342	static int tx4939ide_dma_test_irq(ide_drive_t *drive)
	343	{
	344	ide_hwif_t *hwif = drive->hwif;
	345	void __iomem *base = TX4939IDE_BASE(hwif);
	346	u16 ctl, ide_int;
	347	u8 dma_stat, stat;
	348	int found = 0;
	349
	350	ctl = tx4939ide_check_error_ints(hwif);
	351	ide_int = ctl & (TX4939IDE_INT_XFEREND \| TX4939IDE_INT_HOST);
	352	switch (ide_int) {
	353	case TX4939IDE_INT_HOST:
	354	/* On error, XFEREND might not be asserted. */
	355	stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl);
	356	if ((stat & (ATA_BUSY \| ATA_DRQ \| ATA_ERR)) == ATA_ERR)
	357	found = 1;
	358	else
	359	/* Wait for XFEREND (Mask HOST and unmask XFEREND) */
	360	ctl &= ~TX4939IDE_INT_XFEREND << 8;
	361	ctl \|= ide_int << 8;
	362	break;
	363	case TX4939IDE_INT_HOST \| TX4939IDE_INT_XFEREND:
	364	dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
	365	if (!(dma_stat & ATA_DMA_INTR))
a7f4a27f KW	366	pr_warn("%s: weird interrupt status. "
	367	"DMA_Stat %#02x int_ctl %#04x\n",
	368	hwif->name, dma_stat, ctl);
37897989 AN	369	found = 1;
	370	break;
	371	}
	372	/*
	373	* Do not clear XFEREND, HOST now. They will be cleared by
	374	* clearing bit2 of DMA_Stat.
	375	*/
	376	ctl &= ~ide_int;
	377	tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
	378	return found;
	379	}
	380
592b5315 SS	381	#ifdef __BIG_ENDIAN
	382	static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif)
	383	{
	384	void __iomem *base = TX4939IDE_BASE(hwif);
	385
	386	return tx4939ide_readb(base, TX4939IDE_DMA_Stat);
	387	}
	388	#else
	389	#define tx4939ide_dma_sff_read_status ide_dma_sff_read_status
	390	#endif
	391
37897989 AN	392	static void tx4939ide_init_hwif(ide_hwif_t *hwif)
	393	{
	394	void __iomem *base = TX4939IDE_BASE(hwif);
	395
	396	/* Soft Reset */
	397	tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);
37897989 AN	398	/* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */
	399	ndelay(450);
	400	tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);
	401	/* mask some interrupts and clear all interrupts */
	402	tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) \| 0xff, base,
	403	TX4939IDE_Int_Ctl);
	404
	405	tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt);
	406	tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt);
	407	}
	408
	409	static int tx4939ide_init_dma(ide_hwif_t hwif, const struct ide_port_info d)
	410	{
	411	hwif->dma_base =
	412	hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd);
	413	/*
	414	* Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS
	415	* for big endian.
	416	*/
	417	return ide_allocate_dma_engine(hwif);
	418	}
	419
22aa4b32	420	static void tx4939ide_tf_load_fixup(ide_drive_t *drive)
37897989 AN	421	{
	422	ide_hwif_t *hwif = drive->hwif;
	423	void __iomem *base = TX4939IDE_BASE(hwif);
	424	u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0);
	425
	426	/*
	427	* Fix ATA100 CORE System Control Register. (The write to the
	428	* Device/Head register may write wrong data to the System
	429	* Control Register)
abb596b2	430	* While Sys_Ctl is written here, dev_select() is not needed.
37897989 AN	431	*/
	432	tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
	433	}
	434
c9ff9e7b SS	435	static void tx4939ide_tf_load(ide_drive_t drive, struct ide_taskfile tf,
c9ff9e7b SS	436	u8 valid)
37897989	437	{
c9ff9e7b	438	ide_tf_load(drive, tf, valid);
d68bab50	439
c9ff9e7b	440	if (valid & IDE_VALID_DEVICE)
22aa4b32	441	tx4939ide_tf_load_fixup(drive);
37897989 AN	442	}
37897989 AN	443
d68bab50	444	#ifdef __BIG_ENDIAN
37897989	445
d68bab50	446	/* custom iops (independent from SWAP_IO_SPACE) */
aa24d978	447	static void tx4939ide_input_data_swap(ide_drive_t drive, struct ide_cmd cmd,
37897989 AN	448	void *buf, unsigned int len)
	449	{
	450	unsigned long port = drive->hwif->io_ports.data_addr;
	451	unsigned short *ptr = buf;
	452	unsigned int count = (len + 1) / 2;
	453
	454	while (count--)
	455	ptr++ = cpu_to_le16(__raw_readw((void __iomem )port));
f26f6cea	456	__ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
37897989 AN	457	}
37897989 AN	458
aa24d978	459	static void tx4939ide_output_data_swap(ide_drive_t drive, struct ide_cmd cmd,
37897989 AN	460	void *buf, unsigned int len)
	461	{
	462	unsigned long port = drive->hwif->io_ports.data_addr;
	463	unsigned short *ptr = buf;
	464	unsigned int count = (len + 1) / 2;
	465
	466	while (count--) {
	467	__raw_writew(le16_to_cpu(ptr), (void __iomem )port);
	468	ptr++;
	469	}
f26f6cea	470	__ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
37897989 AN	471	}
	472
	473	static const struct ide_tp_ops tx4939ide_tp_ops = {
	474	.exec_command = ide_exec_command,
	475	.read_status = ide_read_status,
	476	.read_altstatus = ide_read_altstatus,
ecf3a31d	477	.write_devctl = ide_write_devctl,
37897989	478
abb596b2	479	.dev_select = ide_dev_select,
37897989	480	.tf_load = tx4939ide_tf_load,
d68bab50	481	.tf_read = ide_tf_read,
37897989 AN	482
	483	.input_data = tx4939ide_input_data_swap,
	484	.output_data = tx4939ide_output_data_swap,
	485	};
	486
	487	#else /* __LITTLE_ENDIAN */
	488
37897989 AN	489	static const struct ide_tp_ops tx4939ide_tp_ops = {
	490	.exec_command = ide_exec_command,
	491	.read_status = ide_read_status,
	492	.read_altstatus = ide_read_altstatus,
ecf3a31d	493	.write_devctl = ide_write_devctl,
37897989	494
abb596b2	495	.dev_select = ide_dev_select,
37897989 AN	496	.tf_load = tx4939ide_tf_load,
	497	.tf_read = ide_tf_read,
	498
	499	.input_data = ide_input_data,
	500	.output_data = ide_output_data,
	501	};
	502
	503	#endif /* __LITTLE_ENDIAN */
	504
	505	static const struct ide_port_ops tx4939ide_port_ops = {
3ee86dcd BZ	506	.set_pio_mode = tx4939ide_set_pio_mode,
	507	.set_dma_mode = tx4939ide_set_dma_mode,
	508	.clear_irq = tx4939ide_clear_irq,
	509	.cable_detect = tx4939ide_cable_detect,
37897989 AN	510	};
	511
	512	static const struct ide_dma_ops tx4939ide_dma_ops = {
3ee86dcd BZ	513	.dma_host_set = tx4939ide_dma_host_set,
3ee86dcd BZ	514	.dma_setup = tx4939ide_dma_setup,
3ee86dcd BZ	515	.dma_start = ide_dma_start,
	516	.dma_end = tx4939ide_dma_end,
	517	.dma_test_irq = tx4939ide_dma_test_irq,
	518	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	519	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	520	.dma_sff_read_status = tx4939ide_dma_sff_read_status,
37897989 AN	521	};
37897989 AN	522
e6b53703	523	static const struct ide_port_info tx4939ide_port_info __initconst = {
3ee86dcd BZ	524	.init_hwif = tx4939ide_init_hwif,
	525	.init_dma = tx4939ide_init_dma,
	526	.port_ops = &tx4939ide_port_ops,
	527	.dma_ops = &tx4939ide_dma_ops,
	528	.tp_ops = &tx4939ide_tp_ops,
	529	.host_flags = IDE_HFLAG_MMIO,
	530	.pio_mask = ATA_PIO4,
	531	.mwdma_mask = ATA_MWDMA2,
	532	.udma_mask = ATA_UDMA5,
b1d249e8	533	.chipset = ide_generic,
37897989 AN	534	};
	535
	536	static int __init tx4939ide_probe(struct platform_device *pdev)
	537	{
9f36d314	538	struct ide_hw hw, *hws[] = { &hw };
37897989 AN	539	struct ide_host *host;
	540	struct resource *res;
	541	int irq, ret;
	542	unsigned long mapbase;
	543
	544	irq = platform_get_irq(pdev, 0);
	545	if (irq < 0)
	546	return -ENODEV;
	547	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	548	if (!res)
	549	return -ENODEV;
	550
	551	if (!devm_request_mem_region(&pdev->dev, res->start,
044b1a93	552	resource_size(res), MODNAME))
37897989 AN	553	return -EBUSY;
37897989 AN	554	mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
28f65c11	555	resource_size(res));
37897989 AN	556	if (!mapbase)
	557	return -EBUSY;
	558	memset(&hw, 0, sizeof(hw));
	559	hw.io_ports.data_addr =
	560	mapbase + tx4939ide_swizzlew(TX4939IDE_Data);
	561	hw.io_ports.error_addr =
	562	mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature);
	563	hw.io_ports.nsect_addr =
	564	mapbase + tx4939ide_swizzleb(TX4939IDE_Sec);
	565	hw.io_ports.lbal_addr =
	566	mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0);
	567	hw.io_ports.lbam_addr =
	568	mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1);
	569	hw.io_ports.lbah_addr =
	570	mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2);
	571	hw.io_ports.device_addr =
	572	mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead);
	573	hw.io_ports.command_addr =
	574	mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd);
	575	hw.io_ports.ctl_addr =
	576	mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl);
	577	hw.irq = irq;
	578	hw.dev = &pdev->dev;
	579
	580	pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq);
dca39830	581	host = ide_host_alloc(&tx4939ide_port_info, hws, 1);
37897989 AN	582	if (!host)
	583	return -ENOMEM;
	584	/* use extra_base for base address of the all registers */
	585	host->ports[0]->extra_base = mapbase;
	586	ret = ide_host_register(host, &tx4939ide_port_info, hws);
	587	if (ret) {
	588	ide_host_free(host);
	589	return ret;
	590	}
	591	platform_set_drvdata(pdev, host);
	592	return 0;
	593	}
	594
	595	static int __exit tx4939ide_remove(struct platform_device *pdev)
	596	{
	597	struct ide_host *host = platform_get_drvdata(pdev);
	598
	599	ide_host_remove(host);
	600	return 0;
	601	}
	602
	603	#ifdef CONFIG_PM
	604	static int tx4939ide_resume(struct platform_device *dev)
	605	{
	606	struct ide_host *host = platform_get_drvdata(dev);
	607	ide_hwif_t *hwif = host->ports[0];
	608
	609	tx4939ide_init_hwif(hwif);
	610	return 0;
	611	}
	612	#else
	613	#define tx4939ide_resume NULL
	614	#endif
	615
	616	static struct platform_driver tx4939ide_driver = {
	617	.driver = {
	618	.name = MODNAME,
37897989 AN	619	},
	620	.remove = __exit_p(tx4939ide_remove),
	621	.resume = tx4939ide_resume,
	622	};
	623
477c17db	624	module_platform_driver_probe(tx4939ide_driver, tx4939ide_probe);
37897989 AN	625
	626	MODULE_DESCRIPTION("TX4939 internal IDE driver");
	627	MODULE_LICENSE("GPL");
	628	MODULE_ALIAS("platform:tx4939ide");