[linux-2.6-block.git] / drivers / ide / slc90e66.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
 *
 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
 * but this keeps the ISA-Bridge and slots alive.
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#define DRV_NAME "slc90e66"

static DEFINE_SPINLOCK(slc90e66_lock);

static void slc90e66_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	int is_slave		= drive->dn & 1;
	int master_port		= hwif->channel ? 0x42 : 0x40;
	int slave_port		= 0x44;
	unsigned long flags;
	u16 master_data;
	u8 slave_data;
	int control = 0;
	const u8 pio = drive->pio_mode - XFER_PIO_0;

				     /* ISP  RTC */
	static const u8 timings[][2] = {
					{ 0, 0 },
					{ 0, 0 },
					{ 1, 0 },
					{ 2, 1 },
					{ 2, 3 }, };

	spin_lock_irqsave(&slc90e66_lock, flags);
	pci_read_config_word(dev, master_port, &master_data);

	if (pio > 1)
		control |= 1;	/* Programmable timing on */
	if (drive->media == ide_disk)
		control |= 4;	/* Prefetch, post write */
	if (ide_pio_need_iordy(drive, pio))
		control |= 2;	/* IORDY */
	if (is_slave) {
		master_data |=  0x4000;
		master_data &= ~0x0070;
		if (pio > 1) {
			/* Set PPE, IE and TIME */
			master_data |= control << 4;
		}
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data &= hwif->channel ? 0x0f : 0xf0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
			       (hwif->channel ? 4 : 0);
	} else {
		master_data &= ~0x3307;
		if (pio > 1) {
			/* enable PPE, IE and TIME */
			master_data |= control;
		}
		master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
	spin_unlock_irqrestore(&slc90e66_lock, flags);
}

static void slc90e66_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	u8 maslave		= hwif->channel ? 0x42 : 0x40;
	int sitre = 0, a_speed	= 7 << (drive->dn * 4);
	int u_speed = 0, u_flag = 1 << drive->dn;
	u16			reg4042, reg44, reg48, reg4a;
	const u8 speed		= drive->dma_mode;

	pci_read_config_word(dev, maslave, &reg4042);
	sitre = (reg4042 & 0x4000) ? 1 : 0;
	pci_read_config_word(dev, 0x44, &reg44);
	pci_read_config_word(dev, 0x48, &reg48);
	pci_read_config_word(dev, 0x4a, &reg4a);

	if (speed >= XFER_UDMA_0) {
		u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);

		if (!(reg48 & u_flag))
			pci_write_config_word(dev, 0x48, reg48|u_flag);
		if ((reg4a & a_speed) != u_speed) {
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
			pci_read_config_word(dev, 0x4a, &reg4a);
			pci_write_config_word(dev, 0x4a, reg4a|u_speed);
		}
	} else {
		const u8 mwdma_to_pio[] = { 0, 3, 4 };

		if (reg48 & u_flag)
			pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
		if (reg4a & a_speed)
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);

		if (speed >= XFER_MW_DMA_0)
			drive->pio_mode =
				mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
		else
			drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */

		slc90e66_set_pio_mode(hwif, drive);
	}
}

static u8 slc90e66_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02;

	pci_read_config_byte(dev, 0x47, &reg47);

	/* bit[0(1)]: 0:80, 1:40 */
	return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
}

static const struct ide_port_ops slc90e66_port_ops = {
	.set_pio_mode		= slc90e66_set_pio_mode,
	.set_dma_mode		= slc90e66_set_dma_mode,
	.cable_detect		= slc90e66_cable_detect,
};

static const struct ide_port_info slc90e66_chipset = {
	.name		= DRV_NAME,
	.enablebits	= { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} },
	.port_ops	= &slc90e66_port_ops,
	.pio_mask	= ATA_PIO4,
	.swdma_mask	= ATA_SWDMA2_ONLY,
	.mwdma_mask	= ATA_MWDMA12_ONLY,
	.udma_mask	= ATA_UDMA4,
};

static int slc90e66_init_one(struct pci_dev *dev,
			     const struct pci_device_id *id)
{
	return ide_pci_init_one(dev, &slc90e66_chipset, NULL);
}

static const struct pci_device_id slc90e66_pci_tbl[] = {
	{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);

static struct pci_driver slc90e66_pci_driver = {
	.name		= "SLC90e66_IDE",
	.id_table	= slc90e66_pci_tbl,
	.probe		= slc90e66_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init slc90e66_ide_init(void)
{
	return ide_pci_register_driver(&slc90e66_pci_driver);
}

static void __exit slc90e66_ide_exit(void)
{
	pci_unregister_driver(&slc90e66_pci_driver);
}

module_init(slc90e66_ide_init);
module_exit(slc90e66_ide_exit);

MODULE_AUTHOR("Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4	2	/*
1da177e4	3	* Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
07af4276	4	* Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
1da177e4	5	*
44854add	6	* This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
1da177e4 LT	7	* but this keeps the ISA-Bridge and slots alive.
	8	*
	9	*/
	10
1da177e4 LT	11	#include <linux/types.h>
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
1da177e4	14	#include <linux/pci.h>
1da177e4	15	#include <linux/ide.h>
1da177e4 LT	16	#include <linux/init.h>
1da177e4 LT	17
ced3ec8a BZ	18	#define DRV_NAME "slc90e66"
ced3ec8a BZ	19
a482958b BZ	20	static DEFINE_SPINLOCK(slc90e66_lock);
a482958b BZ	21
e085b3ca	22	static void slc90e66_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	23	{
36501650	24	struct pci_dev *dev = to_pci_dev(hwif->dev);
24e6458d	25	int is_slave = drive->dn & 1;
1da177e4 LT	26	int master_port = hwif->channel ? 0x42 : 0x40;
	27	int slave_port = 0x44;
	28	unsigned long flags;
	29	u16 master_data;
	30	u8 slave_data;
5749c847	31	int control = 0;
e085b3ca BZ	32	const u8 pio = drive->pio_mode - XFER_PIO_0;
e085b3ca BZ	33
24e6458d	34	/* ISP RTC */
5749c847	35	static const u8 timings[][2] = {
24e6458d SS	36	{ 0, 0 },
	37	{ 0, 0 },
	38	{ 1, 0 },
	39	{ 2, 1 },
	40	{ 2, 3 }, };
1da177e4	41
a482958b	42	spin_lock_irqsave(&slc90e66_lock, flags);
1da177e4	43	pci_read_config_word(dev, master_port, &master_data);
24e6458d SS	44
	45	if (pio > 1)
	46	control \|= 1; /* Programmable timing on */
	47	if (drive->media == ide_disk)
	48	control \|= 4; /* Prefetch, post write */
c9ef59ff	49	if (ide_pio_need_iordy(drive, pio))
24e6458d	50	control \|= 2; /* IORDY */
1da177e4	51	if (is_slave) {
24e6458d SS	52	master_data \|= 0x4000;
	53	master_data &= ~0x0070;
	54	if (pio > 1) {
07af4276 SS	55	/* Set PPE, IE and TIME */
07af4276 SS	56	master_data \|= control << 4;
24e6458d	57	}
1da177e4	58	pci_read_config_byte(dev, slave_port, &slave_data);
07af4276 SS	59	slave_data &= hwif->channel ? 0x0f : 0xf0;
	60	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) <<
	61	(hwif->channel ? 4 : 0);
1da177e4	62	} else {
24e6458d SS	63	master_data &= ~0x3307;
24e6458d SS	64	if (pio > 1) {
1da177e4	65	/* enable PPE, IE and TIME */
07af4276	66	master_data \|= control;
24e6458d	67	}
07af4276	68	master_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
1da177e4 LT	69	}
	70	pci_write_config_word(dev, master_port, master_data);
	71	if (is_slave)
	72	pci_write_config_byte(dev, slave_port, slave_data);
a482958b	73	spin_unlock_irqrestore(&slc90e66_lock, flags);
1da177e4 LT	74	}
1da177e4 LT	75
8776168c	76	static void slc90e66_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	77	{
36501650	78	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	79	u8 maslave = hwif->channel ? 0x42 : 0x40;
1da177e4 LT	80	int sitre = 0, a_speed = 7 << (drive->dn * 4);
	81	int u_speed = 0, u_flag = 1 << drive->dn;
	82	u16 reg4042, reg44, reg48, reg4a;
8776168c	83	const u8 speed = drive->dma_mode;
1da177e4 LT	84
	85	pci_read_config_word(dev, maslave, &reg4042);
	86	sitre = (reg4042 & 0x4000) ? 1 : 0;
	87	pci_read_config_word(dev, 0x44, &reg44);
	88	pci_read_config_word(dev, 0x48, &reg48);
	89	pci_read_config_word(dev, 0x4a, &reg4a);
	90
1da177e4	91	if (speed >= XFER_UDMA_0) {
4db90a14 BZ	92	u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
4db90a14 BZ	93
1da177e4 LT	94	if (!(reg48 & u_flag))
1da177e4 LT	95	pci_write_config_word(dev, 0x48, reg48\|u_flag);
ee31527a	96	if ((reg4a & a_speed) != u_speed) {
1da177e4 LT	97	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
	98	pci_read_config_word(dev, 0x4a, &reg4a);
	99	pci_write_config_word(dev, 0x4a, reg4a\|u_speed);
	100	}
	101	} else {
8c91abf8 BZ	102	const u8 mwdma_to_pio[] = { 0, 3, 4 };
8c91abf8 BZ	103
1da177e4 LT	104	if (reg48 & u_flag)
	105	pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
	106	if (reg4a & a_speed)
	107	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
8c91abf8 BZ	108
8c91abf8 BZ	109	if (speed >= XFER_MW_DMA_0)
e085b3ca BZ	110	drive->pio_mode =
e085b3ca BZ	111	mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
8c91abf8	112	else
e085b3ca	113	drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
1da177e4	114
e085b3ca	115	slc90e66_set_pio_mode(hwif, drive);
1c54a93d	116	}
1da177e4 LT	117	}
1da177e4 LT	118
f454cbe8	119	static u8 slc90e66_cable_detect(ide_hwif_t *hwif)
1da177e4	120	{
36501650	121	struct pci_dev *dev = to_pci_dev(hwif->dev);
bfa14b42	122	u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02;
1da177e4	123
36501650	124	pci_read_config_byte(dev, 0x47, &reg47);
1da177e4	125
bfa14b42 BZ	126	/* bit[0(1)]: 0:80, 1:40 */
	127	return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
	128	}
	129
ac95beed BZ	130	static const struct ide_port_ops slc90e66_port_ops = {
	131	.set_pio_mode = slc90e66_set_pio_mode,
	132	.set_dma_mode = slc90e66_set_dma_mode,
	133	.cable_detect = slc90e66_cable_detect,
	134	};
1da177e4	135
fe31edc8	136	static const struct ide_port_info slc90e66_chipset = {
ced3ec8a	137	.name = DRV_NAME,
5749c847	138	.enablebits = { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} },
ac95beed	139	.port_ops = &slc90e66_port_ops,
4099d143	140	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	141	.swdma_mask = ATA_SWDMA2_ONLY,
	142	.mwdma_mask = ATA_MWDMA12_ONLY,
	143	.udma_mask = ATA_UDMA4,
1da177e4 LT	144	};
1da177e4 LT	145
fe31edc8 GKH	146	static int slc90e66_init_one(struct pci_dev *dev,
fe31edc8 GKH	147	const struct pci_device_id *id)
1da177e4	148	{
6cdf6eb3	149	return ide_pci_init_one(dev, &slc90e66_chipset, NULL);
1da177e4 LT	150	}
1da177e4 LT	151
9cbcc5e3 BZ	152	static const struct pci_device_id slc90e66_pci_tbl[] = {
9cbcc5e3 BZ	153	{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
1da177e4 LT	154	{ 0, },
	155	};
	156	MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
	157
a9ab09e2	158	static struct pci_driver slc90e66_pci_driver = {
1da177e4 LT	159	.name = "SLC90e66_IDE",
	160	.id_table = slc90e66_pci_tbl,
	161	.probe = slc90e66_init_one,
64b0fed3	162	.remove = ide_pci_remove,
feb22b7f BZ	163	.suspend = ide_pci_suspend,
feb22b7f BZ	164	.resume = ide_pci_resume,
1da177e4 LT	165	};
1da177e4 LT	166
82ab1eec	167	static int __init slc90e66_ide_init(void)
1da177e4	168	{
a9ab09e2	169	return ide_pci_register_driver(&slc90e66_pci_driver);
1da177e4 LT	170	}
1da177e4 LT	171
64b0fed3 BZ	172	static void __exit slc90e66_ide_exit(void)
64b0fed3 BZ	173	{
a9ab09e2	174	pci_unregister_driver(&slc90e66_pci_driver);
64b0fed3 BZ	175	}
64b0fed3 BZ	176
1da177e4	177	module_init(slc90e66_ide_init);
64b0fed3	178	module_exit(slc90e66_ide_exit);
1da177e4 LT	179
	180	MODULE_AUTHOR("Andre Hedrick");
	181	MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
	182	MODULE_LICENSE("GPL");