Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
59bca8cc BZ |
2 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 1995-1998 Mark Lord | |
4 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 5 | * |
1da177e4 | 6 | * May be copied or modified under the terms of the GNU General Public License |
1da177e4 LT |
7 | */ |
8 | ||
1da177e4 LT |
9 | #include <linux/module.h> |
10 | #include <linux/types.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/timer.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/ide.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | #include <asm/irq.h> | |
22 | ||
1da177e4 LT |
23 | /** |
24 | * ide_setup_pci_baseregs - place a PCI IDE controller native | |
25 | * @dev: PCI device of interface to switch native | |
26 | * @name: Name of interface | |
27 | * | |
28 | * We attempt to place the PCI interface into PCI native mode. If | |
29 | * we succeed the BARs are ok and the controller is in PCI mode. | |
846bb88a | 30 | * Returns 0 on success or an errno code. |
1da177e4 LT |
31 | * |
32 | * FIXME: if we program the interface and then fail to set the BARS | |
33 | * we don't switch it back to legacy mode. Do we actually care ?? | |
34 | */ | |
846bb88a PC |
35 | |
36 | static int ide_setup_pci_baseregs(struct pci_dev *dev, const char *name) | |
1da177e4 LT |
37 | { |
38 | u8 progif = 0; | |
39 | ||
40 | /* | |
41 | * Place both IDE interfaces into PCI "native" mode: | |
42 | */ | |
43 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
44 | (progif & 5) != 5) { | |
45 | if ((progif & 0xa) != 0xa) { | |
46 | printk(KERN_INFO "%s: device not capable of full " | |
47 | "native PCI mode\n", name); | |
48 | return -EOPNOTSUPP; | |
49 | } | |
50 | printk("%s: placing both ports into native PCI mode\n", name); | |
51 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); | |
52 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
53 | (progif & 5) != 5) { | |
54 | printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted " | |
55 | "0x%04x, got 0x%04x\n", | |
56 | name, progif|5, progif); | |
57 | return -EOPNOTSUPP; | |
58 | } | |
59 | } | |
60 | return 0; | |
61 | } | |
62 | ||
63 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
8ac2b42a BZ |
64 | static void ide_pci_clear_simplex(unsigned long dma_base, const char *name) |
65 | { | |
66 | u8 dma_stat = inb(dma_base + 2); | |
67 | ||
68 | outb(dma_stat & 0x60, dma_base + 2); | |
69 | dma_stat = inb(dma_base + 2); | |
70 | if (dma_stat & 0x80) | |
71 | printk(KERN_INFO "%s: simplex device: DMA forced\n", name); | |
72 | } | |
73 | ||
1da177e4 LT |
74 | /** |
75 | * ide_get_or_set_dma_base - setup BMIBA | |
039788e1 BZ |
76 | * @d: IDE port info |
77 | * @hwif: IDE interface | |
1da177e4 | 78 | * |
c58e79dd BZ |
79 | * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space. |
80 | * Where a device has a partner that is already in DMA mode we check | |
81 | * and enforce IDE simplex rules. | |
1da177e4 LT |
82 | */ |
83 | ||
85620436 | 84 | static unsigned long ide_get_or_set_dma_base(const struct ide_port_info *d, ide_hwif_t *hwif) |
1da177e4 | 85 | { |
36501650 BZ |
86 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
87 | unsigned long dma_base = 0; | |
8ac2b42a | 88 | u8 dma_stat = 0; |
1da177e4 | 89 | |
1da177e4 LT |
90 | if (hwif->mmio) |
91 | return hwif->dma_base; | |
92 | ||
93 | if (hwif->mate && hwif->mate->dma_base) { | |
94 | dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8); | |
95 | } else { | |
9ffcf364 BZ |
96 | u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4; |
97 | ||
98 | dma_base = pci_resource_start(dev, baridx); | |
99 | ||
aea5d375 | 100 | if (dma_base == 0) { |
9ffcf364 | 101 | printk(KERN_ERR "%s: DMA base is invalid\n", d->name); |
aea5d375 BZ |
102 | return 0; |
103 | } | |
1da177e4 LT |
104 | } |
105 | ||
aea5d375 BZ |
106 | if (hwif->channel) |
107 | dma_base += 8; | |
108 | ||
8ac2b42a BZ |
109 | if (d->host_flags & IDE_HFLAG_CS5520) |
110 | goto out; | |
111 | ||
112 | if (d->host_flags & IDE_HFLAG_CLEAR_SIMPLEX) { | |
113 | ide_pci_clear_simplex(dma_base, d->name); | |
114 | goto out; | |
115 | } | |
116 | ||
117 | /* | |
118 | * If the device claims "simplex" DMA, this means that only one of | |
119 | * the two interfaces can be trusted with DMA at any point in time | |
120 | * (so we should enable DMA only on one of the two interfaces). | |
121 | * | |
122 | * FIXME: At this point we haven't probed the drives so we can't make | |
123 | * the appropriate decision. Really we should defer this problem until | |
124 | * we tune the drive then try to grab DMA ownership if we want to be | |
125 | * the DMA end. This has to be become dynamic to handle hot-plug. | |
126 | */ | |
127 | dma_stat = hwif->INB(dma_base + 2); | |
128 | if ((dma_stat & 0x80) && hwif->mate && hwif->mate->dma_base) { | |
129 | printk(KERN_INFO "%s: simplex device: DMA disabled\n", d->name); | |
130 | dma_base = 0; | |
1da177e4 | 131 | } |
8ac2b42a | 132 | out: |
1da177e4 LT |
133 | return dma_base; |
134 | } | |
d54452fb BZ |
135 | |
136 | /* | |
137 | * Set up BM-DMA capability (PnP BIOS should have done this) | |
138 | */ | |
139 | static int ide_pci_set_master(struct pci_dev *dev, const char *name) | |
140 | { | |
141 | u16 pcicmd; | |
142 | ||
143 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
144 | ||
145 | if ((pcicmd & PCI_COMMAND_MASTER) == 0) { | |
146 | pci_set_master(dev); | |
147 | ||
148 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || | |
149 | (pcicmd & PCI_COMMAND_MASTER) == 0) { | |
150 | printk(KERN_ERR "%s: error updating PCICMD on %s\n", | |
151 | name, pci_name(dev)); | |
152 | return -EIO; | |
153 | } | |
154 | } | |
155 | ||
156 | return 0; | |
157 | } | |
1da177e4 LT |
158 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
159 | ||
85620436 | 160 | void ide_setup_pci_noise(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 161 | { |
bde07e5e BZ |
162 | printk(KERN_INFO "%s: IDE controller (0x%04x:0x%04x rev 0x%02x) at " |
163 | " PCI slot %s\n", d->name, dev->vendor, dev->device, | |
164 | dev->revision, pci_name(dev)); | |
1da177e4 | 165 | } |
1da177e4 LT |
166 | EXPORT_SYMBOL_GPL(ide_setup_pci_noise); |
167 | ||
168 | ||
169 | /** | |
170 | * ide_pci_enable - do PCI enables | |
171 | * @dev: PCI device | |
039788e1 | 172 | * @d: IDE port info |
1da177e4 LT |
173 | * |
174 | * Enable the IDE PCI device. We attempt to enable the device in full | |
09483916 BH |
175 | * but if that fails then we only need IO space. The PCI code should |
176 | * have setup the proper resources for us already for controllers in | |
177 | * legacy mode. | |
846bb88a | 178 | * |
1da177e4 LT |
179 | * Returns zero on success or an error code |
180 | */ | |
039788e1 | 181 | |
85620436 | 182 | static int ide_pci_enable(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 183 | { |
0d1bad21 | 184 | int ret, bars; |
1da177e4 LT |
185 | |
186 | if (pci_enable_device(dev)) { | |
09483916 | 187 | ret = pci_enable_device_io(dev); |
1da177e4 LT |
188 | if (ret < 0) { |
189 | printk(KERN_WARNING "%s: (ide_setup_pci_device:) " | |
190 | "Could not enable device.\n", d->name); | |
191 | goto out; | |
192 | } | |
193 | printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name); | |
194 | } | |
195 | ||
196 | /* | |
039788e1 BZ |
197 | * assume all devices can do 32-bit DMA for now, we can add |
198 | * a DMA mask field to the struct ide_port_info if we need it | |
199 | * (or let lower level driver set the DMA mask) | |
1da177e4 LT |
200 | */ |
201 | ret = pci_set_dma_mask(dev, DMA_32BIT_MASK); | |
202 | if (ret < 0) { | |
203 | printk(KERN_ERR "%s: can't set dma mask\n", d->name); | |
204 | goto out; | |
205 | } | |
206 | ||
0d1bad21 BZ |
207 | if (d->host_flags & IDE_HFLAG_SINGLE) |
208 | bars = (1 << 2) - 1; | |
209 | else | |
210 | bars = (1 << 4) - 1; | |
1da177e4 | 211 | |
0d1bad21 BZ |
212 | if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) { |
213 | if (d->host_flags & IDE_HFLAG_CS5520) | |
214 | bars |= (1 << 2); | |
215 | else | |
216 | bars |= (1 << 4); | |
217 | } | |
218 | ||
219 | ret = pci_request_selected_regions(dev, bars, d->name); | |
220 | if (ret < 0) | |
221 | printk(KERN_ERR "%s: can't reserve resources\n", d->name); | |
1da177e4 LT |
222 | out: |
223 | return ret; | |
224 | } | |
225 | ||
226 | /** | |
227 | * ide_pci_configure - configure an unconfigured device | |
228 | * @dev: PCI device | |
039788e1 | 229 | * @d: IDE port info |
1da177e4 LT |
230 | * |
231 | * Enable and configure the PCI device we have been passed. | |
232 | * Returns zero on success or an error code. | |
233 | */ | |
039788e1 | 234 | |
85620436 | 235 | static int ide_pci_configure(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 LT |
236 | { |
237 | u16 pcicmd = 0; | |
238 | /* | |
239 | * PnP BIOS was *supposed* to have setup this device, but we | |
240 | * can do it ourselves, so long as the BIOS has assigned an IRQ | |
241 | * (or possibly the device is using a "legacy header" for IRQs). | |
242 | * Maybe the user deliberately *disabled* the device, | |
243 | * but we'll eventually ignore it again if no drives respond. | |
244 | */ | |
846bb88a PC |
245 | if (ide_setup_pci_baseregs(dev, d->name) || |
246 | pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) { | |
1da177e4 LT |
247 | printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name); |
248 | return -ENODEV; | |
249 | } | |
250 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { | |
251 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
252 | return -EIO; | |
253 | } | |
254 | if (!(pcicmd & PCI_COMMAND_IO)) { | |
255 | printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name); | |
256 | return -ENXIO; | |
257 | } | |
258 | return 0; | |
259 | } | |
260 | ||
261 | /** | |
262 | * ide_pci_check_iomem - check a register is I/O | |
039788e1 BZ |
263 | * @dev: PCI device |
264 | * @d: IDE port info | |
265 | * @bar: BAR number | |
1da177e4 | 266 | * |
1baccff8 SS |
267 | * Checks if a BAR is configured and points to MMIO space. If so, |
268 | * return an error code. Otherwise return 0 | |
1da177e4 | 269 | */ |
039788e1 | 270 | |
1baccff8 SS |
271 | static int ide_pci_check_iomem(struct pci_dev *dev, const struct ide_port_info *d, |
272 | int bar) | |
1da177e4 LT |
273 | { |
274 | ulong flags = pci_resource_flags(dev, bar); | |
846bb88a | 275 | |
1da177e4 LT |
276 | /* Unconfigured ? */ |
277 | if (!flags || pci_resource_len(dev, bar) == 0) | |
278 | return 0; | |
279 | ||
1baccff8 SS |
280 | /* I/O space */ |
281 | if (flags & IORESOURCE_IO) | |
1da177e4 | 282 | return 0; |
846bb88a | 283 | |
1da177e4 | 284 | /* Bad */ |
1da177e4 LT |
285 | return -EINVAL; |
286 | } | |
287 | ||
288 | /** | |
289 | * ide_hwif_configure - configure an IDE interface | |
290 | * @dev: PCI device holding interface | |
039788e1 | 291 | * @d: IDE port info |
1ebf7493 BZ |
292 | * @port: port number |
293 | * @irq: PCI IRQ | |
1da177e4 LT |
294 | * |
295 | * Perform the initial set up for the hardware interface structure. This | |
296 | * is done per interface port rather than per PCI device. There may be | |
297 | * more than one port per device. | |
298 | * | |
299 | * Returns the new hardware interface structure, or NULL on a failure | |
300 | */ | |
039788e1 | 301 | |
1ebf7493 BZ |
302 | static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, |
303 | const struct ide_port_info *d, | |
304 | unsigned int port, int irq) | |
1da177e4 LT |
305 | { |
306 | unsigned long ctl = 0, base = 0; | |
307 | ide_hwif_t *hwif; | |
79127c37 | 308 | struct hw_regs_s hw; |
1da177e4 | 309 | |
a5d8c5c8 | 310 | if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) { |
1baccff8 SS |
311 | if (ide_pci_check_iomem(dev, d, 2 * port) || |
312 | ide_pci_check_iomem(dev, d, 2 * port + 1)) { | |
313 | printk(KERN_ERR "%s: I/O baseregs (BIOS) are reported " | |
314 | "as MEM for port %d!\n", d->name, port); | |
315 | return NULL; | |
316 | } | |
846bb88a | 317 | |
1da177e4 LT |
318 | ctl = pci_resource_start(dev, 2*port+1); |
319 | base = pci_resource_start(dev, 2*port); | |
320 | if ((ctl && !base) || (base && !ctl)) { | |
321 | printk(KERN_ERR "%s: inconsistent baseregs (BIOS) " | |
322 | "for port %d, skipping\n", d->name, port); | |
323 | return NULL; | |
324 | } | |
325 | } | |
846bb88a | 326 | if (!ctl) { |
1da177e4 LT |
327 | /* Use default values */ |
328 | ctl = port ? 0x374 : 0x3f4; | |
329 | base = port ? 0x170 : 0x1f0; | |
330 | } | |
bad7c825 | 331 | |
fe80b937 | 332 | hwif = ide_find_port_slot(d); |
bad7c825 BZ |
333 | if (hwif == NULL) { |
334 | printk(KERN_ERR "%s: too many IDE interfaces, no room in " | |
335 | "table\n", d->name); | |
336 | return NULL; | |
337 | } | |
79127c37 BZ |
338 | |
339 | memset(&hw, 0, sizeof(hw)); | |
aab8ad9e | 340 | hw.irq = irq; |
79127c37 BZ |
341 | hw.dev = &dev->dev; |
342 | hw.chipset = d->chipset ? d->chipset : ide_pci; | |
343 | ide_std_init_ports(&hw, base, ctl | 2); | |
344 | ||
79127c37 BZ |
345 | ide_init_port_hw(hwif, &hw); |
346 | ||
36501650 | 347 | hwif->dev = &dev->dev; |
1da177e4 | 348 | |
1da177e4 LT |
349 | return hwif; |
350 | } | |
351 | ||
c413b9b9 | 352 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
353 | /** |
354 | * ide_hwif_setup_dma - configure DMA interface | |
039788e1 | 355 | * @hwif: IDE interface |
c413b9b9 | 356 | * @d: IDE port info |
1da177e4 LT |
357 | * |
358 | * Set up the DMA base for the interface. Enable the master bits as | |
359 | * necessary and attempt to bring the device DMA into a ready to use | |
360 | * state | |
361 | */ | |
039788e1 | 362 | |
c413b9b9 | 363 | void ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 364 | { |
c413b9b9 | 365 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 366 | |
47b68788 | 367 | if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 || |
1da177e4 LT |
368 | ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && |
369 | (dev->class & 0x80))) { | |
9ffcf364 | 370 | unsigned long dma_base = ide_get_or_set_dma_base(d, hwif); |
d54452fb BZ |
371 | |
372 | if (dma_base == 0 || ide_pci_set_master(dev, d->name) < 0) | |
373 | goto out_disabled; | |
374 | ||
375 | if (d->init_dma) | |
376 | d->init_dma(hwif, dma_base); | |
377 | ||
378 | ide_setup_dma(hwif, dma_base); | |
1da177e4 | 379 | } |
d54452fb BZ |
380 | |
381 | return; | |
382 | ||
383 | out_disabled: | |
384 | printk(KERN_INFO "%s: Bus-Master DMA disabled (BIOS) on %s\n", | |
385 | d->name, pci_name(dev)); | |
039788e1 | 386 | } |
c413b9b9 | 387 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
1da177e4 LT |
388 | |
389 | /** | |
390 | * ide_setup_pci_controller - set up IDE PCI | |
391 | * @dev: PCI device | |
039788e1 | 392 | * @d: IDE port info |
1da177e4 LT |
393 | * @noisy: verbose flag |
394 | * @config: returned as 1 if we configured the hardware | |
395 | * | |
396 | * Set up the PCI and controller side of the IDE interface. This brings | |
397 | * up the PCI side of the device, checks that the device is enabled | |
398 | * and enables it if need be | |
399 | */ | |
039788e1 | 400 | |
85620436 | 401 | static int ide_setup_pci_controller(struct pci_dev *dev, const struct ide_port_info *d, int noisy, int *config) |
1da177e4 LT |
402 | { |
403 | int ret; | |
1da177e4 LT |
404 | u16 pcicmd; |
405 | ||
406 | if (noisy) | |
407 | ide_setup_pci_noise(dev, d); | |
408 | ||
409 | ret = ide_pci_enable(dev, d); | |
410 | if (ret < 0) | |
411 | goto out; | |
412 | ||
413 | ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
414 | if (ret < 0) { | |
415 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
416 | goto out; | |
417 | } | |
418 | if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ | |
419 | ret = ide_pci_configure(dev, d); | |
420 | if (ret < 0) | |
421 | goto out; | |
422 | *config = 1; | |
423 | printk(KERN_INFO "%s: device enabled (Linux)\n", d->name); | |
424 | } | |
425 | ||
1da177e4 LT |
426 | out: |
427 | return ret; | |
428 | } | |
429 | ||
430 | /** | |
431 | * ide_pci_setup_ports - configure ports/devices on PCI IDE | |
432 | * @dev: PCI device | |
039788e1 | 433 | * @d: IDE port info |
1da177e4 | 434 | * @pciirq: IRQ line |
8447d9d5 | 435 | * @idx: ATA index table to update |
1da177e4 LT |
436 | * |
437 | * Scan the interfaces attached to this device and do any | |
438 | * necessary per port setup. Attach the devices and ask the | |
439 | * generic DMA layer to do its work for us. | |
440 | * | |
441 | * Normally called automaticall from do_ide_pci_setup_device, | |
442 | * but is also used directly as a helper function by some controllers | |
443 | * where the chipset setup is not the default PCI IDE one. | |
444 | */ | |
8447d9d5 | 445 | |
85620436 | 446 | void ide_pci_setup_ports(struct pci_dev *dev, const struct ide_port_info *d, int pciirq, u8 *idx) |
1da177e4 | 447 | { |
a5d8c5c8 | 448 | int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port; |
c413b9b9 | 449 | ide_hwif_t *hwif; |
1da177e4 LT |
450 | u8 tmp; |
451 | ||
1da177e4 LT |
452 | /* |
453 | * Set up the IDE ports | |
454 | */ | |
cf6e854e | 455 | |
a5d8c5c8 | 456 | for (port = 0; port < channels; ++port) { |
85620436 BZ |
457 | const ide_pci_enablebit_t *e = &(d->enablebits[port]); |
458 | ||
1da177e4 | 459 | if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || |
cf6e854e BZ |
460 | (tmp & e->mask) != e->val)) { |
461 | printk(KERN_INFO "%s: IDE port disabled\n", d->name); | |
1da177e4 | 462 | continue; /* port not enabled */ |
cf6e854e | 463 | } |
1da177e4 | 464 | |
1ebf7493 BZ |
465 | hwif = ide_hwif_configure(dev, d, port, pciirq); |
466 | if (hwif == NULL) | |
1da177e4 LT |
467 | continue; |
468 | ||
8447d9d5 | 469 | *(idx + port) = hwif->index; |
1ebf7493 | 470 | } |
1da177e4 | 471 | } |
1da177e4 LT |
472 | EXPORT_SYMBOL_GPL(ide_pci_setup_ports); |
473 | ||
474 | /* | |
475 | * ide_setup_pci_device() looks at the primary/secondary interfaces | |
476 | * on a PCI IDE device and, if they are enabled, prepares the IDE driver | |
477 | * for use with them. This generic code works for most PCI chipsets. | |
478 | * | |
479 | * One thing that is not standardized is the location of the | |
480 | * primary/secondary interface "enable/disable" bits. For chipsets that | |
039788e1 | 481 | * we "know" about, this information is in the struct ide_port_info; |
1da177e4 LT |
482 | * for all other chipsets, we just assume both interfaces are enabled. |
483 | */ | |
039788e1 | 484 | static int do_ide_setup_pci_device(struct pci_dev *dev, |
85620436 | 485 | const struct ide_port_info *d, |
8447d9d5 | 486 | u8 *idx, u8 noisy) |
1da177e4 | 487 | { |
1da177e4 LT |
488 | int tried_config = 0; |
489 | int pciirq, ret; | |
490 | ||
491 | ret = ide_setup_pci_controller(dev, d, noisy, &tried_config); | |
492 | if (ret < 0) | |
493 | goto out; | |
494 | ||
495 | /* | |
496 | * Can we trust the reported IRQ? | |
497 | */ | |
498 | pciirq = dev->irq; | |
499 | ||
500 | /* Is it an "IDE storage" device in non-PCI mode? */ | |
501 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) { | |
502 | if (noisy) | |
503 | printk(KERN_INFO "%s: not 100%% native mode: " | |
504 | "will probe irqs later\n", d->name); | |
505 | /* | |
506 | * This allows offboard ide-pci cards the enable a BIOS, | |
507 | * verify interrupt settings of split-mirror pci-config | |
508 | * space, place chipset into init-mode, and/or preserve | |
509 | * an interrupt if the card is not native ide support. | |
510 | */ | |
511 | ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0; | |
512 | if (ret < 0) | |
513 | goto out; | |
514 | pciirq = ret; | |
515 | } else if (tried_config) { | |
516 | if (noisy) | |
517 | printk(KERN_INFO "%s: will probe irqs later\n", d->name); | |
518 | pciirq = 0; | |
519 | } else if (!pciirq) { | |
520 | if (noisy) | |
521 | printk(KERN_WARNING "%s: bad irq (%d): will probe later\n", | |
522 | d->name, pciirq); | |
523 | pciirq = 0; | |
524 | } else { | |
525 | if (d->init_chipset) { | |
526 | ret = d->init_chipset(dev, d->name); | |
527 | if (ret < 0) | |
528 | goto out; | |
529 | } | |
530 | if (noisy) | |
1da177e4 LT |
531 | printk(KERN_INFO "%s: 100%% native mode on irq %d\n", |
532 | d->name, pciirq); | |
1da177e4 LT |
533 | } |
534 | ||
535 | /* FIXME: silent failure can happen */ | |
536 | ||
8447d9d5 | 537 | ide_pci_setup_ports(dev, d, pciirq, idx); |
1da177e4 LT |
538 | out: |
539 | return ret; | |
540 | } | |
541 | ||
85620436 | 542 | int ide_setup_pci_device(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 543 | { |
8447d9d5 | 544 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
545 | int ret; |
546 | ||
8447d9d5 | 547 | ret = do_ide_setup_pci_device(dev, d, &idx[0], 1); |
1da177e4 | 548 | |
8447d9d5 | 549 | if (ret >= 0) |
c413b9b9 | 550 | ide_device_add(idx, d); |
1da177e4 | 551 | |
1da177e4 LT |
552 | return ret; |
553 | } | |
1da177e4 LT |
554 | EXPORT_SYMBOL_GPL(ide_setup_pci_device); |
555 | ||
556 | int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2, | |
85620436 | 557 | const struct ide_port_info *d) |
1da177e4 LT |
558 | { |
559 | struct pci_dev *pdev[] = { dev1, dev2 }; | |
1da177e4 | 560 | int ret, i; |
8447d9d5 | 561 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
562 | |
563 | for (i = 0; i < 2; i++) { | |
8447d9d5 | 564 | ret = do_ide_setup_pci_device(pdev[i], d, &idx[i*2], !i); |
1da177e4 LT |
565 | /* |
566 | * FIXME: Mom, mom, they stole me the helper function to undo | |
567 | * do_ide_setup_pci_device() on the first device! | |
568 | */ | |
569 | if (ret < 0) | |
570 | goto out; | |
571 | } | |
572 | ||
c413b9b9 | 573 | ide_device_add(idx, d); |
1da177e4 LT |
574 | out: |
575 | return ret; | |
576 | } | |
1da177e4 | 577 | EXPORT_SYMBOL_GPL(ide_setup_pci_devices); |