Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
59bca8cc BZ |
2 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
3 | * Copyright (C) 1995-1998 Mark Lord | |
4 | * Copyright (C) 2007 Bartlomiej Zolnierkiewicz | |
58f189fc | 5 | * |
1da177e4 | 6 | * May be copied or modified under the terms of the GNU General Public License |
1da177e4 LT |
7 | */ |
8 | ||
1da177e4 LT |
9 | #include <linux/types.h> |
10 | #include <linux/kernel.h> | |
11 | #include <linux/pci.h> | |
12 | #include <linux/init.h> | |
1da177e4 LT |
13 | #include <linux/interrupt.h> |
14 | #include <linux/ide.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | ||
17 | #include <asm/io.h> | |
1da177e4 | 18 | |
1da177e4 LT |
19 | /** |
20 | * ide_setup_pci_baseregs - place a PCI IDE controller native | |
21 | * @dev: PCI device of interface to switch native | |
22 | * @name: Name of interface | |
23 | * | |
24 | * We attempt to place the PCI interface into PCI native mode. If | |
25 | * we succeed the BARs are ok and the controller is in PCI mode. | |
846bb88a | 26 | * Returns 0 on success or an errno code. |
1da177e4 LT |
27 | * |
28 | * FIXME: if we program the interface and then fail to set the BARS | |
29 | * we don't switch it back to legacy mode. Do we actually care ?? | |
30 | */ | |
846bb88a PC |
31 | |
32 | static int ide_setup_pci_baseregs(struct pci_dev *dev, const char *name) | |
1da177e4 LT |
33 | { |
34 | u8 progif = 0; | |
35 | ||
36 | /* | |
37 | * Place both IDE interfaces into PCI "native" mode: | |
38 | */ | |
39 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
40 | (progif & 5) != 5) { | |
41 | if ((progif & 0xa) != 0xa) { | |
42 | printk(KERN_INFO "%s: device not capable of full " | |
43 | "native PCI mode\n", name); | |
44 | return -EOPNOTSUPP; | |
45 | } | |
46 | printk("%s: placing both ports into native PCI mode\n", name); | |
47 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); | |
48 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
49 | (progif & 5) != 5) { | |
50 | printk(KERN_ERR "%s: rewrite of PROGIF failed, wanted " | |
51 | "0x%04x, got 0x%04x\n", | |
52 | name, progif|5, progif); | |
53 | return -EOPNOTSUPP; | |
54 | } | |
55 | } | |
56 | return 0; | |
57 | } | |
58 | ||
59 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI | |
8ac2b42a BZ |
60 | static void ide_pci_clear_simplex(unsigned long dma_base, const char *name) |
61 | { | |
62 | u8 dma_stat = inb(dma_base + 2); | |
63 | ||
64 | outb(dma_stat & 0x60, dma_base + 2); | |
65 | dma_stat = inb(dma_base + 2); | |
66 | if (dma_stat & 0x80) | |
67 | printk(KERN_INFO "%s: simplex device: DMA forced\n", name); | |
68 | } | |
69 | ||
1da177e4 | 70 | /** |
b123f56e | 71 | * ide_pci_dma_base - setup BMIBA |
039788e1 | 72 | * @hwif: IDE interface |
b123f56e | 73 | * @d: IDE port info |
1da177e4 | 74 | * |
c58e79dd BZ |
75 | * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space. |
76 | * Where a device has a partner that is already in DMA mode we check | |
77 | * and enforce IDE simplex rules. | |
1da177e4 LT |
78 | */ |
79 | ||
b123f56e | 80 | unsigned long ide_pci_dma_base(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 81 | { |
36501650 BZ |
82 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
83 | unsigned long dma_base = 0; | |
8ac2b42a | 84 | u8 dma_stat = 0; |
1da177e4 | 85 | |
13572144 | 86 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
1da177e4 LT |
87 | return hwif->dma_base; |
88 | ||
89 | if (hwif->mate && hwif->mate->dma_base) { | |
90 | dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8); | |
91 | } else { | |
9ffcf364 BZ |
92 | u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4; |
93 | ||
94 | dma_base = pci_resource_start(dev, baridx); | |
95 | ||
aea5d375 | 96 | if (dma_base == 0) { |
9ffcf364 | 97 | printk(KERN_ERR "%s: DMA base is invalid\n", d->name); |
aea5d375 BZ |
98 | return 0; |
99 | } | |
1da177e4 LT |
100 | } |
101 | ||
aea5d375 BZ |
102 | if (hwif->channel) |
103 | dma_base += 8; | |
104 | ||
8ac2b42a BZ |
105 | if (d->host_flags & IDE_HFLAG_CS5520) |
106 | goto out; | |
107 | ||
108 | if (d->host_flags & IDE_HFLAG_CLEAR_SIMPLEX) { | |
109 | ide_pci_clear_simplex(dma_base, d->name); | |
110 | goto out; | |
111 | } | |
112 | ||
113 | /* | |
114 | * If the device claims "simplex" DMA, this means that only one of | |
115 | * the two interfaces can be trusted with DMA at any point in time | |
116 | * (so we should enable DMA only on one of the two interfaces). | |
117 | * | |
118 | * FIXME: At this point we haven't probed the drives so we can't make | |
119 | * the appropriate decision. Really we should defer this problem until | |
120 | * we tune the drive then try to grab DMA ownership if we want to be | |
121 | * the DMA end. This has to be become dynamic to handle hot-plug. | |
122 | */ | |
123 | dma_stat = hwif->INB(dma_base + 2); | |
124 | if ((dma_stat & 0x80) && hwif->mate && hwif->mate->dma_base) { | |
125 | printk(KERN_INFO "%s: simplex device: DMA disabled\n", d->name); | |
126 | dma_base = 0; | |
1da177e4 | 127 | } |
8ac2b42a | 128 | out: |
1da177e4 LT |
129 | return dma_base; |
130 | } | |
b123f56e | 131 | EXPORT_SYMBOL_GPL(ide_pci_dma_base); |
d54452fb BZ |
132 | |
133 | /* | |
134 | * Set up BM-DMA capability (PnP BIOS should have done this) | |
135 | */ | |
b123f56e | 136 | int ide_pci_set_master(struct pci_dev *dev, const char *name) |
d54452fb BZ |
137 | { |
138 | u16 pcicmd; | |
139 | ||
140 | pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
141 | ||
142 | if ((pcicmd & PCI_COMMAND_MASTER) == 0) { | |
143 | pci_set_master(dev); | |
144 | ||
145 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || | |
146 | (pcicmd & PCI_COMMAND_MASTER) == 0) { | |
147 | printk(KERN_ERR "%s: error updating PCICMD on %s\n", | |
148 | name, pci_name(dev)); | |
149 | return -EIO; | |
150 | } | |
151 | } | |
152 | ||
153 | return 0; | |
154 | } | |
b123f56e | 155 | EXPORT_SYMBOL_GPL(ide_pci_set_master); |
1da177e4 LT |
156 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
157 | ||
85620436 | 158 | void ide_setup_pci_noise(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 159 | { |
bde07e5e BZ |
160 | printk(KERN_INFO "%s: IDE controller (0x%04x:0x%04x rev 0x%02x) at " |
161 | " PCI slot %s\n", d->name, dev->vendor, dev->device, | |
162 | dev->revision, pci_name(dev)); | |
1da177e4 | 163 | } |
1da177e4 LT |
164 | EXPORT_SYMBOL_GPL(ide_setup_pci_noise); |
165 | ||
166 | ||
167 | /** | |
168 | * ide_pci_enable - do PCI enables | |
169 | * @dev: PCI device | |
039788e1 | 170 | * @d: IDE port info |
1da177e4 LT |
171 | * |
172 | * Enable the IDE PCI device. We attempt to enable the device in full | |
09483916 BH |
173 | * but if that fails then we only need IO space. The PCI code should |
174 | * have setup the proper resources for us already for controllers in | |
175 | * legacy mode. | |
846bb88a | 176 | * |
1da177e4 LT |
177 | * Returns zero on success or an error code |
178 | */ | |
039788e1 | 179 | |
85620436 | 180 | static int ide_pci_enable(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 181 | { |
0d1bad21 | 182 | int ret, bars; |
1da177e4 LT |
183 | |
184 | if (pci_enable_device(dev)) { | |
09483916 | 185 | ret = pci_enable_device_io(dev); |
1da177e4 LT |
186 | if (ret < 0) { |
187 | printk(KERN_WARNING "%s: (ide_setup_pci_device:) " | |
188 | "Could not enable device.\n", d->name); | |
189 | goto out; | |
190 | } | |
191 | printk(KERN_WARNING "%s: BIOS configuration fixed.\n", d->name); | |
192 | } | |
193 | ||
194 | /* | |
039788e1 BZ |
195 | * assume all devices can do 32-bit DMA for now, we can add |
196 | * a DMA mask field to the struct ide_port_info if we need it | |
197 | * (or let lower level driver set the DMA mask) | |
1da177e4 LT |
198 | */ |
199 | ret = pci_set_dma_mask(dev, DMA_32BIT_MASK); | |
200 | if (ret < 0) { | |
201 | printk(KERN_ERR "%s: can't set dma mask\n", d->name); | |
202 | goto out; | |
203 | } | |
204 | ||
0d1bad21 BZ |
205 | if (d->host_flags & IDE_HFLAG_SINGLE) |
206 | bars = (1 << 2) - 1; | |
207 | else | |
208 | bars = (1 << 4) - 1; | |
1da177e4 | 209 | |
0d1bad21 BZ |
210 | if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) { |
211 | if (d->host_flags & IDE_HFLAG_CS5520) | |
212 | bars |= (1 << 2); | |
213 | else | |
214 | bars |= (1 << 4); | |
215 | } | |
216 | ||
217 | ret = pci_request_selected_regions(dev, bars, d->name); | |
218 | if (ret < 0) | |
219 | printk(KERN_ERR "%s: can't reserve resources\n", d->name); | |
1da177e4 LT |
220 | out: |
221 | return ret; | |
222 | } | |
223 | ||
224 | /** | |
225 | * ide_pci_configure - configure an unconfigured device | |
226 | * @dev: PCI device | |
039788e1 | 227 | * @d: IDE port info |
1da177e4 LT |
228 | * |
229 | * Enable and configure the PCI device we have been passed. | |
230 | * Returns zero on success or an error code. | |
231 | */ | |
039788e1 | 232 | |
85620436 | 233 | static int ide_pci_configure(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 LT |
234 | { |
235 | u16 pcicmd = 0; | |
236 | /* | |
237 | * PnP BIOS was *supposed* to have setup this device, but we | |
238 | * can do it ourselves, so long as the BIOS has assigned an IRQ | |
239 | * (or possibly the device is using a "legacy header" for IRQs). | |
240 | * Maybe the user deliberately *disabled* the device, | |
241 | * but we'll eventually ignore it again if no drives respond. | |
242 | */ | |
846bb88a PC |
243 | if (ide_setup_pci_baseregs(dev, d->name) || |
244 | pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) { | |
1da177e4 LT |
245 | printk(KERN_INFO "%s: device disabled (BIOS)\n", d->name); |
246 | return -ENODEV; | |
247 | } | |
248 | if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { | |
249 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
250 | return -EIO; | |
251 | } | |
252 | if (!(pcicmd & PCI_COMMAND_IO)) { | |
253 | printk(KERN_ERR "%s: unable to enable IDE controller\n", d->name); | |
254 | return -ENXIO; | |
255 | } | |
256 | return 0; | |
257 | } | |
258 | ||
259 | /** | |
260 | * ide_pci_check_iomem - check a register is I/O | |
039788e1 BZ |
261 | * @dev: PCI device |
262 | * @d: IDE port info | |
263 | * @bar: BAR number | |
1da177e4 | 264 | * |
1baccff8 SS |
265 | * Checks if a BAR is configured and points to MMIO space. If so, |
266 | * return an error code. Otherwise return 0 | |
1da177e4 | 267 | */ |
039788e1 | 268 | |
1baccff8 SS |
269 | static int ide_pci_check_iomem(struct pci_dev *dev, const struct ide_port_info *d, |
270 | int bar) | |
1da177e4 LT |
271 | { |
272 | ulong flags = pci_resource_flags(dev, bar); | |
846bb88a | 273 | |
1da177e4 LT |
274 | /* Unconfigured ? */ |
275 | if (!flags || pci_resource_len(dev, bar) == 0) | |
276 | return 0; | |
277 | ||
1baccff8 SS |
278 | /* I/O space */ |
279 | if (flags & IORESOURCE_IO) | |
1da177e4 | 280 | return 0; |
846bb88a | 281 | |
1da177e4 | 282 | /* Bad */ |
1da177e4 LT |
283 | return -EINVAL; |
284 | } | |
285 | ||
286 | /** | |
287 | * ide_hwif_configure - configure an IDE interface | |
288 | * @dev: PCI device holding interface | |
039788e1 | 289 | * @d: IDE port info |
1ebf7493 BZ |
290 | * @port: port number |
291 | * @irq: PCI IRQ | |
c97c6aca | 292 | * @hw: hw_regs_t instance corresponding to this port |
1da177e4 LT |
293 | * |
294 | * Perform the initial set up for the hardware interface structure. This | |
295 | * is done per interface port rather than per PCI device. There may be | |
296 | * more than one port per device. | |
297 | * | |
298 | * Returns the new hardware interface structure, or NULL on a failure | |
299 | */ | |
039788e1 | 300 | |
1ebf7493 BZ |
301 | static ide_hwif_t *ide_hwif_configure(struct pci_dev *dev, |
302 | const struct ide_port_info *d, | |
c97c6aca BZ |
303 | unsigned int port, int irq, |
304 | hw_regs_t *hw) | |
1da177e4 LT |
305 | { |
306 | unsigned long ctl = 0, base = 0; | |
307 | ide_hwif_t *hwif; | |
308 | ||
a5d8c5c8 | 309 | if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) { |
1baccff8 SS |
310 | if (ide_pci_check_iomem(dev, d, 2 * port) || |
311 | ide_pci_check_iomem(dev, d, 2 * port + 1)) { | |
312 | printk(KERN_ERR "%s: I/O baseregs (BIOS) are reported " | |
313 | "as MEM for port %d!\n", d->name, port); | |
314 | return NULL; | |
315 | } | |
846bb88a | 316 | |
1da177e4 LT |
317 | ctl = pci_resource_start(dev, 2*port+1); |
318 | base = pci_resource_start(dev, 2*port); | |
c1da678b | 319 | } else { |
1da177e4 LT |
320 | /* Use default values */ |
321 | ctl = port ? 0x374 : 0x3f4; | |
322 | base = port ? 0x170 : 0x1f0; | |
323 | } | |
bad7c825 | 324 | |
c1da678b BZ |
325 | if (!base || !ctl) { |
326 | printk(KERN_ERR "%s: bad PCI BARs for port %d, skipping\n", | |
327 | d->name, port); | |
328 | return NULL; | |
329 | } | |
330 | ||
c97c6aca BZ |
331 | memset(hw, 0, sizeof(*hw)); |
332 | hw->irq = irq; | |
333 | hw->dev = &dev->dev; | |
334 | hw->chipset = d->chipset ? d->chipset : ide_pci; | |
335 | ide_std_init_ports(hw, base, ctl | 2); | |
336 | ||
fe80b937 | 337 | hwif = ide_find_port_slot(d); |
eb3aff55 | 338 | if (hwif == NULL) |
bad7c825 | 339 | return NULL; |
79127c37 | 340 | |
c97c6aca | 341 | hwif->chipset = hw->chipset; |
79127c37 | 342 | |
1da177e4 LT |
343 | return hwif; |
344 | } | |
345 | ||
c413b9b9 | 346 | #ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
1da177e4 LT |
347 | /** |
348 | * ide_hwif_setup_dma - configure DMA interface | |
039788e1 | 349 | * @hwif: IDE interface |
c413b9b9 | 350 | * @d: IDE port info |
1da177e4 LT |
351 | * |
352 | * Set up the DMA base for the interface. Enable the master bits as | |
353 | * necessary and attempt to bring the device DMA into a ready to use | |
354 | * state | |
355 | */ | |
039788e1 | 356 | |
b123f56e | 357 | int ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d) |
1da177e4 | 358 | { |
c413b9b9 | 359 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
1da177e4 | 360 | |
47b68788 | 361 | if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 || |
1da177e4 LT |
362 | ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && |
363 | (dev->class & 0x80))) { | |
b123f56e | 364 | unsigned long base = ide_pci_dma_base(hwif, d); |
d54452fb | 365 | |
63158d5c | 366 | if (base == 0 || ide_pci_set_master(dev, d->name) < 0) |
b123f56e | 367 | return -1; |
d54452fb | 368 | |
13572144 | 369 | if (hwif->host_flags & IDE_HFLAG_MMIO) |
63158d5c BZ |
370 | printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name); |
371 | else | |
372 | printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n", | |
373 | hwif->name, base, base + 7); | |
374 | ||
375 | hwif->extra_base = base + (hwif->channel ? 8 : 16); | |
376 | ||
b123f56e BZ |
377 | if (ide_allocate_dma_engine(hwif)) |
378 | return -1; | |
d54452fb | 379 | |
f37afdac | 380 | ide_setup_dma(hwif, base); |
b123f56e | 381 | } |
d54452fb | 382 | |
b123f56e | 383 | return 0; |
039788e1 | 384 | } |
c413b9b9 | 385 | #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */ |
1da177e4 LT |
386 | |
387 | /** | |
388 | * ide_setup_pci_controller - set up IDE PCI | |
389 | * @dev: PCI device | |
039788e1 | 390 | * @d: IDE port info |
1da177e4 LT |
391 | * @noisy: verbose flag |
392 | * @config: returned as 1 if we configured the hardware | |
393 | * | |
394 | * Set up the PCI and controller side of the IDE interface. This brings | |
395 | * up the PCI side of the device, checks that the device is enabled | |
396 | * and enables it if need be | |
397 | */ | |
039788e1 | 398 | |
85620436 | 399 | static int ide_setup_pci_controller(struct pci_dev *dev, const struct ide_port_info *d, int noisy, int *config) |
1da177e4 LT |
400 | { |
401 | int ret; | |
1da177e4 LT |
402 | u16 pcicmd; |
403 | ||
404 | if (noisy) | |
405 | ide_setup_pci_noise(dev, d); | |
406 | ||
407 | ret = ide_pci_enable(dev, d); | |
408 | if (ret < 0) | |
409 | goto out; | |
410 | ||
411 | ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd); | |
412 | if (ret < 0) { | |
413 | printk(KERN_ERR "%s: error accessing PCI regs\n", d->name); | |
414 | goto out; | |
415 | } | |
416 | if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ | |
417 | ret = ide_pci_configure(dev, d); | |
418 | if (ret < 0) | |
419 | goto out; | |
420 | *config = 1; | |
421 | printk(KERN_INFO "%s: device enabled (Linux)\n", d->name); | |
422 | } | |
423 | ||
1da177e4 LT |
424 | out: |
425 | return ret; | |
426 | } | |
427 | ||
428 | /** | |
429 | * ide_pci_setup_ports - configure ports/devices on PCI IDE | |
430 | * @dev: PCI device | |
039788e1 | 431 | * @d: IDE port info |
1da177e4 | 432 | * @pciirq: IRQ line |
8447d9d5 | 433 | * @idx: ATA index table to update |
c97c6aca BZ |
434 | * @hw: hw_regs_t instances corresponding to this PCI IDE device |
435 | * @hws: hw_regs_t pointers table to update | |
1da177e4 LT |
436 | * |
437 | * Scan the interfaces attached to this device and do any | |
438 | * necessary per port setup. Attach the devices and ask the | |
439 | * generic DMA layer to do its work for us. | |
440 | * | |
441 | * Normally called automaticall from do_ide_pci_setup_device, | |
442 | * but is also used directly as a helper function by some controllers | |
443 | * where the chipset setup is not the default PCI IDE one. | |
444 | */ | |
8447d9d5 | 445 | |
c97c6aca BZ |
446 | void ide_pci_setup_ports(struct pci_dev *dev, const struct ide_port_info *d, |
447 | int pciirq, u8 *idx, hw_regs_t *hw, hw_regs_t **hws) | |
1da177e4 | 448 | { |
a5d8c5c8 | 449 | int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port; |
c413b9b9 | 450 | ide_hwif_t *hwif; |
1da177e4 LT |
451 | u8 tmp; |
452 | ||
1da177e4 LT |
453 | /* |
454 | * Set up the IDE ports | |
455 | */ | |
cf6e854e | 456 | |
a5d8c5c8 | 457 | for (port = 0; port < channels; ++port) { |
85620436 BZ |
458 | const ide_pci_enablebit_t *e = &(d->enablebits[port]); |
459 | ||
1da177e4 | 460 | if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || |
cf6e854e BZ |
461 | (tmp & e->mask) != e->val)) { |
462 | printk(KERN_INFO "%s: IDE port disabled\n", d->name); | |
1da177e4 | 463 | continue; /* port not enabled */ |
cf6e854e | 464 | } |
1da177e4 | 465 | |
c97c6aca | 466 | hwif = ide_hwif_configure(dev, d, port, pciirq, hw + port); |
1ebf7493 | 467 | if (hwif == NULL) |
1da177e4 LT |
468 | continue; |
469 | ||
c97c6aca | 470 | *(hws + port) = hw + port; |
8447d9d5 | 471 | *(idx + port) = hwif->index; |
1ebf7493 | 472 | } |
1da177e4 | 473 | } |
1da177e4 LT |
474 | EXPORT_SYMBOL_GPL(ide_pci_setup_ports); |
475 | ||
476 | /* | |
477 | * ide_setup_pci_device() looks at the primary/secondary interfaces | |
478 | * on a PCI IDE device and, if they are enabled, prepares the IDE driver | |
479 | * for use with them. This generic code works for most PCI chipsets. | |
480 | * | |
481 | * One thing that is not standardized is the location of the | |
482 | * primary/secondary interface "enable/disable" bits. For chipsets that | |
039788e1 | 483 | * we "know" about, this information is in the struct ide_port_info; |
1da177e4 LT |
484 | * for all other chipsets, we just assume both interfaces are enabled. |
485 | */ | |
039788e1 | 486 | static int do_ide_setup_pci_device(struct pci_dev *dev, |
85620436 | 487 | const struct ide_port_info *d, |
51d87ed0 | 488 | u8 noisy) |
1da177e4 | 489 | { |
1da177e4 LT |
490 | int tried_config = 0; |
491 | int pciirq, ret; | |
492 | ||
493 | ret = ide_setup_pci_controller(dev, d, noisy, &tried_config); | |
494 | if (ret < 0) | |
495 | goto out; | |
496 | ||
497 | /* | |
498 | * Can we trust the reported IRQ? | |
499 | */ | |
500 | pciirq = dev->irq; | |
501 | ||
502 | /* Is it an "IDE storage" device in non-PCI mode? */ | |
503 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) { | |
504 | if (noisy) | |
505 | printk(KERN_INFO "%s: not 100%% native mode: " | |
506 | "will probe irqs later\n", d->name); | |
507 | /* | |
508 | * This allows offboard ide-pci cards the enable a BIOS, | |
509 | * verify interrupt settings of split-mirror pci-config | |
510 | * space, place chipset into init-mode, and/or preserve | |
511 | * an interrupt if the card is not native ide support. | |
512 | */ | |
513 | ret = d->init_chipset ? d->init_chipset(dev, d->name) : 0; | |
514 | if (ret < 0) | |
515 | goto out; | |
516 | pciirq = ret; | |
517 | } else if (tried_config) { | |
518 | if (noisy) | |
519 | printk(KERN_INFO "%s: will probe irqs later\n", d->name); | |
520 | pciirq = 0; | |
521 | } else if (!pciirq) { | |
522 | if (noisy) | |
523 | printk(KERN_WARNING "%s: bad irq (%d): will probe later\n", | |
524 | d->name, pciirq); | |
525 | pciirq = 0; | |
526 | } else { | |
527 | if (d->init_chipset) { | |
528 | ret = d->init_chipset(dev, d->name); | |
529 | if (ret < 0) | |
530 | goto out; | |
531 | } | |
532 | if (noisy) | |
1da177e4 LT |
533 | printk(KERN_INFO "%s: 100%% native mode on irq %d\n", |
534 | d->name, pciirq); | |
1da177e4 LT |
535 | } |
536 | ||
51d87ed0 | 537 | ret = pciirq; |
1da177e4 LT |
538 | out: |
539 | return ret; | |
540 | } | |
541 | ||
85620436 | 542 | int ide_setup_pci_device(struct pci_dev *dev, const struct ide_port_info *d) |
1da177e4 | 543 | { |
8447d9d5 | 544 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
c97c6aca | 545 | hw_regs_t hw[4], *hws[] = { NULL, NULL, NULL, NULL }; |
1da177e4 LT |
546 | int ret; |
547 | ||
51d87ed0 BZ |
548 | ret = do_ide_setup_pci_device(dev, d, 1); |
549 | ||
550 | if (ret >= 0) { | |
551 | /* FIXME: silent failure can happen */ | |
c97c6aca | 552 | ide_pci_setup_ports(dev, d, ret, &idx[0], &hw[0], &hws[0]); |
1da177e4 | 553 | |
c97c6aca | 554 | ide_device_add(idx, d, hws); |
51d87ed0 | 555 | } |
1da177e4 | 556 | |
1da177e4 LT |
557 | return ret; |
558 | } | |
1da177e4 LT |
559 | EXPORT_SYMBOL_GPL(ide_setup_pci_device); |
560 | ||
561 | int ide_setup_pci_devices(struct pci_dev *dev1, struct pci_dev *dev2, | |
85620436 | 562 | const struct ide_port_info *d) |
1da177e4 LT |
563 | { |
564 | struct pci_dev *pdev[] = { dev1, dev2 }; | |
1da177e4 | 565 | int ret, i; |
c97c6aca | 566 | hw_regs_t hw[4], *hws[] = { NULL, NULL, NULL, NULL }; |
8447d9d5 | 567 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
1da177e4 LT |
568 | |
569 | for (i = 0; i < 2; i++) { | |
51d87ed0 BZ |
570 | ret = do_ide_setup_pci_device(pdev[i], d, !i); |
571 | ||
1da177e4 LT |
572 | /* |
573 | * FIXME: Mom, mom, they stole me the helper function to undo | |
574 | * do_ide_setup_pci_device() on the first device! | |
575 | */ | |
576 | if (ret < 0) | |
577 | goto out; | |
51d87ed0 BZ |
578 | |
579 | /* FIXME: silent failure can happen */ | |
c97c6aca BZ |
580 | ide_pci_setup_ports(pdev[i], d, ret, &idx[i*2], &hw[i*2], |
581 | &hws[i*2]); | |
1da177e4 LT |
582 | } |
583 | ||
c97c6aca | 584 | ide_device_add(idx, d, hws); |
1da177e4 LT |
585 | out: |
586 | return ret; | |
587 | } | |
1da177e4 | 588 | EXPORT_SYMBOL_GPL(ide_setup_pci_devices); |