[linux-block.git] / drivers / ide / serverworks.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 1998-2000 Michel Aubry
 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
 * Portions copyright (c) 2001 Sun Microsystems
 *
 *
 * RCC/ServerWorks IDE driver for Linux
 *
 *   OSB4: `Open South Bridge' IDE Interface (fn 1)
 *         supports UDMA mode 2 (33 MB/s)
 *
 *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
 *         all revisions support UDMA mode 4 (66 MB/s)
 *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
 *
 *         *** The CSB5 does not provide ANY register ***
 *         *** to detect 80-conductor cable presence. ***
 *
 *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
 *
 *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
 *   controller same as the CSB6. Single channel ATA100 only.
 *
 * Documentation:
 *	Available under NDA only. Errata info very hard to get.
 *
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "serverworks"

#define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
#define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */

/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
 * can overrun their FIFOs when used with the CSB5 */
static const char *svwks_bad_ata100[] = {
	"ST320011A",
	"ST340016A",
	"ST360021A",
	"ST380021A",
	NULL
};

static int check_in_drive_lists (ide_drive_t *drive, const char **list)
{
	char *m = (char *)&drive->id[ATA_ID_PROD];

	while (*list)
		if (!strcmp(*list++, m))
			return 1;
	return 0;
}

static u8 svwks_udma_filter(ide_drive_t *drive)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);

	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
		return 0x1f;
	} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
		return 0x07;
	} else {
		u8 btr = 0, mode, mask;

		pci_read_config_byte(dev, 0x5A, &btr);
		mode = btr & 0x3;

		/* If someone decides to do UDMA133 on CSB5 the same
		   issue will bite so be inclusive */
		if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
			mode = 2;

		switch(mode) {
		case 3:	 mask = 0x3f; break;
		case 2:	 mask = 0x1f; break;
		case 1:	 mask = 0x07; break;
		default: mask = 0x00; break;
		}

		return mask;
	}
}

static u8 svwks_csb_check (struct pci_dev *dev)
{
	switch (dev->device) {
		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
			return 1;
		default:
			break;
	}
	return 0;
}

static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };

	struct pci_dev *dev = to_pci_dev(hwif->dev);
	const u8 pio = drive->pio_mode - XFER_PIO_0;

	pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);

	if (svwks_csb_check(dev)) {
		u16 csb_pio = 0;

		pci_read_config_word(dev, 0x4a, &csb_pio);

		csb_pio &= ~(0x0f << (4 * drive->dn));
		csb_pio |= (pio << (4 * drive->dn));

		pci_write_config_word(dev, 0x4a, csb_pio);
	}
}

static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	static const u8 udma_modes[]		= { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
	static const u8 dma_modes[]		= { 0x77, 0x21, 0x20 };
	static const u8 drive_pci2[]		= { 0x45, 0x44, 0x47, 0x46 };

	struct pci_dev *dev	= to_pci_dev(hwif->dev);
	const u8 speed		= drive->dma_mode;
	u8 unit			= drive->dn & 1;

	u8 ultra_enable	 = 0, ultra_timing = 0, dma_timing = 0;

	pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
	pci_read_config_byte(dev, 0x54, &ultra_enable);

	ultra_timing	&= ~(0x0F << (4*unit));
	ultra_enable	&= ~(0x01 << drive->dn);

	if (speed >= XFER_UDMA_0) {
		dma_timing   |= dma_modes[2];
		ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
		ultra_enable |= (0x01 << drive->dn);
	} else if (speed >= XFER_MW_DMA_0)
		dma_timing   |= dma_modes[speed - XFER_MW_DMA_0];

	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
	pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
	pci_write_config_byte(dev, 0x54, ultra_enable);
}

static int init_chipset_svwks(struct pci_dev *dev)
{
	unsigned int reg;
	u8 btr;

	/* force Master Latency Timer value to 64 PCICLKs */
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);

	/* OSB4 : South Bridge and IDE */
	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
		struct pci_dev *isa_dev =
			pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
					PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
		if (isa_dev) {
			pci_read_config_dword(isa_dev, 0x64, &reg);
			reg &= ~0x00002000; /* disable 600ns interrupt mask */
			if(!(reg & 0x00004000))
				printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
					"enabled.\n", pci_name(dev));
			reg |=  0x00004000; /* enable UDMA/33 support */
			pci_write_config_dword(isa_dev, 0x64, reg);
			pci_dev_put(isa_dev);
		}
	}

	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {

		/* Third Channel Test */
		if (!(PCI_FUNC(dev->devfn) & 1)) {
			struct pci_dev * findev = NULL;
			u32 reg4c = 0;
			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
				PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
			if (findev) {
				pci_read_config_dword(findev, 0x4C, &reg4c);
				reg4c &= ~0x000007FF;
				reg4c |=  0x00000040;
				reg4c |=  0x00000020;
				pci_write_config_dword(findev, 0x4C, reg4c);
				pci_dev_put(findev);
			}
			outb_p(0x06, 0x0c00);
			dev->irq = inb_p(0x0c01);
		} else {
			struct pci_dev * findev = NULL;
			u8 reg41 = 0;

			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
					PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
			if (findev) {
				pci_read_config_byte(findev, 0x41, &reg41);
				reg41 &= ~0x40;
				pci_write_config_byte(findev, 0x41, reg41);
				pci_dev_put(findev);
			}
			/*
			 * This is a device pin issue on CSB6.
			 * Since there will be a future raid mode,
			 * early versions of the chipset require the
			 * interrupt pin to be set, and it is a compatibility
			 * mode issue.
			 */
			if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
				dev->irq = 0;
		}
//		pci_read_config_dword(dev, 0x40, &pioreg)
//		pci_write_config_dword(dev, 0x40, 0x99999999);
//		pci_read_config_dword(dev, 0x44, &dmareg);
//		pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
		/* setup the UDMA Control register
		 *
		 * 1. clear bit 6 to enable DMA
		 * 2. enable DMA modes with bits 0-1
		 * 	00 : legacy
		 * 	01 : udma2
		 * 	10 : udma2/udma4
		 * 	11 : udma2/udma4/udma5
		 */
		pci_read_config_byte(dev, 0x5A, &btr);
		btr &= ~0x40;
		if (!(PCI_FUNC(dev->devfn) & 1))
			btr |= 0x2;
		else
			btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
		pci_write_config_byte(dev, 0x5A, btr);
	}
	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
		pci_read_config_byte(dev, 0x5A, &btr);
		btr &= ~0x40;
		btr |= 0x3;
		pci_write_config_byte(dev, 0x5A, btr);
	}

	return 0;
}

static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
{
	return ATA_CBL_PATA80;
}

/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 * of the subsystem device ID indicate presence of an 80-pin cable.
 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 * Bit 15 set   = secondary IDE channel has 80-pin cable.
 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 * Bit 14 set   = primary IDE channel has 80-pin cable.
 */
static u8 ata66_svwks_dell(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
	     dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
		return ((1 << (hwif->channel + 14)) &
			dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	return ATA_CBL_PATA40;
}

/* Sun Cobalt Alpine hardware avoids the 80-pin cable
 * detect issue by attaching the drives directly to the board.
 * This check follows the Dell precedent (how scary is that?!)
 *
 * WARNING: this only works on Alpine hardware!
 */
static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
	    dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
		return ((1 << (hwif->channel + 14)) &
			dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
	return ATA_CBL_PATA40;
}

static u8 svwks_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	/* Server Works */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
		return ata66_svwks_svwks (hwif);
	
	/* Dell PowerEdge */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
		return ata66_svwks_dell (hwif);

	/* Cobalt Alpine */
	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
		return ata66_svwks_cobalt (hwif);

	/* Per Specified Design by OEM, and ASIC Architect */
	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
		return ATA_CBL_PATA80;

	return ATA_CBL_PATA40;
}

static const struct ide_port_ops osb4_port_ops = {
	.set_pio_mode		= svwks_set_pio_mode,
	.set_dma_mode		= svwks_set_dma_mode,
};

static const struct ide_port_ops svwks_port_ops = {
	.set_pio_mode		= svwks_set_pio_mode,
	.set_dma_mode		= svwks_set_dma_mode,
	.udma_filter		= svwks_udma_filter,
	.cable_detect		= svwks_cable_detect,
};

static const struct ide_port_info serverworks_chipsets[] = {
	{	/* 0: OSB4 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &osb4_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= 0x00, /* UDMA is problematic on OSB4 */
	},
	{	/* 1: CSB5 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 2: CSB6 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 3: CSB6-2 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.host_flags	= IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 4: HT1000 */
		.name		= DRV_NAME,
		.init_chipset	= init_chipset_svwks,
		.port_ops	= &svwks_port_ops,
		.host_flags	= IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	}
};

/**
 *	svwks_init_one	-	called when a OSB/CSB is found
 *	@dev: the svwks device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */
 
static int svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d;
	u8 idx = id->driver_data;

	d = serverworks_chipsets[idx];

	if (idx == 1)
		d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
	else if (idx == 2 || idx == 3) {
		if ((PCI_FUNC(dev->devfn) & 1) == 0) {
			if (pci_resource_start(dev, 0) != 0x01f1)
				d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
			d.host_flags |= IDE_HFLAG_SINGLE;
		} else
			d.host_flags &= ~IDE_HFLAG_SINGLE;
	}

	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id svwks_pci_tbl[] = {
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE),   1 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE),   2 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2),  3 },
	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);

static struct pci_driver svwks_pci_driver = {
	.name		= "Serverworks_IDE",
	.id_table	= svwks_pci_tbl,
	.probe		= svwks_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init svwks_ide_init(void)
{
	return ide_pci_register_driver(&svwks_pci_driver);
}

static void __exit svwks_ide_exit(void)
{
	pci_unregister_driver(&svwks_pci_driver);
}

module_init(svwks_ide_init);
module_exit(svwks_ide_exit);

MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4	2	/*
1da177e4 LT	3	* Copyright (C) 1998-2000 Michel Aubry
	4	* Copyright (C) 1998-2000 Andrzej Krzysztofowicz
	5	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
e7593af6	6	* Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
1da177e4 LT	7	* Portions copyright (c) 2001 Sun Microsystems
	8	*
	9	*
	10	* RCC/ServerWorks IDE driver for Linux
	11	*
	12	* OSB4: `Open South Bridge' IDE Interface (fn 1)
	13	* supports UDMA mode 2 (33 MB/s)
	14	*
	15	* CSB5: `Champion South Bridge' IDE Interface (fn 1)
	16	* all revisions support UDMA mode 4 (66 MB/s)
	17	* revision A2.0 and up support UDMA mode 5 (100 MB/s)
	18	*
	19	* * The CSB5 does not provide ANY register *
	20	* * to detect 80-conductor cable presence. *
	21	*
	22	* CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
	23	*
84f57fbc NS	24	* HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
	25	* controller same as the CSB6. Single channel ATA100 only.
	26	*
1da177e4 LT	27	* Documentation:
	28	* Available under NDA only. Errata info very hard to get.
	29	*
	30	*/
	31
1da177e4 LT	32	#include <linux/types.h>
	33	#include <linux/module.h>
	34	#include <linux/kernel.h>
1da177e4	35	#include <linux/pci.h>
1da177e4 LT	36	#include <linux/ide.h>
1da177e4 LT	37	#include <linux/init.h>
1da177e4 LT	38
	39	#include <asm/io.h>
	40
ced3ec8a BZ	41	#define DRV_NAME "serverworks"
ced3ec8a BZ	42
1da177e4 LT	43	#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
	44	#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
	45
	46	/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
	47	* can overrun their FIFOs when used with the CSB5 */
	48	static const char *svwks_bad_ata100[] = {
	49	"ST320011A",
	50	"ST340016A",
	51	"ST360021A",
	52	"ST380021A",
	53	NULL
	54	};
	55
1da177e4 LT	56	static int check_in_drive_lists (ide_drive_t drive, const char *list)
1da177e4 LT	57	{
4dde4492 BZ	58	char m = (char )&drive->id[ATA_ID_PROD];
4dde4492 BZ	59
1da177e4	60	while (*list)
4dde4492	61	if (!strcmp(*list++, m))
1da177e4 LT	62	return 1;
	63	return 0;
	64	}
	65
2d5eaa6d	66	static u8 svwks_udma_filter(ide_drive_t *drive)
1da177e4	67	{
36501650	68	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1da177e4	69
e7593af6	70	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
2d5eaa6d	71	return 0x1f;
44c10138	72	} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
2d5eaa6d	73	return 0x07;
e7593af6 BZ	74	} else {
	75	u8 btr = 0, mode, mask;
	76
1da177e4 LT	77	pci_read_config_byte(dev, 0x5A, &btr);
1da177e4 LT	78	mode = btr & 0x3;
2d5eaa6d	79
1da177e4 LT	80	/* If someone decides to do UDMA133 on CSB5 the same
	81	issue will bite so be inclusive */
	82	if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
	83	mode = 2;
2d5eaa6d BZ	84
2d5eaa6d BZ	85	switch(mode) {
0c824b51	86	case 3: mask = 0x3f; break;
2d5eaa6d BZ	87	case 2: mask = 0x1f; break;
	88	case 1: mask = 0x07; break;
	89	default: mask = 0x00; break;
	90	}
2d5eaa6d	91
e7593af6 BZ	92	return mask;
e7593af6 BZ	93	}
1da177e4 LT	94	}
	95
	96	static u8 svwks_csb_check (struct pci_dev *dev)
	97	{
	98	switch (dev->device) {
	99	case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
	100	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
	101	case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
84f57fbc	102	case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
1da177e4 LT	103	return 1;
	104	default:
	105	break;
	106	}
	107	return 0;
	108	}
1880a8d7	109
e085b3ca	110	static void svwks_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
1880a8d7 BZ	111	{
	112	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
	113	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
	114
e085b3ca BZ	115	struct pci_dev *dev = to_pci_dev(hwif->dev);
e085b3ca BZ	116	const u8 pio = drive->pio_mode - XFER_PIO_0;
1880a8d7 BZ	117
	118	pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
	119
	120	if (svwks_csb_check(dev)) {
	121	u16 csb_pio = 0;
	122
	123	pci_read_config_word(dev, 0x4a, &csb_pio);
	124
	125	csb_pio &= ~(0x0f << (4 * drive->dn));
	126	csb_pio \|= (pio << (4 * drive->dn));
	127
	128	pci_write_config_word(dev, 0x4a, csb_pio);
	129	}
	130	}
	131
8776168c	132	static void svwks_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
1da177e4	133	{
f201f504 AC	134	static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
f201f504 AC	135	static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
f201f504	136	static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
1da177e4	137
36501650	138	struct pci_dev *dev = to_pci_dev(hwif->dev);
8776168c	139	const u8 speed = drive->dma_mode;
123995b9	140	u8 unit = drive->dn & 1;
1880a8d7 BZ	141
	142	u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
	143
1da177e4	144	pci_read_config_byte(dev, (0x56\|hwif->channel), &ultra_timing);
1da177e4 LT	145	pci_read_config_byte(dev, 0x54, &ultra_enable);
1da177e4 LT	146
1da177e4 LT	147	ultra_timing &= ~(0x0F << (4*unit));
1da177e4 LT	148	ultra_enable &= ~(0x01 << drive->dn);
1da177e4	149
7b971df1 BZ	150	if (speed >= XFER_UDMA_0) {
	151	dma_timing \|= dma_modes[2];
	152	ultra_timing \|= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
	153	ultra_enable \|= (0x01 << drive->dn);
	154	} else if (speed >= XFER_MW_DMA_0)
	155	dma_timing \|= dma_modes[speed - XFER_MW_DMA_0];
1da177e4	156
1da177e4 LT	157	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
	158	pci_write_config_byte(dev, (0x56\|hwif->channel), ultra_timing);
	159	pci_write_config_byte(dev, 0x54, ultra_enable);
1da177e4 LT	160	}
1da177e4 LT	161
2ed0ef54	162	static int init_chipset_svwks(struct pci_dev *dev)
1da177e4 LT	163	{
	164	unsigned int reg;
	165	u8 btr;
	166
1da177e4 LT	167	/* force Master Latency Timer value to 64 PCICLKs */
	168	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
	169
	170	/* OSB4 : South Bridge and IDE */
	171	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
e7593af6 BZ	172	struct pci_dev *isa_dev =
	173	pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
	174	PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
1da177e4 LT	175	if (isa_dev) {
	176	pci_read_config_dword(isa_dev, 0x64, &reg);
	177	reg &= ~0x00002000; /* disable 600ns interrupt mask */
	178	if(!(reg & 0x00004000))
a326b02b BZ	179	printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
a326b02b BZ	180	"enabled.\n", pci_name(dev));
1da177e4 LT	181	reg \|= 0x00004000; /* enable UDMA/33 support */
1da177e4 LT	182	pci_write_config_dword(isa_dev, 0x64, reg);
cb06fc3f	183	pci_dev_put(isa_dev);
1da177e4 LT	184	}
	185	}
	186
	187	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
	188	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) \|\|
	189	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	190	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
	191
	192	/* Third Channel Test */
	193	if (!(PCI_FUNC(dev->devfn) & 1)) {
	194	struct pci_dev * findev = NULL;
	195	u32 reg4c = 0;
970a6136	196	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	197	PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
	198	if (findev) {
	199	pci_read_config_dword(findev, 0x4C, &reg4c);
	200	reg4c &= ~0x000007FF;
	201	reg4c \|= 0x00000040;
	202	reg4c \|= 0x00000020;
	203	pci_write_config_dword(findev, 0x4C, reg4c);
970a6136	204	pci_dev_put(findev);
1da177e4 LT	205	}
	206	outb_p(0x06, 0x0c00);
	207	dev->irq = inb_p(0x0c01);
1da177e4 LT	208	} else {
	209	struct pci_dev * findev = NULL;
	210	u8 reg41 = 0;
	211
970a6136	212	findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
1da177e4 LT	213	PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
	214	if (findev) {
	215	pci_read_config_byte(findev, 0x41, &reg41);
	216	reg41 &= ~0x40;
	217	pci_write_config_byte(findev, 0x41, reg41);
970a6136	218	pci_dev_put(findev);
1da177e4 LT	219	}
	220	/*
	221	* This is a device pin issue on CSB6.
	222	* Since there will be a future raid mode,
	223	* early versions of the chipset require the
	224	* interrupt pin to be set, and it is a compatibility
	225	* mode issue.
	226	*/
	227	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
	228	dev->irq = 0;
	229	}
	230	// pci_read_config_dword(dev, 0x40, &pioreg)
	231	// pci_write_config_dword(dev, 0x40, 0x99999999);
	232	// pci_read_config_dword(dev, 0x44, &dmareg);
	233	// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
	234	/* setup the UDMA Control register
	235	*
	236	* 1. clear bit 6 to enable DMA
	237	* 2. enable DMA modes with bits 0-1
	238	* 00 : legacy
	239	* 01 : udma2
	240	* 10 : udma2/udma4
	241	* 11 : udma2/udma4/udma5
	242	*/
	243	pci_read_config_byte(dev, 0x5A, &btr);
	244	btr &= ~0x40;
	245	if (!(PCI_FUNC(dev->devfn) & 1))
	246	btr \|= 0x2;
	247	else
44c10138	248	btr \|= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
1da177e4 LT	249	pci_write_config_byte(dev, 0x5A, btr);
1da177e4 LT	250	}
84f57fbc NS	251	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
	252	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
	253	pci_read_config_byte(dev, 0x5A, &btr);
	254	btr &= ~0x40;
	255	btr \|= 0x3;
	256	pci_write_config_byte(dev, 0x5A, btr);
	257	}
1da177e4	258
2ed0ef54	259	return 0;
1da177e4 LT	260	}
1da177e4 LT	261
f454cbe8	262	static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
1da177e4	263	{
49521f97	264	return ATA_CBL_PATA80;
1da177e4 LT	265	}
	266
	267	/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
	268	* of the subsystem device ID indicate presence of an 80-pin cable.
	269	* Bit 15 clear = secondary IDE channel does not have 80-pin cable.
	270	* Bit 15 set = secondary IDE channel has 80-pin cable.
	271	* Bit 14 clear = primary IDE channel does not have 80-pin cable.
	272	* Bit 14 set = primary IDE channel has 80-pin cable.
	273	*/
f454cbe8	274	static u8 ata66_svwks_dell(ide_hwif_t *hwif)
1da177e4	275	{
36501650 BZ	276	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	277
1da177e4 LT	278	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
	279	dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
	280	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE \|\|
	281	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
	282	return ((1 << (hwif->channel + 14)) &
49521f97 BZ	283	dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
49521f97 BZ	284	return ATA_CBL_PATA40;
1da177e4 LT	285	}
	286
	287	/* Sun Cobalt Alpine hardware avoids the 80-pin cable
	288	* detect issue by attaching the drives directly to the board.
	289	* This check follows the Dell precedent (how scary is that?!)
	290	*
	291	* WARNING: this only works on Alpine hardware!
	292	*/
f454cbe8	293	static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
1da177e4	294	{
36501650 BZ	295	struct pci_dev *dev = to_pci_dev(hwif->dev);
36501650 BZ	296
1da177e4 LT	297	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
	298	dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
	299	dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
	300	return ((1 << (hwif->channel + 14)) &
49521f97 BZ	301	dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
49521f97 BZ	302	return ATA_CBL_PATA40;
1da177e4 LT	303	}
1da177e4 LT	304
f454cbe8	305	static u8 svwks_cable_detect(ide_hwif_t *hwif)
1da177e4	306	{
36501650	307	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	308
1da177e4 LT	309	/* Server Works */
	310	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
	311	return ata66_svwks_svwks (hwif);
	312
	313	/* Dell PowerEdge */
	314	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
	315	return ata66_svwks_dell (hwif);
	316
	317	/* Cobalt Alpine */
	318	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
	319	return ata66_svwks_cobalt (hwif);
	320
f201f504 AC	321	/* Per Specified Design by OEM, and ASIC Architect */
	322	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) \|\|
	323	(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
49521f97	324	return ATA_CBL_PATA80;
f201f504	325
49521f97	326	return ATA_CBL_PATA40;
1da177e4 LT	327	}
1da177e4 LT	328
ac95beed BZ	329	static const struct ide_port_ops osb4_port_ops = {
	330	.set_pio_mode = svwks_set_pio_mode,
	331	.set_dma_mode = svwks_set_dma_mode,
ac95beed	332	};
1da177e4	333
ac95beed BZ	334	static const struct ide_port_ops svwks_port_ops = {
	335	.set_pio_mode = svwks_set_pio_mode,
	336	.set_dma_mode = svwks_set_dma_mode,
	337	.udma_filter = svwks_udma_filter,
	338	.cable_detect = svwks_cable_detect,
	339	};
1da177e4	340
fe31edc8	341	static const struct ide_port_info serverworks_chipsets[] = {
ced3ec8a BZ	342	{ /* 0: OSB4 */
ced3ec8a BZ	343	.name = DRV_NAME,
1da177e4	344	.init_chipset = init_chipset_svwks,
ac95beed	345	.port_ops = &osb4_port_ops,
4099d143	346	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	347	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	348	.udma_mask = 0x00, /* UDMA is problematic on OSB4 */
ced3ec8a BZ	349	},
	350	{ /* 1: CSB5 */
	351	.name = DRV_NAME,
1da177e4	352	.init_chipset = init_chipset_svwks,
ac95beed	353	.port_ops = &svwks_port_ops,
4099d143	354	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	355	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	356	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	357	},
	358	{ /* 2: CSB6 */
	359	.name = DRV_NAME,
1da177e4	360	.init_chipset = init_chipset_svwks,
ac95beed	361	.port_ops = &svwks_port_ops,
4099d143	362	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	363	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	364	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	365	},
	366	{ /* 3: CSB6-2 */
	367	.name = DRV_NAME,
1da177e4	368	.init_chipset = init_chipset_svwks,
ac95beed	369	.port_ops = &svwks_port_ops,
2467922a	370	.host_flags = IDE_HFLAG_SINGLE,
4099d143	371	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	372	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	373	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	374	},
	375	{ /* 4: HT1000 */
	376	.name = DRV_NAME,
84f57fbc	377	.init_chipset = init_chipset_svwks,
ac95beed	378	.port_ops = &svwks_port_ops,
2467922a	379	.host_flags = IDE_HFLAG_SINGLE,
4099d143	380	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	381	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	382	.udma_mask = ATA_UDMA5,
1da177e4 LT	383	}
	384	};
	385
	386	/**
	387	* svwks_init_one - called when a OSB/CSB is found
	388	* @dev: the svwks device
	389	* @id: the matching pci id
	390	*
	391	* Called when the PCI registration layer (or the IDE initialization)
	392	* finds a device matching our IDE device tables.
	393	*/
	394
fe31edc8	395	static int svwks_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	396	{
039788e1	397	struct ide_port_info d;
7ed58297 BZ	398	u8 idx = id->driver_data;
	399
	400	d = serverworks_chipsets[idx];
	401
8ac2b42a BZ	402	if (idx == 1)
	403	d.host_flags \|= IDE_HFLAG_CLEAR_SIMPLEX;
	404	else if (idx == 2 \|\| idx == 3) {
7ed58297 BZ	405	if ((PCI_FUNC(dev->devfn) & 1) == 0) {
7ed58297 BZ	406	if (pci_resource_start(dev, 0) != 0x01f1)
5e71d9c5	407	d.host_flags \|= IDE_HFLAG_NON_BOOTABLE;
7ed58297 BZ	408	d.host_flags \|= IDE_HFLAG_SINGLE;
	409	} else
	410	d.host_flags &= ~IDE_HFLAG_SINGLE;
	411	}
1da177e4	412
6cdf6eb3	413	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	414	}
1da177e4 LT	415
9cbcc5e3 BZ	416	static const struct pci_device_id svwks_pci_tbl[] = {
	417	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 },
	418	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 },
	419	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 },
	420	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 },
	421	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
1da177e4 LT	422	{ 0, },
	423	};
	424	MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
	425
a9ab09e2	426	static struct pci_driver svwks_pci_driver = {
1da177e4 LT	427	.name = "Serverworks_IDE",
	428	.id_table = svwks_pci_tbl,
	429	.probe = svwks_init_one,
bc2c9a80	430	.remove = ide_pci_remove,
feb22b7f BZ	431	.suspend = ide_pci_suspend,
feb22b7f BZ	432	.resume = ide_pci_resume,
1da177e4 LT	433	};
1da177e4 LT	434
82ab1eec	435	static int __init svwks_ide_init(void)
1da177e4	436	{
a9ab09e2	437	return ide_pci_register_driver(&svwks_pci_driver);
1da177e4 LT	438	}
1da177e4 LT	439
bc2c9a80 BZ	440	static void __exit svwks_ide_exit(void)
bc2c9a80 BZ	441	{
a9ab09e2	442	pci_unregister_driver(&svwks_pci_driver);
bc2c9a80 BZ	443	}
bc2c9a80 BZ	444
1da177e4	445	module_init(svwks_ide_init);
bc2c9a80	446	module_exit(svwks_ide_exit);
1da177e4	447
e7593af6	448	MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
1da177e4 LT	449	MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
1da177e4 LT	450	MODULE_LICENSE("GPL");